]>
Commit | Line | Data |
---|---|---|
673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
c13d87ea | 32 | #include "i915_gem_dmabuf.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
673a394b | 41 | #include <linux/swap.h> |
79e53945 | 42 | #include <linux/pci.h> |
1286ff73 | 43 | #include <linux/dma-buf.h> |
673a394b | 44 | |
05394f39 | 45 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 46 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 47 | |
c76ce038 CW |
48 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
49 | enum i915_cache_level level) | |
50 | { | |
51 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
52 | } | |
53 | ||
2c22569b CW |
54 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
55 | { | |
b50a5371 AS |
56 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
57 | return false; | |
58 | ||
2c22569b CW |
59 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
60 | return true; | |
61 | ||
62 | return obj->pin_display; | |
63 | } | |
64 | ||
4f1959ee | 65 | static int |
bb6dc8d9 | 66 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
67 | struct drm_mm_node *node, u32 size) |
68 | { | |
69 | memset(node, 0, sizeof(*node)); | |
bb6dc8d9 CW |
70 | return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node, |
71 | size, 0, -1, | |
72 | 0, ggtt->mappable_end, | |
4f1959ee AS |
73 | DRM_MM_SEARCH_DEFAULT, |
74 | DRM_MM_CREATE_DEFAULT); | |
75 | } | |
76 | ||
77 | static void | |
78 | remove_mappable_node(struct drm_mm_node *node) | |
79 | { | |
80 | drm_mm_remove_node(node); | |
81 | } | |
82 | ||
73aa808f CW |
83 | /* some bookkeeping */ |
84 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 85 | u64 size) |
73aa808f | 86 | { |
c20e8355 | 87 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | dev_priv->mm.object_count++; |
89 | dev_priv->mm.object_memory += size; | |
c20e8355 | 90 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | } |
92 | ||
93 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 94 | u64 size) |
73aa808f | 95 | { |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count--; |
98 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
21dd3734 | 102 | static int |
33196ded | 103 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 104 | { |
30dbf0c0 CW |
105 | int ret; |
106 | ||
4c7d62c6 CW |
107 | might_sleep(); |
108 | ||
d98c52cf | 109 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
110 | return 0; |
111 | ||
0a6759c6 DV |
112 | /* |
113 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
114 | * userspace. If it takes that long something really bad is going on and | |
115 | * we should simply try to bail out and fail as gracefully as possible. | |
116 | */ | |
1f83fee0 | 117 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 118 | !i915_reset_in_progress(error), |
b52992c0 | 119 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
120 | if (ret == 0) { |
121 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
122 | return -EIO; | |
123 | } else if (ret < 0) { | |
30dbf0c0 | 124 | return ret; |
d98c52cf CW |
125 | } else { |
126 | return 0; | |
0a6759c6 | 127 | } |
30dbf0c0 CW |
128 | } |
129 | ||
54cf91dc | 130 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 131 | { |
fac5e23e | 132 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
133 | int ret; |
134 | ||
33196ded | 135 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
136 | if (ret) |
137 | return ret; | |
138 | ||
139 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
140 | if (ret) | |
141 | return ret; | |
142 | ||
76c1dec1 CW |
143 | return 0; |
144 | } | |
30dbf0c0 | 145 | |
5a125c3c EA |
146 | int |
147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
5a125c3c | 149 | { |
72e96d64 | 150 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 151 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 152 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 153 | struct i915_vma *vma; |
6299f992 | 154 | size_t pinned; |
5a125c3c | 155 | |
6299f992 | 156 | pinned = 0; |
73aa808f | 157 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 158 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 159 | if (i915_vma_is_pinned(vma)) |
ca1543be | 160 | pinned += vma->node.size; |
1c7f4bca | 161 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 162 | if (i915_vma_is_pinned(vma)) |
ca1543be | 163 | pinned += vma->node.size; |
73aa808f | 164 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 165 | |
72e96d64 | 166 | args->aper_size = ggtt->base.total; |
0206e353 | 167 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 168 | |
5a125c3c EA |
169 | return 0; |
170 | } | |
171 | ||
03ac84f1 | 172 | static struct sg_table * |
6a2c4232 | 173 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 174 | { |
93c76a3d | 175 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 CW |
176 | char *vaddr = obj->phys_handle->vaddr; |
177 | struct sg_table *st; | |
178 | struct scatterlist *sg; | |
179 | int i; | |
00731155 | 180 | |
6a2c4232 | 181 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 182 | return ERR_PTR(-EINVAL); |
6a2c4232 CW |
183 | |
184 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
185 | struct page *page; | |
186 | char *src; | |
187 | ||
188 | page = shmem_read_mapping_page(mapping, i); | |
189 | if (IS_ERR(page)) | |
03ac84f1 | 190 | return ERR_CAST(page); |
6a2c4232 CW |
191 | |
192 | src = kmap_atomic(page); | |
193 | memcpy(vaddr, src, PAGE_SIZE); | |
194 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
195 | kunmap_atomic(src); | |
196 | ||
09cbfeaf | 197 | put_page(page); |
6a2c4232 CW |
198 | vaddr += PAGE_SIZE; |
199 | } | |
200 | ||
c033666a | 201 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
202 | |
203 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
204 | if (st == NULL) | |
03ac84f1 | 205 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
206 | |
207 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
208 | kfree(st); | |
03ac84f1 | 209 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
210 | } |
211 | ||
212 | sg = st->sgl; | |
213 | sg->offset = 0; | |
214 | sg->length = obj->base.size; | |
00731155 | 215 | |
6a2c4232 CW |
216 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
217 | sg_dma_len(sg) = obj->base.size; | |
218 | ||
03ac84f1 | 219 | return st; |
6a2c4232 CW |
220 | } |
221 | ||
222 | static void | |
03ac84f1 | 223 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj) |
6a2c4232 | 224 | { |
a4f5ea64 | 225 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 226 | |
a4f5ea64 CW |
227 | if (obj->mm.madv == I915_MADV_DONTNEED) |
228 | obj->mm.dirty = false; | |
6a2c4232 | 229 | |
03ac84f1 CW |
230 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
231 | i915_gem_clflush_object(obj, false); | |
232 | ||
233 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
234 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
235 | } | |
236 | ||
237 | static void | |
238 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
239 | struct sg_table *pages) | |
240 | { | |
241 | __i915_gem_object_release_shmem(obj); | |
242 | ||
a4f5ea64 | 243 | if (obj->mm.dirty) { |
93c76a3d | 244 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 245 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
246 | int i; |
247 | ||
248 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
249 | struct page *page; |
250 | char *dst; | |
251 | ||
252 | page = shmem_read_mapping_page(mapping, i); | |
253 | if (IS_ERR(page)) | |
254 | continue; | |
255 | ||
256 | dst = kmap_atomic(page); | |
257 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
258 | memcpy(dst, vaddr, PAGE_SIZE); | |
259 | kunmap_atomic(dst); | |
260 | ||
261 | set_page_dirty(page); | |
a4f5ea64 | 262 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 263 | mark_page_accessed(page); |
09cbfeaf | 264 | put_page(page); |
00731155 CW |
265 | vaddr += PAGE_SIZE; |
266 | } | |
a4f5ea64 | 267 | obj->mm.dirty = false; |
00731155 CW |
268 | } |
269 | ||
03ac84f1 CW |
270 | sg_free_table(pages); |
271 | kfree(pages); | |
6a2c4232 CW |
272 | } |
273 | ||
274 | static void | |
275 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
276 | { | |
277 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
a4f5ea64 | 278 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
279 | } |
280 | ||
281 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
282 | .get_pages = i915_gem_object_get_pages_phys, | |
283 | .put_pages = i915_gem_object_put_pages_phys, | |
284 | .release = i915_gem_object_release_phys, | |
285 | }; | |
286 | ||
35a9611c | 287 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
288 | { |
289 | struct i915_vma *vma; | |
290 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
291 | int ret; |
292 | ||
293 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 294 | |
02bef8f9 CW |
295 | /* Closed vma are removed from the obj->vma_list - but they may |
296 | * still have an active binding on the object. To remove those we | |
297 | * must wait for all rendering to complete to the object (as unbinding | |
298 | * must anyway), and retire the requests. | |
aa653a68 | 299 | */ |
e95433c7 CW |
300 | ret = i915_gem_object_wait(obj, |
301 | I915_WAIT_INTERRUPTIBLE | | |
302 | I915_WAIT_LOCKED | | |
303 | I915_WAIT_ALL, | |
304 | MAX_SCHEDULE_TIMEOUT, | |
305 | NULL); | |
02bef8f9 CW |
306 | if (ret) |
307 | return ret; | |
308 | ||
309 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
310 | ||
aa653a68 CW |
311 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
312 | struct i915_vma, | |
313 | obj_link))) { | |
314 | list_move_tail(&vma->obj_link, &still_in_list); | |
315 | ret = i915_vma_unbind(vma); | |
316 | if (ret) | |
317 | break; | |
318 | } | |
319 | list_splice(&still_in_list, &obj->vma_list); | |
320 | ||
321 | return ret; | |
322 | } | |
323 | ||
e95433c7 CW |
324 | static long |
325 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
326 | unsigned int flags, | |
327 | long timeout, | |
328 | struct intel_rps_client *rps) | |
00e60f26 | 329 | { |
e95433c7 | 330 | struct drm_i915_gem_request *rq; |
00e60f26 | 331 | |
e95433c7 | 332 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 333 | |
e95433c7 CW |
334 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
335 | return timeout; | |
336 | ||
337 | if (!dma_fence_is_i915(fence)) | |
338 | return dma_fence_wait_timeout(fence, | |
339 | flags & I915_WAIT_INTERRUPTIBLE, | |
340 | timeout); | |
341 | ||
342 | rq = to_request(fence); | |
343 | if (i915_gem_request_completed(rq)) | |
344 | goto out; | |
345 | ||
346 | /* This client is about to stall waiting for the GPU. In many cases | |
347 | * this is undesirable and limits the throughput of the system, as | |
348 | * many clients cannot continue processing user input/output whilst | |
349 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
350 | * to the GPU load and thus incurs additional latency for the client. | |
351 | * We can circumvent that by promoting the GPU frequency to maximum | |
352 | * before we wait. This makes the GPU throttle up much more quickly | |
353 | * (good for benchmarks and user experience, e.g. window animations), | |
354 | * but at a cost of spending more power processing the workload | |
355 | * (bad for battery). Not all clients even want their results | |
356 | * immediately and for them we should just let the GPU select its own | |
357 | * frequency to maximise efficiency. To prevent a single client from | |
358 | * forcing the clocks too high for the whole system, we only allow | |
359 | * each client to waitboost once in a busy period. | |
360 | */ | |
361 | if (rps) { | |
362 | if (INTEL_GEN(rq->i915) >= 6) | |
363 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
364 | else | |
365 | rps = NULL; | |
00e60f26 CW |
366 | } |
367 | ||
e95433c7 CW |
368 | timeout = i915_wait_request(rq, flags, timeout); |
369 | ||
370 | out: | |
371 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
372 | i915_gem_request_retire_upto(rq); | |
373 | ||
374 | if (rps && rq->fence.seqno == rq->engine->last_submitted_seqno) { | |
375 | /* The GPU is now idle and this client has stalled. | |
376 | * Since no other client has submitted a request in the | |
377 | * meantime, assume that this client is the only one | |
378 | * supplying work to the GPU but is unable to keep that | |
379 | * work supplied because it is waiting. Since the GPU is | |
380 | * then never kept fully busy, RPS autoclocking will | |
381 | * keep the clocks relatively low, causing further delays. | |
382 | * Compensate by giving the synchronous client credit for | |
383 | * a waitboost next time. | |
384 | */ | |
385 | spin_lock(&rq->i915->rps.client_lock); | |
386 | list_del_init(&rps->link); | |
387 | spin_unlock(&rq->i915->rps.client_lock); | |
388 | } | |
389 | ||
390 | return timeout; | |
391 | } | |
392 | ||
393 | static long | |
394 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
395 | unsigned int flags, | |
396 | long timeout, | |
397 | struct intel_rps_client *rps) | |
398 | { | |
399 | struct dma_fence *excl; | |
400 | ||
401 | if (flags & I915_WAIT_ALL) { | |
402 | struct dma_fence **shared; | |
403 | unsigned int count, i; | |
00e60f26 CW |
404 | int ret; |
405 | ||
e95433c7 CW |
406 | ret = reservation_object_get_fences_rcu(resv, |
407 | &excl, &count, &shared); | |
00e60f26 CW |
408 | if (ret) |
409 | return ret; | |
00e60f26 | 410 | |
e95433c7 CW |
411 | for (i = 0; i < count; i++) { |
412 | timeout = i915_gem_object_wait_fence(shared[i], | |
413 | flags, timeout, | |
414 | rps); | |
415 | if (timeout <= 0) | |
416 | break; | |
00e60f26 | 417 | |
e95433c7 CW |
418 | dma_fence_put(shared[i]); |
419 | } | |
420 | ||
421 | for (; i < count; i++) | |
422 | dma_fence_put(shared[i]); | |
423 | kfree(shared); | |
424 | } else { | |
425 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
426 | } |
427 | ||
e95433c7 CW |
428 | if (excl && timeout > 0) |
429 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); | |
430 | ||
431 | dma_fence_put(excl); | |
432 | ||
433 | return timeout; | |
00e60f26 CW |
434 | } |
435 | ||
e95433c7 CW |
436 | /** |
437 | * Waits for rendering to the object to be completed | |
438 | * @obj: i915 gem object | |
439 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
440 | * @timeout: how long to wait | |
441 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 442 | */ |
e95433c7 CW |
443 | int |
444 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
445 | unsigned int flags, | |
446 | long timeout, | |
447 | struct intel_rps_client *rps) | |
00e60f26 | 448 | { |
e95433c7 | 449 | struct reservation_object *resv; |
00e60f26 CW |
450 | struct i915_gem_active *active; |
451 | unsigned long active_mask; | |
b8f9096d | 452 | int idx; |
00e60f26 | 453 | |
e95433c7 CW |
454 | might_sleep(); |
455 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
456 | GEM_BUG_ON(debug_locks && | |
457 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
458 | !!(flags & I915_WAIT_LOCKED)); | |
459 | #endif | |
460 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 461 | |
e95433c7 | 462 | if (flags & I915_WAIT_ALL) { |
00e60f26 | 463 | active = obj->last_read; |
e95433c7 | 464 | active_mask = i915_gem_object_get_active(obj); |
00e60f26 CW |
465 | } else { |
466 | active_mask = 1; | |
467 | active = &obj->last_write; | |
468 | } | |
469 | ||
b8f9096d | 470 | for_each_active(active_mask, idx) { |
e95433c7 CW |
471 | struct drm_i915_gem_request *request; |
472 | ||
473 | request = i915_gem_active_get_unlocked(&active[idx]); | |
474 | if (request) { | |
475 | timeout = i915_gem_object_wait_fence(&request->fence, | |
476 | flags, timeout, | |
477 | rps); | |
478 | i915_gem_request_put(request); | |
479 | } | |
480 | if (timeout < 0) | |
481 | return timeout; | |
00e60f26 CW |
482 | } |
483 | ||
e95433c7 CW |
484 | resv = i915_gem_object_get_dmabuf_resv(obj); |
485 | if (resv) | |
486 | timeout = i915_gem_object_wait_reservation(resv, | |
487 | flags, timeout, | |
488 | rps); | |
489 | return timeout < 0 ? timeout : 0; | |
00e60f26 CW |
490 | } |
491 | ||
492 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
493 | { | |
494 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
495 | ||
496 | return &fpriv->rps; | |
497 | } | |
498 | ||
00731155 CW |
499 | int |
500 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
501 | int align) | |
502 | { | |
503 | drm_dma_handle_t *phys; | |
6a2c4232 | 504 | int ret; |
00731155 CW |
505 | |
506 | if (obj->phys_handle) { | |
507 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
508 | return -EBUSY; | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
a4f5ea64 | 513 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
514 | return -EFAULT; |
515 | ||
516 | if (obj->base.filp == NULL) | |
517 | return -EINVAL; | |
518 | ||
4717ca9e CW |
519 | ret = i915_gem_object_unbind(obj); |
520 | if (ret) | |
521 | return ret; | |
522 | ||
03ac84f1 CW |
523 | __i915_gem_object_put_pages(obj); |
524 | if (obj->mm.pages) | |
525 | return -EBUSY; | |
6a2c4232 | 526 | |
00731155 CW |
527 | /* create a new object */ |
528 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
529 | if (!phys) | |
530 | return -ENOMEM; | |
531 | ||
00731155 | 532 | obj->phys_handle = phys; |
6a2c4232 CW |
533 | obj->ops = &i915_gem_phys_ops; |
534 | ||
a4f5ea64 | 535 | return i915_gem_object_pin_pages(obj); |
00731155 CW |
536 | } |
537 | ||
538 | static int | |
539 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
540 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 541 | struct drm_file *file) |
00731155 CW |
542 | { |
543 | struct drm_device *dev = obj->base.dev; | |
544 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 545 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
e95433c7 | 546 | int ret; |
6a2c4232 CW |
547 | |
548 | /* We manually control the domain here and pretend that it | |
549 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
550 | */ | |
e95433c7 CW |
551 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
552 | ret = i915_gem_object_wait(obj, | |
553 | I915_WAIT_INTERRUPTIBLE | | |
554 | I915_WAIT_LOCKED | | |
555 | I915_WAIT_ALL, | |
556 | MAX_SCHEDULE_TIMEOUT, | |
03ac84f1 | 557 | to_rps_client(file)); |
6a2c4232 CW |
558 | if (ret) |
559 | return ret; | |
00731155 | 560 | |
77a0d1ca | 561 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
562 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
563 | unsigned long unwritten; | |
564 | ||
565 | /* The physical object once assigned is fixed for the lifetime | |
566 | * of the obj, so we can safely drop the lock and continue | |
567 | * to access vaddr. | |
568 | */ | |
569 | mutex_unlock(&dev->struct_mutex); | |
570 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
571 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
572 | if (unwritten) { |
573 | ret = -EFAULT; | |
574 | goto out; | |
575 | } | |
00731155 CW |
576 | } |
577 | ||
6a2c4232 | 578 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 579 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
580 | |
581 | out: | |
de152b62 | 582 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 583 | return ret; |
00731155 CW |
584 | } |
585 | ||
42dcedd4 CW |
586 | void *i915_gem_object_alloc(struct drm_device *dev) |
587 | { | |
fac5e23e | 588 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 589 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
590 | } |
591 | ||
592 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
593 | { | |
fac5e23e | 594 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 595 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
596 | } |
597 | ||
ff72145b DA |
598 | static int |
599 | i915_gem_create(struct drm_file *file, | |
600 | struct drm_device *dev, | |
601 | uint64_t size, | |
602 | uint32_t *handle_p) | |
673a394b | 603 | { |
05394f39 | 604 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
605 | int ret; |
606 | u32 handle; | |
673a394b | 607 | |
ff72145b | 608 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
609 | if (size == 0) |
610 | return -EINVAL; | |
673a394b EA |
611 | |
612 | /* Allocate the new object */ | |
d37cd8a8 | 613 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
614 | if (IS_ERR(obj)) |
615 | return PTR_ERR(obj); | |
673a394b | 616 | |
05394f39 | 617 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 618 | /* drop reference from allocate - handle holds it now */ |
34911fd3 | 619 | i915_gem_object_put_unlocked(obj); |
d861e338 DV |
620 | if (ret) |
621 | return ret; | |
202f2fef | 622 | |
ff72145b | 623 | *handle_p = handle; |
673a394b EA |
624 | return 0; |
625 | } | |
626 | ||
ff72145b DA |
627 | int |
628 | i915_gem_dumb_create(struct drm_file *file, | |
629 | struct drm_device *dev, | |
630 | struct drm_mode_create_dumb *args) | |
631 | { | |
632 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 633 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
634 | args->size = args->pitch * args->height; |
635 | return i915_gem_create(file, dev, | |
da6b51d0 | 636 | args->size, &args->handle); |
ff72145b DA |
637 | } |
638 | ||
ff72145b DA |
639 | /** |
640 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
641 | * @dev: drm device pointer |
642 | * @data: ioctl data blob | |
643 | * @file: drm file pointer | |
ff72145b DA |
644 | */ |
645 | int | |
646 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
647 | struct drm_file *file) | |
648 | { | |
649 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 650 | |
ff72145b | 651 | return i915_gem_create(file, dev, |
da6b51d0 | 652 | args->size, &args->handle); |
ff72145b DA |
653 | } |
654 | ||
8461d226 DV |
655 | static inline int |
656 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
657 | const char *gpu_vaddr, int gpu_offset, | |
658 | int length) | |
659 | { | |
660 | int ret, cpu_offset = 0; | |
661 | ||
662 | while (length > 0) { | |
663 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
664 | int this_length = min(cacheline_end - gpu_offset, length); | |
665 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
666 | ||
667 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
668 | gpu_vaddr + swizzled_gpu_offset, | |
669 | this_length); | |
670 | if (ret) | |
671 | return ret + length; | |
672 | ||
673 | cpu_offset += this_length; | |
674 | gpu_offset += this_length; | |
675 | length -= this_length; | |
676 | } | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
8c59967c | 681 | static inline int |
4f0c7cfb BW |
682 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
683 | const char __user *cpu_vaddr, | |
8c59967c DV |
684 | int length) |
685 | { | |
686 | int ret, cpu_offset = 0; | |
687 | ||
688 | while (length > 0) { | |
689 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
690 | int this_length = min(cacheline_end - gpu_offset, length); | |
691 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
692 | ||
693 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
694 | cpu_vaddr + cpu_offset, | |
695 | this_length); | |
696 | if (ret) | |
697 | return ret + length; | |
698 | ||
699 | cpu_offset += this_length; | |
700 | gpu_offset += this_length; | |
701 | length -= this_length; | |
702 | } | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
4c914c0c BV |
707 | /* |
708 | * Pins the specified object's pages and synchronizes the object with | |
709 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
710 | * flush the object from the CPU cache. | |
711 | */ | |
712 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 713 | unsigned int *needs_clflush) |
4c914c0c BV |
714 | { |
715 | int ret; | |
716 | ||
e95433c7 | 717 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 718 | |
e95433c7 | 719 | *needs_clflush = 0; |
43394c7d CW |
720 | if (!i915_gem_object_has_struct_page(obj)) |
721 | return -ENODEV; | |
4c914c0c | 722 | |
e95433c7 CW |
723 | ret = i915_gem_object_wait(obj, |
724 | I915_WAIT_INTERRUPTIBLE | | |
725 | I915_WAIT_LOCKED, | |
726 | MAX_SCHEDULE_TIMEOUT, | |
727 | NULL); | |
c13d87ea CW |
728 | if (ret) |
729 | return ret; | |
730 | ||
a4f5ea64 | 731 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
732 | if (ret) |
733 | return ret; | |
734 | ||
a314d5cb CW |
735 | i915_gem_object_flush_gtt_write_domain(obj); |
736 | ||
43394c7d CW |
737 | /* If we're not in the cpu read domain, set ourself into the gtt |
738 | * read domain and manually flush cachelines (if required). This | |
739 | * optimizes for the case when the gpu will dirty the data | |
740 | * anyway again before the next pread happens. | |
741 | */ | |
742 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
743 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
744 | obj->cache_level); | |
43394c7d | 745 | |
43394c7d CW |
746 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
747 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
748 | if (ret) |
749 | goto err_unpin; | |
750 | ||
43394c7d | 751 | *needs_clflush = 0; |
4c914c0c BV |
752 | } |
753 | ||
9764951e | 754 | /* return with the pages pinned */ |
43394c7d | 755 | return 0; |
9764951e CW |
756 | |
757 | err_unpin: | |
758 | i915_gem_object_unpin_pages(obj); | |
759 | return ret; | |
43394c7d CW |
760 | } |
761 | ||
762 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
763 | unsigned int *needs_clflush) | |
764 | { | |
765 | int ret; | |
766 | ||
e95433c7 CW |
767 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
768 | ||
43394c7d CW |
769 | *needs_clflush = 0; |
770 | if (!i915_gem_object_has_struct_page(obj)) | |
771 | return -ENODEV; | |
772 | ||
e95433c7 CW |
773 | ret = i915_gem_object_wait(obj, |
774 | I915_WAIT_INTERRUPTIBLE | | |
775 | I915_WAIT_LOCKED | | |
776 | I915_WAIT_ALL, | |
777 | MAX_SCHEDULE_TIMEOUT, | |
778 | NULL); | |
43394c7d CW |
779 | if (ret) |
780 | return ret; | |
781 | ||
a4f5ea64 | 782 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
783 | if (ret) |
784 | return ret; | |
785 | ||
a314d5cb CW |
786 | i915_gem_object_flush_gtt_write_domain(obj); |
787 | ||
43394c7d CW |
788 | /* If we're not in the cpu write domain, set ourself into the |
789 | * gtt write domain and manually flush cachelines (as required). | |
790 | * This optimizes for the case when the gpu will use the data | |
791 | * right away and we therefore have to clflush anyway. | |
792 | */ | |
793 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
794 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
795 | ||
796 | /* Same trick applies to invalidate partially written cachelines read | |
797 | * before writing. | |
798 | */ | |
799 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
800 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
801 | obj->cache_level); | |
802 | ||
43394c7d CW |
803 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
804 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
805 | if (ret) |
806 | goto err_unpin; | |
807 | ||
43394c7d CW |
808 | *needs_clflush = 0; |
809 | } | |
810 | ||
811 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
812 | obj->cache_dirty = true; | |
813 | ||
814 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
a4f5ea64 | 815 | obj->mm.dirty = true; |
9764951e | 816 | /* return with the pages pinned */ |
43394c7d | 817 | return 0; |
9764951e CW |
818 | |
819 | err_unpin: | |
820 | i915_gem_object_unpin_pages(obj); | |
821 | return ret; | |
4c914c0c BV |
822 | } |
823 | ||
23c18c71 DV |
824 | static void |
825 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
826 | bool swizzled) | |
827 | { | |
e7e58eb5 | 828 | if (unlikely(swizzled)) { |
23c18c71 DV |
829 | unsigned long start = (unsigned long) addr; |
830 | unsigned long end = (unsigned long) addr + length; | |
831 | ||
832 | /* For swizzling simply ensure that we always flush both | |
833 | * channels. Lame, but simple and it works. Swizzled | |
834 | * pwrite/pread is far from a hotpath - current userspace | |
835 | * doesn't use it at all. */ | |
836 | start = round_down(start, 128); | |
837 | end = round_up(end, 128); | |
838 | ||
839 | drm_clflush_virt_range((void *)start, end - start); | |
840 | } else { | |
841 | drm_clflush_virt_range(addr, length); | |
842 | } | |
843 | ||
844 | } | |
845 | ||
d174bd64 DV |
846 | /* Only difference to the fast-path function is that this can handle bit17 |
847 | * and uses non-atomic copy and kmap functions. */ | |
848 | static int | |
bb6dc8d9 | 849 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
850 | char __user *user_data, |
851 | bool page_do_bit17_swizzling, bool needs_clflush) | |
852 | { | |
853 | char *vaddr; | |
854 | int ret; | |
855 | ||
856 | vaddr = kmap(page); | |
857 | if (needs_clflush) | |
bb6dc8d9 | 858 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 859 | page_do_bit17_swizzling); |
d174bd64 DV |
860 | |
861 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 862 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 863 | else |
bb6dc8d9 | 864 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
865 | kunmap(page); |
866 | ||
f60d7f0c | 867 | return ret ? - EFAULT : 0; |
d174bd64 DV |
868 | } |
869 | ||
bb6dc8d9 CW |
870 | static int |
871 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
872 | bool page_do_bit17_swizzling, bool needs_clflush) | |
873 | { | |
874 | int ret; | |
875 | ||
876 | ret = -ENODEV; | |
877 | if (!page_do_bit17_swizzling) { | |
878 | char *vaddr = kmap_atomic(page); | |
879 | ||
880 | if (needs_clflush) | |
881 | drm_clflush_virt_range(vaddr + offset, length); | |
882 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
883 | kunmap_atomic(vaddr); | |
884 | } | |
885 | if (ret == 0) | |
886 | return 0; | |
887 | ||
888 | return shmem_pread_slow(page, offset, length, user_data, | |
889 | page_do_bit17_swizzling, needs_clflush); | |
890 | } | |
891 | ||
892 | static int | |
893 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
894 | struct drm_i915_gem_pread *args) | |
895 | { | |
896 | char __user *user_data; | |
897 | u64 remain; | |
898 | unsigned int obj_do_bit17_swizzling; | |
899 | unsigned int needs_clflush; | |
900 | unsigned int idx, offset; | |
901 | int ret; | |
902 | ||
903 | obj_do_bit17_swizzling = 0; | |
904 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
905 | obj_do_bit17_swizzling = BIT(17); | |
906 | ||
907 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
908 | if (ret) | |
909 | return ret; | |
910 | ||
911 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
912 | mutex_unlock(&obj->base.dev->struct_mutex); | |
913 | if (ret) | |
914 | return ret; | |
915 | ||
916 | remain = args->size; | |
917 | user_data = u64_to_user_ptr(args->data_ptr); | |
918 | offset = offset_in_page(args->offset); | |
919 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
920 | struct page *page = i915_gem_object_get_page(obj, idx); | |
921 | int length; | |
922 | ||
923 | length = remain; | |
924 | if (offset + length > PAGE_SIZE) | |
925 | length = PAGE_SIZE - offset; | |
926 | ||
927 | ret = shmem_pread(page, offset, length, user_data, | |
928 | page_to_phys(page) & obj_do_bit17_swizzling, | |
929 | needs_clflush); | |
930 | if (ret) | |
931 | break; | |
932 | ||
933 | remain -= length; | |
934 | user_data += length; | |
935 | offset = 0; | |
936 | } | |
937 | ||
938 | i915_gem_obj_finish_shmem_access(obj); | |
939 | return ret; | |
940 | } | |
941 | ||
942 | static inline bool | |
943 | gtt_user_read(struct io_mapping *mapping, | |
944 | loff_t base, int offset, | |
945 | char __user *user_data, int length) | |
b50a5371 | 946 | { |
b50a5371 | 947 | void *vaddr; |
bb6dc8d9 | 948 | unsigned long unwritten; |
b50a5371 | 949 | |
b50a5371 | 950 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
951 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
952 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
953 | io_mapping_unmap_atomic(vaddr); | |
954 | if (unwritten) { | |
955 | vaddr = (void __force *) | |
956 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
957 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
958 | io_mapping_unmap(vaddr); | |
959 | } | |
b50a5371 AS |
960 | return unwritten; |
961 | } | |
962 | ||
963 | static int | |
bb6dc8d9 CW |
964 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
965 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 966 | { |
bb6dc8d9 CW |
967 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
968 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 969 | struct drm_mm_node node; |
bb6dc8d9 CW |
970 | struct i915_vma *vma; |
971 | void __user *user_data; | |
972 | u64 remain, offset; | |
b50a5371 AS |
973 | int ret; |
974 | ||
bb6dc8d9 CW |
975 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
976 | if (ret) | |
977 | return ret; | |
978 | ||
979 | intel_runtime_pm_get(i915); | |
980 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
981 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
982 | if (!IS_ERR(vma)) { |
983 | node.start = i915_ggtt_offset(vma); | |
984 | node.allocated = false; | |
49ef5294 | 985 | ret = i915_vma_put_fence(vma); |
18034584 CW |
986 | if (ret) { |
987 | i915_vma_unpin(vma); | |
988 | vma = ERR_PTR(ret); | |
989 | } | |
990 | } | |
058d88c4 | 991 | if (IS_ERR(vma)) { |
bb6dc8d9 | 992 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 993 | if (ret) |
bb6dc8d9 CW |
994 | goto out_unlock; |
995 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
996 | } |
997 | ||
998 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
999 | if (ret) | |
1000 | goto out_unpin; | |
1001 | ||
bb6dc8d9 | 1002 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1003 | |
bb6dc8d9 CW |
1004 | user_data = u64_to_user_ptr(args->data_ptr); |
1005 | remain = args->size; | |
1006 | offset = args->offset; | |
b50a5371 AS |
1007 | |
1008 | while (remain > 0) { | |
1009 | /* Operation in this page | |
1010 | * | |
1011 | * page_base = page offset within aperture | |
1012 | * page_offset = offset within page | |
1013 | * page_length = bytes to copy for this page | |
1014 | */ | |
1015 | u32 page_base = node.start; | |
1016 | unsigned page_offset = offset_in_page(offset); | |
1017 | unsigned page_length = PAGE_SIZE - page_offset; | |
1018 | page_length = remain < page_length ? remain : page_length; | |
1019 | if (node.allocated) { | |
1020 | wmb(); | |
1021 | ggtt->base.insert_page(&ggtt->base, | |
1022 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1023 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1024 | wmb(); |
1025 | } else { | |
1026 | page_base += offset & PAGE_MASK; | |
1027 | } | |
bb6dc8d9 CW |
1028 | |
1029 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1030 | user_data, page_length)) { | |
b50a5371 AS |
1031 | ret = -EFAULT; |
1032 | break; | |
1033 | } | |
1034 | ||
1035 | remain -= page_length; | |
1036 | user_data += page_length; | |
1037 | offset += page_length; | |
1038 | } | |
1039 | ||
bb6dc8d9 | 1040 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1041 | out_unpin: |
1042 | if (node.allocated) { | |
1043 | wmb(); | |
1044 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1045 | node.start, node.size); |
b50a5371 AS |
1046 | remove_mappable_node(&node); |
1047 | } else { | |
058d88c4 | 1048 | i915_vma_unpin(vma); |
b50a5371 | 1049 | } |
bb6dc8d9 CW |
1050 | out_unlock: |
1051 | intel_runtime_pm_put(i915); | |
1052 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1053 | |
eb01459f EA |
1054 | return ret; |
1055 | } | |
1056 | ||
673a394b EA |
1057 | /** |
1058 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1059 | * @dev: drm device pointer |
1060 | * @data: ioctl data blob | |
1061 | * @file: drm file pointer | |
673a394b EA |
1062 | * |
1063 | * On error, the contents of *data are undefined. | |
1064 | */ | |
1065 | int | |
1066 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1067 | struct drm_file *file) |
673a394b EA |
1068 | { |
1069 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1070 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1071 | int ret; |
673a394b | 1072 | |
51311d0a CW |
1073 | if (args->size == 0) |
1074 | return 0; | |
1075 | ||
1076 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1077 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1078 | args->size)) |
1079 | return -EFAULT; | |
1080 | ||
03ac0642 | 1081 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1082 | if (!obj) |
1083 | return -ENOENT; | |
673a394b | 1084 | |
7dcd2499 | 1085 | /* Bounds check source. */ |
05394f39 CW |
1086 | if (args->offset > obj->base.size || |
1087 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1088 | ret = -EINVAL; |
bb6dc8d9 | 1089 | goto out; |
ce9d419d CW |
1090 | } |
1091 | ||
db53a302 CW |
1092 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1093 | ||
e95433c7 CW |
1094 | ret = i915_gem_object_wait(obj, |
1095 | I915_WAIT_INTERRUPTIBLE, | |
1096 | MAX_SCHEDULE_TIMEOUT, | |
1097 | to_rps_client(file)); | |
258a5ede | 1098 | if (ret) |
bb6dc8d9 | 1099 | goto out; |
258a5ede | 1100 | |
bb6dc8d9 | 1101 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1102 | if (ret) |
bb6dc8d9 | 1103 | goto out; |
673a394b | 1104 | |
bb6dc8d9 | 1105 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1106 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1107 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1108 | |
bb6dc8d9 CW |
1109 | i915_gem_object_unpin_pages(obj); |
1110 | out: | |
258a5ede | 1111 | i915_gem_object_put_unlocked(obj); |
eb01459f | 1112 | return ret; |
673a394b EA |
1113 | } |
1114 | ||
0839ccb8 KP |
1115 | /* This is the fast write path which cannot handle |
1116 | * page faults in the source data | |
9b7530cc | 1117 | */ |
0839ccb8 | 1118 | |
fe115628 CW |
1119 | static inline bool |
1120 | ggtt_write(struct io_mapping *mapping, | |
1121 | loff_t base, int offset, | |
1122 | char __user *user_data, int length) | |
9b7530cc | 1123 | { |
4f0c7cfb | 1124 | void *vaddr; |
0839ccb8 | 1125 | unsigned long unwritten; |
9b7530cc | 1126 | |
4f0c7cfb | 1127 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1128 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1129 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1130 | user_data, length); |
fe115628 CW |
1131 | io_mapping_unmap_atomic(vaddr); |
1132 | if (unwritten) { | |
1133 | vaddr = (void __force *) | |
1134 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1135 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1136 | io_mapping_unmap(vaddr); | |
1137 | } | |
bb6dc8d9 | 1138 | |
bb6dc8d9 CW |
1139 | return unwritten; |
1140 | } | |
1141 | ||
3de09aa3 EA |
1142 | /** |
1143 | * This is the fast pwrite path, where we copy the data directly from the | |
1144 | * user into the GTT, uncached. | |
fe115628 | 1145 | * @obj: i915 GEM object |
14bb2c11 | 1146 | * @args: pwrite arguments structure |
3de09aa3 | 1147 | */ |
673a394b | 1148 | static int |
fe115628 CW |
1149 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1150 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1151 | { |
fe115628 | 1152 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1153 | struct i915_ggtt *ggtt = &i915->ggtt; |
1154 | struct drm_mm_node node; | |
fe115628 CW |
1155 | struct i915_vma *vma; |
1156 | u64 remain, offset; | |
1157 | void __user *user_data; | |
4f1959ee | 1158 | int ret; |
b50a5371 | 1159 | |
fe115628 CW |
1160 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1161 | if (ret) | |
1162 | return ret; | |
935aaa69 | 1163 | |
9c870d03 | 1164 | intel_runtime_pm_get(i915); |
058d88c4 | 1165 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1166 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1167 | if (!IS_ERR(vma)) { |
1168 | node.start = i915_ggtt_offset(vma); | |
1169 | node.allocated = false; | |
49ef5294 | 1170 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1171 | if (ret) { |
1172 | i915_vma_unpin(vma); | |
1173 | vma = ERR_PTR(ret); | |
1174 | } | |
1175 | } | |
058d88c4 | 1176 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1177 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1178 | if (ret) |
fe115628 CW |
1179 | goto out_unlock; |
1180 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1181 | } |
935aaa69 DV |
1182 | |
1183 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1184 | if (ret) | |
1185 | goto out_unpin; | |
1186 | ||
fe115628 CW |
1187 | mutex_unlock(&i915->drm.struct_mutex); |
1188 | ||
b19482d7 | 1189 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1190 | |
4f1959ee AS |
1191 | user_data = u64_to_user_ptr(args->data_ptr); |
1192 | offset = args->offset; | |
1193 | remain = args->size; | |
1194 | while (remain) { | |
673a394b EA |
1195 | /* Operation in this page |
1196 | * | |
0839ccb8 KP |
1197 | * page_base = page offset within aperture |
1198 | * page_offset = offset within page | |
1199 | * page_length = bytes to copy for this page | |
673a394b | 1200 | */ |
4f1959ee | 1201 | u32 page_base = node.start; |
bb6dc8d9 CW |
1202 | unsigned int page_offset = offset_in_page(offset); |
1203 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1204 | page_length = remain < page_length ? remain : page_length; |
1205 | if (node.allocated) { | |
1206 | wmb(); /* flush the write before we modify the GGTT */ | |
1207 | ggtt->base.insert_page(&ggtt->base, | |
1208 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1209 | node.start, I915_CACHE_NONE, 0); | |
1210 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1211 | } else { | |
1212 | page_base += offset & PAGE_MASK; | |
1213 | } | |
0839ccb8 | 1214 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1215 | * source page isn't available. Return the error and we'll |
1216 | * retry in the slow path. | |
b50a5371 AS |
1217 | * If the object is non-shmem backed, we retry again with the |
1218 | * path that handles page fault. | |
0839ccb8 | 1219 | */ |
fe115628 CW |
1220 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1221 | user_data, page_length)) { | |
1222 | ret = -EFAULT; | |
1223 | break; | |
935aaa69 | 1224 | } |
673a394b | 1225 | |
0839ccb8 KP |
1226 | remain -= page_length; |
1227 | user_data += page_length; | |
1228 | offset += page_length; | |
673a394b | 1229 | } |
b19482d7 | 1230 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 CW |
1231 | |
1232 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1233 | out_unpin: |
4f1959ee AS |
1234 | if (node.allocated) { |
1235 | wmb(); | |
1236 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1237 | node.start, node.size); |
4f1959ee AS |
1238 | remove_mappable_node(&node); |
1239 | } else { | |
058d88c4 | 1240 | i915_vma_unpin(vma); |
4f1959ee | 1241 | } |
fe115628 | 1242 | out_unlock: |
9c870d03 | 1243 | intel_runtime_pm_put(i915); |
fe115628 | 1244 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1245 | return ret; |
673a394b EA |
1246 | } |
1247 | ||
3043c60c | 1248 | static int |
fe115628 | 1249 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1250 | char __user *user_data, |
1251 | bool page_do_bit17_swizzling, | |
1252 | bool needs_clflush_before, | |
1253 | bool needs_clflush_after) | |
673a394b | 1254 | { |
d174bd64 DV |
1255 | char *vaddr; |
1256 | int ret; | |
e5281ccd | 1257 | |
d174bd64 | 1258 | vaddr = kmap(page); |
e7e58eb5 | 1259 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1260 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1261 | page_do_bit17_swizzling); |
d174bd64 | 1262 | if (page_do_bit17_swizzling) |
fe115628 CW |
1263 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1264 | length); | |
d174bd64 | 1265 | else |
fe115628 | 1266 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1267 | if (needs_clflush_after) |
fe115628 | 1268 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1269 | page_do_bit17_swizzling); |
d174bd64 | 1270 | kunmap(page); |
40123c1f | 1271 | |
755d2218 | 1272 | return ret ? -EFAULT : 0; |
40123c1f EA |
1273 | } |
1274 | ||
fe115628 CW |
1275 | /* Per-page copy function for the shmem pwrite fastpath. |
1276 | * Flushes invalid cachelines before writing to the target if | |
1277 | * needs_clflush_before is set and flushes out any written cachelines after | |
1278 | * writing if needs_clflush is set. | |
1279 | */ | |
40123c1f | 1280 | static int |
fe115628 CW |
1281 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1282 | bool page_do_bit17_swizzling, | |
1283 | bool needs_clflush_before, | |
1284 | bool needs_clflush_after) | |
40123c1f | 1285 | { |
fe115628 CW |
1286 | int ret; |
1287 | ||
1288 | ret = -ENODEV; | |
1289 | if (!page_do_bit17_swizzling) { | |
1290 | char *vaddr = kmap_atomic(page); | |
1291 | ||
1292 | if (needs_clflush_before) | |
1293 | drm_clflush_virt_range(vaddr + offset, len); | |
1294 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1295 | if (needs_clflush_after) | |
1296 | drm_clflush_virt_range(vaddr + offset, len); | |
1297 | ||
1298 | kunmap_atomic(vaddr); | |
1299 | } | |
1300 | if (ret == 0) | |
1301 | return ret; | |
1302 | ||
1303 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1304 | page_do_bit17_swizzling, | |
1305 | needs_clflush_before, | |
1306 | needs_clflush_after); | |
1307 | } | |
1308 | ||
1309 | static int | |
1310 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1311 | const struct drm_i915_gem_pwrite *args) | |
1312 | { | |
1313 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1314 | void __user *user_data; | |
1315 | u64 remain; | |
1316 | unsigned int obj_do_bit17_swizzling; | |
1317 | unsigned int partial_cacheline_write; | |
43394c7d | 1318 | unsigned int needs_clflush; |
fe115628 CW |
1319 | unsigned int offset, idx; |
1320 | int ret; | |
40123c1f | 1321 | |
fe115628 | 1322 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1323 | if (ret) |
1324 | return ret; | |
1325 | ||
fe115628 CW |
1326 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1327 | mutex_unlock(&i915->drm.struct_mutex); | |
1328 | if (ret) | |
1329 | return ret; | |
673a394b | 1330 | |
fe115628 CW |
1331 | obj_do_bit17_swizzling = 0; |
1332 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1333 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1334 | |
fe115628 CW |
1335 | /* If we don't overwrite a cacheline completely we need to be |
1336 | * careful to have up-to-date data by first clflushing. Don't | |
1337 | * overcomplicate things and flush the entire patch. | |
1338 | */ | |
1339 | partial_cacheline_write = 0; | |
1340 | if (needs_clflush & CLFLUSH_BEFORE) | |
1341 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1342 | |
fe115628 CW |
1343 | user_data = u64_to_user_ptr(args->data_ptr); |
1344 | remain = args->size; | |
1345 | offset = offset_in_page(args->offset); | |
1346 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1347 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1348 | int length; | |
40123c1f | 1349 | |
fe115628 CW |
1350 | length = remain; |
1351 | if (offset + length > PAGE_SIZE) | |
1352 | length = PAGE_SIZE - offset; | |
755d2218 | 1353 | |
fe115628 CW |
1354 | ret = shmem_pwrite(page, offset, length, user_data, |
1355 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1356 | (offset | length) & partial_cacheline_write, | |
1357 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1358 | if (ret) |
fe115628 | 1359 | break; |
755d2218 | 1360 | |
fe115628 CW |
1361 | remain -= length; |
1362 | user_data += length; | |
1363 | offset = 0; | |
8c59967c | 1364 | } |
673a394b | 1365 | |
de152b62 | 1366 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 | 1367 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1368 | return ret; |
673a394b EA |
1369 | } |
1370 | ||
1371 | /** | |
1372 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1373 | * @dev: drm device |
1374 | * @data: ioctl data blob | |
1375 | * @file: drm file | |
673a394b EA |
1376 | * |
1377 | * On error, the contents of the buffer that were to be modified are undefined. | |
1378 | */ | |
1379 | int | |
1380 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1381 | struct drm_file *file) |
673a394b EA |
1382 | { |
1383 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1384 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1385 | int ret; |
1386 | ||
1387 | if (args->size == 0) | |
1388 | return 0; | |
1389 | ||
1390 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1391 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1392 | args->size)) |
1393 | return -EFAULT; | |
1394 | ||
03ac0642 | 1395 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1396 | if (!obj) |
1397 | return -ENOENT; | |
673a394b | 1398 | |
7dcd2499 | 1399 | /* Bounds check destination. */ |
05394f39 CW |
1400 | if (args->offset > obj->base.size || |
1401 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1402 | ret = -EINVAL; |
258a5ede | 1403 | goto err; |
ce9d419d CW |
1404 | } |
1405 | ||
db53a302 CW |
1406 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1407 | ||
e95433c7 CW |
1408 | ret = i915_gem_object_wait(obj, |
1409 | I915_WAIT_INTERRUPTIBLE | | |
1410 | I915_WAIT_ALL, | |
1411 | MAX_SCHEDULE_TIMEOUT, | |
1412 | to_rps_client(file)); | |
258a5ede CW |
1413 | if (ret) |
1414 | goto err; | |
1415 | ||
fe115628 | 1416 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1417 | if (ret) |
fe115628 | 1418 | goto err; |
258a5ede | 1419 | |
935aaa69 | 1420 | ret = -EFAULT; |
673a394b EA |
1421 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1422 | * it would end up going through the fenced access, and we'll get | |
1423 | * different detiling behavior between reading and writing. | |
1424 | * pread/pwrite currently are reading and writing from the CPU | |
1425 | * perspective, requiring manual detiling by the client. | |
1426 | */ | |
6eae0059 | 1427 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1428 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1429 | /* Note that the gtt paths might fail with non-page-backed user |
1430 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1431 | * textures). Fallback to the shmem path in that case. |
1432 | */ | |
fe115628 | 1433 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1434 | |
d1054ee4 | 1435 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1436 | if (obj->phys_handle) |
1437 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1438 | else |
fe115628 | 1439 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1440 | } |
5c0480f2 | 1441 | |
fe115628 | 1442 | i915_gem_object_unpin_pages(obj); |
258a5ede CW |
1443 | err: |
1444 | i915_gem_object_put_unlocked(obj); | |
1445 | return ret; | |
673a394b EA |
1446 | } |
1447 | ||
d243ad82 | 1448 | static inline enum fb_op_origin |
aeecc969 CW |
1449 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1450 | { | |
50349247 CW |
1451 | return (domain == I915_GEM_DOMAIN_GTT ? |
1452 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1453 | } |
1454 | ||
673a394b | 1455 | /** |
2ef7eeaa EA |
1456 | * Called when user space prepares to use an object with the CPU, either |
1457 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1458 | * @dev: drm device |
1459 | * @data: ioctl data blob | |
1460 | * @file: drm file | |
673a394b EA |
1461 | */ |
1462 | int | |
1463 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1464 | struct drm_file *file) |
673a394b EA |
1465 | { |
1466 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1467 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1468 | uint32_t read_domains = args->read_domains; |
1469 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1470 | int ret; |
1471 | ||
2ef7eeaa | 1472 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1473 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1474 | return -EINVAL; |
1475 | ||
1476 | /* Having something in the write domain implies it's in the read | |
1477 | * domain, and only that read domain. Enforce that in the request. | |
1478 | */ | |
1479 | if (write_domain != 0 && read_domains != write_domain) | |
1480 | return -EINVAL; | |
1481 | ||
03ac0642 | 1482 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1483 | if (!obj) |
1484 | return -ENOENT; | |
673a394b | 1485 | |
3236f57a CW |
1486 | /* Try to flush the object off the GPU without holding the lock. |
1487 | * We will repeat the flush holding the lock in the normal manner | |
1488 | * to catch cases where we are gazumped. | |
1489 | */ | |
e95433c7 CW |
1490 | ret = i915_gem_object_wait(obj, |
1491 | I915_WAIT_INTERRUPTIBLE | | |
1492 | (write_domain ? I915_WAIT_ALL : 0), | |
1493 | MAX_SCHEDULE_TIMEOUT, | |
1494 | to_rps_client(file)); | |
b8f9096d CW |
1495 | if (ret) |
1496 | goto err; | |
1497 | ||
1498 | ret = i915_mutex_lock_interruptible(dev); | |
3236f57a | 1499 | if (ret) |
b8f9096d | 1500 | goto err; |
3236f57a | 1501 | |
43566ded | 1502 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1503 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1504 | else |
e47c68e9 | 1505 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1506 | |
031b698a | 1507 | if (write_domain != 0) |
aeecc969 | 1508 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1509 | |
f8c417cd | 1510 | i915_gem_object_put(obj); |
673a394b EA |
1511 | mutex_unlock(&dev->struct_mutex); |
1512 | return ret; | |
b8f9096d CW |
1513 | |
1514 | err: | |
1515 | i915_gem_object_put_unlocked(obj); | |
1516 | return ret; | |
673a394b EA |
1517 | } |
1518 | ||
1519 | /** | |
1520 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1521 | * @dev: drm device |
1522 | * @data: ioctl data blob | |
1523 | * @file: drm file | |
673a394b EA |
1524 | */ |
1525 | int | |
1526 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1527 | struct drm_file *file) |
673a394b EA |
1528 | { |
1529 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1530 | struct drm_i915_gem_object *obj; |
c21724cc | 1531 | int err = 0; |
1d7cfea1 | 1532 | |
03ac0642 | 1533 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1534 | if (!obj) |
1535 | return -ENOENT; | |
673a394b | 1536 | |
673a394b | 1537 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1538 | if (READ_ONCE(obj->pin_display)) { |
1539 | err = i915_mutex_lock_interruptible(dev); | |
1540 | if (!err) { | |
1541 | i915_gem_object_flush_cpu_write_domain(obj); | |
1542 | mutex_unlock(&dev->struct_mutex); | |
1543 | } | |
1544 | } | |
e47c68e9 | 1545 | |
c21724cc CW |
1546 | i915_gem_object_put_unlocked(obj); |
1547 | return err; | |
673a394b EA |
1548 | } |
1549 | ||
1550 | /** | |
14bb2c11 TU |
1551 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1552 | * it is mapped to. | |
1553 | * @dev: drm device | |
1554 | * @data: ioctl data blob | |
1555 | * @file: drm file | |
673a394b EA |
1556 | * |
1557 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1558 | * imply a ref on the object itself. | |
34367381 DV |
1559 | * |
1560 | * IMPORTANT: | |
1561 | * | |
1562 | * DRM driver writers who look a this function as an example for how to do GEM | |
1563 | * mmap support, please don't implement mmap support like here. The modern way | |
1564 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1565 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1566 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1567 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1568 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1569 | */ |
1570 | int | |
1571 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1572 | struct drm_file *file) |
673a394b EA |
1573 | { |
1574 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1575 | struct drm_i915_gem_object *obj; |
673a394b EA |
1576 | unsigned long addr; |
1577 | ||
1816f923 AG |
1578 | if (args->flags & ~(I915_MMAP_WC)) |
1579 | return -EINVAL; | |
1580 | ||
568a58e5 | 1581 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1582 | return -ENODEV; |
1583 | ||
03ac0642 CW |
1584 | obj = i915_gem_object_lookup(file, args->handle); |
1585 | if (!obj) | |
bf79cb91 | 1586 | return -ENOENT; |
673a394b | 1587 | |
1286ff73 DV |
1588 | /* prime objects have no backing filp to GEM mmap |
1589 | * pages from. | |
1590 | */ | |
03ac0642 | 1591 | if (!obj->base.filp) { |
34911fd3 | 1592 | i915_gem_object_put_unlocked(obj); |
1286ff73 DV |
1593 | return -EINVAL; |
1594 | } | |
1595 | ||
03ac0642 | 1596 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1597 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1598 | args->offset); | |
1816f923 AG |
1599 | if (args->flags & I915_MMAP_WC) { |
1600 | struct mm_struct *mm = current->mm; | |
1601 | struct vm_area_struct *vma; | |
1602 | ||
80a89a5e | 1603 | if (down_write_killable(&mm->mmap_sem)) { |
34911fd3 | 1604 | i915_gem_object_put_unlocked(obj); |
80a89a5e MH |
1605 | return -EINTR; |
1606 | } | |
1816f923 AG |
1607 | vma = find_vma(mm, addr); |
1608 | if (vma) | |
1609 | vma->vm_page_prot = | |
1610 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1611 | else | |
1612 | addr = -ENOMEM; | |
1613 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1614 | |
1615 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1616 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1617 | } |
34911fd3 | 1618 | i915_gem_object_put_unlocked(obj); |
673a394b EA |
1619 | if (IS_ERR((void *)addr)) |
1620 | return addr; | |
1621 | ||
1622 | args->addr_ptr = (uint64_t) addr; | |
1623 | ||
1624 | return 0; | |
1625 | } | |
1626 | ||
03af84fe CW |
1627 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1628 | { | |
1629 | u64 size; | |
1630 | ||
1631 | size = i915_gem_object_get_stride(obj); | |
1632 | size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8; | |
1633 | ||
1634 | return size >> PAGE_SHIFT; | |
1635 | } | |
1636 | ||
4cc69075 CW |
1637 | /** |
1638 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1639 | * | |
1640 | * A history of the GTT mmap interface: | |
1641 | * | |
1642 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1643 | * aligned and suitable for fencing, and still fit into the available | |
1644 | * mappable space left by the pinned display objects. A classic problem | |
1645 | * we called the page-fault-of-doom where we would ping-pong between | |
1646 | * two objects that could not fit inside the GTT and so the memcpy | |
1647 | * would page one object in at the expense of the other between every | |
1648 | * single byte. | |
1649 | * | |
1650 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1651 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1652 | * object is too large for the available space (or simply too large | |
1653 | * for the mappable aperture!), a view is created instead and faulted | |
1654 | * into userspace. (This view is aligned and sized appropriately for | |
1655 | * fenced access.) | |
1656 | * | |
1657 | * Restrictions: | |
1658 | * | |
1659 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1660 | * hangs on some architectures, corruption on others. An attempt to service | |
1661 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1662 | * | |
1663 | * * the object must be able to fit into RAM (physical memory, though no | |
1664 | * limited to the mappable aperture). | |
1665 | * | |
1666 | * | |
1667 | * Caveats: | |
1668 | * | |
1669 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1670 | * all data to system memory. Subsequent access will not be synchronized. | |
1671 | * | |
1672 | * * all mappings are revoked on runtime device suspend. | |
1673 | * | |
1674 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1675 | * (older machines require fence register for display and blitter access | |
1676 | * as well). Contention of the fence registers will cause the previous users | |
1677 | * to be unmapped and any new access will generate new page faults. | |
1678 | * | |
1679 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1680 | * rather than the expected SIGSEGV. | |
1681 | */ | |
1682 | int i915_gem_mmap_gtt_version(void) | |
1683 | { | |
1684 | return 1; | |
1685 | } | |
1686 | ||
de151cf6 JB |
1687 | /** |
1688 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1689 | * @area: CPU VMA in question |
d9072a3e | 1690 | * @vmf: fault info |
de151cf6 JB |
1691 | * |
1692 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1693 | * from userspace. The fault handler takes care of binding the object to | |
1694 | * the GTT (if needed), allocating and programming a fence register (again, | |
1695 | * only if needed based on whether the old reg is still valid or the object | |
1696 | * is tiled) and inserting a new PTE into the faulting process. | |
1697 | * | |
1698 | * Note that the faulting process may involve evicting existing objects | |
1699 | * from the GTT and/or fence registers to make room. So performance may | |
1700 | * suffer if the GTT working set is large or there are few fence registers | |
1701 | * left. | |
4cc69075 CW |
1702 | * |
1703 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1704 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1705 | */ |
058d88c4 | 1706 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1707 | { |
03af84fe | 1708 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1709 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1710 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1711 | struct drm_i915_private *dev_priv = to_i915(dev); |
1712 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1713 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1714 | struct i915_vma *vma; |
de151cf6 | 1715 | pgoff_t page_offset; |
82118877 | 1716 | unsigned int flags; |
b8f9096d | 1717 | int ret; |
f65c9168 | 1718 | |
de151cf6 | 1719 | /* We don't use vmf->pgoff since that has the fake offset */ |
058d88c4 | 1720 | page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >> |
de151cf6 JB |
1721 | PAGE_SHIFT; |
1722 | ||
db53a302 CW |
1723 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1724 | ||
6e4930f6 | 1725 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1726 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1727 | * repeat the flush holding the lock in the normal manner to catch cases |
1728 | * where we are gazumped. | |
1729 | */ | |
e95433c7 CW |
1730 | ret = i915_gem_object_wait(obj, |
1731 | I915_WAIT_INTERRUPTIBLE, | |
1732 | MAX_SCHEDULE_TIMEOUT, | |
1733 | NULL); | |
6e4930f6 | 1734 | if (ret) |
b8f9096d CW |
1735 | goto err; |
1736 | ||
1737 | intel_runtime_pm_get(dev_priv); | |
1738 | ||
1739 | ret = i915_mutex_lock_interruptible(dev); | |
1740 | if (ret) | |
1741 | goto err_rpm; | |
6e4930f6 | 1742 | |
eb119bd6 CW |
1743 | /* Access to snoopable pages through the GTT is incoherent. */ |
1744 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1745 | ret = -EFAULT; |
b8f9096d | 1746 | goto err_unlock; |
eb119bd6 CW |
1747 | } |
1748 | ||
82118877 CW |
1749 | /* If the object is smaller than a couple of partial vma, it is |
1750 | * not worth only creating a single partial vma - we may as well | |
1751 | * clear enough space for the full object. | |
1752 | */ | |
1753 | flags = PIN_MAPPABLE; | |
1754 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1755 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1756 | ||
a61007a8 | 1757 | /* Now pin it into the GTT as needed */ |
82118877 | 1758 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 CW |
1759 | if (IS_ERR(vma)) { |
1760 | struct i915_ggtt_view view; | |
03af84fe CW |
1761 | unsigned int chunk_size; |
1762 | ||
a61007a8 | 1763 | /* Use a partial view if it is bigger than available space */ |
03af84fe CW |
1764 | chunk_size = MIN_CHUNK_PAGES; |
1765 | if (i915_gem_object_is_tiled(obj)) | |
1766 | chunk_size = max(chunk_size, tile_row_pages(obj)); | |
e7ded2d7 | 1767 | |
c5ad54cf JL |
1768 | memset(&view, 0, sizeof(view)); |
1769 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1770 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1771 | view.params.partial.size = | |
a61007a8 | 1772 | min_t(unsigned int, chunk_size, |
908b1232 | 1773 | vma_pages(area) - view.params.partial.offset); |
c5ad54cf | 1774 | |
aa136d9d CW |
1775 | /* If the partial covers the entire object, just create a |
1776 | * normal VMA. | |
1777 | */ | |
1778 | if (chunk_size >= obj->base.size >> PAGE_SHIFT) | |
1779 | view.type = I915_GGTT_VIEW_NORMAL; | |
1780 | ||
50349247 CW |
1781 | /* Userspace is now writing through an untracked VMA, abandon |
1782 | * all hope that the hardware is able to track future writes. | |
1783 | */ | |
1784 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1785 | ||
a61007a8 CW |
1786 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1787 | } | |
058d88c4 CW |
1788 | if (IS_ERR(vma)) { |
1789 | ret = PTR_ERR(vma); | |
b8f9096d | 1790 | goto err_unlock; |
058d88c4 | 1791 | } |
4a684a41 | 1792 | |
c9839303 CW |
1793 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1794 | if (ret) | |
b8f9096d | 1795 | goto err_unpin; |
74898d7e | 1796 | |
49ef5294 | 1797 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1798 | if (ret) |
b8f9096d | 1799 | goto err_unpin; |
7d1c4804 | 1800 | |
275f039d | 1801 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1802 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1803 | if (list_empty(&obj->userfault_link)) |
1804 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1805 | |
b90b91d8 | 1806 | /* Finally, remap it using the new GTT offset */ |
c58305af CW |
1807 | ret = remap_io_mapping(area, |
1808 | area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT), | |
1809 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, | |
1810 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1811 | &ggtt->mappable); | |
a61007a8 | 1812 | |
b8f9096d | 1813 | err_unpin: |
058d88c4 | 1814 | __i915_vma_unpin(vma); |
b8f9096d | 1815 | err_unlock: |
de151cf6 | 1816 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1817 | err_rpm: |
1818 | intel_runtime_pm_put(dev_priv); | |
1819 | err: | |
de151cf6 | 1820 | switch (ret) { |
d9bc7e9f | 1821 | case -EIO: |
2232f031 DV |
1822 | /* |
1823 | * We eat errors when the gpu is terminally wedged to avoid | |
1824 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1825 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1826 | * and so needs to be reported. | |
1827 | */ | |
1828 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1829 | ret = VM_FAULT_SIGBUS; |
1830 | break; | |
1831 | } | |
045e769a | 1832 | case -EAGAIN: |
571c608d DV |
1833 | /* |
1834 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1835 | * handler to reset everything when re-faulting in | |
1836 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1837 | */ |
c715089f CW |
1838 | case 0: |
1839 | case -ERESTARTSYS: | |
bed636ab | 1840 | case -EINTR: |
e79e0fe3 DR |
1841 | case -EBUSY: |
1842 | /* | |
1843 | * EBUSY is ok: this just means that another thread | |
1844 | * already did the job. | |
1845 | */ | |
f65c9168 PZ |
1846 | ret = VM_FAULT_NOPAGE; |
1847 | break; | |
de151cf6 | 1848 | case -ENOMEM: |
f65c9168 PZ |
1849 | ret = VM_FAULT_OOM; |
1850 | break; | |
a7c2e1aa | 1851 | case -ENOSPC: |
45d67817 | 1852 | case -EFAULT: |
f65c9168 PZ |
1853 | ret = VM_FAULT_SIGBUS; |
1854 | break; | |
de151cf6 | 1855 | default: |
a7c2e1aa | 1856 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1857 | ret = VM_FAULT_SIGBUS; |
1858 | break; | |
de151cf6 | 1859 | } |
f65c9168 | 1860 | return ret; |
de151cf6 JB |
1861 | } |
1862 | ||
901782b2 CW |
1863 | /** |
1864 | * i915_gem_release_mmap - remove physical page mappings | |
1865 | * @obj: obj in question | |
1866 | * | |
af901ca1 | 1867 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1868 | * relinquish ownership of the pages back to the system. |
1869 | * | |
1870 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1871 | * object through the GTT and then lose the fence register due to | |
1872 | * resource pressure. Similarly if the object has been moved out of the | |
1873 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1874 | * mapping will then trigger a page fault on the next user access, allowing | |
1875 | * fixup by i915_gem_fault(). | |
1876 | */ | |
d05ca301 | 1877 | void |
05394f39 | 1878 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1879 | { |
275f039d | 1880 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 1881 | |
349f2ccf CW |
1882 | /* Serialisation between user GTT access and our code depends upon |
1883 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1884 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
1885 | * |
1886 | * Note that RPM complicates somewhat by adding an additional | |
1887 | * requirement that operations to the GGTT be made holding the RPM | |
1888 | * wakeref. | |
349f2ccf | 1889 | */ |
275f039d | 1890 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 1891 | intel_runtime_pm_get(i915); |
349f2ccf | 1892 | |
3594a3e2 | 1893 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 1894 | goto out; |
901782b2 | 1895 | |
3594a3e2 | 1896 | list_del_init(&obj->userfault_link); |
6796cb16 DH |
1897 | drm_vma_node_unmap(&obj->base.vma_node, |
1898 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1899 | |
1900 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1901 | * memory transactions from userspace before we return. The TLB | |
1902 | * flushing implied above by changing the PTE above *should* be | |
1903 | * sufficient, an extra barrier here just provides us with a bit | |
1904 | * of paranoid documentation about our requirement to serialise | |
1905 | * memory writes before touching registers / GSM. | |
1906 | */ | |
1907 | wmb(); | |
9c870d03 CW |
1908 | |
1909 | out: | |
1910 | intel_runtime_pm_put(i915); | |
901782b2 CW |
1911 | } |
1912 | ||
7c108fd8 | 1913 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 1914 | { |
3594a3e2 | 1915 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 1916 | int i; |
eedd10f4 | 1917 | |
3594a3e2 CW |
1918 | /* |
1919 | * Only called during RPM suspend. All users of the userfault_list | |
1920 | * must be holding an RPM wakeref to ensure that this can not | |
1921 | * run concurrently with themselves (and use the struct_mutex for | |
1922 | * protection between themselves). | |
1923 | */ | |
275f039d | 1924 | |
3594a3e2 CW |
1925 | list_for_each_entry_safe(obj, on, |
1926 | &dev_priv->mm.userfault_list, userfault_link) { | |
1927 | list_del_init(&obj->userfault_link); | |
275f039d CW |
1928 | drm_vma_node_unmap(&obj->base.vma_node, |
1929 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 1930 | } |
7c108fd8 CW |
1931 | |
1932 | /* The fence will be lost when the device powers down. If any were | |
1933 | * in use by hardware (i.e. they are pinned), we should not be powering | |
1934 | * down! All other fences will be reacquired by the user upon waking. | |
1935 | */ | |
1936 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
1937 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
1938 | ||
1939 | if (WARN_ON(reg->pin_count)) | |
1940 | continue; | |
1941 | ||
1942 | if (!reg->vma) | |
1943 | continue; | |
1944 | ||
1945 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
1946 | reg->dirty = true; | |
1947 | } | |
eedd10f4 CW |
1948 | } |
1949 | ||
ad1a7d20 CW |
1950 | /** |
1951 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 1952 | * @dev_priv: i915 device |
ad1a7d20 CW |
1953 | * @size: object size |
1954 | * @tiling_mode: tiling mode | |
1955 | * | |
1956 | * Return the required global GTT size for an object, taking into account | |
1957 | * potential fence register mapping. | |
1958 | */ | |
a9f1481f CW |
1959 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
1960 | u64 size, int tiling_mode) | |
92b88aeb | 1961 | { |
ad1a7d20 | 1962 | u64 ggtt_size; |
92b88aeb | 1963 | |
ad1a7d20 CW |
1964 | GEM_BUG_ON(size == 0); |
1965 | ||
a9f1481f | 1966 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
1967 | tiling_mode == I915_TILING_NONE) |
1968 | return size; | |
92b88aeb CW |
1969 | |
1970 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 1971 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 1972 | ggtt_size = 1024*1024; |
92b88aeb | 1973 | else |
ad1a7d20 | 1974 | ggtt_size = 512*1024; |
92b88aeb | 1975 | |
ad1a7d20 CW |
1976 | while (ggtt_size < size) |
1977 | ggtt_size <<= 1; | |
92b88aeb | 1978 | |
ad1a7d20 | 1979 | return ggtt_size; |
92b88aeb CW |
1980 | } |
1981 | ||
de151cf6 | 1982 | /** |
ad1a7d20 | 1983 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 1984 | * @dev_priv: i915 device |
14bb2c11 TU |
1985 | * @size: object size |
1986 | * @tiling_mode: tiling mode | |
ad1a7d20 | 1987 | * @fenced: is fenced alignment required or not |
de151cf6 | 1988 | * |
ad1a7d20 | 1989 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 1990 | * potential fence register mapping. |
de151cf6 | 1991 | */ |
a9f1481f | 1992 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 1993 | int tiling_mode, bool fenced) |
de151cf6 | 1994 | { |
ad1a7d20 CW |
1995 | GEM_BUG_ON(size == 0); |
1996 | ||
de151cf6 JB |
1997 | /* |
1998 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1999 | * if a fence register is needed for the object. | |
2000 | */ | |
a9f1481f | 2001 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 2002 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2003 | return 4096; |
2004 | ||
a00b10c3 CW |
2005 | /* |
2006 | * Previous chips need to be aligned to the size of the smallest | |
2007 | * fence register that can contain the object. | |
2008 | */ | |
a9f1481f | 2009 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
2010 | } |
2011 | ||
d8cb5086 CW |
2012 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2013 | { | |
fac5e23e | 2014 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2015 | int err; |
da494d7c | 2016 | |
f3f6184c CW |
2017 | err = drm_gem_create_mmap_offset(&obj->base); |
2018 | if (!err) | |
2019 | return 0; | |
d8cb5086 | 2020 | |
f3f6184c CW |
2021 | /* We can idle the GPU locklessly to flush stale objects, but in order |
2022 | * to claim that space for ourselves, we need to take the big | |
2023 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 2024 | */ |
ea746f36 | 2025 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); |
f3f6184c CW |
2026 | if (err) |
2027 | return err; | |
2028 | ||
2029 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
2030 | if (!err) { | |
2031 | i915_gem_retire_requests(dev_priv); | |
2032 | err = drm_gem_create_mmap_offset(&obj->base); | |
2033 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2034 | } | |
da494d7c | 2035 | |
f3f6184c | 2036 | return err; |
d8cb5086 CW |
2037 | } |
2038 | ||
2039 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2040 | { | |
d8cb5086 CW |
2041 | drm_gem_free_mmap_offset(&obj->base); |
2042 | } | |
2043 | ||
da6b51d0 | 2044 | int |
ff72145b DA |
2045 | i915_gem_mmap_gtt(struct drm_file *file, |
2046 | struct drm_device *dev, | |
da6b51d0 | 2047 | uint32_t handle, |
ff72145b | 2048 | uint64_t *offset) |
de151cf6 | 2049 | { |
05394f39 | 2050 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2051 | int ret; |
2052 | ||
03ac0642 | 2053 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2054 | if (!obj) |
2055 | return -ENOENT; | |
ab18282d | 2056 | |
d8cb5086 | 2057 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2058 | if (ret == 0) |
2059 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2060 | |
f3f6184c | 2061 | i915_gem_object_put_unlocked(obj); |
1d7cfea1 | 2062 | return ret; |
de151cf6 JB |
2063 | } |
2064 | ||
ff72145b DA |
2065 | /** |
2066 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2067 | * @dev: DRM device | |
2068 | * @data: GTT mapping ioctl data | |
2069 | * @file: GEM object info | |
2070 | * | |
2071 | * Simply returns the fake offset to userspace so it can mmap it. | |
2072 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2073 | * up so we can get faults in the handler above. | |
2074 | * | |
2075 | * The fault handler will take care of binding the object into the GTT | |
2076 | * (since it may have been evicted to make room for something), allocating | |
2077 | * a fence register, and mapping the appropriate aperture address into | |
2078 | * userspace. | |
2079 | */ | |
2080 | int | |
2081 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2082 | struct drm_file *file) | |
2083 | { | |
2084 | struct drm_i915_gem_mmap_gtt *args = data; | |
2085 | ||
da6b51d0 | 2086 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2087 | } |
2088 | ||
225067ee DV |
2089 | /* Immediately discard the backing storage */ |
2090 | static void | |
2091 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2092 | { |
4d6294bf | 2093 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2094 | |
4d6294bf CW |
2095 | if (obj->base.filp == NULL) |
2096 | return; | |
e5281ccd | 2097 | |
225067ee DV |
2098 | /* Our goal here is to return as much of the memory as |
2099 | * is possible back to the system as we are called from OOM. | |
2100 | * To do this we must instruct the shmfs to drop all of its | |
2101 | * backing pages, *now*. | |
2102 | */ | |
5537252b | 2103 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2104 | obj->mm.madv = __I915_MADV_PURGED; |
225067ee | 2105 | } |
e5281ccd | 2106 | |
5537252b | 2107 | /* Try to discard unwanted pages */ |
03ac84f1 | 2108 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2109 | { |
5537252b CW |
2110 | struct address_space *mapping; |
2111 | ||
1233e2db CW |
2112 | lockdep_assert_held(&obj->mm.lock); |
2113 | GEM_BUG_ON(obj->mm.pages); | |
2114 | ||
a4f5ea64 | 2115 | switch (obj->mm.madv) { |
5537252b CW |
2116 | case I915_MADV_DONTNEED: |
2117 | i915_gem_object_truncate(obj); | |
2118 | case __I915_MADV_PURGED: | |
2119 | return; | |
2120 | } | |
2121 | ||
2122 | if (obj->base.filp == NULL) | |
2123 | return; | |
2124 | ||
93c76a3d | 2125 | mapping = obj->base.filp->f_mapping, |
5537252b | 2126 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2127 | } |
2128 | ||
5cdf5881 | 2129 | static void |
03ac84f1 CW |
2130 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2131 | struct sg_table *pages) | |
673a394b | 2132 | { |
85d1225e DG |
2133 | struct sgt_iter sgt_iter; |
2134 | struct page *page; | |
1286ff73 | 2135 | |
03ac84f1 | 2136 | __i915_gem_object_release_shmem(obj); |
673a394b | 2137 | |
03ac84f1 | 2138 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2139 | |
6dacfd2f | 2140 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2141 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2142 | |
03ac84f1 | 2143 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2144 | if (obj->mm.dirty) |
9da3da66 | 2145 | set_page_dirty(page); |
3ef94daa | 2146 | |
a4f5ea64 | 2147 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2148 | mark_page_accessed(page); |
3ef94daa | 2149 | |
09cbfeaf | 2150 | put_page(page); |
3ef94daa | 2151 | } |
a4f5ea64 | 2152 | obj->mm.dirty = false; |
673a394b | 2153 | |
03ac84f1 CW |
2154 | sg_free_table(pages); |
2155 | kfree(pages); | |
37e680a1 | 2156 | } |
6c085a72 | 2157 | |
96d77634 CW |
2158 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2159 | { | |
2160 | struct radix_tree_iter iter; | |
2161 | void **slot; | |
2162 | ||
a4f5ea64 CW |
2163 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2164 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2165 | } |
2166 | ||
03ac84f1 | 2167 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2168 | { |
03ac84f1 | 2169 | struct sg_table *pages; |
37e680a1 | 2170 | |
a4f5ea64 | 2171 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2172 | return; |
a5570178 | 2173 | |
15717de2 | 2174 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2175 | if (!READ_ONCE(obj->mm.pages)) |
2176 | return; | |
2177 | ||
2178 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
2179 | mutex_lock_nested(&obj->mm.lock, SINGLE_DEPTH_NESTING); | |
2180 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) | |
2181 | goto unlock; | |
3e123027 | 2182 | |
a2165e31 CW |
2183 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2184 | * array, hence protect them from being reaped by removing them from gtt | |
2185 | * lists early. */ | |
03ac84f1 CW |
2186 | pages = fetch_and_zero(&obj->mm.pages); |
2187 | GEM_BUG_ON(!pages); | |
a2165e31 | 2188 | |
a4f5ea64 | 2189 | if (obj->mm.mapping) { |
4b30cb23 CW |
2190 | void *ptr; |
2191 | ||
a4f5ea64 | 2192 | ptr = ptr_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2193 | if (is_vmalloc_addr(ptr)) |
2194 | vunmap(ptr); | |
fb8621d3 | 2195 | else |
4b30cb23 CW |
2196 | kunmap(kmap_to_page(ptr)); |
2197 | ||
a4f5ea64 | 2198 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2199 | } |
2200 | ||
96d77634 CW |
2201 | __i915_gem_object_reset_page_iter(obj); |
2202 | ||
03ac84f1 | 2203 | obj->ops->put_pages(obj, pages); |
1233e2db CW |
2204 | unlock: |
2205 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2206 | } |
2207 | ||
4ff340f0 | 2208 | static unsigned int swiotlb_max_size(void) |
871dfbd6 CW |
2209 | { |
2210 | #if IS_ENABLED(CONFIG_SWIOTLB) | |
2211 | return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE); | |
2212 | #else | |
2213 | return 0; | |
2214 | #endif | |
2215 | } | |
2216 | ||
03ac84f1 | 2217 | static struct sg_table * |
6c085a72 | 2218 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2219 | { |
fac5e23e | 2220 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2221 | int page_count, i; |
2222 | struct address_space *mapping; | |
9da3da66 CW |
2223 | struct sg_table *st; |
2224 | struct scatterlist *sg; | |
85d1225e | 2225 | struct sgt_iter sgt_iter; |
e5281ccd | 2226 | struct page *page; |
90797e6d | 2227 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2228 | unsigned int max_segment; |
e2273302 | 2229 | int ret; |
6c085a72 | 2230 | gfp_t gfp; |
e5281ccd | 2231 | |
6c085a72 CW |
2232 | /* Assert that the object is not currently in any GPU domain. As it |
2233 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2234 | * a GPU cache | |
2235 | */ | |
03ac84f1 CW |
2236 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2237 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2238 | |
871dfbd6 CW |
2239 | max_segment = swiotlb_max_size(); |
2240 | if (!max_segment) | |
4ff340f0 | 2241 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2242 | |
9da3da66 CW |
2243 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2244 | if (st == NULL) | |
03ac84f1 | 2245 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2246 | |
05394f39 | 2247 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2248 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2249 | kfree(st); |
03ac84f1 | 2250 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2251 | } |
e5281ccd | 2252 | |
9da3da66 CW |
2253 | /* Get the list of pages out of our struct file. They'll be pinned |
2254 | * at this point until we release them. | |
2255 | * | |
2256 | * Fail silently without starting the shrinker | |
2257 | */ | |
93c76a3d | 2258 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2259 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2260 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2261 | sg = st->sgl; |
2262 | st->nents = 0; | |
2263 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2264 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2265 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2266 | i915_gem_shrink(dev_priv, |
2267 | page_count, | |
2268 | I915_SHRINK_BOUND | | |
2269 | I915_SHRINK_UNBOUND | | |
2270 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2271 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2272 | } | |
2273 | if (IS_ERR(page)) { | |
2274 | /* We've tried hard to allocate the memory by reaping | |
2275 | * our own buffer, now let the real VM do its job and | |
2276 | * go down in flames if truly OOM. | |
2277 | */ | |
f461d1be | 2278 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2279 | if (IS_ERR(page)) { |
2280 | ret = PTR_ERR(page); | |
6c085a72 | 2281 | goto err_pages; |
e2273302 | 2282 | } |
6c085a72 | 2283 | } |
871dfbd6 CW |
2284 | if (!i || |
2285 | sg->length >= max_segment || | |
2286 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2287 | if (i) |
2288 | sg = sg_next(sg); | |
2289 | st->nents++; | |
2290 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2291 | } else { | |
2292 | sg->length += PAGE_SIZE; | |
2293 | } | |
2294 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2295 | |
2296 | /* Check that the i965g/gm workaround works. */ | |
2297 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2298 | } |
871dfbd6 | 2299 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2300 | sg_mark_end(sg); |
74ce6b6c | 2301 | |
03ac84f1 | 2302 | ret = i915_gem_gtt_prepare_pages(obj, st); |
e2273302 ID |
2303 | if (ret) |
2304 | goto err_pages; | |
2305 | ||
6dacfd2f | 2306 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2307 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2308 | |
3e510a8e | 2309 | if (i915_gem_object_is_tiled(obj) && |
656bfa3a | 2310 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
a4f5ea64 | 2311 | __i915_gem_object_pin_pages(obj); |
656bfa3a | 2312 | |
03ac84f1 | 2313 | return st; |
e5281ccd CW |
2314 | |
2315 | err_pages: | |
90797e6d | 2316 | sg_mark_end(sg); |
85d1225e DG |
2317 | for_each_sgt_page(page, sgt_iter, st) |
2318 | put_page(page); | |
9da3da66 CW |
2319 | sg_free_table(st); |
2320 | kfree(st); | |
0820baf3 CW |
2321 | |
2322 | /* shmemfs first checks if there is enough memory to allocate the page | |
2323 | * and reports ENOSPC should there be insufficient, along with the usual | |
2324 | * ENOMEM for a genuine allocation failure. | |
2325 | * | |
2326 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2327 | * space and so want to translate the error from shmemfs back to our | |
2328 | * usual understanding of ENOMEM. | |
2329 | */ | |
e2273302 ID |
2330 | if (ret == -ENOSPC) |
2331 | ret = -ENOMEM; | |
2332 | ||
03ac84f1 CW |
2333 | return ERR_PTR(ret); |
2334 | } | |
2335 | ||
2336 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2337 | struct sg_table *pages) | |
2338 | { | |
1233e2db | 2339 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2340 | |
2341 | obj->mm.get_page.sg_pos = pages->sgl; | |
2342 | obj->mm.get_page.sg_idx = 0; | |
2343 | ||
2344 | obj->mm.pages = pages; | |
2345 | } | |
2346 | ||
2347 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2348 | { | |
2349 | struct sg_table *pages; | |
2350 | ||
2351 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { | |
2352 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2353 | return -EFAULT; | |
2354 | } | |
2355 | ||
2356 | pages = obj->ops->get_pages(obj); | |
2357 | if (unlikely(IS_ERR(pages))) | |
2358 | return PTR_ERR(pages); | |
2359 | ||
2360 | __i915_gem_object_set_pages(obj, pages); | |
2361 | return 0; | |
673a394b EA |
2362 | } |
2363 | ||
37e680a1 | 2364 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2365 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2366 | * multiple times before they are released by a single call to |
1233e2db | 2367 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2368 | * either as a result of memory pressure (reaping pages under the shrinker) |
2369 | * or as the object is itself released. | |
2370 | */ | |
a4f5ea64 | 2371 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2372 | { |
03ac84f1 | 2373 | int err; |
37e680a1 | 2374 | |
1233e2db CW |
2375 | err = mutex_lock_interruptible(&obj->mm.lock); |
2376 | if (err) | |
2377 | return err; | |
4c7d62c6 | 2378 | |
1233e2db CW |
2379 | if (likely(obj->mm.pages)) { |
2380 | __i915_gem_object_pin_pages(obj); | |
2381 | goto unlock; | |
2382 | } | |
2383 | ||
2384 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); | |
37e680a1 | 2385 | |
03ac84f1 | 2386 | err = ____i915_gem_object_get_pages(obj); |
1233e2db CW |
2387 | if (!err) |
2388 | atomic_set_release(&obj->mm.pages_pin_count, 1); | |
ee286370 | 2389 | |
1233e2db CW |
2390 | unlock: |
2391 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2392 | return err; |
673a394b EA |
2393 | } |
2394 | ||
dd6034c6 | 2395 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2396 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2397 | enum i915_map_type type) | |
dd6034c6 DG |
2398 | { |
2399 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2400 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2401 | struct sgt_iter sgt_iter; |
2402 | struct page *page; | |
b338fa47 DG |
2403 | struct page *stack_pages[32]; |
2404 | struct page **pages = stack_pages; | |
dd6034c6 | 2405 | unsigned long i = 0; |
d31d7cb1 | 2406 | pgprot_t pgprot; |
dd6034c6 DG |
2407 | void *addr; |
2408 | ||
2409 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2410 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2411 | return kmap(sg_page(sgt->sgl)); |
2412 | ||
b338fa47 DG |
2413 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2414 | /* Too big for stack -- allocate temporary array instead */ | |
2415 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2416 | if (!pages) | |
2417 | return NULL; | |
2418 | } | |
dd6034c6 | 2419 | |
85d1225e DG |
2420 | for_each_sgt_page(page, sgt_iter, sgt) |
2421 | pages[i++] = page; | |
dd6034c6 DG |
2422 | |
2423 | /* Check that we have the expected number of pages */ | |
2424 | GEM_BUG_ON(i != n_pages); | |
2425 | ||
d31d7cb1 CW |
2426 | switch (type) { |
2427 | case I915_MAP_WB: | |
2428 | pgprot = PAGE_KERNEL; | |
2429 | break; | |
2430 | case I915_MAP_WC: | |
2431 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2432 | break; | |
2433 | } | |
2434 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2435 | |
b338fa47 DG |
2436 | if (pages != stack_pages) |
2437 | drm_free_large(pages); | |
dd6034c6 DG |
2438 | |
2439 | return addr; | |
2440 | } | |
2441 | ||
2442 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2443 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2444 | enum i915_map_type type) | |
0a798eb9 | 2445 | { |
d31d7cb1 CW |
2446 | enum i915_map_type has_type; |
2447 | bool pinned; | |
2448 | void *ptr; | |
0a798eb9 CW |
2449 | int ret; |
2450 | ||
d31d7cb1 | 2451 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2452 | |
1233e2db | 2453 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2454 | if (ret) |
2455 | return ERR_PTR(ret); | |
2456 | ||
1233e2db CW |
2457 | pinned = true; |
2458 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
2459 | ret = ____i915_gem_object_get_pages(obj); | |
2460 | if (ret) | |
2461 | goto err_unlock; | |
2462 | ||
2463 | GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count)); | |
2464 | atomic_set_release(&obj->mm.pages_pin_count, 1); | |
2465 | pinned = false; | |
2466 | } | |
2467 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2468 | |
a4f5ea64 | 2469 | ptr = ptr_unpack_bits(obj->mm.mapping, has_type); |
d31d7cb1 CW |
2470 | if (ptr && has_type != type) { |
2471 | if (pinned) { | |
2472 | ret = -EBUSY; | |
1233e2db | 2473 | goto err_unpin; |
0a798eb9 | 2474 | } |
d31d7cb1 CW |
2475 | |
2476 | if (is_vmalloc_addr(ptr)) | |
2477 | vunmap(ptr); | |
2478 | else | |
2479 | kunmap(kmap_to_page(ptr)); | |
2480 | ||
a4f5ea64 | 2481 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2482 | } |
2483 | ||
d31d7cb1 CW |
2484 | if (!ptr) { |
2485 | ptr = i915_gem_object_map(obj, type); | |
2486 | if (!ptr) { | |
2487 | ret = -ENOMEM; | |
1233e2db | 2488 | goto err_unpin; |
d31d7cb1 CW |
2489 | } |
2490 | ||
a4f5ea64 | 2491 | obj->mm.mapping = ptr_pack_bits(ptr, type); |
d31d7cb1 CW |
2492 | } |
2493 | ||
1233e2db CW |
2494 | out_unlock: |
2495 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2496 | return ptr; |
2497 | ||
1233e2db CW |
2498 | err_unpin: |
2499 | atomic_dec(&obj->mm.pages_pin_count); | |
2500 | err_unlock: | |
2501 | ptr = ERR_PTR(ret); | |
2502 | goto out_unlock; | |
0a798eb9 CW |
2503 | } |
2504 | ||
b4716185 | 2505 | static void |
fa545cbf CW |
2506 | i915_gem_object_retire__write(struct i915_gem_active *active, |
2507 | struct drm_i915_gem_request *request) | |
e2d05a8b | 2508 | { |
fa545cbf CW |
2509 | struct drm_i915_gem_object *obj = |
2510 | container_of(active, struct drm_i915_gem_object, last_write); | |
b4716185 | 2511 | |
de152b62 | 2512 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2513 | } |
2514 | ||
caea7476 | 2515 | static void |
fa545cbf CW |
2516 | i915_gem_object_retire__read(struct i915_gem_active *active, |
2517 | struct drm_i915_gem_request *request) | |
ce44b0ea | 2518 | { |
fa545cbf CW |
2519 | int idx = request->engine->id; |
2520 | struct drm_i915_gem_object *obj = | |
2521 | container_of(active, struct drm_i915_gem_object, last_read[idx]); | |
ce44b0ea | 2522 | |
573adb39 | 2523 | GEM_BUG_ON(!i915_gem_object_has_active_engine(obj, idx)); |
b4716185 | 2524 | |
573adb39 CW |
2525 | i915_gem_object_clear_active(obj, idx); |
2526 | if (i915_gem_object_is_active(obj)) | |
b4716185 | 2527 | return; |
caea7476 | 2528 | |
6c246959 CW |
2529 | /* Bump our place on the bound list to keep it roughly in LRU order |
2530 | * so that we don't steal from recently used but inactive objects | |
2531 | * (unless we are forced to ofc!) | |
2532 | */ | |
b0decaf7 CW |
2533 | if (obj->bind_count) |
2534 | list_move_tail(&obj->global_list, | |
2535 | &request->i915->mm.bound_list); | |
caea7476 | 2536 | |
f8a7fde4 CW |
2537 | if (i915_gem_object_has_active_reference(obj)) { |
2538 | i915_gem_object_clear_active_reference(obj); | |
2539 | i915_gem_object_put(obj); | |
2540 | } | |
c8725f3d CW |
2541 | } |
2542 | ||
7b4d3a16 | 2543 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2544 | { |
44e2c070 | 2545 | unsigned long elapsed; |
be62acb4 | 2546 | |
44e2c070 | 2547 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2548 | return true; |
2549 | ||
7b4d3a16 | 2550 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2551 | if (ctx->hang_stats.ban_period_seconds && |
2552 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2553 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2554 | return true; | |
be62acb4 MK |
2555 | } |
2556 | ||
2557 | return false; | |
2558 | } | |
2559 | ||
7b4d3a16 | 2560 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2561 | const bool guilty) |
aa60c664 | 2562 | { |
7b4d3a16 | 2563 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2564 | |
2565 | if (guilty) { | |
7b4d3a16 | 2566 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2567 | hs->batch_active++; |
2568 | hs->guilty_ts = get_seconds(); | |
2569 | } else { | |
2570 | hs->batch_pending++; | |
aa60c664 MK |
2571 | } |
2572 | } | |
2573 | ||
8d9fc7fd | 2574 | struct drm_i915_gem_request * |
0bc40be8 | 2575 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2576 | { |
4db080f9 CW |
2577 | struct drm_i915_gem_request *request; |
2578 | ||
f69a02c9 CW |
2579 | /* We are called by the error capture and reset at a random |
2580 | * point in time. In particular, note that neither is crucially | |
2581 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2582 | * assume that no more writes can happen (we waited long enough for | |
2583 | * all writes that were in transaction to be flushed) - adding an | |
2584 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2585 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2586 | */ | |
efdf7c06 | 2587 | list_for_each_entry(request, &engine->request_list, link) { |
f69a02c9 | 2588 | if (i915_gem_request_completed(request)) |
4db080f9 | 2589 | continue; |
aa60c664 | 2590 | |
5590af3e CW |
2591 | if (!i915_sw_fence_done(&request->submit)) |
2592 | break; | |
2593 | ||
b6b0fac0 | 2594 | return request; |
4db080f9 | 2595 | } |
b6b0fac0 MK |
2596 | |
2597 | return NULL; | |
2598 | } | |
2599 | ||
821ed7df CW |
2600 | static void reset_request(struct drm_i915_gem_request *request) |
2601 | { | |
2602 | void *vaddr = request->ring->vaddr; | |
2603 | u32 head; | |
2604 | ||
2605 | /* As this request likely depends on state from the lost | |
2606 | * context, clear out all the user operations leaving the | |
2607 | * breadcrumb at the end (so we get the fence notifications). | |
2608 | */ | |
2609 | head = request->head; | |
2610 | if (request->postfix < head) { | |
2611 | memset(vaddr + head, 0, request->ring->size - head); | |
2612 | head = 0; | |
2613 | } | |
2614 | memset(vaddr + head, 0, request->postfix - head); | |
2615 | } | |
2616 | ||
2617 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) | |
b6b0fac0 MK |
2618 | { |
2619 | struct drm_i915_gem_request *request; | |
821ed7df | 2620 | struct i915_gem_context *incomplete_ctx; |
b6b0fac0 MK |
2621 | bool ring_hung; |
2622 | ||
821ed7df CW |
2623 | if (engine->irq_seqno_barrier) |
2624 | engine->irq_seqno_barrier(engine); | |
2625 | ||
0bc40be8 | 2626 | request = i915_gem_find_active_request(engine); |
821ed7df | 2627 | if (!request) |
b6b0fac0 MK |
2628 | return; |
2629 | ||
0bc40be8 | 2630 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
77c60701 CW |
2631 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) |
2632 | ring_hung = false; | |
2633 | ||
7b4d3a16 | 2634 | i915_set_reset_status(request->ctx, ring_hung); |
821ed7df CW |
2635 | if (!ring_hung) |
2636 | return; | |
2637 | ||
2638 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
2639 | engine->name, request->fence.seqno); | |
2640 | ||
2641 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2642 | engine->reset_hw(engine, request); | |
2643 | ||
2644 | /* Users of the default context do not rely on logical state | |
2645 | * preserved between batches. They have to emit full state on | |
2646 | * every batch and so it is safe to execute queued requests following | |
2647 | * the hang. | |
2648 | * | |
2649 | * Other contexts preserve state, now corrupt. We want to skip all | |
2650 | * queued requests that reference the corrupt context. | |
2651 | */ | |
2652 | incomplete_ctx = request->ctx; | |
2653 | if (i915_gem_context_is_default(incomplete_ctx)) | |
2654 | return; | |
2655 | ||
efdf7c06 | 2656 | list_for_each_entry_continue(request, &engine->request_list, link) |
821ed7df CW |
2657 | if (request->ctx == incomplete_ctx) |
2658 | reset_request(request); | |
4db080f9 | 2659 | } |
aa60c664 | 2660 | |
821ed7df | 2661 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2662 | { |
821ed7df | 2663 | struct intel_engine_cs *engine; |
3b3f1650 | 2664 | enum intel_engine_id id; |
608c1a52 | 2665 | |
4c7d62c6 CW |
2666 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2667 | ||
821ed7df CW |
2668 | i915_gem_retire_requests(dev_priv); |
2669 | ||
3b3f1650 | 2670 | for_each_engine(engine, dev_priv, id) |
821ed7df CW |
2671 | i915_gem_reset_engine(engine); |
2672 | ||
2673 | i915_gem_restore_fences(&dev_priv->drm); | |
f2a91d1a CW |
2674 | |
2675 | if (dev_priv->gt.awake) { | |
2676 | intel_sanitize_gt_powersave(dev_priv); | |
2677 | intel_enable_gt_powersave(dev_priv); | |
2678 | if (INTEL_GEN(dev_priv) >= 6) | |
2679 | gen6_rps_busy(dev_priv); | |
2680 | } | |
821ed7df CW |
2681 | } |
2682 | ||
2683 | static void nop_submit_request(struct drm_i915_gem_request *request) | |
2684 | { | |
2685 | } | |
2686 | ||
2687 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) | |
2688 | { | |
2689 | engine->submit_request = nop_submit_request; | |
70c2a24d | 2690 | |
c4b0930b CW |
2691 | /* Mark all pending requests as complete so that any concurrent |
2692 | * (lockless) lookup doesn't try and wait upon the request as we | |
2693 | * reset it. | |
2694 | */ | |
87b723a1 | 2695 | intel_engine_init_seqno(engine, engine->last_submitted_seqno); |
c4b0930b | 2696 | |
dcb4c12a OM |
2697 | /* |
2698 | * Clear the execlists queue up before freeing the requests, as those | |
2699 | * are the ones that keep the context and ringbuffer backing objects | |
2700 | * pinned in place. | |
2701 | */ | |
dcb4c12a | 2702 | |
7de1691a | 2703 | if (i915.enable_execlists) { |
70c2a24d CW |
2704 | spin_lock(&engine->execlist_lock); |
2705 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2706 | i915_gem_request_put(engine->execlist_port[0].request); | |
2707 | i915_gem_request_put(engine->execlist_port[1].request); | |
2708 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
2709 | spin_unlock(&engine->execlist_lock); | |
dcb4c12a OM |
2710 | } |
2711 | ||
b913b33c | 2712 | engine->i915->gt.active_engines &= ~intel_engine_flag(engine); |
673a394b EA |
2713 | } |
2714 | ||
821ed7df | 2715 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) |
673a394b | 2716 | { |
e2f80391 | 2717 | struct intel_engine_cs *engine; |
3b3f1650 | 2718 | enum intel_engine_id id; |
673a394b | 2719 | |
821ed7df CW |
2720 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2721 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2722 | |
821ed7df | 2723 | i915_gem_context_lost(dev_priv); |
3b3f1650 | 2724 | for_each_engine(engine, dev_priv, id) |
821ed7df | 2725 | i915_gem_cleanup_engine(engine); |
b913b33c | 2726 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2727 | |
821ed7df | 2728 | i915_gem_retire_requests(dev_priv); |
673a394b EA |
2729 | } |
2730 | ||
75ef9da2 | 2731 | static void |
673a394b EA |
2732 | i915_gem_retire_work_handler(struct work_struct *work) |
2733 | { | |
b29c19b6 | 2734 | struct drm_i915_private *dev_priv = |
67d97da3 | 2735 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2736 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2737 | |
891b48cf | 2738 | /* Come back later if the device is busy... */ |
b29c19b6 | 2739 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2740 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2741 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2742 | } |
67d97da3 CW |
2743 | |
2744 | /* Keep the retire handler running until we are finally idle. | |
2745 | * We do not need to do this test under locking as in the worst-case | |
2746 | * we queue the retire worker once too often. | |
2747 | */ | |
c9615613 CW |
2748 | if (READ_ONCE(dev_priv->gt.awake)) { |
2749 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2750 | queue_delayed_work(dev_priv->wq, |
2751 | &dev_priv->gt.retire_work, | |
bcb45086 | 2752 | round_jiffies_up_relative(HZ)); |
c9615613 | 2753 | } |
b29c19b6 | 2754 | } |
0a58705b | 2755 | |
b29c19b6 CW |
2756 | static void |
2757 | i915_gem_idle_work_handler(struct work_struct *work) | |
2758 | { | |
2759 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2760 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2761 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2762 | struct intel_engine_cs *engine; |
3b3f1650 | 2763 | enum intel_engine_id id; |
67d97da3 CW |
2764 | bool rearm_hangcheck; |
2765 | ||
2766 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2767 | return; | |
2768 | ||
2769 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
2770 | return; | |
2771 | ||
2772 | rearm_hangcheck = | |
2773 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2774 | ||
2775 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2776 | /* Currently busy, come back later */ | |
2777 | mod_delayed_work(dev_priv->wq, | |
2778 | &dev_priv->gt.idle_work, | |
2779 | msecs_to_jiffies(50)); | |
2780 | goto out_rearm; | |
2781 | } | |
2782 | ||
2783 | if (dev_priv->gt.active_engines) | |
2784 | goto out_unlock; | |
b29c19b6 | 2785 | |
3b3f1650 | 2786 | for_each_engine(engine, dev_priv, id) |
67d97da3 | 2787 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2788 | |
67d97da3 CW |
2789 | GEM_BUG_ON(!dev_priv->gt.awake); |
2790 | dev_priv->gt.awake = false; | |
2791 | rearm_hangcheck = false; | |
30ecad77 | 2792 | |
67d97da3 CW |
2793 | if (INTEL_GEN(dev_priv) >= 6) |
2794 | gen6_rps_idle(dev_priv); | |
2795 | intel_runtime_pm_put(dev_priv); | |
2796 | out_unlock: | |
2797 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2798 | |
67d97da3 CW |
2799 | out_rearm: |
2800 | if (rearm_hangcheck) { | |
2801 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2802 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2803 | } |
673a394b EA |
2804 | } |
2805 | ||
b1f788c6 CW |
2806 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2807 | { | |
2808 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2809 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2810 | struct i915_vma *vma, *vn; | |
2811 | ||
2812 | mutex_lock(&obj->base.dev->struct_mutex); | |
2813 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2814 | if (vma->vm->file == fpriv) | |
2815 | i915_vma_close(vma); | |
f8a7fde4 CW |
2816 | |
2817 | if (i915_gem_object_is_active(obj) && | |
2818 | !i915_gem_object_has_active_reference(obj)) { | |
2819 | i915_gem_object_set_active_reference(obj); | |
2820 | i915_gem_object_get(obj); | |
2821 | } | |
b1f788c6 CW |
2822 | mutex_unlock(&obj->base.dev->struct_mutex); |
2823 | } | |
2824 | ||
e95433c7 CW |
2825 | static unsigned long to_wait_timeout(s64 timeout_ns) |
2826 | { | |
2827 | if (timeout_ns < 0) | |
2828 | return MAX_SCHEDULE_TIMEOUT; | |
2829 | ||
2830 | if (timeout_ns == 0) | |
2831 | return 0; | |
2832 | ||
2833 | return nsecs_to_jiffies_timeout(timeout_ns); | |
2834 | } | |
2835 | ||
23ba4fd0 BW |
2836 | /** |
2837 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2838 | * @dev: drm device pointer |
2839 | * @data: ioctl data blob | |
2840 | * @file: drm file pointer | |
23ba4fd0 BW |
2841 | * |
2842 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2843 | * the timeout parameter. | |
2844 | * -ETIME: object is still busy after timeout | |
2845 | * -ERESTARTSYS: signal interrupted the wait | |
2846 | * -ENONENT: object doesn't exist | |
2847 | * Also possible, but rare: | |
2848 | * -EAGAIN: GPU wedged | |
2849 | * -ENOMEM: damn | |
2850 | * -ENODEV: Internal IRQ fail | |
2851 | * -E?: The add request failed | |
2852 | * | |
2853 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2854 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2855 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2856 | * without holding struct_mutex the object may become re-busied before this | |
2857 | * function completes. A similar but shorter * race condition exists in the busy | |
2858 | * ioctl | |
2859 | */ | |
2860 | int | |
2861 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2862 | { | |
2863 | struct drm_i915_gem_wait *args = data; | |
2864 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
2865 | ktime_t start; |
2866 | long ret; | |
23ba4fd0 | 2867 | |
11b5d511 DV |
2868 | if (args->flags != 0) |
2869 | return -EINVAL; | |
2870 | ||
03ac0642 | 2871 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 2872 | if (!obj) |
23ba4fd0 | 2873 | return -ENOENT; |
23ba4fd0 | 2874 | |
e95433c7 CW |
2875 | start = ktime_get(); |
2876 | ||
2877 | ret = i915_gem_object_wait(obj, | |
2878 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
2879 | to_wait_timeout(args->timeout_ns), | |
2880 | to_rps_client(file)); | |
2881 | ||
2882 | if (args->timeout_ns > 0) { | |
2883 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
2884 | if (args->timeout_ns < 0) | |
2885 | args->timeout_ns = 0; | |
b4716185 CW |
2886 | } |
2887 | ||
033d549b | 2888 | i915_gem_object_put_unlocked(obj); |
ff865885 | 2889 | return ret; |
23ba4fd0 BW |
2890 | } |
2891 | ||
8ef8561f CW |
2892 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2893 | { | |
20dfbde4 | 2894 | GEM_BUG_ON(i915_vma_is_pinned(vma)); |
8ef8561f CW |
2895 | |
2896 | if (vma->iomap == NULL) | |
2897 | return; | |
2898 | ||
2899 | io_mapping_unmap(vma->iomap); | |
2900 | vma->iomap = NULL; | |
2901 | } | |
2902 | ||
df0e9a28 | 2903 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2904 | { |
07fe0b12 | 2905 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 | 2906 | unsigned long active; |
43e28f09 | 2907 | int ret; |
673a394b | 2908 | |
4c7d62c6 CW |
2909 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
2910 | ||
b0decaf7 CW |
2911 | /* First wait upon any activity as retiring the request may |
2912 | * have side-effects such as unpinning or even unbinding this vma. | |
2913 | */ | |
2914 | active = i915_vma_get_active(vma); | |
df0e9a28 | 2915 | if (active) { |
b0decaf7 CW |
2916 | int idx; |
2917 | ||
b1f788c6 CW |
2918 | /* When a closed VMA is retired, it is unbound - eek. |
2919 | * In order to prevent it from being recursively closed, | |
2920 | * take a pin on the vma so that the second unbind is | |
2921 | * aborted. | |
2922 | */ | |
20dfbde4 | 2923 | __i915_vma_pin(vma); |
b1f788c6 | 2924 | |
b0decaf7 CW |
2925 | for_each_active(active, idx) { |
2926 | ret = i915_gem_active_retire(&vma->last_read[idx], | |
2927 | &vma->vm->dev->struct_mutex); | |
2928 | if (ret) | |
b1f788c6 | 2929 | break; |
b0decaf7 CW |
2930 | } |
2931 | ||
20dfbde4 | 2932 | __i915_vma_unpin(vma); |
b1f788c6 CW |
2933 | if (ret) |
2934 | return ret; | |
2935 | ||
b0decaf7 CW |
2936 | GEM_BUG_ON(i915_vma_is_active(vma)); |
2937 | } | |
2938 | ||
20dfbde4 | 2939 | if (i915_vma_is_pinned(vma)) |
b0decaf7 CW |
2940 | return -EBUSY; |
2941 | ||
b1f788c6 CW |
2942 | if (!drm_mm_node_allocated(&vma->node)) |
2943 | goto destroy; | |
433544bd | 2944 | |
15717de2 | 2945 | GEM_BUG_ON(obj->bind_count == 0); |
a4f5ea64 | 2946 | GEM_BUG_ON(!obj->mm.pages); |
c4670ad0 | 2947 | |
05a20d09 | 2948 | if (i915_vma_is_map_and_fenceable(vma)) { |
8b1bc9b4 | 2949 | /* release the fence reg _after_ flushing */ |
49ef5294 | 2950 | ret = i915_vma_put_fence(vma); |
8b1bc9b4 DV |
2951 | if (ret) |
2952 | return ret; | |
8ef8561f | 2953 | |
cd3127d6 CW |
2954 | /* Force a pagefault for domain tracking on next user access */ |
2955 | i915_gem_release_mmap(obj); | |
2956 | ||
8ef8561f | 2957 | __i915_vma_iounmap(vma); |
05a20d09 | 2958 | vma->flags &= ~I915_VMA_CAN_FENCE; |
8b1bc9b4 | 2959 | } |
96b47b65 | 2960 | |
50e046b6 CW |
2961 | if (likely(!vma->vm->closed)) { |
2962 | trace_i915_vma_unbind(vma); | |
2963 | vma->vm->unbind_vma(vma); | |
2964 | } | |
3272db53 | 2965 | vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
6f65e29a | 2966 | |
50e046b6 CW |
2967 | drm_mm_remove_node(&vma->node); |
2968 | list_move_tail(&vma->vm_link, &vma->vm->unbound_list); | |
2969 | ||
a4f5ea64 | 2970 | if (vma->pages != obj->mm.pages) { |
05a20d09 CW |
2971 | GEM_BUG_ON(!vma->pages); |
2972 | sg_free_table(vma->pages); | |
2973 | kfree(vma->pages); | |
fe14d5f4 | 2974 | } |
247177dd | 2975 | vma->pages = NULL; |
673a394b | 2976 | |
2f633156 | 2977 | /* Since the unbound list is global, only move to that list if |
b93dab6e | 2978 | * no more VMAs exist. */ |
15717de2 CW |
2979 | if (--obj->bind_count == 0) |
2980 | list_move_tail(&obj->global_list, | |
2981 | &to_i915(obj->base.dev)->mm.unbound_list); | |
673a394b | 2982 | |
70903c3b CW |
2983 | /* And finally now the object is completely decoupled from this vma, |
2984 | * we can drop its hold on the backing storage and allow it to be | |
2985 | * reaped by the shrinker. | |
2986 | */ | |
2987 | i915_gem_object_unpin_pages(obj); | |
2988 | ||
b1f788c6 | 2989 | destroy: |
3272db53 | 2990 | if (unlikely(i915_vma_is_closed(vma))) |
b1f788c6 CW |
2991 | i915_vma_destroy(vma); |
2992 | ||
88241785 | 2993 | return 0; |
54cf91dc CW |
2994 | } |
2995 | ||
dcff85c8 | 2996 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
ea746f36 | 2997 | unsigned int flags) |
4df2faf4 | 2998 | { |
e2f80391 | 2999 | struct intel_engine_cs *engine; |
3b3f1650 | 3000 | enum intel_engine_id id; |
b4ac5afc | 3001 | int ret; |
4df2faf4 | 3002 | |
3b3f1650 | 3003 | for_each_engine(engine, dev_priv, id) { |
62e63007 CW |
3004 | if (engine->last_context == NULL) |
3005 | continue; | |
3006 | ||
ea746f36 | 3007 | ret = intel_engine_idle(engine, flags); |
1ec14ad3 CW |
3008 | if (ret) |
3009 | return ret; | |
3010 | } | |
4df2faf4 | 3011 | |
8a1a49f9 | 3012 | return 0; |
4df2faf4 DV |
3013 | } |
3014 | ||
4144f9b5 | 3015 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3016 | unsigned long cache_level) |
3017 | { | |
4144f9b5 | 3018 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3019 | struct drm_mm_node *other; |
3020 | ||
4144f9b5 CW |
3021 | /* |
3022 | * On some machines we have to be careful when putting differing types | |
3023 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3024 | * domains and dying. During vm initialisation, we decide whether or not | |
3025 | * these constraints apply and set the drm_mm.color_adjust | |
3026 | * appropriately. | |
42d6ab48 | 3027 | */ |
4144f9b5 | 3028 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3029 | return true; |
3030 | ||
c6cfb325 | 3031 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3032 | return true; |
3033 | ||
3034 | if (list_empty(>t_space->node_list)) | |
3035 | return true; | |
3036 | ||
3037 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3038 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3039 | return false; | |
3040 | ||
3041 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3042 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3043 | return false; | |
3044 | ||
3045 | return true; | |
3046 | } | |
3047 | ||
673a394b | 3048 | /** |
59bfa124 CW |
3049 | * i915_vma_insert - finds a slot for the vma in its address space |
3050 | * @vma: the vma | |
91b2db6f | 3051 | * @size: requested size in bytes (can be larger than the VMA) |
59bfa124 | 3052 | * @alignment: required alignment |
14bb2c11 | 3053 | * @flags: mask of PIN_* flags to use |
59bfa124 CW |
3054 | * |
3055 | * First we try to allocate some free space that meets the requirements for | |
3056 | * the VMA. Failiing that, if the flags permit, it will evict an old VMA, | |
3057 | * preferrably the oldest idle entry to make room for the new VMA. | |
3058 | * | |
3059 | * Returns: | |
3060 | * 0 on success, negative error code otherwise. | |
673a394b | 3061 | */ |
59bfa124 CW |
3062 | static int |
3063 | i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 3064 | { |
59bfa124 CW |
3065 | struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); |
3066 | struct drm_i915_gem_object *obj = vma->obj; | |
de180033 | 3067 | u64 start, end; |
07f73f69 | 3068 | int ret; |
673a394b | 3069 | |
3272db53 | 3070 | GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); |
59bfa124 | 3071 | GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); |
de180033 CW |
3072 | |
3073 | size = max(size, vma->size); | |
3074 | if (flags & PIN_MAPPABLE) | |
3e510a8e CW |
3075 | size = i915_gem_get_ggtt_size(dev_priv, size, |
3076 | i915_gem_object_get_tiling(obj)); | |
de180033 | 3077 | |
d8923dcf CW |
3078 | alignment = max(max(alignment, vma->display_alignment), |
3079 | i915_gem_get_ggtt_alignment(dev_priv, size, | |
3080 | i915_gem_object_get_tiling(obj), | |
3081 | flags & PIN_MAPPABLE)); | |
a00b10c3 | 3082 | |
101b506a | 3083 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
de180033 CW |
3084 | |
3085 | end = vma->vm->total; | |
101b506a | 3086 | if (flags & PIN_MAPPABLE) |
91b2db6f | 3087 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 3088 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3089 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3090 | |
91e6711e JL |
3091 | /* If binding the object/GGTT view requires more space than the entire |
3092 | * aperture has, reject it early before evicting everything in a vain | |
3093 | * attempt to find space. | |
654fc607 | 3094 | */ |
91e6711e | 3095 | if (size > end) { |
de180033 | 3096 | DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", |
91b2db6f | 3097 | size, obj->base.size, |
1ec9e26d | 3098 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3099 | end); |
59bfa124 | 3100 | return -E2BIG; |
654fc607 CW |
3101 | } |
3102 | ||
a4f5ea64 | 3103 | ret = i915_gem_object_pin_pages(obj); |
6c085a72 | 3104 | if (ret) |
59bfa124 | 3105 | return ret; |
6c085a72 | 3106 | |
506a8e87 | 3107 | if (flags & PIN_OFFSET_FIXED) { |
59bfa124 | 3108 | u64 offset = flags & PIN_OFFSET_MASK; |
de180033 | 3109 | if (offset & (alignment - 1) || offset > end - size) { |
506a8e87 | 3110 | ret = -EINVAL; |
de180033 | 3111 | goto err_unpin; |
506a8e87 | 3112 | } |
de180033 | 3113 | |
506a8e87 CW |
3114 | vma->node.start = offset; |
3115 | vma->node.size = size; | |
3116 | vma->node.color = obj->cache_level; | |
de180033 | 3117 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
506a8e87 CW |
3118 | if (ret) { |
3119 | ret = i915_gem_evict_for_vma(vma); | |
3120 | if (ret == 0) | |
de180033 CW |
3121 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
3122 | if (ret) | |
3123 | goto err_unpin; | |
506a8e87 | 3124 | } |
101b506a | 3125 | } else { |
de180033 CW |
3126 | u32 search_flag, alloc_flag; |
3127 | ||
506a8e87 CW |
3128 | if (flags & PIN_HIGH) { |
3129 | search_flag = DRM_MM_SEARCH_BELOW; | |
3130 | alloc_flag = DRM_MM_CREATE_TOP; | |
3131 | } else { | |
3132 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3133 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3134 | } | |
101b506a | 3135 | |
954c4691 CW |
3136 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, |
3137 | * so we know that we always have a minimum alignment of 4096. | |
3138 | * The drm_mm range manager is optimised to return results | |
3139 | * with zero alignment, so where possible use the optimal | |
3140 | * path. | |
3141 | */ | |
3142 | if (alignment <= 4096) | |
3143 | alignment = 0; | |
3144 | ||
0a9ae0d7 | 3145 | search_free: |
de180033 CW |
3146 | ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, |
3147 | &vma->node, | |
506a8e87 CW |
3148 | size, alignment, |
3149 | obj->cache_level, | |
3150 | start, end, | |
3151 | search_flag, | |
3152 | alloc_flag); | |
3153 | if (ret) { | |
de180033 | 3154 | ret = i915_gem_evict_something(vma->vm, size, alignment, |
506a8e87 CW |
3155 | obj->cache_level, |
3156 | start, end, | |
3157 | flags); | |
3158 | if (ret == 0) | |
3159 | goto search_free; | |
9731129c | 3160 | |
de180033 | 3161 | goto err_unpin; |
506a8e87 | 3162 | } |
ad16d2ed CW |
3163 | |
3164 | GEM_BUG_ON(vma->node.start < start); | |
3165 | GEM_BUG_ON(vma->node.start + vma->node.size > end); | |
673a394b | 3166 | } |
37508589 | 3167 | GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); |
673a394b | 3168 | |
35c20a60 | 3169 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
de180033 | 3170 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
15717de2 | 3171 | obj->bind_count++; |
bf1a1092 | 3172 | |
59bfa124 | 3173 | return 0; |
2f633156 | 3174 | |
bc6bc15b | 3175 | err_unpin: |
2f633156 | 3176 | i915_gem_object_unpin_pages(obj); |
59bfa124 | 3177 | return ret; |
673a394b EA |
3178 | } |
3179 | ||
000433b6 | 3180 | bool |
2c22569b CW |
3181 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3182 | bool force) | |
673a394b | 3183 | { |
673a394b EA |
3184 | /* If we don't have a page list set up, then we're not pinned |
3185 | * to GPU, and we can ignore the cache flush because it'll happen | |
3186 | * again at bind time. | |
3187 | */ | |
a4f5ea64 | 3188 | if (!obj->mm.pages) |
000433b6 | 3189 | return false; |
673a394b | 3190 | |
769ce464 ID |
3191 | /* |
3192 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3193 | * marked as wc by the system, or the system is cache-coherent. | |
3194 | */ | |
6a2c4232 | 3195 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3196 | return false; |
769ce464 | 3197 | |
9c23f7fc CW |
3198 | /* If the GPU is snooping the contents of the CPU cache, |
3199 | * we do not need to manually clear the CPU cache lines. However, | |
3200 | * the caches are only snooped when the render cache is | |
3201 | * flushed/invalidated. As we always have to emit invalidations | |
3202 | * and flushes when moving into and out of the RENDER domain, correct | |
3203 | * snooping behaviour occurs naturally as the result of our domain | |
3204 | * tracking. | |
3205 | */ | |
0f71979a CW |
3206 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3207 | obj->cache_dirty = true; | |
000433b6 | 3208 | return false; |
0f71979a | 3209 | } |
9c23f7fc | 3210 | |
1c5d22f7 | 3211 | trace_i915_gem_object_clflush(obj); |
a4f5ea64 | 3212 | drm_clflush_sg(obj->mm.pages); |
0f71979a | 3213 | obj->cache_dirty = false; |
000433b6 CW |
3214 | |
3215 | return true; | |
e47c68e9 EA |
3216 | } |
3217 | ||
3218 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3219 | static void | |
05394f39 | 3220 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3221 | { |
3b5724d7 | 3222 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3223 | |
05394f39 | 3224 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3225 | return; |
3226 | ||
63256ec5 | 3227 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3228 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3229 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3230 | * |
3231 | * However, we do have to enforce the order so that all writes through | |
3232 | * the GTT land before any writes to the device, such as updates to | |
3233 | * the GATT itself. | |
3b5724d7 CW |
3234 | * |
3235 | * We also have to wait a bit for the writes to land from the GTT. | |
3236 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3237 | * timing. This issue has only been observed when switching quickly | |
3238 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3239 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3240 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3241 | */ |
63256ec5 | 3242 | wmb(); |
3b5724d7 | 3243 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3b3f1650 | 3244 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); |
63256ec5 | 3245 | |
d243ad82 | 3246 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3247 | |
b0dc465f | 3248 | obj->base.write_domain = 0; |
1c5d22f7 | 3249 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3250 | obj->base.read_domains, |
b0dc465f | 3251 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3252 | } |
3253 | ||
3254 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3255 | static void | |
e62b59e4 | 3256 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3257 | { |
05394f39 | 3258 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3259 | return; |
3260 | ||
e62b59e4 | 3261 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3262 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3263 | |
de152b62 | 3264 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3265 | |
b0dc465f | 3266 | obj->base.write_domain = 0; |
1c5d22f7 | 3267 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3268 | obj->base.read_domains, |
b0dc465f | 3269 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3270 | } |
3271 | ||
383d5823 CW |
3272 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
3273 | { | |
3274 | struct i915_vma *vma; | |
3275 | ||
3276 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
3277 | if (!i915_vma_is_ggtt(vma)) | |
3278 | continue; | |
3279 | ||
3280 | if (i915_vma_is_active(vma)) | |
3281 | continue; | |
3282 | ||
3283 | if (!drm_mm_node_allocated(&vma->node)) | |
3284 | continue; | |
3285 | ||
3286 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3287 | } | |
3288 | } | |
3289 | ||
2ef7eeaa EA |
3290 | /** |
3291 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3292 | * @obj: object to act on |
3293 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3294 | * |
3295 | * This function returns when the move is complete, including waiting on | |
3296 | * flushes to occur. | |
3297 | */ | |
79e53945 | 3298 | int |
2021746e | 3299 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3300 | { |
1c5d22f7 | 3301 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3302 | int ret; |
2ef7eeaa | 3303 | |
e95433c7 | 3304 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3305 | |
e95433c7 CW |
3306 | ret = i915_gem_object_wait(obj, |
3307 | I915_WAIT_INTERRUPTIBLE | | |
3308 | I915_WAIT_LOCKED | | |
3309 | (write ? I915_WAIT_ALL : 0), | |
3310 | MAX_SCHEDULE_TIMEOUT, | |
3311 | NULL); | |
88241785 CW |
3312 | if (ret) |
3313 | return ret; | |
3314 | ||
c13d87ea CW |
3315 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3316 | return 0; | |
3317 | ||
43566ded CW |
3318 | /* Flush and acquire obj->pages so that we are coherent through |
3319 | * direct access in memory with previous cached writes through | |
3320 | * shmemfs and that our cache domain tracking remains valid. | |
3321 | * For example, if the obj->filp was moved to swap without us | |
3322 | * being notified and releasing the pages, we would mistakenly | |
3323 | * continue to assume that the obj remained out of the CPU cached | |
3324 | * domain. | |
3325 | */ | |
a4f5ea64 | 3326 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3327 | if (ret) |
3328 | return ret; | |
3329 | ||
e62b59e4 | 3330 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3331 | |
d0a57789 CW |
3332 | /* Serialise direct access to this object with the barriers for |
3333 | * coherent writes from the GPU, by effectively invalidating the | |
3334 | * GTT domain upon first access. | |
3335 | */ | |
3336 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3337 | mb(); | |
3338 | ||
05394f39 CW |
3339 | old_write_domain = obj->base.write_domain; |
3340 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3341 | |
e47c68e9 EA |
3342 | /* It should now be out of any other write domains, and we can update |
3343 | * the domain values for our changes. | |
3344 | */ | |
05394f39 CW |
3345 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3346 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3347 | if (write) { |
05394f39 CW |
3348 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3349 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3350 | obj->mm.dirty = true; |
2ef7eeaa EA |
3351 | } |
3352 | ||
1c5d22f7 CW |
3353 | trace_i915_gem_object_change_domain(obj, |
3354 | old_read_domains, | |
3355 | old_write_domain); | |
3356 | ||
8325a09d | 3357 | /* And bump the LRU for this access */ |
383d5823 | 3358 | i915_gem_object_bump_inactive_ggtt(obj); |
a4f5ea64 | 3359 | i915_gem_object_unpin_pages(obj); |
8325a09d | 3360 | |
e47c68e9 EA |
3361 | return 0; |
3362 | } | |
3363 | ||
ef55f92a CW |
3364 | /** |
3365 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3366 | * @obj: object to act on |
3367 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3368 | * |
3369 | * After this function returns, the object will be in the new cache-level | |
3370 | * across all GTT and the contents of the backing storage will be coherent, | |
3371 | * with respect to the new cache-level. In order to keep the backing storage | |
3372 | * coherent for all users, we only allow a single cache level to be set | |
3373 | * globally on the object and prevent it from being changed whilst the | |
3374 | * hardware is reading from the object. That is if the object is currently | |
3375 | * on the scanout it will be set to uncached (or equivalent display | |
3376 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3377 | * that all direct access to the scanout remains coherent. | |
3378 | */ | |
e4ffd173 CW |
3379 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3380 | enum i915_cache_level cache_level) | |
3381 | { | |
aa653a68 | 3382 | struct i915_vma *vma; |
ed75a55b | 3383 | int ret = 0; |
e4ffd173 | 3384 | |
4c7d62c6 CW |
3385 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3386 | ||
e4ffd173 | 3387 | if (obj->cache_level == cache_level) |
ed75a55b | 3388 | goto out; |
e4ffd173 | 3389 | |
ef55f92a CW |
3390 | /* Inspect the list of currently bound VMA and unbind any that would |
3391 | * be invalid given the new cache-level. This is principally to | |
3392 | * catch the issue of the CS prefetch crossing page boundaries and | |
3393 | * reading an invalid PTE on older architectures. | |
3394 | */ | |
aa653a68 CW |
3395 | restart: |
3396 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3397 | if (!drm_mm_node_allocated(&vma->node)) |
3398 | continue; | |
3399 | ||
20dfbde4 | 3400 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3401 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3402 | return -EBUSY; | |
3403 | } | |
3404 | ||
aa653a68 CW |
3405 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3406 | continue; | |
3407 | ||
3408 | ret = i915_vma_unbind(vma); | |
3409 | if (ret) | |
3410 | return ret; | |
3411 | ||
3412 | /* As unbinding may affect other elements in the | |
3413 | * obj->vma_list (due to side-effects from retiring | |
3414 | * an active vma), play safe and restart the iterator. | |
3415 | */ | |
3416 | goto restart; | |
42d6ab48 CW |
3417 | } |
3418 | ||
ef55f92a CW |
3419 | /* We can reuse the existing drm_mm nodes but need to change the |
3420 | * cache-level on the PTE. We could simply unbind them all and | |
3421 | * rebind with the correct cache-level on next use. However since | |
3422 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3423 | * rewrite the PTE in the belief that doing so tramples upon less | |
3424 | * state and so involves less work. | |
3425 | */ | |
15717de2 | 3426 | if (obj->bind_count) { |
ef55f92a CW |
3427 | /* Before we change the PTE, the GPU must not be accessing it. |
3428 | * If we wait upon the object, we know that all the bound | |
3429 | * VMA are no longer active. | |
3430 | */ | |
e95433c7 CW |
3431 | ret = i915_gem_object_wait(obj, |
3432 | I915_WAIT_INTERRUPTIBLE | | |
3433 | I915_WAIT_LOCKED | | |
3434 | I915_WAIT_ALL, | |
3435 | MAX_SCHEDULE_TIMEOUT, | |
3436 | NULL); | |
e4ffd173 CW |
3437 | if (ret) |
3438 | return ret; | |
3439 | ||
aa653a68 | 3440 | if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { |
ef55f92a CW |
3441 | /* Access to snoopable pages through the GTT is |
3442 | * incoherent and on some machines causes a hard | |
3443 | * lockup. Relinquish the CPU mmaping to force | |
3444 | * userspace to refault in the pages and we can | |
3445 | * then double check if the GTT mapping is still | |
3446 | * valid for that pointer access. | |
3447 | */ | |
3448 | i915_gem_release_mmap(obj); | |
3449 | ||
3450 | /* As we no longer need a fence for GTT access, | |
3451 | * we can relinquish it now (and so prevent having | |
3452 | * to steal a fence from someone else on the next | |
3453 | * fence request). Note GPU activity would have | |
3454 | * dropped the fence as all snoopable access is | |
3455 | * supposed to be linear. | |
3456 | */ | |
49ef5294 CW |
3457 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3458 | ret = i915_vma_put_fence(vma); | |
3459 | if (ret) | |
3460 | return ret; | |
3461 | } | |
ef55f92a CW |
3462 | } else { |
3463 | /* We either have incoherent backing store and | |
3464 | * so no GTT access or the architecture is fully | |
3465 | * coherent. In such cases, existing GTT mmaps | |
3466 | * ignore the cache bit in the PTE and we can | |
3467 | * rewrite it without confusing the GPU or having | |
3468 | * to force userspace to fault back in its mmaps. | |
3469 | */ | |
e4ffd173 CW |
3470 | } |
3471 | ||
1c7f4bca | 3472 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3473 | if (!drm_mm_node_allocated(&vma->node)) |
3474 | continue; | |
3475 | ||
3476 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3477 | if (ret) | |
3478 | return ret; | |
3479 | } | |
e4ffd173 CW |
3480 | } |
3481 | ||
1c7f4bca | 3482 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3483 | vma->node.color = cache_level; |
3484 | obj->cache_level = cache_level; | |
3485 | ||
ed75a55b | 3486 | out: |
ef55f92a CW |
3487 | /* Flush the dirty CPU caches to the backing storage so that the |
3488 | * object is now coherent at its new cache level (with respect | |
3489 | * to the access domain). | |
3490 | */ | |
b50a5371 | 3491 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3492 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3493 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3494 | } |
3495 | ||
e4ffd173 CW |
3496 | return 0; |
3497 | } | |
3498 | ||
199adf40 BW |
3499 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3500 | struct drm_file *file) | |
e6994aee | 3501 | { |
199adf40 | 3502 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3503 | struct drm_i915_gem_object *obj; |
e6994aee | 3504 | |
03ac0642 CW |
3505 | obj = i915_gem_object_lookup(file, args->handle); |
3506 | if (!obj) | |
432be69d | 3507 | return -ENOENT; |
e6994aee | 3508 | |
651d794f CW |
3509 | switch (obj->cache_level) { |
3510 | case I915_CACHE_LLC: | |
3511 | case I915_CACHE_L3_LLC: | |
3512 | args->caching = I915_CACHING_CACHED; | |
3513 | break; | |
3514 | ||
4257d3ba CW |
3515 | case I915_CACHE_WT: |
3516 | args->caching = I915_CACHING_DISPLAY; | |
3517 | break; | |
3518 | ||
651d794f CW |
3519 | default: |
3520 | args->caching = I915_CACHING_NONE; | |
3521 | break; | |
3522 | } | |
e6994aee | 3523 | |
34911fd3 | 3524 | i915_gem_object_put_unlocked(obj); |
432be69d | 3525 | return 0; |
e6994aee CW |
3526 | } |
3527 | ||
199adf40 BW |
3528 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3529 | struct drm_file *file) | |
e6994aee | 3530 | { |
9c870d03 | 3531 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3532 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3533 | struct drm_i915_gem_object *obj; |
3534 | enum i915_cache_level level; | |
3535 | int ret; | |
3536 | ||
199adf40 BW |
3537 | switch (args->caching) { |
3538 | case I915_CACHING_NONE: | |
e6994aee CW |
3539 | level = I915_CACHE_NONE; |
3540 | break; | |
199adf40 | 3541 | case I915_CACHING_CACHED: |
e5756c10 ID |
3542 | /* |
3543 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3544 | * snooped mapping may leave stale data in a corresponding CPU | |
3545 | * cacheline, whereas normally such cachelines would get | |
3546 | * invalidated. | |
3547 | */ | |
9c870d03 | 3548 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3549 | return -ENODEV; |
3550 | ||
e6994aee CW |
3551 | level = I915_CACHE_LLC; |
3552 | break; | |
4257d3ba | 3553 | case I915_CACHING_DISPLAY: |
9c870d03 | 3554 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3555 | break; |
e6994aee CW |
3556 | default: |
3557 | return -EINVAL; | |
3558 | } | |
3559 | ||
3bc2913e BW |
3560 | ret = i915_mutex_lock_interruptible(dev); |
3561 | if (ret) | |
9c870d03 | 3562 | return ret; |
3bc2913e | 3563 | |
03ac0642 CW |
3564 | obj = i915_gem_object_lookup(file, args->handle); |
3565 | if (!obj) { | |
e6994aee CW |
3566 | ret = -ENOENT; |
3567 | goto unlock; | |
3568 | } | |
3569 | ||
3570 | ret = i915_gem_object_set_cache_level(obj, level); | |
f8c417cd | 3571 | i915_gem_object_put(obj); |
e6994aee CW |
3572 | unlock: |
3573 | mutex_unlock(&dev->struct_mutex); | |
3574 | return ret; | |
3575 | } | |
3576 | ||
b9241ea3 | 3577 | /* |
2da3b9b9 CW |
3578 | * Prepare buffer for display plane (scanout, cursors, etc). |
3579 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3580 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3581 | */ |
058d88c4 | 3582 | struct i915_vma * |
2da3b9b9 CW |
3583 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3584 | u32 alignment, | |
e6617330 | 3585 | const struct i915_ggtt_view *view) |
b9241ea3 | 3586 | { |
058d88c4 | 3587 | struct i915_vma *vma; |
2da3b9b9 | 3588 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3589 | int ret; |
3590 | ||
4c7d62c6 CW |
3591 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3592 | ||
cc98b413 CW |
3593 | /* Mark the pin_display early so that we account for the |
3594 | * display coherency whilst setting up the cache domains. | |
3595 | */ | |
8a0c39b1 | 3596 | obj->pin_display++; |
cc98b413 | 3597 | |
a7ef0640 EA |
3598 | /* The display engine is not coherent with the LLC cache on gen6. As |
3599 | * a result, we make sure that the pinning that is about to occur is | |
3600 | * done with uncached PTEs. This is lowest common denominator for all | |
3601 | * chipsets. | |
3602 | * | |
3603 | * However for gen6+, we could do better by using the GFDT bit instead | |
3604 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3605 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3606 | */ | |
651d794f | 3607 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3608 | HAS_WT(to_i915(obj->base.dev)) ? |
3609 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3610 | if (ret) { |
3611 | vma = ERR_PTR(ret); | |
cc98b413 | 3612 | goto err_unpin_display; |
058d88c4 | 3613 | } |
a7ef0640 | 3614 | |
2da3b9b9 CW |
3615 | /* As the user may map the buffer once pinned in the display plane |
3616 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3617 | * always use map_and_fenceable for all scanout buffers. However, |
3618 | * it may simply be too big to fit into mappable, in which case | |
3619 | * put it anyway and hope that userspace can cope (but always first | |
3620 | * try to preserve the existing ABI). | |
2da3b9b9 | 3621 | */ |
2efb813d CW |
3622 | vma = ERR_PTR(-ENOSPC); |
3623 | if (view->type == I915_GGTT_VIEW_NORMAL) | |
3624 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, | |
3625 | PIN_MAPPABLE | PIN_NONBLOCK); | |
3626 | if (IS_ERR(vma)) | |
3627 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 0); | |
058d88c4 | 3628 | if (IS_ERR(vma)) |
cc98b413 | 3629 | goto err_unpin_display; |
2da3b9b9 | 3630 | |
d8923dcf CW |
3631 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3632 | ||
e62b59e4 | 3633 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3634 | |
2da3b9b9 | 3635 | old_write_domain = obj->base.write_domain; |
05394f39 | 3636 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3637 | |
3638 | /* It should now be out of any other write domains, and we can update | |
3639 | * the domain values for our changes. | |
3640 | */ | |
e5f1d962 | 3641 | obj->base.write_domain = 0; |
05394f39 | 3642 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3643 | |
3644 | trace_i915_gem_object_change_domain(obj, | |
3645 | old_read_domains, | |
2da3b9b9 | 3646 | old_write_domain); |
b9241ea3 | 3647 | |
058d88c4 | 3648 | return vma; |
cc98b413 CW |
3649 | |
3650 | err_unpin_display: | |
8a0c39b1 | 3651 | obj->pin_display--; |
058d88c4 | 3652 | return vma; |
cc98b413 CW |
3653 | } |
3654 | ||
3655 | void | |
058d88c4 | 3656 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3657 | { |
4c7d62c6 CW |
3658 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
3659 | ||
058d88c4 | 3660 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3661 | return; |
3662 | ||
d8923dcf CW |
3663 | if (--vma->obj->pin_display == 0) |
3664 | vma->display_alignment = 0; | |
e6617330 | 3665 | |
383d5823 CW |
3666 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
3667 | if (!i915_vma_is_active(vma)) | |
3668 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3669 | ||
058d88c4 | 3670 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3671 | } |
3672 | ||
e47c68e9 EA |
3673 | /** |
3674 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3675 | * @obj: object to act on |
3676 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3677 | * |
3678 | * This function returns when the move is complete, including waiting on | |
3679 | * flushes to occur. | |
3680 | */ | |
dabdfe02 | 3681 | int |
919926ae | 3682 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3683 | { |
1c5d22f7 | 3684 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3685 | int ret; |
3686 | ||
e95433c7 | 3687 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3688 | |
e95433c7 CW |
3689 | ret = i915_gem_object_wait(obj, |
3690 | I915_WAIT_INTERRUPTIBLE | | |
3691 | I915_WAIT_LOCKED | | |
3692 | (write ? I915_WAIT_ALL : 0), | |
3693 | MAX_SCHEDULE_TIMEOUT, | |
3694 | NULL); | |
88241785 CW |
3695 | if (ret) |
3696 | return ret; | |
3697 | ||
c13d87ea CW |
3698 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3699 | return 0; | |
3700 | ||
e47c68e9 | 3701 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3702 | |
05394f39 CW |
3703 | old_write_domain = obj->base.write_domain; |
3704 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3705 | |
e47c68e9 | 3706 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3707 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3708 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3709 | |
05394f39 | 3710 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3711 | } |
3712 | ||
3713 | /* It should now be out of any other write domains, and we can update | |
3714 | * the domain values for our changes. | |
3715 | */ | |
05394f39 | 3716 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3717 | |
3718 | /* If we're writing through the CPU, then the GPU read domains will | |
3719 | * need to be invalidated at next use. | |
3720 | */ | |
3721 | if (write) { | |
05394f39 CW |
3722 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3723 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3724 | } |
2ef7eeaa | 3725 | |
1c5d22f7 CW |
3726 | trace_i915_gem_object_change_domain(obj, |
3727 | old_read_domains, | |
3728 | old_write_domain); | |
3729 | ||
2ef7eeaa EA |
3730 | return 0; |
3731 | } | |
3732 | ||
673a394b EA |
3733 | /* Throttle our rendering by waiting until the ring has completed our requests |
3734 | * emitted over 20 msec ago. | |
3735 | * | |
b962442e EA |
3736 | * Note that if we were to use the current jiffies each time around the loop, |
3737 | * we wouldn't escape the function with any frames outstanding if the time to | |
3738 | * render a frame was over 20ms. | |
3739 | * | |
673a394b EA |
3740 | * This should get us reasonable parallelism between CPU and GPU but also |
3741 | * relatively low latency when blocking on a particular request to finish. | |
3742 | */ | |
40a5f0de | 3743 | static int |
f787a5f5 | 3744 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3745 | { |
fac5e23e | 3746 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3747 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3748 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3749 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3750 | long ret; |
93533c29 | 3751 | |
f4457ae7 CW |
3752 | /* ABI: return -EIO if already wedged */ |
3753 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3754 | return -EIO; | |
e110e8d6 | 3755 | |
1c25595f | 3756 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3757 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3758 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3759 | break; | |
40a5f0de | 3760 | |
fcfa423c JH |
3761 | /* |
3762 | * Note that the request might not have been submitted yet. | |
3763 | * In which case emitted_jiffies will be zero. | |
3764 | */ | |
3765 | if (!request->emitted_jiffies) | |
3766 | continue; | |
3767 | ||
54fb2411 | 3768 | target = request; |
b962442e | 3769 | } |
ff865885 | 3770 | if (target) |
e8a261ea | 3771 | i915_gem_request_get(target); |
1c25595f | 3772 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3773 | |
54fb2411 | 3774 | if (target == NULL) |
f787a5f5 | 3775 | return 0; |
2bc43b5c | 3776 | |
e95433c7 CW |
3777 | ret = i915_wait_request(target, |
3778 | I915_WAIT_INTERRUPTIBLE, | |
3779 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3780 | i915_gem_request_put(target); |
ff865885 | 3781 | |
e95433c7 | 3782 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3783 | } |
3784 | ||
d23db88c | 3785 | static bool |
91b2db6f | 3786 | i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) |
d23db88c | 3787 | { |
59bfa124 CW |
3788 | if (!drm_mm_node_allocated(&vma->node)) |
3789 | return false; | |
3790 | ||
91b2db6f CW |
3791 | if (vma->node.size < size) |
3792 | return true; | |
3793 | ||
3794 | if (alignment && vma->node.start & (alignment - 1)) | |
d23db88c CW |
3795 | return true; |
3796 | ||
05a20d09 | 3797 | if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma)) |
d23db88c CW |
3798 | return true; |
3799 | ||
3800 | if (flags & PIN_OFFSET_BIAS && | |
3801 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3802 | return true; | |
3803 | ||
506a8e87 CW |
3804 | if (flags & PIN_OFFSET_FIXED && |
3805 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3806 | return true; | |
3807 | ||
d23db88c CW |
3808 | return false; |
3809 | } | |
3810 | ||
d0710abb CW |
3811 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3812 | { | |
3813 | struct drm_i915_gem_object *obj = vma->obj; | |
a9f1481f | 3814 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d0710abb CW |
3815 | bool mappable, fenceable; |
3816 | u32 fence_size, fence_alignment; | |
3817 | ||
a9f1481f | 3818 | fence_size = i915_gem_get_ggtt_size(dev_priv, |
05a20d09 | 3819 | vma->size, |
3e510a8e | 3820 | i915_gem_object_get_tiling(obj)); |
a9f1481f | 3821 | fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, |
05a20d09 | 3822 | vma->size, |
3e510a8e | 3823 | i915_gem_object_get_tiling(obj), |
ad1a7d20 | 3824 | true); |
d0710abb CW |
3825 | |
3826 | fenceable = (vma->node.size == fence_size && | |
3827 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3828 | ||
3829 | mappable = (vma->node.start + fence_size <= | |
a9f1481f | 3830 | dev_priv->ggtt.mappable_end); |
d0710abb | 3831 | |
07ee2bce TU |
3832 | /* |
3833 | * Explicitly disable for rotated VMA since the display does not | |
3834 | * need the fence and the VMA is not accessible to other users. | |
3835 | */ | |
3836 | if (mappable && fenceable && | |
3837 | vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED) | |
05a20d09 CW |
3838 | vma->flags |= I915_VMA_CAN_FENCE; |
3839 | else | |
3840 | vma->flags &= ~I915_VMA_CAN_FENCE; | |
d0710abb CW |
3841 | } |
3842 | ||
305bc234 CW |
3843 | int __i915_vma_do_pin(struct i915_vma *vma, |
3844 | u64 size, u64 alignment, u64 flags) | |
673a394b | 3845 | { |
305bc234 | 3846 | unsigned int bound = vma->flags; |
673a394b EA |
3847 | int ret; |
3848 | ||
4c7d62c6 | 3849 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
59bfa124 | 3850 | GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); |
3272db53 | 3851 | GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); |
d7f46fc4 | 3852 | |
305bc234 CW |
3853 | if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { |
3854 | ret = -EBUSY; | |
3855 | goto err; | |
3856 | } | |
ac0c6b5a | 3857 | |
de895082 | 3858 | if ((bound & I915_VMA_BIND_MASK) == 0) { |
59bfa124 CW |
3859 | ret = i915_vma_insert(vma, size, alignment, flags); |
3860 | if (ret) | |
3861 | goto err; | |
fe14d5f4 | 3862 | } |
74898d7e | 3863 | |
59bfa124 | 3864 | ret = i915_vma_bind(vma, vma->obj->cache_level, flags); |
3b16525c | 3865 | if (ret) |
59bfa124 | 3866 | goto err; |
3b16525c | 3867 | |
3272db53 | 3868 | if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) |
d0710abb | 3869 | __i915_vma_set_map_and_fenceable(vma); |
ef79e17c | 3870 | |
3b16525c | 3871 | GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); |
673a394b | 3872 | return 0; |
673a394b | 3873 | |
59bfa124 CW |
3874 | err: |
3875 | __i915_vma_unpin(vma); | |
3876 | return ret; | |
ec7adb6e JL |
3877 | } |
3878 | ||
058d88c4 | 3879 | struct i915_vma * |
ec7adb6e JL |
3880 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3881 | const struct i915_ggtt_view *view, | |
91b2db6f | 3882 | u64 size, |
2ffffd0f CW |
3883 | u64 alignment, |
3884 | u64 flags) | |
ec7adb6e | 3885 | { |
ad16d2ed CW |
3886 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3887 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3888 | struct i915_vma *vma; |
3889 | int ret; | |
72e96d64 | 3890 | |
4c7d62c6 CW |
3891 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3892 | ||
058d88c4 | 3893 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view); |
59bfa124 | 3894 | if (IS_ERR(vma)) |
058d88c4 | 3895 | return vma; |
59bfa124 CW |
3896 | |
3897 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3898 | if (flags & PIN_NONBLOCK && | |
3899 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3900 | return ERR_PTR(-ENOSPC); |
59bfa124 | 3901 | |
ad16d2ed CW |
3902 | if (flags & PIN_MAPPABLE) { |
3903 | u32 fence_size; | |
3904 | ||
3905 | fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size, | |
3906 | i915_gem_object_get_tiling(obj)); | |
3907 | /* If the required space is larger than the available | |
3908 | * aperture, we will not able to find a slot for the | |
3909 | * object and unbinding the object now will be in | |
3910 | * vain. Worse, doing so may cause us to ping-pong | |
3911 | * the object in and out of the Global GTT and | |
3912 | * waste a lot of cycles under the mutex. | |
3913 | */ | |
3914 | if (fence_size > dev_priv->ggtt.mappable_end) | |
3915 | return ERR_PTR(-E2BIG); | |
3916 | ||
3917 | /* If NONBLOCK is set the caller is optimistically | |
3918 | * trying to cache the full object within the mappable | |
3919 | * aperture, and *must* have a fallback in place for | |
3920 | * situations where we cannot bind the object. We | |
3921 | * can be a little more lax here and use the fallback | |
3922 | * more often to avoid costly migrations of ourselves | |
3923 | * and other objects within the aperture. | |
3924 | * | |
3925 | * Half-the-aperture is used as a simple heuristic. | |
3926 | * More interesting would to do search for a free | |
3927 | * block prior to making the commitment to unbind. | |
3928 | * That caters for the self-harm case, and with a | |
3929 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
3930 | * we could try to minimise harm to others. | |
3931 | */ | |
3932 | if (flags & PIN_NONBLOCK && | |
3933 | fence_size > dev_priv->ggtt.mappable_end / 2) | |
3934 | return ERR_PTR(-ENOSPC); | |
3935 | } | |
3936 | ||
59bfa124 CW |
3937 | WARN(i915_vma_is_pinned(vma), |
3938 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3939 | " offset=%08x, req.alignment=%llx," |
3940 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3941 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3942 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3943 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3944 | ret = i915_vma_unbind(vma); |
3945 | if (ret) | |
058d88c4 | 3946 | return ERR_PTR(ret); |
59bfa124 CW |
3947 | } |
3948 | ||
058d88c4 CW |
3949 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3950 | if (ret) | |
3951 | return ERR_PTR(ret); | |
ec7adb6e | 3952 | |
058d88c4 | 3953 | return vma; |
673a394b EA |
3954 | } |
3955 | ||
edf6b76f | 3956 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3957 | { |
3958 | /* Note that we could alias engines in the execbuf API, but | |
3959 | * that would be very unwise as it prevents userspace from | |
3960 | * fine control over engine selection. Ahem. | |
3961 | * | |
3962 | * This should be something like EXEC_MAX_ENGINE instead of | |
3963 | * I915_NUM_ENGINES. | |
3964 | */ | |
3965 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3966 | return 0x10000 << id; | |
3967 | } | |
3968 | ||
3969 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3970 | { | |
70cb472c CW |
3971 | /* The uABI guarantees an active writer is also amongst the read |
3972 | * engines. This would be true if we accessed the activity tracking | |
3973 | * under the lock, but as we perform the lookup of the object and | |
3974 | * its activity locklessly we can not guarantee that the last_write | |
3975 | * being active implies that we have set the same engine flag from | |
3976 | * last_read - hence we always set both read and write busy for | |
3977 | * last_write. | |
3978 | */ | |
3979 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3980 | } |
3981 | ||
edf6b76f | 3982 | static __always_inline unsigned int |
3fdc13c7 CW |
3983 | __busy_set_if_active(const struct i915_gem_active *active, |
3984 | unsigned int (*flag)(unsigned int id)) | |
3985 | { | |
1255501d | 3986 | struct drm_i915_gem_request *request; |
3fdc13c7 | 3987 | |
1255501d CW |
3988 | request = rcu_dereference(active->request); |
3989 | if (!request || i915_gem_request_completed(request)) | |
3990 | return 0; | |
3fdc13c7 | 3991 | |
1255501d CW |
3992 | /* This is racy. See __i915_gem_active_get_rcu() for an in detail |
3993 | * discussion of how to handle the race correctly, but for reporting | |
3994 | * the busy state we err on the side of potentially reporting the | |
3995 | * wrong engine as being busy (but we guarantee that the result | |
3996 | * is at least self-consistent). | |
3997 | * | |
3998 | * As we use SLAB_DESTROY_BY_RCU, the request may be reallocated | |
3999 | * whilst we are inspecting it, even under the RCU read lock as we are. | |
4000 | * This means that there is a small window for the engine and/or the | |
4001 | * seqno to have been overwritten. The seqno will always be in the | |
4002 | * future compared to the intended, and so we know that if that | |
4003 | * seqno is idle (on whatever engine) our request is idle and the | |
4004 | * return 0 above is correct. | |
4005 | * | |
4006 | * The issue is that if the engine is switched, it is just as likely | |
4007 | * to report that it is busy (but since the switch happened, we know | |
4008 | * the request should be idle). So there is a small chance that a busy | |
4009 | * result is actually the wrong engine. | |
4010 | * | |
4011 | * So why don't we care? | |
4012 | * | |
4013 | * For starters, the busy ioctl is a heuristic that is by definition | |
4014 | * racy. Even with perfect serialisation in the driver, the hardware | |
4015 | * state is constantly advancing - the state we report to the user | |
4016 | * is stale. | |
4017 | * | |
4018 | * The critical information for the busy-ioctl is whether the object | |
4019 | * is idle as userspace relies on that to detect whether its next | |
4020 | * access will stall, or if it has missed submitting commands to | |
4021 | * the hardware allowing the GPU to stall. We never generate a | |
4022 | * false-positive for idleness, thus busy-ioctl is reliable at the | |
4023 | * most fundamental level, and we maintain the guarantee that a | |
4024 | * busy object left to itself will eventually become idle (and stay | |
4025 | * idle!). | |
4026 | * | |
4027 | * We allow ourselves the leeway of potentially misreporting the busy | |
4028 | * state because that is an optimisation heuristic that is constantly | |
4029 | * in flux. Being quickly able to detect the busy/idle state is much | |
4030 | * more important than accurate logging of exactly which engines were | |
4031 | * busy. | |
4032 | * | |
4033 | * For accuracy in reporting the engine, we could use | |
4034 | * | |
4035 | * result = 0; | |
4036 | * request = __i915_gem_active_get_rcu(active); | |
4037 | * if (request) { | |
4038 | * if (!i915_gem_request_completed(request)) | |
4039 | * result = flag(request->engine->exec_id); | |
4040 | * i915_gem_request_put(request); | |
4041 | * } | |
4042 | * | |
4043 | * but that still remains susceptible to both hardware and userspace | |
4044 | * races. So we accept making the result of that race slightly worse, | |
4045 | * given the rarity of the race and its low impact on the result. | |
4046 | */ | |
4047 | return flag(READ_ONCE(request->engine->exec_id)); | |
3fdc13c7 CW |
4048 | } |
4049 | ||
edf6b76f | 4050 | static __always_inline unsigned int |
3fdc13c7 CW |
4051 | busy_check_reader(const struct i915_gem_active *active) |
4052 | { | |
4053 | return __busy_set_if_active(active, __busy_read_flag); | |
4054 | } | |
4055 | ||
edf6b76f | 4056 | static __always_inline unsigned int |
3fdc13c7 CW |
4057 | busy_check_writer(const struct i915_gem_active *active) |
4058 | { | |
4059 | return __busy_set_if_active(active, __busy_write_id); | |
4060 | } | |
4061 | ||
673a394b EA |
4062 | int |
4063 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4064 | struct drm_file *file) |
673a394b EA |
4065 | { |
4066 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4067 | struct drm_i915_gem_object *obj; |
3fdc13c7 | 4068 | unsigned long active; |
673a394b | 4069 | |
03ac0642 | 4070 | obj = i915_gem_object_lookup(file, args->handle); |
3fdc13c7 CW |
4071 | if (!obj) |
4072 | return -ENOENT; | |
d1b851fc | 4073 | |
426960be | 4074 | args->busy = 0; |
3fdc13c7 CW |
4075 | active = __I915_BO_ACTIVE(obj); |
4076 | if (active) { | |
4077 | int idx; | |
426960be | 4078 | |
3fdc13c7 CW |
4079 | /* Yes, the lookups are intentionally racy. |
4080 | * | |
4081 | * First, we cannot simply rely on __I915_BO_ACTIVE. We have | |
4082 | * to regard the value as stale and as our ABI guarantees | |
4083 | * forward progress, we confirm the status of each active | |
4084 | * request with the hardware. | |
4085 | * | |
4086 | * Even though we guard the pointer lookup by RCU, that only | |
4087 | * guarantees that the pointer and its contents remain | |
4088 | * dereferencable and does *not* mean that the request we | |
4089 | * have is the same as the one being tracked by the object. | |
4090 | * | |
4091 | * Consider that we lookup the request just as it is being | |
4092 | * retired and freed. We take a local copy of the pointer, | |
4093 | * but before we add its engine into the busy set, the other | |
4094 | * thread reallocates it and assigns it to a task on another | |
1255501d CW |
4095 | * engine with a fresh and incomplete seqno. Guarding against |
4096 | * that requires careful serialisation and reference counting, | |
4097 | * i.e. using __i915_gem_active_get_request_rcu(). We don't, | |
4098 | * instead we expect that if the result is busy, which engines | |
4099 | * are busy is not completely reliable - we only guarantee | |
4100 | * that the object was busy. | |
3fdc13c7 CW |
4101 | */ |
4102 | rcu_read_lock(); | |
4103 | ||
4104 | for_each_active(active, idx) | |
4105 | args->busy |= busy_check_reader(&obj->last_read[idx]); | |
4106 | ||
4107 | /* For ABI sanity, we only care that the write engine is in | |
70cb472c CW |
4108 | * the set of read engines. This should be ensured by the |
4109 | * ordering of setting last_read/last_write in | |
4110 | * i915_vma_move_to_active(), and then in reverse in retire. | |
4111 | * However, for good measure, we always report the last_write | |
4112 | * request as a busy read as well as being a busy write. | |
3fdc13c7 CW |
4113 | * |
4114 | * We don't care that the set of active read/write engines | |
4115 | * may change during construction of the result, as it is | |
4116 | * equally liable to change before userspace can inspect | |
4117 | * the result. | |
4118 | */ | |
4119 | args->busy |= busy_check_writer(&obj->last_write); | |
4120 | ||
4121 | rcu_read_unlock(); | |
426960be | 4122 | } |
673a394b | 4123 | |
3fdc13c7 CW |
4124 | i915_gem_object_put_unlocked(obj); |
4125 | return 0; | |
673a394b EA |
4126 | } |
4127 | ||
4128 | int | |
4129 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4130 | struct drm_file *file_priv) | |
4131 | { | |
0206e353 | 4132 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4133 | } |
4134 | ||
3ef94daa CW |
4135 | int |
4136 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4137 | struct drm_file *file_priv) | |
4138 | { | |
fac5e23e | 4139 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4140 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4141 | struct drm_i915_gem_object *obj; |
1233e2db | 4142 | int err; |
3ef94daa CW |
4143 | |
4144 | switch (args->madv) { | |
4145 | case I915_MADV_DONTNEED: | |
4146 | case I915_MADV_WILLNEED: | |
4147 | break; | |
4148 | default: | |
4149 | return -EINVAL; | |
4150 | } | |
4151 | ||
03ac0642 | 4152 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
4153 | if (!obj) |
4154 | return -ENOENT; | |
4155 | ||
4156 | err = mutex_lock_interruptible(&obj->mm.lock); | |
4157 | if (err) | |
4158 | goto out; | |
3ef94daa | 4159 | |
a4f5ea64 | 4160 | if (obj->mm.pages && |
3e510a8e | 4161 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 4162 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
a4f5ea64 CW |
4163 | if (obj->mm.madv == I915_MADV_WILLNEED) |
4164 | __i915_gem_object_unpin_pages(obj); | |
656bfa3a | 4165 | if (args->madv == I915_MADV_WILLNEED) |
a4f5ea64 | 4166 | __i915_gem_object_pin_pages(obj); |
656bfa3a DV |
4167 | } |
4168 | ||
a4f5ea64 CW |
4169 | if (obj->mm.madv != __I915_MADV_PURGED) |
4170 | obj->mm.madv = args->madv; | |
3ef94daa | 4171 | |
6c085a72 | 4172 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 4173 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
4174 | i915_gem_object_truncate(obj); |
4175 | ||
a4f5ea64 | 4176 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 4177 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 4178 | |
1233e2db | 4179 | out: |
f8c417cd | 4180 | i915_gem_object_put(obj); |
1233e2db | 4181 | return err; |
3ef94daa CW |
4182 | } |
4183 | ||
37e680a1 CW |
4184 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4185 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4186 | { |
b4716185 CW |
4187 | int i; |
4188 | ||
1233e2db CW |
4189 | mutex_init(&obj->mm.lock); |
4190 | ||
35c20a60 | 4191 | INIT_LIST_HEAD(&obj->global_list); |
275f039d | 4192 | INIT_LIST_HEAD(&obj->userfault_link); |
666796da | 4193 | for (i = 0; i < I915_NUM_ENGINES; i++) |
fa545cbf CW |
4194 | init_request_active(&obj->last_read[i], |
4195 | i915_gem_object_retire__read); | |
4196 | init_request_active(&obj->last_write, | |
4197 | i915_gem_object_retire__write); | |
b25cb2f8 | 4198 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4199 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4200 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4201 | |
37e680a1 CW |
4202 | obj->ops = ops; |
4203 | ||
50349247 | 4204 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
a4f5ea64 CW |
4205 | |
4206 | obj->mm.madv = I915_MADV_WILLNEED; | |
4207 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4208 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4209 | |
f19ec8cb | 4210 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4211 | } |
4212 | ||
37e680a1 | 4213 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4214 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4215 | .get_pages = i915_gem_object_get_pages_gtt, |
4216 | .put_pages = i915_gem_object_put_pages_gtt, | |
4217 | }; | |
4218 | ||
b4bcbe2a CW |
4219 | /* Note we don't consider signbits :| */ |
4220 | #define overflows_type(x, T) \ | |
4221 | (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE)) | |
4222 | ||
4223 | struct drm_i915_gem_object * | |
4224 | i915_gem_object_create(struct drm_device *dev, u64 size) | |
ac52bc56 | 4225 | { |
c397b908 | 4226 | struct drm_i915_gem_object *obj; |
5949eac4 | 4227 | struct address_space *mapping; |
1a240d4d | 4228 | gfp_t mask; |
fe3db79b | 4229 | int ret; |
ac52bc56 | 4230 | |
b4bcbe2a CW |
4231 | /* There is a prevalence of the assumption that we fit the object's |
4232 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4233 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4234 | * such a local variable, please consider fixing! | |
4235 | */ | |
4236 | if (WARN_ON(size >> PAGE_SHIFT > INT_MAX)) | |
4237 | return ERR_PTR(-E2BIG); | |
4238 | ||
4239 | if (overflows_type(size, obj->base.size)) | |
4240 | return ERR_PTR(-E2BIG); | |
4241 | ||
42dcedd4 | 4242 | obj = i915_gem_object_alloc(dev); |
c397b908 | 4243 | if (obj == NULL) |
fe3db79b | 4244 | return ERR_PTR(-ENOMEM); |
673a394b | 4245 | |
fe3db79b CW |
4246 | ret = drm_gem_object_init(dev, &obj->base, size); |
4247 | if (ret) | |
4248 | goto fail; | |
673a394b | 4249 | |
bed1ea95 CW |
4250 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4251 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4252 | /* 965gm cannot relocate objects above 4GiB. */ | |
4253 | mask &= ~__GFP_HIGHMEM; | |
4254 | mask |= __GFP_DMA32; | |
4255 | } | |
4256 | ||
93c76a3d | 4257 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4258 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4259 | |
37e680a1 | 4260 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4261 | |
c397b908 DV |
4262 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4263 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4264 | |
3d29b842 ED |
4265 | if (HAS_LLC(dev)) { |
4266 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4267 | * cache) for about a 10% performance improvement |
4268 | * compared to uncached. Graphics requests other than | |
4269 | * display scanout are coherent with the CPU in | |
4270 | * accessing this cache. This means in this mode we | |
4271 | * don't need to clflush on the CPU side, and on the | |
4272 | * GPU side we only need to flush internal caches to | |
4273 | * get data visible to the CPU. | |
4274 | * | |
4275 | * However, we maintain the display planes as UC, and so | |
4276 | * need to rebind when first used as such. | |
4277 | */ | |
4278 | obj->cache_level = I915_CACHE_LLC; | |
4279 | } else | |
4280 | obj->cache_level = I915_CACHE_NONE; | |
4281 | ||
d861e338 DV |
4282 | trace_i915_gem_object_create(obj); |
4283 | ||
05394f39 | 4284 | return obj; |
fe3db79b CW |
4285 | |
4286 | fail: | |
4287 | i915_gem_object_free(obj); | |
4288 | ||
4289 | return ERR_PTR(ret); | |
c397b908 DV |
4290 | } |
4291 | ||
340fbd8c CW |
4292 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4293 | { | |
4294 | /* If we are the last user of the backing storage (be it shmemfs | |
4295 | * pages or stolen etc), we know that the pages are going to be | |
4296 | * immediately released. In this case, we can then skip copying | |
4297 | * back the contents from the GPU. | |
4298 | */ | |
4299 | ||
a4f5ea64 | 4300 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4301 | return false; |
4302 | ||
4303 | if (obj->base.filp == NULL) | |
4304 | return true; | |
4305 | ||
4306 | /* At first glance, this looks racy, but then again so would be | |
4307 | * userspace racing mmap against close. However, the first external | |
4308 | * reference to the filp can only be obtained through the | |
4309 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4310 | * acquiring such a reference whilst we are in the middle of | |
4311 | * freeing the object. | |
4312 | */ | |
4313 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4314 | } | |
4315 | ||
1488fc08 | 4316 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4317 | { |
1488fc08 | 4318 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4319 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 4320 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 4321 | struct i915_vma *vma, *next; |
673a394b | 4322 | |
f65c9168 PZ |
4323 | intel_runtime_pm_get(dev_priv); |
4324 | ||
26e12f89 CW |
4325 | trace_i915_gem_object_destroy(obj); |
4326 | ||
b1f788c6 CW |
4327 | /* All file-owned VMA should have been released by this point through |
4328 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4329 | * However, the object may also be bound into the global GTT (e.g. | |
4330 | * older GPUs without per-process support, or for direct access through | |
4331 | * the GTT either for the user or for scanout). Those VMA still need to | |
4332 | * unbound now. | |
4333 | */ | |
1c7f4bca | 4334 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
3272db53 | 4335 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
b1f788c6 | 4336 | GEM_BUG_ON(i915_vma_is_active(vma)); |
3272db53 | 4337 | vma->flags &= ~I915_VMA_PIN_MASK; |
b1f788c6 | 4338 | i915_vma_close(vma); |
1488fc08 | 4339 | } |
15717de2 | 4340 | GEM_BUG_ON(obj->bind_count); |
1488fc08 | 4341 | |
faf5bf0a | 4342 | WARN_ON(atomic_read(&obj->frontbuffer_bits)); |
a071fa00 | 4343 | |
a4f5ea64 | 4344 | if (obj->mm.pages && obj->mm.madv == I915_MADV_WILLNEED && |
656bfa3a | 4345 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
3e510a8e | 4346 | i915_gem_object_is_tiled(obj)) |
a4f5ea64 | 4347 | __i915_gem_object_unpin_pages(obj); |
656bfa3a | 4348 | |
a4f5ea64 CW |
4349 | if (obj->ops->release) |
4350 | obj->ops->release(obj); | |
4351 | ||
4352 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) | |
1233e2db | 4353 | atomic_set(&obj->mm.pages_pin_count, 0); |
340fbd8c | 4354 | if (discard_backing_storage(obj)) |
a4f5ea64 CW |
4355 | obj->mm.madv = I915_MADV_DONTNEED; |
4356 | __i915_gem_object_put_pages(obj); | |
de151cf6 | 4357 | |
a4f5ea64 | 4358 | GEM_BUG_ON(obj->mm.pages); |
9da3da66 | 4359 | |
2f745ad3 CW |
4360 | if (obj->base.import_attach) |
4361 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4362 | |
05394f39 CW |
4363 | drm_gem_object_release(&obj->base); |
4364 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4365 | |
05394f39 | 4366 | kfree(obj->bit_17); |
42dcedd4 | 4367 | i915_gem_object_free(obj); |
f65c9168 PZ |
4368 | |
4369 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4370 | } |
4371 | ||
f8a7fde4 CW |
4372 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4373 | { | |
4374 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4375 | ||
4376 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4377 | if (i915_gem_object_is_active(obj)) | |
4378 | i915_gem_object_set_active_reference(obj); | |
4379 | else | |
4380 | i915_gem_object_put(obj); | |
4381 | } | |
4382 | ||
dcff85c8 | 4383 | int i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4384 | { |
fac5e23e | 4385 | struct drm_i915_private *dev_priv = to_i915(dev); |
dcff85c8 | 4386 | int ret; |
28dfe52a | 4387 | |
54b4f68f CW |
4388 | intel_suspend_gt_powersave(dev_priv); |
4389 | ||
45c5f202 | 4390 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4391 | |
4392 | /* We have to flush all the executing contexts to main memory so | |
4393 | * that they can saved in the hibernation image. To ensure the last | |
4394 | * context image is coherent, we have to switch away from it. That | |
4395 | * leaves the dev_priv->kernel_context still active when | |
4396 | * we actually suspend, and its image in memory may not match the GPU | |
4397 | * state. Fortunately, the kernel_context is disposable and we do | |
4398 | * not rely on its state. | |
4399 | */ | |
4400 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4401 | if (ret) | |
4402 | goto err; | |
4403 | ||
22dd3bb9 CW |
4404 | ret = i915_gem_wait_for_idle(dev_priv, |
4405 | I915_WAIT_INTERRUPTIBLE | | |
4406 | I915_WAIT_LOCKED); | |
f7403347 | 4407 | if (ret) |
45c5f202 | 4408 | goto err; |
f7403347 | 4409 | |
c033666a | 4410 | i915_gem_retire_requests(dev_priv); |
673a394b | 4411 | |
b2e862d0 | 4412 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4413 | mutex_unlock(&dev->struct_mutex); |
4414 | ||
737b1506 | 4415 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4416 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4417 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 4418 | |
bdcf120b CW |
4419 | /* Assert that we sucessfully flushed all the work and |
4420 | * reset the GPU back to its idle, low power state. | |
4421 | */ | |
67d97da3 | 4422 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4423 | |
1c777c5d ID |
4424 | /* |
4425 | * Neither the BIOS, ourselves or any other kernel | |
4426 | * expects the system to be in execlists mode on startup, | |
4427 | * so we need to reset the GPU back to legacy mode. And the only | |
4428 | * known way to disable logical contexts is through a GPU reset. | |
4429 | * | |
4430 | * So in order to leave the system in a known default configuration, | |
4431 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4432 | * clean up the GEM state tracking, flushing off the requests and | |
4433 | * leaving the system in a known idle state. | |
4434 | * | |
4435 | * Note that is of the upmost importance that the GPU is idle and | |
4436 | * all stray writes are flushed *before* we dismantle the backing | |
4437 | * storage for the pinned objects. | |
4438 | * | |
4439 | * However, since we are uncertain that resetting the GPU on older | |
4440 | * machines is a good idea, we don't - just in case it leaves the | |
4441 | * machine in an unusable condition. | |
4442 | */ | |
4443 | if (HAS_HW_CONTEXTS(dev)) { | |
4444 | int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); | |
4445 | WARN_ON(reset && reset != -ENODEV); | |
4446 | } | |
4447 | ||
673a394b | 4448 | return 0; |
45c5f202 CW |
4449 | |
4450 | err: | |
4451 | mutex_unlock(&dev->struct_mutex); | |
4452 | return ret; | |
673a394b EA |
4453 | } |
4454 | ||
5ab57c70 CW |
4455 | void i915_gem_resume(struct drm_device *dev) |
4456 | { | |
4457 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4458 | ||
4459 | mutex_lock(&dev->struct_mutex); | |
4460 | i915_gem_restore_gtt_mappings(dev); | |
4461 | ||
4462 | /* As we didn't flush the kernel context before suspend, we cannot | |
4463 | * guarantee that the context image is complete. So let's just reset | |
4464 | * it and start again. | |
4465 | */ | |
821ed7df | 4466 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4467 | |
4468 | mutex_unlock(&dev->struct_mutex); | |
4469 | } | |
4470 | ||
f691e2f4 DV |
4471 | void i915_gem_init_swizzling(struct drm_device *dev) |
4472 | { | |
fac5e23e | 4473 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4474 | |
11782b02 | 4475 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4476 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4477 | return; | |
4478 | ||
4479 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4480 | DISP_TILE_SURFACE_SWIZZLING); | |
4481 | ||
5db94019 | 4482 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4483 | return; |
4484 | ||
f691e2f4 | 4485 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4486 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4487 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4488 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4489 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4490 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4491 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4492 | else |
4493 | BUG(); | |
f691e2f4 | 4494 | } |
e21af88d | 4495 | |
50a0bc90 | 4496 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4497 | { |
81e7f200 VS |
4498 | I915_WRITE(RING_CTL(base), 0); |
4499 | I915_WRITE(RING_HEAD(base), 0); | |
4500 | I915_WRITE(RING_TAIL(base), 0); | |
4501 | I915_WRITE(RING_START(base), 0); | |
4502 | } | |
4503 | ||
50a0bc90 | 4504 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4505 | { |
50a0bc90 TU |
4506 | if (IS_I830(dev_priv)) { |
4507 | init_unused_ring(dev_priv, PRB1_BASE); | |
4508 | init_unused_ring(dev_priv, SRB0_BASE); | |
4509 | init_unused_ring(dev_priv, SRB1_BASE); | |
4510 | init_unused_ring(dev_priv, SRB2_BASE); | |
4511 | init_unused_ring(dev_priv, SRB3_BASE); | |
4512 | } else if (IS_GEN2(dev_priv)) { | |
4513 | init_unused_ring(dev_priv, SRB0_BASE); | |
4514 | init_unused_ring(dev_priv, SRB1_BASE); | |
4515 | } else if (IS_GEN3(dev_priv)) { | |
4516 | init_unused_ring(dev_priv, PRB1_BASE); | |
4517 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4518 | } |
4519 | } | |
4520 | ||
4fc7c971 BW |
4521 | int |
4522 | i915_gem_init_hw(struct drm_device *dev) | |
4523 | { | |
fac5e23e | 4524 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4525 | struct intel_engine_cs *engine; |
3b3f1650 | 4526 | enum intel_engine_id id; |
d200cda6 | 4527 | int ret; |
4fc7c971 | 4528 | |
de867c20 CW |
4529 | dev_priv->gt.last_init_time = ktime_get(); |
4530 | ||
5e4f5189 CW |
4531 | /* Double layer security blanket, see i915_gem_init() */ |
4532 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4533 | ||
3accaf7e | 4534 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4535 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4536 | |
772c2a51 | 4537 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4538 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4539 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4540 | |
6e266956 | 4541 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4542 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4543 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4544 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4545 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4546 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4547 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4548 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4549 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4550 | } | |
88a2b2a3 BW |
4551 | } |
4552 | ||
4fc7c971 BW |
4553 | i915_gem_init_swizzling(dev); |
4554 | ||
d5abdfda DV |
4555 | /* |
4556 | * At least 830 can leave some of the unused rings | |
4557 | * "active" (ie. head != tail) after resume which | |
4558 | * will prevent c3 entry. Makes sure all unused rings | |
4559 | * are totally idle. | |
4560 | */ | |
50a0bc90 | 4561 | init_unused_rings(dev_priv); |
d5abdfda | 4562 | |
ed54c1a1 | 4563 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4564 | |
4ad2fd88 JH |
4565 | ret = i915_ppgtt_init_hw(dev); |
4566 | if (ret) { | |
4567 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4568 | goto out; | |
4569 | } | |
4570 | ||
4571 | /* Need to do basic initialisation of all rings first: */ | |
3b3f1650 | 4572 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 4573 | ret = engine->init_hw(engine); |
35a57ffb | 4574 | if (ret) |
5e4f5189 | 4575 | goto out; |
35a57ffb | 4576 | } |
99433931 | 4577 | |
0ccdacf6 PA |
4578 | intel_mocs_init_l3cc_table(dev); |
4579 | ||
33a732f4 | 4580 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4581 | ret = intel_guc_setup(dev); |
4582 | if (ret) | |
4583 | goto out; | |
33a732f4 | 4584 | |
5e4f5189 CW |
4585 | out: |
4586 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4587 | return ret; |
8187a2b7 ZN |
4588 | } |
4589 | ||
39df9190 CW |
4590 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4591 | { | |
4592 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4593 | return false; | |
4594 | ||
4595 | /* TODO: make semaphores and Execlists play nicely together */ | |
4596 | if (i915.enable_execlists) | |
4597 | return false; | |
4598 | ||
4599 | if (value >= 0) | |
4600 | return value; | |
4601 | ||
4602 | #ifdef CONFIG_INTEL_IOMMU | |
4603 | /* Enable semaphores on SNB when IO remapping is off */ | |
4604 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4605 | return false; | |
4606 | #endif | |
4607 | ||
4608 | return true; | |
4609 | } | |
4610 | ||
1070a42b CW |
4611 | int i915_gem_init(struct drm_device *dev) |
4612 | { | |
fac5e23e | 4613 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4614 | int ret; |
4615 | ||
1070a42b | 4616 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4617 | |
a83014d3 | 4618 | if (!i915.enable_execlists) { |
821ed7df | 4619 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4620 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4621 | } else { |
821ed7df | 4622 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4623 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4624 | } |
4625 | ||
5e4f5189 CW |
4626 | /* This is just a security blanket to placate dragons. |
4627 | * On some systems, we very sporadically observe that the first TLBs | |
4628 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4629 | * we hold the forcewake during initialisation these problems | |
4630 | * just magically go away. | |
4631 | */ | |
4632 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4633 | ||
72778cb2 | 4634 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4635 | |
4636 | ret = i915_gem_init_ggtt(dev_priv); | |
4637 | if (ret) | |
4638 | goto out_unlock; | |
d62b4892 | 4639 | |
2fa48d8d | 4640 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4641 | if (ret) |
4642 | goto out_unlock; | |
2fa48d8d | 4643 | |
8b3e2d36 | 4644 | ret = intel_engines_init(dev); |
35a57ffb | 4645 | if (ret) |
7bcc3777 | 4646 | goto out_unlock; |
2fa48d8d | 4647 | |
1070a42b | 4648 | ret = i915_gem_init_hw(dev); |
60990320 | 4649 | if (ret == -EIO) { |
7e21d648 | 4650 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4651 | * wedged. But we only want to do this where the GPU is angry, |
4652 | * for all other failure, such as an allocation failure, bail. | |
4653 | */ | |
4654 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4655 | i915_gem_set_wedged(dev_priv); |
60990320 | 4656 | ret = 0; |
1070a42b | 4657 | } |
7bcc3777 JN |
4658 | |
4659 | out_unlock: | |
5e4f5189 | 4660 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4661 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4662 | |
60990320 | 4663 | return ret; |
1070a42b CW |
4664 | } |
4665 | ||
8187a2b7 | 4666 | void |
117897f4 | 4667 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4668 | { |
fac5e23e | 4669 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4670 | struct intel_engine_cs *engine; |
3b3f1650 | 4671 | enum intel_engine_id id; |
8187a2b7 | 4672 | |
3b3f1650 | 4673 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4674 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4675 | } |
4676 | ||
40ae4e16 ID |
4677 | void |
4678 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4679 | { | |
91c8a326 | 4680 | struct drm_device *dev = &dev_priv->drm; |
49ef5294 | 4681 | int i; |
40ae4e16 ID |
4682 | |
4683 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4684 | !IS_CHERRYVIEW(dev_priv)) | |
4685 | dev_priv->num_fence_regs = 32; | |
4686 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4687 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4688 | dev_priv->num_fence_regs = 16; | |
4689 | else | |
4690 | dev_priv->num_fence_regs = 8; | |
4691 | ||
c033666a | 4692 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4693 | dev_priv->num_fence_regs = |
4694 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4695 | ||
4696 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4697 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4698 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4699 | ||
4700 | fence->i915 = dev_priv; | |
4701 | fence->id = i; | |
4702 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4703 | } | |
40ae4e16 ID |
4704 | i915_gem_restore_fences(dev); |
4705 | ||
4706 | i915_gem_detect_bit_6_swizzle(dev); | |
4707 | } | |
4708 | ||
673a394b | 4709 | void |
d64aa096 | 4710 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4711 | { |
fac5e23e | 4712 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 | 4713 | |
efab6d8d | 4714 | dev_priv->objects = |
42dcedd4 CW |
4715 | kmem_cache_create("i915_gem_object", |
4716 | sizeof(struct drm_i915_gem_object), 0, | |
4717 | SLAB_HWCACHE_ALIGN, | |
4718 | NULL); | |
e20d2ab7 CW |
4719 | dev_priv->vmas = |
4720 | kmem_cache_create("i915_gem_vma", | |
4721 | sizeof(struct i915_vma), 0, | |
4722 | SLAB_HWCACHE_ALIGN, | |
4723 | NULL); | |
efab6d8d CW |
4724 | dev_priv->requests = |
4725 | kmem_cache_create("i915_gem_request", | |
4726 | sizeof(struct drm_i915_gem_request), 0, | |
0eafec6d CW |
4727 | SLAB_HWCACHE_ALIGN | |
4728 | SLAB_RECLAIM_ACCOUNT | | |
4729 | SLAB_DESTROY_BY_RCU, | |
efab6d8d | 4730 | NULL); |
673a394b | 4731 | |
a33afea5 | 4732 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4733 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4734 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4735 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4736 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4737 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4738 | i915_gem_retire_work_handler); |
67d97da3 | 4739 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4740 | i915_gem_idle_work_handler); |
1f15b76f | 4741 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4742 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4743 | |
72bfa19c CW |
4744 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4745 | ||
6b95a207 | 4746 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4747 | |
ce453d81 CW |
4748 | dev_priv->mm.interruptible = true; |
4749 | ||
6f633402 JL |
4750 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4751 | ||
b5add959 | 4752 | spin_lock_init(&dev_priv->fb_tracking.lock); |
673a394b | 4753 | } |
71acb5eb | 4754 | |
d64aa096 ID |
4755 | void i915_gem_load_cleanup(struct drm_device *dev) |
4756 | { | |
4757 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4758 | ||
4759 | kmem_cache_destroy(dev_priv->requests); | |
4760 | kmem_cache_destroy(dev_priv->vmas); | |
4761 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4762 | |
4763 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4764 | rcu_barrier(); | |
d64aa096 ID |
4765 | } |
4766 | ||
6a800eab CW |
4767 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4768 | { | |
4769 | intel_runtime_pm_get(dev_priv); | |
4770 | ||
4771 | mutex_lock(&dev_priv->drm.struct_mutex); | |
4772 | i915_gem_shrink_all(dev_priv); | |
4773 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4774 | ||
4775 | intel_runtime_pm_put(dev_priv); | |
4776 | ||
4777 | return 0; | |
4778 | } | |
4779 | ||
461fb99c CW |
4780 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4781 | { | |
4782 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4783 | struct list_head *phases[] = { |
4784 | &dev_priv->mm.unbound_list, | |
4785 | &dev_priv->mm.bound_list, | |
4786 | NULL | |
4787 | }, **p; | |
461fb99c CW |
4788 | |
4789 | /* Called just before we write the hibernation image. | |
4790 | * | |
4791 | * We need to update the domain tracking to reflect that the CPU | |
4792 | * will be accessing all the pages to create and restore from the | |
4793 | * hibernation, and so upon restoration those pages will be in the | |
4794 | * CPU domain. | |
4795 | * | |
4796 | * To make sure the hibernation image contains the latest state, | |
4797 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4798 | * |
4799 | * To try and reduce the hibernation image, we manually shrink | |
4800 | * the objects as well. | |
461fb99c CW |
4801 | */ |
4802 | ||
6a800eab CW |
4803 | mutex_lock(&dev_priv->drm.struct_mutex); |
4804 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); | |
461fb99c | 4805 | |
7aab2d53 CW |
4806 | for (p = phases; *p; p++) { |
4807 | list_for_each_entry(obj, *p, global_list) { | |
4808 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4809 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4810 | } | |
461fb99c | 4811 | } |
6a800eab | 4812 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
4813 | |
4814 | return 0; | |
4815 | } | |
4816 | ||
f787a5f5 | 4817 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4818 | { |
f787a5f5 | 4819 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4820 | struct drm_i915_gem_request *request; |
b962442e EA |
4821 | |
4822 | /* Clean up our request list when the client is going away, so that | |
4823 | * later retire_requests won't dereference our soon-to-be-gone | |
4824 | * file_priv. | |
4825 | */ | |
1c25595f | 4826 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4827 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4828 | request->file_priv = NULL; |
1c25595f | 4829 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4830 | |
2e1b8730 | 4831 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4832 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4833 | list_del(&file_priv->rps.link); |
8d3afd7d | 4834 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4835 | } |
b29c19b6 CW |
4836 | } |
4837 | ||
4838 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4839 | { | |
4840 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4841 | int ret; |
b29c19b6 CW |
4842 | |
4843 | DRM_DEBUG_DRIVER("\n"); | |
4844 | ||
4845 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4846 | if (!file_priv) | |
4847 | return -ENOMEM; | |
4848 | ||
4849 | file->driver_priv = file_priv; | |
f19ec8cb | 4850 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4851 | file_priv->file = file; |
2e1b8730 | 4852 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4853 | |
4854 | spin_lock_init(&file_priv->mm.lock); | |
4855 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4856 | |
c80ff16e | 4857 | file_priv->bsd_engine = -1; |
de1add36 | 4858 | |
e422b888 BW |
4859 | ret = i915_gem_context_open(dev, file); |
4860 | if (ret) | |
4861 | kfree(file_priv); | |
b29c19b6 | 4862 | |
e422b888 | 4863 | return ret; |
b29c19b6 CW |
4864 | } |
4865 | ||
b680c37a DV |
4866 | /** |
4867 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4868 | * @old: current GEM buffer for the frontbuffer slots |
4869 | * @new: new GEM buffer for the frontbuffer slots | |
4870 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4871 | * |
4872 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4873 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4874 | */ | |
a071fa00 DV |
4875 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4876 | struct drm_i915_gem_object *new, | |
4877 | unsigned frontbuffer_bits) | |
4878 | { | |
faf5bf0a CW |
4879 | /* Control of individual bits within the mask are guarded by |
4880 | * the owning plane->mutex, i.e. we can never see concurrent | |
4881 | * manipulation of individual bits. But since the bitfield as a whole | |
4882 | * is updated using RMW, we need to use atomics in order to update | |
4883 | * the bits. | |
4884 | */ | |
4885 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4886 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4887 | ||
a071fa00 | 4888 | if (old) { |
faf5bf0a CW |
4889 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4890 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4891 | } |
4892 | ||
4893 | if (new) { | |
faf5bf0a CW |
4894 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4895 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4896 | } |
4897 | } | |
4898 | ||
ea70299d DG |
4899 | /* Allocate a new GEM object and fill it with the supplied data */ |
4900 | struct drm_i915_gem_object * | |
4901 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4902 | const void *data, size_t size) | |
4903 | { | |
4904 | struct drm_i915_gem_object *obj; | |
4905 | struct sg_table *sg; | |
4906 | size_t bytes; | |
4907 | int ret; | |
4908 | ||
d37cd8a8 | 4909 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4910 | if (IS_ERR(obj)) |
ea70299d DG |
4911 | return obj; |
4912 | ||
4913 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4914 | if (ret) | |
4915 | goto fail; | |
4916 | ||
a4f5ea64 | 4917 | ret = i915_gem_object_pin_pages(obj); |
ea70299d DG |
4918 | if (ret) |
4919 | goto fail; | |
4920 | ||
a4f5ea64 | 4921 | sg = obj->mm.pages; |
ea70299d | 4922 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
a4f5ea64 | 4923 | obj->mm.dirty = true; /* Backing store is now out of date */ |
ea70299d DG |
4924 | i915_gem_object_unpin_pages(obj); |
4925 | ||
4926 | if (WARN_ON(bytes != size)) { | |
4927 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4928 | ret = -EFAULT; | |
4929 | goto fail; | |
4930 | } | |
4931 | ||
4932 | return obj; | |
4933 | ||
4934 | fail: | |
f8c417cd | 4935 | i915_gem_object_put(obj); |
ea70299d DG |
4936 | return ERR_PTR(ret); |
4937 | } | |
96d77634 CW |
4938 | |
4939 | struct scatterlist * | |
4940 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
4941 | unsigned int n, | |
4942 | unsigned int *offset) | |
4943 | { | |
a4f5ea64 | 4944 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
4945 | struct scatterlist *sg; |
4946 | unsigned int idx, count; | |
4947 | ||
4948 | might_sleep(); | |
4949 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 4950 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
4951 | |
4952 | /* As we iterate forward through the sg, we record each entry in a | |
4953 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
4954 | * this index previously, we will have an entry for it. | |
4955 | * | |
4956 | * Initial lookup is O(N), but this is amortized to O(1) for | |
4957 | * sequential page access (where each new request is consecutive | |
4958 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
4959 | * i.e. O(1) with a large constant! | |
4960 | */ | |
4961 | if (n < READ_ONCE(iter->sg_idx)) | |
4962 | goto lookup; | |
4963 | ||
4964 | mutex_lock(&iter->lock); | |
4965 | ||
4966 | /* We prefer to reuse the last sg so that repeated lookup of this | |
4967 | * (or the subsequent) sg are fast - comparing against the last | |
4968 | * sg is faster than going through the radixtree. | |
4969 | */ | |
4970 | ||
4971 | sg = iter->sg_pos; | |
4972 | idx = iter->sg_idx; | |
4973 | count = __sg_page_count(sg); | |
4974 | ||
4975 | while (idx + count <= n) { | |
4976 | unsigned long exception, i; | |
4977 | int ret; | |
4978 | ||
4979 | /* If we cannot allocate and insert this entry, or the | |
4980 | * individual pages from this range, cancel updating the | |
4981 | * sg_idx so that on this lookup we are forced to linearly | |
4982 | * scan onwards, but on future lookups we will try the | |
4983 | * insertion again (in which case we need to be careful of | |
4984 | * the error return reporting that we have already inserted | |
4985 | * this index). | |
4986 | */ | |
4987 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
4988 | if (ret && ret != -EEXIST) | |
4989 | goto scan; | |
4990 | ||
4991 | exception = | |
4992 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
4993 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4994 | for (i = 1; i < count; i++) { | |
4995 | ret = radix_tree_insert(&iter->radix, idx + i, | |
4996 | (void *)exception); | |
4997 | if (ret && ret != -EEXIST) | |
4998 | goto scan; | |
4999 | } | |
5000 | ||
5001 | idx += count; | |
5002 | sg = ____sg_next(sg); | |
5003 | count = __sg_page_count(sg); | |
5004 | } | |
5005 | ||
5006 | scan: | |
5007 | iter->sg_pos = sg; | |
5008 | iter->sg_idx = idx; | |
5009 | ||
5010 | mutex_unlock(&iter->lock); | |
5011 | ||
5012 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
5013 | goto lookup; | |
5014 | ||
5015 | /* In case we failed to insert the entry into the radixtree, we need | |
5016 | * to look beyond the current sg. | |
5017 | */ | |
5018 | while (idx + count <= n) { | |
5019 | idx += count; | |
5020 | sg = ____sg_next(sg); | |
5021 | count = __sg_page_count(sg); | |
5022 | } | |
5023 | ||
5024 | *offset = n - idx; | |
5025 | return sg; | |
5026 | ||
5027 | lookup: | |
5028 | rcu_read_lock(); | |
5029 | ||
5030 | sg = radix_tree_lookup(&iter->radix, n); | |
5031 | GEM_BUG_ON(!sg); | |
5032 | ||
5033 | /* If this index is in the middle of multi-page sg entry, | |
5034 | * the radixtree will contain an exceptional entry that points | |
5035 | * to the start of that range. We will return the pointer to | |
5036 | * the base page and the offset of this page within the | |
5037 | * sg entry's range. | |
5038 | */ | |
5039 | *offset = 0; | |
5040 | if (unlikely(radix_tree_exception(sg))) { | |
5041 | unsigned long base = | |
5042 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5043 | ||
5044 | sg = radix_tree_lookup(&iter->radix, base); | |
5045 | GEM_BUG_ON(!sg); | |
5046 | ||
5047 | *offset = n - base; | |
5048 | } | |
5049 | ||
5050 | rcu_read_unlock(); | |
5051 | ||
5052 | return sg; | |
5053 | } | |
5054 | ||
5055 | struct page * | |
5056 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
5057 | { | |
5058 | struct scatterlist *sg; | |
5059 | unsigned int offset; | |
5060 | ||
5061 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
5062 | ||
5063 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5064 | return nth_page(sg_page(sg), offset); | |
5065 | } | |
5066 | ||
5067 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
5068 | struct page * | |
5069 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
5070 | unsigned int n) | |
5071 | { | |
5072 | struct page *page; | |
5073 | ||
5074 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 5075 | if (!obj->mm.dirty) |
96d77634 CW |
5076 | set_page_dirty(page); |
5077 | ||
5078 | return page; | |
5079 | } | |
5080 | ||
5081 | dma_addr_t | |
5082 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
5083 | unsigned long n) | |
5084 | { | |
5085 | struct scatterlist *sg; | |
5086 | unsigned int offset; | |
5087 | ||
5088 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5089 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
5090 | } |