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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
ceabbba5 | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 57 | struct shrink_control *sc); |
ceabbba5 | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 59 | struct shrink_control *sc); |
2cfcd32a CW |
60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
61 | unsigned long event, | |
62 | void *ptr); | |
d9973b43 | 63 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
31169714 | 64 | |
c76ce038 CW |
65 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
66 | enum i915_cache_level level) | |
67 | { | |
68 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
69 | } | |
70 | ||
2c22569b CW |
71 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
72 | { | |
73 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
74 | return true; | |
75 | ||
76 | return obj->pin_display; | |
77 | } | |
78 | ||
61050808 CW |
79 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
80 | { | |
81 | if (obj->tiling_mode) | |
82 | i915_gem_release_mmap(obj); | |
83 | ||
84 | /* As we do not have an associated fence register, we will force | |
85 | * a tiling change if we ever need to acquire one. | |
86 | */ | |
5d82e3e6 | 87 | obj->fence_dirty = false; |
61050808 CW |
88 | obj->fence_reg = I915_FENCE_REG_NONE; |
89 | } | |
90 | ||
73aa808f CW |
91 | /* some bookkeeping */ |
92 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
93 | size_t size) | |
94 | { | |
c20e8355 | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | dev_priv->mm.object_count++; |
97 | dev_priv->mm.object_memory += size; | |
c20e8355 | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
102 | size_t size) | |
103 | { | |
c20e8355 | 104 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | dev_priv->mm.object_count--; |
106 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 107 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
108 | } |
109 | ||
21dd3734 | 110 | static int |
33196ded | 111 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 112 | { |
30dbf0c0 CW |
113 | int ret; |
114 | ||
7abb690a DV |
115 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
116 | i915_terminally_wedged(error)) | |
1f83fee0 | 117 | if (EXIT_COND) |
30dbf0c0 CW |
118 | return 0; |
119 | ||
0a6759c6 DV |
120 | /* |
121 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
122 | * userspace. If it takes that long something really bad is going on and | |
123 | * we should simply try to bail out and fail as gracefully as possible. | |
124 | */ | |
1f83fee0 DV |
125 | ret = wait_event_interruptible_timeout(error->reset_queue, |
126 | EXIT_COND, | |
127 | 10*HZ); | |
0a6759c6 DV |
128 | if (ret == 0) { |
129 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
130 | return -EIO; | |
131 | } else if (ret < 0) { | |
30dbf0c0 | 132 | return ret; |
0a6759c6 | 133 | } |
1f83fee0 | 134 | #undef EXIT_COND |
30dbf0c0 | 135 | |
21dd3734 | 136 | return 0; |
30dbf0c0 CW |
137 | } |
138 | ||
54cf91dc | 139 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 140 | { |
33196ded | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
142 | int ret; |
143 | ||
33196ded | 144 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
145 | if (ret) |
146 | return ret; | |
147 | ||
148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
149 | if (ret) | |
150 | return ret; | |
151 | ||
23bc5982 | 152 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
153 | return 0; |
154 | } | |
30dbf0c0 | 155 | |
7d1c4804 | 156 | static inline bool |
05394f39 | 157 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 158 | { |
9843877d | 159 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
160 | } |
161 | ||
5a125c3c EA |
162 | int |
163 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 164 | struct drm_file *file) |
5a125c3c | 165 | { |
73aa808f | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 167 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
168 | struct drm_i915_gem_object *obj; |
169 | size_t pinned; | |
5a125c3c | 170 | |
6299f992 | 171 | pinned = 0; |
73aa808f | 172 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 173 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 174 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 175 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 176 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 177 | |
853ba5d2 | 178 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 179 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 180 | |
5a125c3c EA |
181 | return 0; |
182 | } | |
183 | ||
6a2c4232 CW |
184 | static int |
185 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 186 | { |
6a2c4232 CW |
187 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
188 | char *vaddr = obj->phys_handle->vaddr; | |
189 | struct sg_table *st; | |
190 | struct scatterlist *sg; | |
191 | int i; | |
00731155 | 192 | |
6a2c4232 CW |
193 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
194 | return -EINVAL; | |
195 | ||
196 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
197 | struct page *page; | |
198 | char *src; | |
199 | ||
200 | page = shmem_read_mapping_page(mapping, i); | |
201 | if (IS_ERR(page)) | |
202 | return PTR_ERR(page); | |
203 | ||
204 | src = kmap_atomic(page); | |
205 | memcpy(vaddr, src, PAGE_SIZE); | |
206 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
207 | kunmap_atomic(src); | |
208 | ||
209 | page_cache_release(page); | |
210 | vaddr += PAGE_SIZE; | |
211 | } | |
212 | ||
213 | i915_gem_chipset_flush(obj->base.dev); | |
214 | ||
215 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
216 | if (st == NULL) | |
217 | return -ENOMEM; | |
218 | ||
219 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
220 | kfree(st); | |
221 | return -ENOMEM; | |
222 | } | |
223 | ||
224 | sg = st->sgl; | |
225 | sg->offset = 0; | |
226 | sg->length = obj->base.size; | |
00731155 | 227 | |
6a2c4232 CW |
228 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
229 | sg_dma_len(sg) = obj->base.size; | |
230 | ||
231 | obj->pages = st; | |
232 | obj->has_dma_mapping = true; | |
233 | return 0; | |
234 | } | |
235 | ||
236 | static void | |
237 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
238 | { | |
239 | int ret; | |
240 | ||
241 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 242 | |
6a2c4232 CW |
243 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
244 | if (ret) { | |
245 | /* In the event of a disaster, abandon all caches and | |
246 | * hope for the best. | |
247 | */ | |
248 | WARN_ON(ret != -EIO); | |
249 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
250 | } | |
251 | ||
252 | if (obj->madv == I915_MADV_DONTNEED) | |
253 | obj->dirty = 0; | |
254 | ||
255 | if (obj->dirty) { | |
00731155 | 256 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 257 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
258 | int i; |
259 | ||
260 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
261 | struct page *page; |
262 | char *dst; | |
263 | ||
264 | page = shmem_read_mapping_page(mapping, i); | |
265 | if (IS_ERR(page)) | |
266 | continue; | |
267 | ||
268 | dst = kmap_atomic(page); | |
269 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
270 | memcpy(dst, vaddr, PAGE_SIZE); | |
271 | kunmap_atomic(dst); | |
272 | ||
273 | set_page_dirty(page); | |
274 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 275 | mark_page_accessed(page); |
6a2c4232 | 276 | page_cache_release(page); |
00731155 CW |
277 | vaddr += PAGE_SIZE; |
278 | } | |
6a2c4232 | 279 | obj->dirty = 0; |
00731155 CW |
280 | } |
281 | ||
6a2c4232 CW |
282 | sg_free_table(obj->pages); |
283 | kfree(obj->pages); | |
284 | ||
285 | obj->has_dma_mapping = false; | |
286 | } | |
287 | ||
288 | static void | |
289 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
290 | { | |
291 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
292 | } | |
293 | ||
294 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
295 | .get_pages = i915_gem_object_get_pages_phys, | |
296 | .put_pages = i915_gem_object_put_pages_phys, | |
297 | .release = i915_gem_object_release_phys, | |
298 | }; | |
299 | ||
300 | static int | |
301 | drop_pages(struct drm_i915_gem_object *obj) | |
302 | { | |
303 | struct i915_vma *vma, *next; | |
304 | int ret; | |
305 | ||
306 | drm_gem_object_reference(&obj->base); | |
307 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
308 | if (i915_vma_unbind(vma)) | |
309 | break; | |
310 | ||
311 | ret = i915_gem_object_put_pages(obj); | |
312 | drm_gem_object_unreference(&obj->base); | |
313 | ||
314 | return ret; | |
00731155 CW |
315 | } |
316 | ||
317 | int | |
318 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
319 | int align) | |
320 | { | |
321 | drm_dma_handle_t *phys; | |
6a2c4232 | 322 | int ret; |
00731155 CW |
323 | |
324 | if (obj->phys_handle) { | |
325 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
326 | return -EBUSY; | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | if (obj->madv != I915_MADV_WILLNEED) | |
332 | return -EFAULT; | |
333 | ||
334 | if (obj->base.filp == NULL) | |
335 | return -EINVAL; | |
336 | ||
6a2c4232 CW |
337 | ret = drop_pages(obj); |
338 | if (ret) | |
339 | return ret; | |
340 | ||
00731155 CW |
341 | /* create a new object */ |
342 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
343 | if (!phys) | |
344 | return -ENOMEM; | |
345 | ||
00731155 | 346 | obj->phys_handle = phys; |
6a2c4232 CW |
347 | obj->ops = &i915_gem_phys_ops; |
348 | ||
349 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
350 | } |
351 | ||
352 | static int | |
353 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
354 | struct drm_i915_gem_pwrite *args, | |
355 | struct drm_file *file_priv) | |
356 | { | |
357 | struct drm_device *dev = obj->base.dev; | |
358 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
359 | char __user *user_data = to_user_ptr(args->data_ptr); | |
6a2c4232 CW |
360 | int ret; |
361 | ||
362 | /* We manually control the domain here and pretend that it | |
363 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
364 | */ | |
365 | ret = i915_gem_object_wait_rendering(obj, false); | |
366 | if (ret) | |
367 | return ret; | |
00731155 CW |
368 | |
369 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
370 | unsigned long unwritten; | |
371 | ||
372 | /* The physical object once assigned is fixed for the lifetime | |
373 | * of the obj, so we can safely drop the lock and continue | |
374 | * to access vaddr. | |
375 | */ | |
376 | mutex_unlock(&dev->struct_mutex); | |
377 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
378 | mutex_lock(&dev->struct_mutex); | |
379 | if (unwritten) | |
380 | return -EFAULT; | |
381 | } | |
382 | ||
6a2c4232 | 383 | drm_clflush_virt_range(vaddr, args->size); |
00731155 CW |
384 | i915_gem_chipset_flush(dev); |
385 | return 0; | |
386 | } | |
387 | ||
42dcedd4 CW |
388 | void *i915_gem_object_alloc(struct drm_device *dev) |
389 | { | |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 391 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
392 | } |
393 | ||
394 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
395 | { | |
396 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
397 | kmem_cache_free(dev_priv->slab, obj); | |
398 | } | |
399 | ||
ff72145b DA |
400 | static int |
401 | i915_gem_create(struct drm_file *file, | |
402 | struct drm_device *dev, | |
403 | uint64_t size, | |
355a7018 | 404 | bool dumb, |
ff72145b | 405 | uint32_t *handle_p) |
673a394b | 406 | { |
05394f39 | 407 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
408 | int ret; |
409 | u32 handle; | |
673a394b | 410 | |
ff72145b | 411 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
412 | if (size == 0) |
413 | return -EINVAL; | |
673a394b EA |
414 | |
415 | /* Allocate the new object */ | |
ff72145b | 416 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
417 | if (obj == NULL) |
418 | return -ENOMEM; | |
419 | ||
355a7018 | 420 | obj->base.dumb = dumb; |
05394f39 | 421 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 422 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
423 | drm_gem_object_unreference_unlocked(&obj->base); |
424 | if (ret) | |
425 | return ret; | |
202f2fef | 426 | |
ff72145b | 427 | *handle_p = handle; |
673a394b EA |
428 | return 0; |
429 | } | |
430 | ||
ff72145b DA |
431 | int |
432 | i915_gem_dumb_create(struct drm_file *file, | |
433 | struct drm_device *dev, | |
434 | struct drm_mode_create_dumb *args) | |
435 | { | |
436 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 437 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
438 | args->size = args->pitch * args->height; |
439 | return i915_gem_create(file, dev, | |
355a7018 | 440 | args->size, true, &args->handle); |
ff72145b DA |
441 | } |
442 | ||
ff72145b DA |
443 | /** |
444 | * Creates a new mm object and returns a handle to it. | |
445 | */ | |
446 | int | |
447 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
448 | struct drm_file *file) | |
449 | { | |
450 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 451 | |
ff72145b | 452 | return i915_gem_create(file, dev, |
355a7018 | 453 | args->size, false, &args->handle); |
ff72145b DA |
454 | } |
455 | ||
8461d226 DV |
456 | static inline int |
457 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
458 | const char *gpu_vaddr, int gpu_offset, | |
459 | int length) | |
460 | { | |
461 | int ret, cpu_offset = 0; | |
462 | ||
463 | while (length > 0) { | |
464 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
465 | int this_length = min(cacheline_end - gpu_offset, length); | |
466 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
467 | ||
468 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
469 | gpu_vaddr + swizzled_gpu_offset, | |
470 | this_length); | |
471 | if (ret) | |
472 | return ret + length; | |
473 | ||
474 | cpu_offset += this_length; | |
475 | gpu_offset += this_length; | |
476 | length -= this_length; | |
477 | } | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
8c59967c | 482 | static inline int |
4f0c7cfb BW |
483 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
484 | const char __user *cpu_vaddr, | |
8c59967c DV |
485 | int length) |
486 | { | |
487 | int ret, cpu_offset = 0; | |
488 | ||
489 | while (length > 0) { | |
490 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
491 | int this_length = min(cacheline_end - gpu_offset, length); | |
492 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
493 | ||
494 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
495 | cpu_vaddr + cpu_offset, | |
496 | this_length); | |
497 | if (ret) | |
498 | return ret + length; | |
499 | ||
500 | cpu_offset += this_length; | |
501 | gpu_offset += this_length; | |
502 | length -= this_length; | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
4c914c0c BV |
508 | /* |
509 | * Pins the specified object's pages and synchronizes the object with | |
510 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
511 | * flush the object from the CPU cache. | |
512 | */ | |
513 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
514 | int *needs_clflush) | |
515 | { | |
516 | int ret; | |
517 | ||
518 | *needs_clflush = 0; | |
519 | ||
520 | if (!obj->base.filp) | |
521 | return -EINVAL; | |
522 | ||
523 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
524 | /* If we're not in the cpu read domain, set ourself into the gtt | |
525 | * read domain and manually flush cachelines (if required). This | |
526 | * optimizes for the case when the gpu will dirty the data | |
527 | * anyway again before the next pread happens. */ | |
528 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
529 | obj->cache_level); | |
530 | ret = i915_gem_object_wait_rendering(obj, true); | |
531 | if (ret) | |
532 | return ret; | |
c8725f3d CW |
533 | |
534 | i915_gem_object_retire(obj); | |
4c914c0c BV |
535 | } |
536 | ||
537 | ret = i915_gem_object_get_pages(obj); | |
538 | if (ret) | |
539 | return ret; | |
540 | ||
541 | i915_gem_object_pin_pages(obj); | |
542 | ||
543 | return ret; | |
544 | } | |
545 | ||
d174bd64 DV |
546 | /* Per-page copy function for the shmem pread fastpath. |
547 | * Flushes invalid cachelines before reading the target if | |
548 | * needs_clflush is set. */ | |
eb01459f | 549 | static int |
d174bd64 DV |
550 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
551 | char __user *user_data, | |
552 | bool page_do_bit17_swizzling, bool needs_clflush) | |
553 | { | |
554 | char *vaddr; | |
555 | int ret; | |
556 | ||
e7e58eb5 | 557 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
558 | return -EINVAL; |
559 | ||
560 | vaddr = kmap_atomic(page); | |
561 | if (needs_clflush) | |
562 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
563 | page_length); | |
564 | ret = __copy_to_user_inatomic(user_data, | |
565 | vaddr + shmem_page_offset, | |
566 | page_length); | |
567 | kunmap_atomic(vaddr); | |
568 | ||
f60d7f0c | 569 | return ret ? -EFAULT : 0; |
d174bd64 DV |
570 | } |
571 | ||
23c18c71 DV |
572 | static void |
573 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
574 | bool swizzled) | |
575 | { | |
e7e58eb5 | 576 | if (unlikely(swizzled)) { |
23c18c71 DV |
577 | unsigned long start = (unsigned long) addr; |
578 | unsigned long end = (unsigned long) addr + length; | |
579 | ||
580 | /* For swizzling simply ensure that we always flush both | |
581 | * channels. Lame, but simple and it works. Swizzled | |
582 | * pwrite/pread is far from a hotpath - current userspace | |
583 | * doesn't use it at all. */ | |
584 | start = round_down(start, 128); | |
585 | end = round_up(end, 128); | |
586 | ||
587 | drm_clflush_virt_range((void *)start, end - start); | |
588 | } else { | |
589 | drm_clflush_virt_range(addr, length); | |
590 | } | |
591 | ||
592 | } | |
593 | ||
d174bd64 DV |
594 | /* Only difference to the fast-path function is that this can handle bit17 |
595 | * and uses non-atomic copy and kmap functions. */ | |
596 | static int | |
597 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
598 | char __user *user_data, | |
599 | bool page_do_bit17_swizzling, bool needs_clflush) | |
600 | { | |
601 | char *vaddr; | |
602 | int ret; | |
603 | ||
604 | vaddr = kmap(page); | |
605 | if (needs_clflush) | |
23c18c71 DV |
606 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
607 | page_length, | |
608 | page_do_bit17_swizzling); | |
d174bd64 DV |
609 | |
610 | if (page_do_bit17_swizzling) | |
611 | ret = __copy_to_user_swizzled(user_data, | |
612 | vaddr, shmem_page_offset, | |
613 | page_length); | |
614 | else | |
615 | ret = __copy_to_user(user_data, | |
616 | vaddr + shmem_page_offset, | |
617 | page_length); | |
618 | kunmap(page); | |
619 | ||
f60d7f0c | 620 | return ret ? - EFAULT : 0; |
d174bd64 DV |
621 | } |
622 | ||
eb01459f | 623 | static int |
dbf7bff0 DV |
624 | i915_gem_shmem_pread(struct drm_device *dev, |
625 | struct drm_i915_gem_object *obj, | |
626 | struct drm_i915_gem_pread *args, | |
627 | struct drm_file *file) | |
eb01459f | 628 | { |
8461d226 | 629 | char __user *user_data; |
eb01459f | 630 | ssize_t remain; |
8461d226 | 631 | loff_t offset; |
eb2c0c81 | 632 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 633 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 634 | int prefaulted = 0; |
8489731c | 635 | int needs_clflush = 0; |
67d5a50c | 636 | struct sg_page_iter sg_iter; |
eb01459f | 637 | |
2bb4629a | 638 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
639 | remain = args->size; |
640 | ||
8461d226 | 641 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 642 | |
4c914c0c | 643 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
644 | if (ret) |
645 | return ret; | |
646 | ||
8461d226 | 647 | offset = args->offset; |
eb01459f | 648 | |
67d5a50c ID |
649 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
650 | offset >> PAGE_SHIFT) { | |
2db76d7c | 651 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
652 | |
653 | if (remain <= 0) | |
654 | break; | |
655 | ||
eb01459f EA |
656 | /* Operation in this page |
657 | * | |
eb01459f | 658 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
659 | * page_length = bytes to copy for this page |
660 | */ | |
c8cbbb8b | 661 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
662 | page_length = remain; |
663 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
664 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 665 | |
8461d226 DV |
666 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
667 | (page_to_phys(page) & (1 << 17)) != 0; | |
668 | ||
d174bd64 DV |
669 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
670 | user_data, page_do_bit17_swizzling, | |
671 | needs_clflush); | |
672 | if (ret == 0) | |
673 | goto next_page; | |
dbf7bff0 | 674 | |
dbf7bff0 DV |
675 | mutex_unlock(&dev->struct_mutex); |
676 | ||
d330a953 | 677 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 678 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
679 | /* Userspace is tricking us, but we've already clobbered |
680 | * its pages with the prefault and promised to write the | |
681 | * data up to the first fault. Hence ignore any errors | |
682 | * and just continue. */ | |
683 | (void)ret; | |
684 | prefaulted = 1; | |
685 | } | |
eb01459f | 686 | |
d174bd64 DV |
687 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
688 | user_data, page_do_bit17_swizzling, | |
689 | needs_clflush); | |
eb01459f | 690 | |
dbf7bff0 | 691 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 692 | |
f60d7f0c | 693 | if (ret) |
8461d226 | 694 | goto out; |
8461d226 | 695 | |
17793c9a | 696 | next_page: |
eb01459f | 697 | remain -= page_length; |
8461d226 | 698 | user_data += page_length; |
eb01459f EA |
699 | offset += page_length; |
700 | } | |
701 | ||
4f27b75d | 702 | out: |
f60d7f0c CW |
703 | i915_gem_object_unpin_pages(obj); |
704 | ||
eb01459f EA |
705 | return ret; |
706 | } | |
707 | ||
673a394b EA |
708 | /** |
709 | * Reads data from the object referenced by handle. | |
710 | * | |
711 | * On error, the contents of *data are undefined. | |
712 | */ | |
713 | int | |
714 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 715 | struct drm_file *file) |
673a394b EA |
716 | { |
717 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 718 | struct drm_i915_gem_object *obj; |
35b62a89 | 719 | int ret = 0; |
673a394b | 720 | |
51311d0a CW |
721 | if (args->size == 0) |
722 | return 0; | |
723 | ||
724 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 725 | to_user_ptr(args->data_ptr), |
51311d0a CW |
726 | args->size)) |
727 | return -EFAULT; | |
728 | ||
4f27b75d | 729 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 730 | if (ret) |
4f27b75d | 731 | return ret; |
673a394b | 732 | |
05394f39 | 733 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 734 | if (&obj->base == NULL) { |
1d7cfea1 CW |
735 | ret = -ENOENT; |
736 | goto unlock; | |
4f27b75d | 737 | } |
673a394b | 738 | |
7dcd2499 | 739 | /* Bounds check source. */ |
05394f39 CW |
740 | if (args->offset > obj->base.size || |
741 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 742 | ret = -EINVAL; |
35b62a89 | 743 | goto out; |
ce9d419d CW |
744 | } |
745 | ||
1286ff73 DV |
746 | /* prime objects have no backing filp to GEM pread/pwrite |
747 | * pages from. | |
748 | */ | |
749 | if (!obj->base.filp) { | |
750 | ret = -EINVAL; | |
751 | goto out; | |
752 | } | |
753 | ||
db53a302 CW |
754 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
755 | ||
dbf7bff0 | 756 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 757 | |
35b62a89 | 758 | out: |
05394f39 | 759 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 760 | unlock: |
4f27b75d | 761 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 762 | return ret; |
673a394b EA |
763 | } |
764 | ||
0839ccb8 KP |
765 | /* This is the fast write path which cannot handle |
766 | * page faults in the source data | |
9b7530cc | 767 | */ |
0839ccb8 KP |
768 | |
769 | static inline int | |
770 | fast_user_write(struct io_mapping *mapping, | |
771 | loff_t page_base, int page_offset, | |
772 | char __user *user_data, | |
773 | int length) | |
9b7530cc | 774 | { |
4f0c7cfb BW |
775 | void __iomem *vaddr_atomic; |
776 | void *vaddr; | |
0839ccb8 | 777 | unsigned long unwritten; |
9b7530cc | 778 | |
3e4d3af5 | 779 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
780 | /* We can use the cpu mem copy function because this is X86. */ |
781 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
782 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 783 | user_data, length); |
3e4d3af5 | 784 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 785 | return unwritten; |
0839ccb8 KP |
786 | } |
787 | ||
3de09aa3 EA |
788 | /** |
789 | * This is the fast pwrite path, where we copy the data directly from the | |
790 | * user into the GTT, uncached. | |
791 | */ | |
673a394b | 792 | static int |
05394f39 CW |
793 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
794 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 795 | struct drm_i915_gem_pwrite *args, |
05394f39 | 796 | struct drm_file *file) |
673a394b | 797 | { |
3e31c6c0 | 798 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 799 | ssize_t remain; |
0839ccb8 | 800 | loff_t offset, page_base; |
673a394b | 801 | char __user *user_data; |
935aaa69 DV |
802 | int page_offset, page_length, ret; |
803 | ||
1ec9e26d | 804 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
805 | if (ret) |
806 | goto out; | |
807 | ||
808 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
809 | if (ret) | |
810 | goto out_unpin; | |
811 | ||
812 | ret = i915_gem_object_put_fence(obj); | |
813 | if (ret) | |
814 | goto out_unpin; | |
673a394b | 815 | |
2bb4629a | 816 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 817 | remain = args->size; |
673a394b | 818 | |
f343c5f6 | 819 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
820 | |
821 | while (remain > 0) { | |
822 | /* Operation in this page | |
823 | * | |
0839ccb8 KP |
824 | * page_base = page offset within aperture |
825 | * page_offset = offset within page | |
826 | * page_length = bytes to copy for this page | |
673a394b | 827 | */ |
c8cbbb8b CW |
828 | page_base = offset & PAGE_MASK; |
829 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
830 | page_length = remain; |
831 | if ((page_offset + remain) > PAGE_SIZE) | |
832 | page_length = PAGE_SIZE - page_offset; | |
833 | ||
0839ccb8 | 834 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
835 | * source page isn't available. Return the error and we'll |
836 | * retry in the slow path. | |
0839ccb8 | 837 | */ |
5d4545ae | 838 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
839 | page_offset, user_data, page_length)) { |
840 | ret = -EFAULT; | |
841 | goto out_unpin; | |
842 | } | |
673a394b | 843 | |
0839ccb8 KP |
844 | remain -= page_length; |
845 | user_data += page_length; | |
846 | offset += page_length; | |
673a394b | 847 | } |
673a394b | 848 | |
935aaa69 | 849 | out_unpin: |
d7f46fc4 | 850 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 851 | out: |
3de09aa3 | 852 | return ret; |
673a394b EA |
853 | } |
854 | ||
d174bd64 DV |
855 | /* Per-page copy function for the shmem pwrite fastpath. |
856 | * Flushes invalid cachelines before writing to the target if | |
857 | * needs_clflush_before is set and flushes out any written cachelines after | |
858 | * writing if needs_clflush is set. */ | |
3043c60c | 859 | static int |
d174bd64 DV |
860 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
861 | char __user *user_data, | |
862 | bool page_do_bit17_swizzling, | |
863 | bool needs_clflush_before, | |
864 | bool needs_clflush_after) | |
673a394b | 865 | { |
d174bd64 | 866 | char *vaddr; |
673a394b | 867 | int ret; |
3de09aa3 | 868 | |
e7e58eb5 | 869 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 870 | return -EINVAL; |
3de09aa3 | 871 | |
d174bd64 DV |
872 | vaddr = kmap_atomic(page); |
873 | if (needs_clflush_before) | |
874 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
875 | page_length); | |
c2831a94 CW |
876 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
877 | user_data, page_length); | |
d174bd64 DV |
878 | if (needs_clflush_after) |
879 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
880 | page_length); | |
881 | kunmap_atomic(vaddr); | |
3de09aa3 | 882 | |
755d2218 | 883 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
884 | } |
885 | ||
d174bd64 DV |
886 | /* Only difference to the fast-path function is that this can handle bit17 |
887 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 888 | static int |
d174bd64 DV |
889 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
890 | char __user *user_data, | |
891 | bool page_do_bit17_swizzling, | |
892 | bool needs_clflush_before, | |
893 | bool needs_clflush_after) | |
673a394b | 894 | { |
d174bd64 DV |
895 | char *vaddr; |
896 | int ret; | |
e5281ccd | 897 | |
d174bd64 | 898 | vaddr = kmap(page); |
e7e58eb5 | 899 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
900 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
901 | page_length, | |
902 | page_do_bit17_swizzling); | |
d174bd64 DV |
903 | if (page_do_bit17_swizzling) |
904 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
905 | user_data, |
906 | page_length); | |
d174bd64 DV |
907 | else |
908 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
909 | user_data, | |
910 | page_length); | |
911 | if (needs_clflush_after) | |
23c18c71 DV |
912 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
913 | page_length, | |
914 | page_do_bit17_swizzling); | |
d174bd64 | 915 | kunmap(page); |
40123c1f | 916 | |
755d2218 | 917 | return ret ? -EFAULT : 0; |
40123c1f EA |
918 | } |
919 | ||
40123c1f | 920 | static int |
e244a443 DV |
921 | i915_gem_shmem_pwrite(struct drm_device *dev, |
922 | struct drm_i915_gem_object *obj, | |
923 | struct drm_i915_gem_pwrite *args, | |
924 | struct drm_file *file) | |
40123c1f | 925 | { |
40123c1f | 926 | ssize_t remain; |
8c59967c DV |
927 | loff_t offset; |
928 | char __user *user_data; | |
eb2c0c81 | 929 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 930 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 931 | int hit_slowpath = 0; |
58642885 DV |
932 | int needs_clflush_after = 0; |
933 | int needs_clflush_before = 0; | |
67d5a50c | 934 | struct sg_page_iter sg_iter; |
40123c1f | 935 | |
2bb4629a | 936 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
937 | remain = args->size; |
938 | ||
8c59967c | 939 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 940 | |
58642885 DV |
941 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
942 | /* If we're not in the cpu write domain, set ourself into the gtt | |
943 | * write domain and manually flush cachelines (if required). This | |
944 | * optimizes for the case when the gpu will use the data | |
945 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 946 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
947 | ret = i915_gem_object_wait_rendering(obj, false); |
948 | if (ret) | |
949 | return ret; | |
c8725f3d CW |
950 | |
951 | i915_gem_object_retire(obj); | |
58642885 | 952 | } |
c76ce038 CW |
953 | /* Same trick applies to invalidate partially written cachelines read |
954 | * before writing. */ | |
955 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
956 | needs_clflush_before = | |
957 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 958 | |
755d2218 CW |
959 | ret = i915_gem_object_get_pages(obj); |
960 | if (ret) | |
961 | return ret; | |
962 | ||
963 | i915_gem_object_pin_pages(obj); | |
964 | ||
673a394b | 965 | offset = args->offset; |
05394f39 | 966 | obj->dirty = 1; |
673a394b | 967 | |
67d5a50c ID |
968 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
969 | offset >> PAGE_SHIFT) { | |
2db76d7c | 970 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 971 | int partial_cacheline_write; |
e5281ccd | 972 | |
9da3da66 CW |
973 | if (remain <= 0) |
974 | break; | |
975 | ||
40123c1f EA |
976 | /* Operation in this page |
977 | * | |
40123c1f | 978 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
979 | * page_length = bytes to copy for this page |
980 | */ | |
c8cbbb8b | 981 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
982 | |
983 | page_length = remain; | |
984 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
985 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 986 | |
58642885 DV |
987 | /* If we don't overwrite a cacheline completely we need to be |
988 | * careful to have up-to-date data by first clflushing. Don't | |
989 | * overcomplicate things and flush the entire patch. */ | |
990 | partial_cacheline_write = needs_clflush_before && | |
991 | ((shmem_page_offset | page_length) | |
992 | & (boot_cpu_data.x86_clflush_size - 1)); | |
993 | ||
8c59967c DV |
994 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
995 | (page_to_phys(page) & (1 << 17)) != 0; | |
996 | ||
d174bd64 DV |
997 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
998 | user_data, page_do_bit17_swizzling, | |
999 | partial_cacheline_write, | |
1000 | needs_clflush_after); | |
1001 | if (ret == 0) | |
1002 | goto next_page; | |
e244a443 DV |
1003 | |
1004 | hit_slowpath = 1; | |
e244a443 | 1005 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1006 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1007 | user_data, page_do_bit17_swizzling, | |
1008 | partial_cacheline_write, | |
1009 | needs_clflush_after); | |
40123c1f | 1010 | |
e244a443 | 1011 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1012 | |
755d2218 | 1013 | if (ret) |
8c59967c | 1014 | goto out; |
8c59967c | 1015 | |
17793c9a | 1016 | next_page: |
40123c1f | 1017 | remain -= page_length; |
8c59967c | 1018 | user_data += page_length; |
40123c1f | 1019 | offset += page_length; |
673a394b EA |
1020 | } |
1021 | ||
fbd5a26d | 1022 | out: |
755d2218 CW |
1023 | i915_gem_object_unpin_pages(obj); |
1024 | ||
e244a443 | 1025 | if (hit_slowpath) { |
8dcf015e DV |
1026 | /* |
1027 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1028 | * cachelines in-line while writing and the object moved | |
1029 | * out of the cpu write domain while we've dropped the lock. | |
1030 | */ | |
1031 | if (!needs_clflush_after && | |
1032 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
1033 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
1034 | i915_gem_chipset_flush(dev); | |
e244a443 | 1035 | } |
8c59967c | 1036 | } |
673a394b | 1037 | |
58642885 | 1038 | if (needs_clflush_after) |
e76e9aeb | 1039 | i915_gem_chipset_flush(dev); |
58642885 | 1040 | |
40123c1f | 1041 | return ret; |
673a394b EA |
1042 | } |
1043 | ||
1044 | /** | |
1045 | * Writes data to the object referenced by handle. | |
1046 | * | |
1047 | * On error, the contents of the buffer that were to be modified are undefined. | |
1048 | */ | |
1049 | int | |
1050 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1051 | struct drm_file *file) |
673a394b EA |
1052 | { |
1053 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1054 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1055 | int ret; |
1056 | ||
1057 | if (args->size == 0) | |
1058 | return 0; | |
1059 | ||
1060 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1061 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1062 | args->size)) |
1063 | return -EFAULT; | |
1064 | ||
d330a953 | 1065 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1066 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1067 | args->size); | |
1068 | if (ret) | |
1069 | return -EFAULT; | |
1070 | } | |
673a394b | 1071 | |
fbd5a26d | 1072 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1073 | if (ret) |
fbd5a26d | 1074 | return ret; |
1d7cfea1 | 1075 | |
05394f39 | 1076 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1077 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1078 | ret = -ENOENT; |
1079 | goto unlock; | |
fbd5a26d | 1080 | } |
673a394b | 1081 | |
7dcd2499 | 1082 | /* Bounds check destination. */ |
05394f39 CW |
1083 | if (args->offset > obj->base.size || |
1084 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1085 | ret = -EINVAL; |
35b62a89 | 1086 | goto out; |
ce9d419d CW |
1087 | } |
1088 | ||
1286ff73 DV |
1089 | /* prime objects have no backing filp to GEM pread/pwrite |
1090 | * pages from. | |
1091 | */ | |
1092 | if (!obj->base.filp) { | |
1093 | ret = -EINVAL; | |
1094 | goto out; | |
1095 | } | |
1096 | ||
db53a302 CW |
1097 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1098 | ||
935aaa69 | 1099 | ret = -EFAULT; |
673a394b EA |
1100 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1101 | * it would end up going through the fenced access, and we'll get | |
1102 | * different detiling behavior between reading and writing. | |
1103 | * pread/pwrite currently are reading and writing from the CPU | |
1104 | * perspective, requiring manual detiling by the client. | |
1105 | */ | |
2c22569b CW |
1106 | if (obj->tiling_mode == I915_TILING_NONE && |
1107 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1108 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1109 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1110 | /* Note that the gtt paths might fail with non-page-backed user |
1111 | * pointers (e.g. gtt mappings when moving data between | |
1112 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1113 | } |
673a394b | 1114 | |
6a2c4232 CW |
1115 | if (ret == -EFAULT || ret == -ENOSPC) { |
1116 | if (obj->phys_handle) | |
1117 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1118 | else | |
1119 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1120 | } | |
5c0480f2 | 1121 | |
35b62a89 | 1122 | out: |
05394f39 | 1123 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1124 | unlock: |
fbd5a26d | 1125 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1126 | return ret; |
1127 | } | |
1128 | ||
b361237b | 1129 | int |
33196ded | 1130 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1131 | bool interruptible) |
1132 | { | |
1f83fee0 | 1133 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1134 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1135 | * -EIO unconditionally for these. */ | |
1136 | if (!interruptible) | |
1137 | return -EIO; | |
1138 | ||
1f83fee0 DV |
1139 | /* Recovery complete, but the reset failed ... */ |
1140 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1141 | return -EIO; |
1142 | ||
6689c167 MA |
1143 | /* |
1144 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1145 | * to work properly to reinit the hw state while the gpu is | |
1146 | * still marked as reset-in-progress. Handle this with a flag. | |
1147 | */ | |
1148 | if (!error->reload_in_reset) | |
1149 | return -EAGAIN; | |
b361237b CW |
1150 | } |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | /* | |
b6660d59 | 1156 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
b361237b | 1157 | */ |
84c33a64 | 1158 | int |
b6660d59 | 1159 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
b361237b CW |
1160 | { |
1161 | int ret; | |
1162 | ||
b6660d59 | 1163 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
b361237b CW |
1164 | |
1165 | ret = 0; | |
b6660d59 | 1166 | if (req == req->ring->outstanding_lazy_request) |
9400ae5c | 1167 | ret = i915_add_request(req->ring); |
b361237b CW |
1168 | |
1169 | return ret; | |
1170 | } | |
1171 | ||
094f9a54 CW |
1172 | static void fake_irq(unsigned long data) |
1173 | { | |
1174 | wake_up_process((struct task_struct *)data); | |
1175 | } | |
1176 | ||
1177 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1178 | struct intel_engine_cs *ring) |
094f9a54 CW |
1179 | { |
1180 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1181 | } | |
1182 | ||
b29c19b6 CW |
1183 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1184 | { | |
1185 | if (file_priv == NULL) | |
1186 | return true; | |
1187 | ||
1188 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1189 | } | |
1190 | ||
b361237b | 1191 | /** |
9c654818 JH |
1192 | * __i915_wait_request - wait until execution of request has finished |
1193 | * @req: duh! | |
1194 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1195 | * @interruptible: do an interruptible wait (normally yes) |
1196 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1197 | * | |
f69061be DV |
1198 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1199 | * values have been read by the caller in an smp safe manner. Where read-side | |
1200 | * locks are involved, it is sufficient to read the reset_counter before | |
1201 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1202 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1203 | * inserted. | |
1204 | * | |
9c654818 | 1205 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1206 | * errno with remaining time filled in timeout argument. |
1207 | */ | |
9c654818 | 1208 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1209 | unsigned reset_counter, |
b29c19b6 | 1210 | bool interruptible, |
5ed0bdf2 | 1211 | s64 *timeout, |
b29c19b6 | 1212 | struct drm_i915_file_private *file_priv) |
b361237b | 1213 | { |
9c654818 | 1214 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
3d13ef2e | 1215 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1216 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1217 | const bool irq_test_in_progress = |
1218 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1219 | DEFINE_WAIT(wait); |
47e9766d | 1220 | unsigned long timeout_expire; |
5ed0bdf2 | 1221 | s64 before, now; |
b361237b CW |
1222 | int ret; |
1223 | ||
9df7575f | 1224 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1225 | |
9c654818 JH |
1226 | if (i915_seqno_passed(ring->get_seqno(ring, true), |
1227 | i915_gem_request_get_seqno(req))) | |
b361237b CW |
1228 | return 0; |
1229 | ||
5ed0bdf2 | 1230 | timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0; |
b361237b | 1231 | |
ec5cc0f9 | 1232 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1233 | gen6_rps_boost(dev_priv); |
1234 | if (file_priv) | |
1235 | mod_delayed_work(dev_priv->wq, | |
1236 | &file_priv->mm.idle_work, | |
1237 | msecs_to_jiffies(100)); | |
1238 | } | |
1239 | ||
168c3f21 | 1240 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1241 | return -ENODEV; |
1242 | ||
094f9a54 | 1243 | /* Record current time in case interrupted by signal, or wedged */ |
74328ee5 | 1244 | trace_i915_gem_request_wait_begin(req); |
5ed0bdf2 | 1245 | before = ktime_get_raw_ns(); |
094f9a54 CW |
1246 | for (;;) { |
1247 | struct timer_list timer; | |
b361237b | 1248 | |
094f9a54 CW |
1249 | prepare_to_wait(&ring->irq_queue, &wait, |
1250 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1251 | |
f69061be DV |
1252 | /* We need to check whether any gpu reset happened in between |
1253 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1254 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1255 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1256 | * is truely gone. */ | |
1257 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1258 | if (ret == 0) | |
1259 | ret = -EAGAIN; | |
1260 | break; | |
1261 | } | |
f69061be | 1262 | |
9c654818 JH |
1263 | if (i915_seqno_passed(ring->get_seqno(ring, false), |
1264 | i915_gem_request_get_seqno(req))) { | |
094f9a54 CW |
1265 | ret = 0; |
1266 | break; | |
1267 | } | |
b361237b | 1268 | |
094f9a54 CW |
1269 | if (interruptible && signal_pending(current)) { |
1270 | ret = -ERESTARTSYS; | |
1271 | break; | |
1272 | } | |
1273 | ||
47e9766d | 1274 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1275 | ret = -ETIME; |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | timer.function = NULL; | |
1280 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1281 | unsigned long expire; |
1282 | ||
094f9a54 | 1283 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1284 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1285 | mod_timer(&timer, expire); |
1286 | } | |
1287 | ||
5035c275 | 1288 | io_schedule(); |
094f9a54 | 1289 | |
094f9a54 CW |
1290 | if (timer.function) { |
1291 | del_singleshot_timer_sync(&timer); | |
1292 | destroy_timer_on_stack(&timer); | |
1293 | } | |
1294 | } | |
5ed0bdf2 | 1295 | now = ktime_get_raw_ns(); |
74328ee5 | 1296 | trace_i915_gem_request_wait_end(req); |
b361237b | 1297 | |
168c3f21 MK |
1298 | if (!irq_test_in_progress) |
1299 | ring->irq_put(ring); | |
094f9a54 CW |
1300 | |
1301 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1302 | |
1303 | if (timeout) { | |
5ed0bdf2 TG |
1304 | s64 tres = *timeout - (now - before); |
1305 | ||
1306 | *timeout = tres < 0 ? 0 : tres; | |
b361237b CW |
1307 | } |
1308 | ||
094f9a54 | 1309 | return ret; |
b361237b CW |
1310 | } |
1311 | ||
1312 | /** | |
a4b3a571 | 1313 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1314 | * request and object lists appropriately for that event. |
1315 | */ | |
1316 | int | |
a4b3a571 | 1317 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1318 | { |
a4b3a571 DV |
1319 | struct drm_device *dev; |
1320 | struct drm_i915_private *dev_priv; | |
1321 | bool interruptible; | |
16e9a21f | 1322 | unsigned reset_counter; |
b361237b CW |
1323 | int ret; |
1324 | ||
a4b3a571 DV |
1325 | BUG_ON(req == NULL); |
1326 | ||
1327 | dev = req->ring->dev; | |
1328 | dev_priv = dev->dev_private; | |
1329 | interruptible = dev_priv->mm.interruptible; | |
1330 | ||
b361237b | 1331 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1332 | |
33196ded | 1333 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1334 | if (ret) |
1335 | return ret; | |
1336 | ||
a4b3a571 | 1337 | ret = i915_gem_check_olr(req); |
b361237b CW |
1338 | if (ret) |
1339 | return ret; | |
1340 | ||
16e9a21f | 1341 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
a4b3a571 | 1342 | i915_gem_request_reference(req); |
9c654818 JH |
1343 | ret = __i915_wait_request(req, reset_counter, |
1344 | interruptible, NULL, NULL); | |
a4b3a571 DV |
1345 | i915_gem_request_unreference(req); |
1346 | return ret; | |
b361237b CW |
1347 | } |
1348 | ||
d26e3af8 | 1349 | static int |
8e639549 | 1350 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
d26e3af8 | 1351 | { |
c8725f3d CW |
1352 | if (!obj->active) |
1353 | return 0; | |
d26e3af8 CW |
1354 | |
1355 | /* Manually manage the write flush as we may have not yet | |
1356 | * retired the buffer. | |
1357 | * | |
97b2a6a1 JH |
1358 | * Note that the last_write_req is always the earlier of |
1359 | * the two (read/write) requests, so if we haved successfully waited, | |
d26e3af8 CW |
1360 | * we know we have passed the last write. |
1361 | */ | |
97b2a6a1 | 1362 | i915_gem_request_assign(&obj->last_write_req, NULL); |
d26e3af8 CW |
1363 | |
1364 | return 0; | |
1365 | } | |
1366 | ||
b361237b CW |
1367 | /** |
1368 | * Ensures that all rendering to the object has completed and the object is | |
1369 | * safe to unbind from the GTT or access from the CPU. | |
1370 | */ | |
1371 | static __must_check int | |
1372 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1373 | bool readonly) | |
1374 | { | |
97b2a6a1 | 1375 | struct drm_i915_gem_request *req; |
b361237b CW |
1376 | int ret; |
1377 | ||
97b2a6a1 JH |
1378 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1379 | if (!req) | |
b361237b CW |
1380 | return 0; |
1381 | ||
a4b3a571 | 1382 | ret = i915_wait_request(req); |
b361237b CW |
1383 | if (ret) |
1384 | return ret; | |
1385 | ||
8e639549 | 1386 | return i915_gem_object_wait_rendering__tail(obj); |
b361237b CW |
1387 | } |
1388 | ||
3236f57a CW |
1389 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1390 | * as the object state may change during this call. | |
1391 | */ | |
1392 | static __must_check int | |
1393 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1394 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1395 | bool readonly) |
1396 | { | |
97b2a6a1 | 1397 | struct drm_i915_gem_request *req; |
3236f57a CW |
1398 | struct drm_device *dev = obj->base.dev; |
1399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f69061be | 1400 | unsigned reset_counter; |
3236f57a CW |
1401 | int ret; |
1402 | ||
1403 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1404 | BUG_ON(!dev_priv->mm.interruptible); | |
1405 | ||
97b2a6a1 JH |
1406 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1407 | if (!req) | |
3236f57a CW |
1408 | return 0; |
1409 | ||
33196ded | 1410 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1411 | if (ret) |
1412 | return ret; | |
1413 | ||
b6660d59 | 1414 | ret = i915_gem_check_olr(req); |
3236f57a CW |
1415 | if (ret) |
1416 | return ret; | |
1417 | ||
f69061be | 1418 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 1419 | i915_gem_request_reference(req); |
3236f57a | 1420 | mutex_unlock(&dev->struct_mutex); |
9c654818 | 1421 | ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv); |
3236f57a | 1422 | mutex_lock(&dev->struct_mutex); |
ff865885 | 1423 | i915_gem_request_unreference(req); |
d26e3af8 CW |
1424 | if (ret) |
1425 | return ret; | |
3236f57a | 1426 | |
8e639549 | 1427 | return i915_gem_object_wait_rendering__tail(obj); |
3236f57a CW |
1428 | } |
1429 | ||
673a394b | 1430 | /** |
2ef7eeaa EA |
1431 | * Called when user space prepares to use an object with the CPU, either |
1432 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1433 | */ |
1434 | int | |
1435 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1436 | struct drm_file *file) |
673a394b EA |
1437 | { |
1438 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1439 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1440 | uint32_t read_domains = args->read_domains; |
1441 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1442 | int ret; |
1443 | ||
2ef7eeaa | 1444 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1445 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1446 | return -EINVAL; |
1447 | ||
21d509e3 | 1448 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1449 | return -EINVAL; |
1450 | ||
1451 | /* Having something in the write domain implies it's in the read | |
1452 | * domain, and only that read domain. Enforce that in the request. | |
1453 | */ | |
1454 | if (write_domain != 0 && read_domains != write_domain) | |
1455 | return -EINVAL; | |
1456 | ||
76c1dec1 | 1457 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1458 | if (ret) |
76c1dec1 | 1459 | return ret; |
1d7cfea1 | 1460 | |
05394f39 | 1461 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1462 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1463 | ret = -ENOENT; |
1464 | goto unlock; | |
76c1dec1 | 1465 | } |
673a394b | 1466 | |
3236f57a CW |
1467 | /* Try to flush the object off the GPU without holding the lock. |
1468 | * We will repeat the flush holding the lock in the normal manner | |
1469 | * to catch cases where we are gazumped. | |
1470 | */ | |
6e4930f6 CW |
1471 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1472 | file->driver_priv, | |
1473 | !write_domain); | |
3236f57a CW |
1474 | if (ret) |
1475 | goto unref; | |
1476 | ||
2ef7eeaa EA |
1477 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1478 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1479 | |
1480 | /* Silently promote "you're not bound, there was nothing to do" | |
1481 | * to success, since the client was just asking us to | |
1482 | * make sure everything was done. | |
1483 | */ | |
1484 | if (ret == -EINVAL) | |
1485 | ret = 0; | |
2ef7eeaa | 1486 | } else { |
e47c68e9 | 1487 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1488 | } |
1489 | ||
3236f57a | 1490 | unref: |
05394f39 | 1491 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1492 | unlock: |
673a394b EA |
1493 | mutex_unlock(&dev->struct_mutex); |
1494 | return ret; | |
1495 | } | |
1496 | ||
1497 | /** | |
1498 | * Called when user space has done writes to this buffer | |
1499 | */ | |
1500 | int | |
1501 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1502 | struct drm_file *file) |
673a394b EA |
1503 | { |
1504 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1505 | struct drm_i915_gem_object *obj; |
673a394b EA |
1506 | int ret = 0; |
1507 | ||
76c1dec1 | 1508 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1509 | if (ret) |
76c1dec1 | 1510 | return ret; |
1d7cfea1 | 1511 | |
05394f39 | 1512 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1513 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1514 | ret = -ENOENT; |
1515 | goto unlock; | |
673a394b EA |
1516 | } |
1517 | ||
673a394b | 1518 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1519 | if (obj->pin_display) |
1520 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1521 | |
05394f39 | 1522 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1523 | unlock: |
673a394b EA |
1524 | mutex_unlock(&dev->struct_mutex); |
1525 | return ret; | |
1526 | } | |
1527 | ||
1528 | /** | |
1529 | * Maps the contents of an object, returning the address it is mapped | |
1530 | * into. | |
1531 | * | |
1532 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1533 | * imply a ref on the object itself. | |
34367381 DV |
1534 | * |
1535 | * IMPORTANT: | |
1536 | * | |
1537 | * DRM driver writers who look a this function as an example for how to do GEM | |
1538 | * mmap support, please don't implement mmap support like here. The modern way | |
1539 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1540 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1541 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1542 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1543 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1544 | */ |
1545 | int | |
1546 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1547 | struct drm_file *file) |
673a394b EA |
1548 | { |
1549 | struct drm_i915_gem_mmap *args = data; | |
1550 | struct drm_gem_object *obj; | |
673a394b EA |
1551 | unsigned long addr; |
1552 | ||
05394f39 | 1553 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1554 | if (obj == NULL) |
bf79cb91 | 1555 | return -ENOENT; |
673a394b | 1556 | |
1286ff73 DV |
1557 | /* prime objects have no backing filp to GEM mmap |
1558 | * pages from. | |
1559 | */ | |
1560 | if (!obj->filp) { | |
1561 | drm_gem_object_unreference_unlocked(obj); | |
1562 | return -EINVAL; | |
1563 | } | |
1564 | ||
6be5ceb0 | 1565 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1566 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1567 | args->offset); | |
bc9025bd | 1568 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1569 | if (IS_ERR((void *)addr)) |
1570 | return addr; | |
1571 | ||
1572 | args->addr_ptr = (uint64_t) addr; | |
1573 | ||
1574 | return 0; | |
1575 | } | |
1576 | ||
de151cf6 JB |
1577 | /** |
1578 | * i915_gem_fault - fault a page into the GTT | |
1579 | * vma: VMA in question | |
1580 | * vmf: fault info | |
1581 | * | |
1582 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1583 | * from userspace. The fault handler takes care of binding the object to | |
1584 | * the GTT (if needed), allocating and programming a fence register (again, | |
1585 | * only if needed based on whether the old reg is still valid or the object | |
1586 | * is tiled) and inserting a new PTE into the faulting process. | |
1587 | * | |
1588 | * Note that the faulting process may involve evicting existing objects | |
1589 | * from the GTT and/or fence registers to make room. So performance may | |
1590 | * suffer if the GTT working set is large or there are few fence registers | |
1591 | * left. | |
1592 | */ | |
1593 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1594 | { | |
05394f39 CW |
1595 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1596 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1597 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1598 | pgoff_t page_offset; |
1599 | unsigned long pfn; | |
1600 | int ret = 0; | |
0f973f27 | 1601 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1602 | |
f65c9168 PZ |
1603 | intel_runtime_pm_get(dev_priv); |
1604 | ||
de151cf6 JB |
1605 | /* We don't use vmf->pgoff since that has the fake offset */ |
1606 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1607 | PAGE_SHIFT; | |
1608 | ||
d9bc7e9f CW |
1609 | ret = i915_mutex_lock_interruptible(dev); |
1610 | if (ret) | |
1611 | goto out; | |
a00b10c3 | 1612 | |
db53a302 CW |
1613 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1614 | ||
6e4930f6 CW |
1615 | /* Try to flush the object off the GPU first without holding the lock. |
1616 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1617 | * repeat the flush holding the lock in the normal manner to catch cases | |
1618 | * where we are gazumped. | |
1619 | */ | |
1620 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1621 | if (ret) | |
1622 | goto unlock; | |
1623 | ||
eb119bd6 CW |
1624 | /* Access to snoopable pages through the GTT is incoherent. */ |
1625 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1626 | ret = -EFAULT; |
eb119bd6 CW |
1627 | goto unlock; |
1628 | } | |
1629 | ||
d9bc7e9f | 1630 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1631 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1632 | if (ret) |
1633 | goto unlock; | |
4a684a41 | 1634 | |
c9839303 CW |
1635 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1636 | if (ret) | |
1637 | goto unpin; | |
74898d7e | 1638 | |
06d98131 | 1639 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1640 | if (ret) |
c9839303 | 1641 | goto unpin; |
7d1c4804 | 1642 | |
b90b91d8 | 1643 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1644 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1645 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1646 | |
b90b91d8 | 1647 | if (!obj->fault_mappable) { |
beff0d0f VS |
1648 | unsigned long size = min_t(unsigned long, |
1649 | vma->vm_end - vma->vm_start, | |
1650 | obj->base.size); | |
b90b91d8 CW |
1651 | int i; |
1652 | ||
beff0d0f | 1653 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1654 | ret = vm_insert_pfn(vma, |
1655 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1656 | pfn + i); | |
1657 | if (ret) | |
1658 | break; | |
1659 | } | |
1660 | ||
1661 | obj->fault_mappable = true; | |
1662 | } else | |
1663 | ret = vm_insert_pfn(vma, | |
1664 | (unsigned long)vmf->virtual_address, | |
1665 | pfn + page_offset); | |
c9839303 | 1666 | unpin: |
d7f46fc4 | 1667 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1668 | unlock: |
de151cf6 | 1669 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1670 | out: |
de151cf6 | 1671 | switch (ret) { |
d9bc7e9f | 1672 | case -EIO: |
2232f031 DV |
1673 | /* |
1674 | * We eat errors when the gpu is terminally wedged to avoid | |
1675 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1676 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1677 | * and so needs to be reported. | |
1678 | */ | |
1679 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1680 | ret = VM_FAULT_SIGBUS; |
1681 | break; | |
1682 | } | |
045e769a | 1683 | case -EAGAIN: |
571c608d DV |
1684 | /* |
1685 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1686 | * handler to reset everything when re-faulting in | |
1687 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1688 | */ |
c715089f CW |
1689 | case 0: |
1690 | case -ERESTARTSYS: | |
bed636ab | 1691 | case -EINTR: |
e79e0fe3 DR |
1692 | case -EBUSY: |
1693 | /* | |
1694 | * EBUSY is ok: this just means that another thread | |
1695 | * already did the job. | |
1696 | */ | |
f65c9168 PZ |
1697 | ret = VM_FAULT_NOPAGE; |
1698 | break; | |
de151cf6 | 1699 | case -ENOMEM: |
f65c9168 PZ |
1700 | ret = VM_FAULT_OOM; |
1701 | break; | |
a7c2e1aa | 1702 | case -ENOSPC: |
45d67817 | 1703 | case -EFAULT: |
f65c9168 PZ |
1704 | ret = VM_FAULT_SIGBUS; |
1705 | break; | |
de151cf6 | 1706 | default: |
a7c2e1aa | 1707 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1708 | ret = VM_FAULT_SIGBUS; |
1709 | break; | |
de151cf6 | 1710 | } |
f65c9168 PZ |
1711 | |
1712 | intel_runtime_pm_put(dev_priv); | |
1713 | return ret; | |
de151cf6 JB |
1714 | } |
1715 | ||
901782b2 CW |
1716 | /** |
1717 | * i915_gem_release_mmap - remove physical page mappings | |
1718 | * @obj: obj in question | |
1719 | * | |
af901ca1 | 1720 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1721 | * relinquish ownership of the pages back to the system. |
1722 | * | |
1723 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1724 | * object through the GTT and then lose the fence register due to | |
1725 | * resource pressure. Similarly if the object has been moved out of the | |
1726 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1727 | * mapping will then trigger a page fault on the next user access, allowing | |
1728 | * fixup by i915_gem_fault(). | |
1729 | */ | |
d05ca301 | 1730 | void |
05394f39 | 1731 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1732 | { |
6299f992 CW |
1733 | if (!obj->fault_mappable) |
1734 | return; | |
901782b2 | 1735 | |
6796cb16 DH |
1736 | drm_vma_node_unmap(&obj->base.vma_node, |
1737 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1738 | obj->fault_mappable = false; |
901782b2 CW |
1739 | } |
1740 | ||
eedd10f4 CW |
1741 | void |
1742 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1743 | { | |
1744 | struct drm_i915_gem_object *obj; | |
1745 | ||
1746 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1747 | i915_gem_release_mmap(obj); | |
1748 | } | |
1749 | ||
0fa87796 | 1750 | uint32_t |
e28f8711 | 1751 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1752 | { |
e28f8711 | 1753 | uint32_t gtt_size; |
92b88aeb CW |
1754 | |
1755 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1756 | tiling_mode == I915_TILING_NONE) |
1757 | return size; | |
92b88aeb CW |
1758 | |
1759 | /* Previous chips need a power-of-two fence region when tiling */ | |
1760 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1761 | gtt_size = 1024*1024; |
92b88aeb | 1762 | else |
e28f8711 | 1763 | gtt_size = 512*1024; |
92b88aeb | 1764 | |
e28f8711 CW |
1765 | while (gtt_size < size) |
1766 | gtt_size <<= 1; | |
92b88aeb | 1767 | |
e28f8711 | 1768 | return gtt_size; |
92b88aeb CW |
1769 | } |
1770 | ||
de151cf6 JB |
1771 | /** |
1772 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1773 | * @obj: object to check | |
1774 | * | |
1775 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1776 | * potential fence register mapping. |
de151cf6 | 1777 | */ |
d865110c ID |
1778 | uint32_t |
1779 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1780 | int tiling_mode, bool fenced) | |
de151cf6 | 1781 | { |
de151cf6 JB |
1782 | /* |
1783 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1784 | * if a fence register is needed for the object. | |
1785 | */ | |
d865110c | 1786 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1787 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1788 | return 4096; |
1789 | ||
a00b10c3 CW |
1790 | /* |
1791 | * Previous chips need to be aligned to the size of the smallest | |
1792 | * fence register that can contain the object. | |
1793 | */ | |
e28f8711 | 1794 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1795 | } |
1796 | ||
d8cb5086 CW |
1797 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1798 | { | |
1799 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1800 | int ret; | |
1801 | ||
0de23977 | 1802 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1803 | return 0; |
1804 | ||
da494d7c DV |
1805 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1806 | ||
d8cb5086 CW |
1807 | ret = drm_gem_create_mmap_offset(&obj->base); |
1808 | if (ret != -ENOSPC) | |
da494d7c | 1809 | goto out; |
d8cb5086 CW |
1810 | |
1811 | /* Badly fragmented mmap space? The only way we can recover | |
1812 | * space is by destroying unwanted objects. We can't randomly release | |
1813 | * mmap_offsets as userspace expects them to be persistent for the | |
1814 | * lifetime of the objects. The closest we can is to release the | |
1815 | * offsets on purgeable objects by truncating it and marking it purged, | |
1816 | * which prevents userspace from ever using that object again. | |
1817 | */ | |
21ab4e74 CW |
1818 | i915_gem_shrink(dev_priv, |
1819 | obj->base.size >> PAGE_SHIFT, | |
1820 | I915_SHRINK_BOUND | | |
1821 | I915_SHRINK_UNBOUND | | |
1822 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1823 | ret = drm_gem_create_mmap_offset(&obj->base); |
1824 | if (ret != -ENOSPC) | |
da494d7c | 1825 | goto out; |
d8cb5086 CW |
1826 | |
1827 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1828 | ret = drm_gem_create_mmap_offset(&obj->base); |
1829 | out: | |
1830 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1831 | ||
1832 | return ret; | |
d8cb5086 CW |
1833 | } |
1834 | ||
1835 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1836 | { | |
d8cb5086 CW |
1837 | drm_gem_free_mmap_offset(&obj->base); |
1838 | } | |
1839 | ||
355a7018 | 1840 | static int |
ff72145b DA |
1841 | i915_gem_mmap_gtt(struct drm_file *file, |
1842 | struct drm_device *dev, | |
355a7018 | 1843 | uint32_t handle, bool dumb, |
ff72145b | 1844 | uint64_t *offset) |
de151cf6 | 1845 | { |
da761a6e | 1846 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1847 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1848 | int ret; |
1849 | ||
76c1dec1 | 1850 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1851 | if (ret) |
76c1dec1 | 1852 | return ret; |
de151cf6 | 1853 | |
ff72145b | 1854 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1855 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1856 | ret = -ENOENT; |
1857 | goto unlock; | |
1858 | } | |
de151cf6 | 1859 | |
355a7018 TH |
1860 | /* |
1861 | * We don't allow dumb mmaps on objects created using another | |
1862 | * interface. | |
1863 | */ | |
1864 | WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach), | |
1865 | "Illegal dumb map of accelerated buffer.\n"); | |
1866 | ||
5d4545ae | 1867 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1868 | ret = -E2BIG; |
ff56b0bc | 1869 | goto out; |
da761a6e CW |
1870 | } |
1871 | ||
05394f39 | 1872 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1873 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1874 | ret = -EFAULT; |
1d7cfea1 | 1875 | goto out; |
ab18282d CW |
1876 | } |
1877 | ||
d8cb5086 CW |
1878 | ret = i915_gem_object_create_mmap_offset(obj); |
1879 | if (ret) | |
1880 | goto out; | |
de151cf6 | 1881 | |
0de23977 | 1882 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1883 | |
1d7cfea1 | 1884 | out: |
05394f39 | 1885 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1886 | unlock: |
de151cf6 | 1887 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1888 | return ret; |
de151cf6 JB |
1889 | } |
1890 | ||
355a7018 TH |
1891 | int |
1892 | i915_gem_dumb_map_offset(struct drm_file *file, | |
1893 | struct drm_device *dev, | |
1894 | uint32_t handle, | |
1895 | uint64_t *offset) | |
1896 | { | |
1897 | return i915_gem_mmap_gtt(file, dev, handle, true, offset); | |
1898 | } | |
1899 | ||
ff72145b DA |
1900 | /** |
1901 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1902 | * @dev: DRM device | |
1903 | * @data: GTT mapping ioctl data | |
1904 | * @file: GEM object info | |
1905 | * | |
1906 | * Simply returns the fake offset to userspace so it can mmap it. | |
1907 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1908 | * up so we can get faults in the handler above. | |
1909 | * | |
1910 | * The fault handler will take care of binding the object into the GTT | |
1911 | * (since it may have been evicted to make room for something), allocating | |
1912 | * a fence register, and mapping the appropriate aperture address into | |
1913 | * userspace. | |
1914 | */ | |
1915 | int | |
1916 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1917 | struct drm_file *file) | |
1918 | { | |
1919 | struct drm_i915_gem_mmap_gtt *args = data; | |
1920 | ||
355a7018 | 1921 | return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset); |
ff72145b DA |
1922 | } |
1923 | ||
5537252b CW |
1924 | static inline int |
1925 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1926 | { | |
1927 | return obj->madv == I915_MADV_DONTNEED; | |
1928 | } | |
1929 | ||
225067ee DV |
1930 | /* Immediately discard the backing storage */ |
1931 | static void | |
1932 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1933 | { |
4d6294bf | 1934 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1935 | |
4d6294bf CW |
1936 | if (obj->base.filp == NULL) |
1937 | return; | |
e5281ccd | 1938 | |
225067ee DV |
1939 | /* Our goal here is to return as much of the memory as |
1940 | * is possible back to the system as we are called from OOM. | |
1941 | * To do this we must instruct the shmfs to drop all of its | |
1942 | * backing pages, *now*. | |
1943 | */ | |
5537252b | 1944 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1945 | obj->madv = __I915_MADV_PURGED; |
1946 | } | |
e5281ccd | 1947 | |
5537252b CW |
1948 | /* Try to discard unwanted pages */ |
1949 | static void | |
1950 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1951 | { |
5537252b CW |
1952 | struct address_space *mapping; |
1953 | ||
1954 | switch (obj->madv) { | |
1955 | case I915_MADV_DONTNEED: | |
1956 | i915_gem_object_truncate(obj); | |
1957 | case __I915_MADV_PURGED: | |
1958 | return; | |
1959 | } | |
1960 | ||
1961 | if (obj->base.filp == NULL) | |
1962 | return; | |
1963 | ||
1964 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1965 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1966 | } |
1967 | ||
5cdf5881 | 1968 | static void |
05394f39 | 1969 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1970 | { |
90797e6d ID |
1971 | struct sg_page_iter sg_iter; |
1972 | int ret; | |
1286ff73 | 1973 | |
05394f39 | 1974 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1975 | |
6c085a72 CW |
1976 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1977 | if (ret) { | |
1978 | /* In the event of a disaster, abandon all caches and | |
1979 | * hope for the best. | |
1980 | */ | |
1981 | WARN_ON(ret != -EIO); | |
2c22569b | 1982 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1983 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1984 | } | |
1985 | ||
6dacfd2f | 1986 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1987 | i915_gem_object_save_bit_17_swizzle(obj); |
1988 | ||
05394f39 CW |
1989 | if (obj->madv == I915_MADV_DONTNEED) |
1990 | obj->dirty = 0; | |
3ef94daa | 1991 | |
90797e6d | 1992 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1993 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1994 | |
05394f39 | 1995 | if (obj->dirty) |
9da3da66 | 1996 | set_page_dirty(page); |
3ef94daa | 1997 | |
05394f39 | 1998 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1999 | mark_page_accessed(page); |
3ef94daa | 2000 | |
9da3da66 | 2001 | page_cache_release(page); |
3ef94daa | 2002 | } |
05394f39 | 2003 | obj->dirty = 0; |
673a394b | 2004 | |
9da3da66 CW |
2005 | sg_free_table(obj->pages); |
2006 | kfree(obj->pages); | |
37e680a1 | 2007 | } |
6c085a72 | 2008 | |
dd624afd | 2009 | int |
37e680a1 CW |
2010 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2011 | { | |
2012 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2013 | ||
2f745ad3 | 2014 | if (obj->pages == NULL) |
37e680a1 CW |
2015 | return 0; |
2016 | ||
a5570178 CW |
2017 | if (obj->pages_pin_count) |
2018 | return -EBUSY; | |
2019 | ||
9843877d | 2020 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2021 | |
a2165e31 CW |
2022 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2023 | * array, hence protect them from being reaped by removing them from gtt | |
2024 | * lists early. */ | |
35c20a60 | 2025 | list_del(&obj->global_list); |
a2165e31 | 2026 | |
37e680a1 | 2027 | ops->put_pages(obj); |
05394f39 | 2028 | obj->pages = NULL; |
37e680a1 | 2029 | |
5537252b | 2030 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2031 | |
2032 | return 0; | |
2033 | } | |
2034 | ||
21ab4e74 CW |
2035 | unsigned long |
2036 | i915_gem_shrink(struct drm_i915_private *dev_priv, | |
2037 | long target, unsigned flags) | |
6c085a72 | 2038 | { |
60a53727 CW |
2039 | const struct { |
2040 | struct list_head *list; | |
2041 | unsigned int bit; | |
2042 | } phases[] = { | |
2043 | { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, | |
2044 | { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, | |
2045 | { NULL, 0 }, | |
2046 | }, *phase; | |
d9973b43 | 2047 | unsigned long count = 0; |
6c085a72 | 2048 | |
57094f82 | 2049 | /* |
c8725f3d | 2050 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
2051 | * (due to retiring requests) we have to strictly process only |
2052 | * one element of the list at the time, and recheck the list | |
2053 | * on every iteration. | |
c8725f3d CW |
2054 | * |
2055 | * In particular, we must hold a reference whilst removing the | |
2056 | * object as we may end up waiting for and/or retiring the objects. | |
2057 | * This might release the final reference (held by the active list) | |
2058 | * and result in the object being freed from under us. This is | |
2059 | * similar to the precautions the eviction code must take whilst | |
2060 | * removing objects. | |
2061 | * | |
2062 | * Also note that although these lists do not hold a reference to | |
2063 | * the object we can safely grab one here: The final object | |
2064 | * unreferencing and the bound_list are both protected by the | |
2065 | * dev->struct_mutex and so we won't ever be able to observe an | |
2066 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 2067 | */ |
60a53727 | 2068 | for (phase = phases; phase->list; phase++) { |
21ab4e74 | 2069 | struct list_head still_in_list; |
c8725f3d | 2070 | |
60a53727 CW |
2071 | if ((flags & phase->bit) == 0) |
2072 | continue; | |
80dcfdbd | 2073 | |
21ab4e74 | 2074 | INIT_LIST_HEAD(&still_in_list); |
60a53727 | 2075 | while (count < target && !list_empty(phase->list)) { |
21ab4e74 CW |
2076 | struct drm_i915_gem_object *obj; |
2077 | struct i915_vma *vma, *v; | |
57094f82 | 2078 | |
60a53727 | 2079 | obj = list_first_entry(phase->list, |
21ab4e74 CW |
2080 | typeof(*obj), global_list); |
2081 | list_move_tail(&obj->global_list, &still_in_list); | |
80dcfdbd | 2082 | |
60a53727 CW |
2083 | if (flags & I915_SHRINK_PURGEABLE && |
2084 | !i915_gem_object_is_purgeable(obj)) | |
21ab4e74 | 2085 | continue; |
57094f82 | 2086 | |
21ab4e74 | 2087 | drm_gem_object_reference(&obj->base); |
80dcfdbd | 2088 | |
60a53727 CW |
2089 | /* For the unbound phase, this should be a no-op! */ |
2090 | list_for_each_entry_safe(vma, v, | |
2091 | &obj->vma_list, vma_link) | |
21ab4e74 CW |
2092 | if (i915_vma_unbind(vma)) |
2093 | break; | |
57094f82 | 2094 | |
21ab4e74 CW |
2095 | if (i915_gem_object_put_pages(obj) == 0) |
2096 | count += obj->base.size >> PAGE_SHIFT; | |
2097 | ||
2098 | drm_gem_object_unreference(&obj->base); | |
2099 | } | |
60a53727 | 2100 | list_splice(&still_in_list, phase->list); |
6c085a72 CW |
2101 | } |
2102 | ||
2103 | return count; | |
2104 | } | |
2105 | ||
d9973b43 | 2106 | static unsigned long |
6c085a72 CW |
2107 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2108 | { | |
6c085a72 | 2109 | i915_gem_evict_everything(dev_priv->dev); |
21ab4e74 CW |
2110 | return i915_gem_shrink(dev_priv, LONG_MAX, |
2111 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); | |
225067ee DV |
2112 | } |
2113 | ||
37e680a1 | 2114 | static int |
6c085a72 | 2115 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2116 | { |
6c085a72 | 2117 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2118 | int page_count, i; |
2119 | struct address_space *mapping; | |
9da3da66 CW |
2120 | struct sg_table *st; |
2121 | struct scatterlist *sg; | |
90797e6d | 2122 | struct sg_page_iter sg_iter; |
e5281ccd | 2123 | struct page *page; |
90797e6d | 2124 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2125 | gfp_t gfp; |
e5281ccd | 2126 | |
6c085a72 CW |
2127 | /* Assert that the object is not currently in any GPU domain. As it |
2128 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2129 | * a GPU cache | |
2130 | */ | |
2131 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2132 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2133 | ||
9da3da66 CW |
2134 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2135 | if (st == NULL) | |
2136 | return -ENOMEM; | |
2137 | ||
05394f39 | 2138 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2139 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2140 | kfree(st); |
e5281ccd | 2141 | return -ENOMEM; |
9da3da66 | 2142 | } |
e5281ccd | 2143 | |
9da3da66 CW |
2144 | /* Get the list of pages out of our struct file. They'll be pinned |
2145 | * at this point until we release them. | |
2146 | * | |
2147 | * Fail silently without starting the shrinker | |
2148 | */ | |
496ad9aa | 2149 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2150 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2151 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2152 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2153 | sg = st->sgl; |
2154 | st->nents = 0; | |
2155 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2156 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2157 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2158 | i915_gem_shrink(dev_priv, |
2159 | page_count, | |
2160 | I915_SHRINK_BOUND | | |
2161 | I915_SHRINK_UNBOUND | | |
2162 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2163 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2164 | } | |
2165 | if (IS_ERR(page)) { | |
2166 | /* We've tried hard to allocate the memory by reaping | |
2167 | * our own buffer, now let the real VM do its job and | |
2168 | * go down in flames if truly OOM. | |
2169 | */ | |
6c085a72 | 2170 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2171 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2172 | if (IS_ERR(page)) |
2173 | goto err_pages; | |
6c085a72 | 2174 | } |
426729dc KRW |
2175 | #ifdef CONFIG_SWIOTLB |
2176 | if (swiotlb_nr_tbl()) { | |
2177 | st->nents++; | |
2178 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2179 | sg = sg_next(sg); | |
2180 | continue; | |
2181 | } | |
2182 | #endif | |
90797e6d ID |
2183 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2184 | if (i) | |
2185 | sg = sg_next(sg); | |
2186 | st->nents++; | |
2187 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2188 | } else { | |
2189 | sg->length += PAGE_SIZE; | |
2190 | } | |
2191 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2192 | |
2193 | /* Check that the i965g/gm workaround works. */ | |
2194 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2195 | } |
426729dc KRW |
2196 | #ifdef CONFIG_SWIOTLB |
2197 | if (!swiotlb_nr_tbl()) | |
2198 | #endif | |
2199 | sg_mark_end(sg); | |
74ce6b6c CW |
2200 | obj->pages = st; |
2201 | ||
6dacfd2f | 2202 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2203 | i915_gem_object_do_bit_17_swizzle(obj); |
2204 | ||
656bfa3a DV |
2205 | if (obj->tiling_mode != I915_TILING_NONE && |
2206 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2207 | i915_gem_object_pin_pages(obj); | |
2208 | ||
e5281ccd CW |
2209 | return 0; |
2210 | ||
2211 | err_pages: | |
90797e6d ID |
2212 | sg_mark_end(sg); |
2213 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2214 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2215 | sg_free_table(st); |
2216 | kfree(st); | |
0820baf3 CW |
2217 | |
2218 | /* shmemfs first checks if there is enough memory to allocate the page | |
2219 | * and reports ENOSPC should there be insufficient, along with the usual | |
2220 | * ENOMEM for a genuine allocation failure. | |
2221 | * | |
2222 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2223 | * space and so want to translate the error from shmemfs back to our | |
2224 | * usual understanding of ENOMEM. | |
2225 | */ | |
2226 | if (PTR_ERR(page) == -ENOSPC) | |
2227 | return -ENOMEM; | |
2228 | else | |
2229 | return PTR_ERR(page); | |
673a394b EA |
2230 | } |
2231 | ||
37e680a1 CW |
2232 | /* Ensure that the associated pages are gathered from the backing storage |
2233 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2234 | * multiple times before they are released by a single call to | |
2235 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2236 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2237 | * or as the object is itself released. | |
2238 | */ | |
2239 | int | |
2240 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2241 | { | |
2242 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2243 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2244 | int ret; | |
2245 | ||
2f745ad3 | 2246 | if (obj->pages) |
37e680a1 CW |
2247 | return 0; |
2248 | ||
43e28f09 | 2249 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2250 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2251 | return -EFAULT; |
43e28f09 CW |
2252 | } |
2253 | ||
a5570178 CW |
2254 | BUG_ON(obj->pages_pin_count); |
2255 | ||
37e680a1 CW |
2256 | ret = ops->get_pages(obj); |
2257 | if (ret) | |
2258 | return ret; | |
2259 | ||
35c20a60 | 2260 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2261 | return 0; |
673a394b EA |
2262 | } |
2263 | ||
e2d05a8b | 2264 | static void |
05394f39 | 2265 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2266 | struct intel_engine_cs *ring) |
673a394b | 2267 | { |
97b2a6a1 | 2268 | struct drm_i915_gem_request *req = intel_ring_get_request(ring); |
617dbe27 | 2269 | |
852835f3 | 2270 | BUG_ON(ring == NULL); |
97b2a6a1 JH |
2271 | if (obj->ring != ring && obj->last_write_req) { |
2272 | /* Keep the request relative to the current ring */ | |
2273 | i915_gem_request_assign(&obj->last_write_req, req); | |
02978ff5 | 2274 | } |
05394f39 | 2275 | obj->ring = ring; |
673a394b EA |
2276 | |
2277 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2278 | if (!obj->active) { |
2279 | drm_gem_object_reference(&obj->base); | |
2280 | obj->active = 1; | |
673a394b | 2281 | } |
e35a41de | 2282 | |
05394f39 | 2283 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2284 | |
97b2a6a1 | 2285 | i915_gem_request_assign(&obj->last_read_req, req); |
caea7476 CW |
2286 | } |
2287 | ||
e2d05a8b | 2288 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2289 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2290 | { |
2291 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2292 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2293 | } | |
2294 | ||
caea7476 | 2295 | static void |
caea7476 | 2296 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2297 | { |
ca191b13 | 2298 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2299 | struct i915_address_space *vm; |
2300 | struct i915_vma *vma; | |
ce44b0ea | 2301 | |
65ce3027 | 2302 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2303 | BUG_ON(!obj->active); |
caea7476 | 2304 | |
feb822cf BW |
2305 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2306 | vma = i915_gem_obj_to_vma(obj, vm); | |
2307 | if (vma && !list_empty(&vma->mm_list)) | |
2308 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2309 | } | |
caea7476 | 2310 | |
f99d7069 DV |
2311 | intel_fb_obj_flush(obj, true); |
2312 | ||
65ce3027 | 2313 | list_del_init(&obj->ring_list); |
caea7476 CW |
2314 | obj->ring = NULL; |
2315 | ||
97b2a6a1 JH |
2316 | i915_gem_request_assign(&obj->last_read_req, NULL); |
2317 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
65ce3027 CW |
2318 | obj->base.write_domain = 0; |
2319 | ||
97b2a6a1 | 2320 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 CW |
2321 | |
2322 | obj->active = 0; | |
2323 | drm_gem_object_unreference(&obj->base); | |
2324 | ||
2325 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2326 | } |
673a394b | 2327 | |
c8725f3d CW |
2328 | static void |
2329 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2330 | { | |
a4872ba6 | 2331 | struct intel_engine_cs *ring = obj->ring; |
c8725f3d CW |
2332 | |
2333 | if (ring == NULL) | |
2334 | return; | |
2335 | ||
2336 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
97b2a6a1 | 2337 | i915_gem_request_get_seqno(obj->last_read_req))) |
c8725f3d CW |
2338 | i915_gem_object_move_to_inactive(obj); |
2339 | } | |
2340 | ||
9d773091 | 2341 | static int |
fca26bb4 | 2342 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2343 | { |
9d773091 | 2344 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2345 | struct intel_engine_cs *ring; |
9d773091 | 2346 | int ret, i, j; |
53d227f2 | 2347 | |
107f27a5 | 2348 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2349 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2350 | ret = intel_ring_idle(ring); |
2351 | if (ret) | |
2352 | return ret; | |
9d773091 | 2353 | } |
9d773091 | 2354 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2355 | |
2356 | /* Finally reset hw state */ | |
9d773091 | 2357 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2358 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2359 | |
ebc348b2 BW |
2360 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2361 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2362 | } |
53d227f2 | 2363 | |
9d773091 | 2364 | return 0; |
53d227f2 DV |
2365 | } |
2366 | ||
fca26bb4 MK |
2367 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2368 | { | |
2369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2370 | int ret; | |
2371 | ||
2372 | if (seqno == 0) | |
2373 | return -EINVAL; | |
2374 | ||
2375 | /* HWS page needs to be set less than what we | |
2376 | * will inject to ring | |
2377 | */ | |
2378 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2379 | if (ret) | |
2380 | return ret; | |
2381 | ||
2382 | /* Carefully set the last_seqno value so that wrap | |
2383 | * detection still works | |
2384 | */ | |
2385 | dev_priv->next_seqno = seqno; | |
2386 | dev_priv->last_seqno = seqno - 1; | |
2387 | if (dev_priv->last_seqno == 0) | |
2388 | dev_priv->last_seqno--; | |
2389 | ||
2390 | return 0; | |
2391 | } | |
2392 | ||
9d773091 CW |
2393 | int |
2394 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2395 | { |
9d773091 CW |
2396 | struct drm_i915_private *dev_priv = dev->dev_private; |
2397 | ||
2398 | /* reserve 0 for non-seqno */ | |
2399 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2400 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2401 | if (ret) |
2402 | return ret; | |
53d227f2 | 2403 | |
9d773091 CW |
2404 | dev_priv->next_seqno = 1; |
2405 | } | |
53d227f2 | 2406 | |
f72b3435 | 2407 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2408 | return 0; |
53d227f2 DV |
2409 | } |
2410 | ||
a4872ba6 | 2411 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2412 | struct drm_file *file, |
9400ae5c | 2413 | struct drm_i915_gem_object *obj) |
673a394b | 2414 | { |
3e31c6c0 | 2415 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2416 | struct drm_i915_gem_request *request; |
48e29f55 | 2417 | struct intel_ringbuffer *ringbuf; |
7d736f4f | 2418 | u32 request_ring_position, request_start; |
3cce469c CW |
2419 | int ret; |
2420 | ||
6259cead | 2421 | request = ring->outstanding_lazy_request; |
48e29f55 OM |
2422 | if (WARN_ON(request == NULL)) |
2423 | return -ENOMEM; | |
2424 | ||
2425 | if (i915.enable_execlists) { | |
2426 | struct intel_context *ctx = request->ctx; | |
2427 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2428 | } else | |
2429 | ringbuf = ring->buffer; | |
2430 | ||
2431 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2432 | /* |
2433 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2434 | * after having emitted the batchbuffer command. Hence we need to fix | |
2435 | * things up similar to emitting the lazy request. The difference here | |
2436 | * is that the flush _must_ happen before the next request, no matter | |
2437 | * what. | |
2438 | */ | |
48e29f55 OM |
2439 | if (i915.enable_execlists) { |
2440 | ret = logical_ring_flush_all_caches(ringbuf); | |
2441 | if (ret) | |
2442 | return ret; | |
2443 | } else { | |
2444 | ret = intel_ring_flush_all_caches(ring); | |
2445 | if (ret) | |
2446 | return ret; | |
2447 | } | |
cc889e0f | 2448 | |
a71d8d94 CW |
2449 | /* Record the position of the start of the request so that |
2450 | * should we detect the updated seqno part-way through the | |
2451 | * GPU processing the request, we never over-estimate the | |
2452 | * position of the head. | |
2453 | */ | |
48e29f55 | 2454 | request_ring_position = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2455 | |
48e29f55 OM |
2456 | if (i915.enable_execlists) { |
2457 | ret = ring->emit_request(ringbuf); | |
2458 | if (ret) | |
2459 | return ret; | |
2460 | } else { | |
2461 | ret = ring->add_request(ring); | |
2462 | if (ret) | |
2463 | return ret; | |
2464 | } | |
673a394b | 2465 | |
7d736f4f | 2466 | request->head = request_start; |
a71d8d94 | 2467 | request->tail = request_ring_position; |
7d736f4f MK |
2468 | |
2469 | /* Whilst this request exists, batch_obj will be on the | |
2470 | * active_list, and so will hold the active reference. Only when this | |
2471 | * request is retired will the the batch_obj be moved onto the | |
2472 | * inactive_list and lose its active reference. Hence we do not need | |
2473 | * to explicitly hold another reference here. | |
2474 | */ | |
9a7e0c2a | 2475 | request->batch_obj = obj; |
0e50e96b | 2476 | |
48e29f55 OM |
2477 | if (!i915.enable_execlists) { |
2478 | /* Hold a reference to the current context so that we can inspect | |
2479 | * it later in case a hangcheck error event fires. | |
2480 | */ | |
2481 | request->ctx = ring->last_context; | |
2482 | if (request->ctx) | |
2483 | i915_gem_context_reference(request->ctx); | |
2484 | } | |
0e50e96b | 2485 | |
673a394b | 2486 | request->emitted_jiffies = jiffies; |
852835f3 | 2487 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2488 | request->file_priv = NULL; |
852835f3 | 2489 | |
db53a302 CW |
2490 | if (file) { |
2491 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2492 | ||
1c25595f | 2493 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2494 | request->file_priv = file_priv; |
b962442e | 2495 | list_add_tail(&request->client_list, |
f787a5f5 | 2496 | &file_priv->mm.request_list); |
1c25595f | 2497 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2498 | } |
673a394b | 2499 | |
74328ee5 | 2500 | trace_i915_gem_request_add(request); |
6259cead | 2501 | ring->outstanding_lazy_request = NULL; |
db53a302 | 2502 | |
87255483 | 2503 | i915_queue_hangcheck(ring->dev); |
10cd45b6 | 2504 | |
87255483 DV |
2505 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2506 | queue_delayed_work(dev_priv->wq, | |
2507 | &dev_priv->mm.retire_work, | |
2508 | round_jiffies_up_relative(HZ)); | |
2509 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2510 | |
3cce469c | 2511 | return 0; |
673a394b EA |
2512 | } |
2513 | ||
f787a5f5 CW |
2514 | static inline void |
2515 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2516 | { |
1c25595f | 2517 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2518 | |
1c25595f CW |
2519 | if (!file_priv) |
2520 | return; | |
1c5d22f7 | 2521 | |
1c25595f | 2522 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2523 | list_del(&request->client_list); |
2524 | request->file_priv = NULL; | |
1c25595f | 2525 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2526 | } |
673a394b | 2527 | |
939fd762 | 2528 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2529 | const struct intel_context *ctx) |
be62acb4 | 2530 | { |
44e2c070 | 2531 | unsigned long elapsed; |
be62acb4 | 2532 | |
44e2c070 MK |
2533 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2534 | ||
2535 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2536 | return true; |
2537 | ||
2538 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2539 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2540 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2541 | return true; |
88b4aa87 MK |
2542 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2543 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2544 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2545 | return true; |
3fac8978 | 2546 | } |
be62acb4 MK |
2547 | } |
2548 | ||
2549 | return false; | |
2550 | } | |
2551 | ||
939fd762 | 2552 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2553 | struct intel_context *ctx, |
b6b0fac0 | 2554 | const bool guilty) |
aa60c664 | 2555 | { |
44e2c070 MK |
2556 | struct i915_ctx_hang_stats *hs; |
2557 | ||
2558 | if (WARN_ON(!ctx)) | |
2559 | return; | |
aa60c664 | 2560 | |
44e2c070 MK |
2561 | hs = &ctx->hang_stats; |
2562 | ||
2563 | if (guilty) { | |
939fd762 | 2564 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2565 | hs->batch_active++; |
2566 | hs->guilty_ts = get_seconds(); | |
2567 | } else { | |
2568 | hs->batch_pending++; | |
aa60c664 MK |
2569 | } |
2570 | } | |
2571 | ||
0e50e96b MK |
2572 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2573 | { | |
2574 | list_del(&request->list); | |
2575 | i915_gem_request_remove_from_client(request); | |
2576 | ||
abfe262a JH |
2577 | i915_gem_request_unreference(request); |
2578 | } | |
2579 | ||
2580 | void i915_gem_request_free(struct kref *req_ref) | |
2581 | { | |
2582 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2583 | typeof(*req), ref); | |
2584 | struct intel_context *ctx = req->ctx; | |
2585 | ||
0794aed3 TD |
2586 | if (ctx) { |
2587 | if (i915.enable_execlists) { | |
abfe262a | 2588 | struct intel_engine_cs *ring = req->ring; |
0e50e96b | 2589 | |
0794aed3 TD |
2590 | if (ctx != ring->default_context) |
2591 | intel_lr_context_unpin(ring, ctx); | |
2592 | } | |
abfe262a | 2593 | |
dcb4c12a OM |
2594 | i915_gem_context_unreference(ctx); |
2595 | } | |
abfe262a JH |
2596 | |
2597 | kfree(req); | |
0e50e96b MK |
2598 | } |
2599 | ||
8d9fc7fd | 2600 | struct drm_i915_gem_request * |
a4872ba6 | 2601 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2602 | { |
4db080f9 | 2603 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2604 | u32 completed_seqno; |
2605 | ||
2606 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2607 | |
2608 | list_for_each_entry(request, &ring->request_list, list) { | |
2609 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2610 | continue; | |
aa60c664 | 2611 | |
b6b0fac0 | 2612 | return request; |
4db080f9 | 2613 | } |
b6b0fac0 MK |
2614 | |
2615 | return NULL; | |
2616 | } | |
2617 | ||
2618 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2619 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2620 | { |
2621 | struct drm_i915_gem_request *request; | |
2622 | bool ring_hung; | |
2623 | ||
8d9fc7fd | 2624 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2625 | |
2626 | if (request == NULL) | |
2627 | return; | |
2628 | ||
2629 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2630 | ||
939fd762 | 2631 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2632 | |
2633 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2634 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2635 | } |
aa60c664 | 2636 | |
4db080f9 | 2637 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2638 | struct intel_engine_cs *ring) |
4db080f9 | 2639 | { |
dfaae392 | 2640 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2641 | struct drm_i915_gem_object *obj; |
9375e446 | 2642 | |
05394f39 CW |
2643 | obj = list_first_entry(&ring->active_list, |
2644 | struct drm_i915_gem_object, | |
2645 | ring_list); | |
9375e446 | 2646 | |
05394f39 | 2647 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2648 | } |
1d62beea | 2649 | |
dcb4c12a OM |
2650 | /* |
2651 | * Clear the execlists queue up before freeing the requests, as those | |
2652 | * are the ones that keep the context and ringbuffer backing objects | |
2653 | * pinned in place. | |
2654 | */ | |
2655 | while (!list_empty(&ring->execlist_queue)) { | |
2656 | struct intel_ctx_submit_request *submit_req; | |
2657 | ||
2658 | submit_req = list_first_entry(&ring->execlist_queue, | |
2659 | struct intel_ctx_submit_request, | |
2660 | execlist_link); | |
2661 | list_del(&submit_req->execlist_link); | |
2662 | intel_runtime_pm_put(dev_priv); | |
2663 | i915_gem_context_unreference(submit_req->ctx); | |
2664 | kfree(submit_req); | |
2665 | } | |
2666 | ||
1d62beea BW |
2667 | /* |
2668 | * We must free the requests after all the corresponding objects have | |
2669 | * been moved off active lists. Which is the same order as the normal | |
2670 | * retire_requests function does. This is important if object hold | |
2671 | * implicit references on things like e.g. ppgtt address spaces through | |
2672 | * the request. | |
2673 | */ | |
2674 | while (!list_empty(&ring->request_list)) { | |
2675 | struct drm_i915_gem_request *request; | |
2676 | ||
2677 | request = list_first_entry(&ring->request_list, | |
2678 | struct drm_i915_gem_request, | |
2679 | list); | |
2680 | ||
2681 | i915_gem_free_request(request); | |
2682 | } | |
e3efda49 | 2683 | |
6259cead JH |
2684 | /* This may not have been flushed before the reset, so clean it now */ |
2685 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); | |
673a394b EA |
2686 | } |
2687 | ||
19b2dbde | 2688 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2689 | { |
2690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2691 | int i; | |
2692 | ||
4b9de737 | 2693 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2694 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2695 | |
94a335db DV |
2696 | /* |
2697 | * Commit delayed tiling changes if we have an object still | |
2698 | * attached to the fence, otherwise just clear the fence. | |
2699 | */ | |
2700 | if (reg->obj) { | |
2701 | i915_gem_object_update_fence(reg->obj, reg, | |
2702 | reg->obj->tiling_mode); | |
2703 | } else { | |
2704 | i915_gem_write_fence(dev, i, NULL); | |
2705 | } | |
312817a3 CW |
2706 | } |
2707 | } | |
2708 | ||
069efc1d | 2709 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2710 | { |
77f01230 | 2711 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2712 | struct intel_engine_cs *ring; |
1ec14ad3 | 2713 | int i; |
673a394b | 2714 | |
4db080f9 CW |
2715 | /* |
2716 | * Before we free the objects from the requests, we need to inspect | |
2717 | * them for finding the guilty party. As the requests only borrow | |
2718 | * their reference to the objects, the inspection must be done first. | |
2719 | */ | |
2720 | for_each_ring(ring, dev_priv, i) | |
2721 | i915_gem_reset_ring_status(dev_priv, ring); | |
2722 | ||
b4519513 | 2723 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2724 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2725 | |
acce9ffa BW |
2726 | i915_gem_context_reset(dev); |
2727 | ||
19b2dbde | 2728 | i915_gem_restore_fences(dev); |
673a394b EA |
2729 | } |
2730 | ||
2731 | /** | |
2732 | * This function clears the request list as sequence numbers are passed. | |
2733 | */ | |
1cf0ba14 | 2734 | void |
a4872ba6 | 2735 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2736 | { |
673a394b EA |
2737 | uint32_t seqno; |
2738 | ||
db53a302 | 2739 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2740 | return; |
2741 | ||
db53a302 | 2742 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2743 | |
b2eadbc8 | 2744 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2745 | |
e9103038 CW |
2746 | /* Move any buffers on the active list that are no longer referenced |
2747 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2748 | * before we free the context associated with the requests. | |
2749 | */ | |
2750 | while (!list_empty(&ring->active_list)) { | |
2751 | struct drm_i915_gem_object *obj; | |
2752 | ||
2753 | obj = list_first_entry(&ring->active_list, | |
2754 | struct drm_i915_gem_object, | |
2755 | ring_list); | |
2756 | ||
97b2a6a1 JH |
2757 | if (!i915_seqno_passed(seqno, |
2758 | i915_gem_request_get_seqno(obj->last_read_req))) | |
e9103038 CW |
2759 | break; |
2760 | ||
2761 | i915_gem_object_move_to_inactive(obj); | |
2762 | } | |
2763 | ||
2764 | ||
852835f3 | 2765 | while (!list_empty(&ring->request_list)) { |
673a394b | 2766 | struct drm_i915_gem_request *request; |
48e29f55 | 2767 | struct intel_ringbuffer *ringbuf; |
673a394b | 2768 | |
852835f3 | 2769 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2770 | struct drm_i915_gem_request, |
2771 | list); | |
673a394b | 2772 | |
dfaae392 | 2773 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2774 | break; |
2775 | ||
74328ee5 | 2776 | trace_i915_gem_request_retire(request); |
48e29f55 OM |
2777 | |
2778 | /* This is one of the few common intersection points | |
2779 | * between legacy ringbuffer submission and execlists: | |
2780 | * we need to tell them apart in order to find the correct | |
2781 | * ringbuffer to which the request belongs to. | |
2782 | */ | |
2783 | if (i915.enable_execlists) { | |
2784 | struct intel_context *ctx = request->ctx; | |
2785 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2786 | } else | |
2787 | ringbuf = ring->buffer; | |
2788 | ||
a71d8d94 CW |
2789 | /* We know the GPU must have read the request to have |
2790 | * sent us the seqno + interrupt, so use the position | |
2791 | * of tail of the request to update the last known position | |
2792 | * of the GPU head. | |
2793 | */ | |
48e29f55 | 2794 | ringbuf->last_retired_head = request->tail; |
b84d5f0c | 2795 | |
0e50e96b | 2796 | i915_gem_free_request(request); |
b84d5f0c | 2797 | } |
673a394b | 2798 | |
db53a302 CW |
2799 | if (unlikely(ring->trace_irq_seqno && |
2800 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2801 | ring->irq_put(ring); |
db53a302 | 2802 | ring->trace_irq_seqno = 0; |
9d34e5db | 2803 | } |
23bc5982 | 2804 | |
db53a302 | 2805 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2806 | } |
2807 | ||
b29c19b6 | 2808 | bool |
b09a1fec CW |
2809 | i915_gem_retire_requests(struct drm_device *dev) |
2810 | { | |
3e31c6c0 | 2811 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2812 | struct intel_engine_cs *ring; |
b29c19b6 | 2813 | bool idle = true; |
1ec14ad3 | 2814 | int i; |
b09a1fec | 2815 | |
b29c19b6 | 2816 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2817 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2818 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2819 | if (i915.enable_execlists) { |
2820 | unsigned long flags; | |
2821 | ||
2822 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2823 | idle &= list_empty(&ring->execlist_queue); | |
2824 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2825 | ||
2826 | intel_execlists_retire_requests(ring); | |
2827 | } | |
b29c19b6 CW |
2828 | } |
2829 | ||
2830 | if (idle) | |
2831 | mod_delayed_work(dev_priv->wq, | |
2832 | &dev_priv->mm.idle_work, | |
2833 | msecs_to_jiffies(100)); | |
2834 | ||
2835 | return idle; | |
b09a1fec CW |
2836 | } |
2837 | ||
75ef9da2 | 2838 | static void |
673a394b EA |
2839 | i915_gem_retire_work_handler(struct work_struct *work) |
2840 | { | |
b29c19b6 CW |
2841 | struct drm_i915_private *dev_priv = |
2842 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2843 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2844 | bool idle; |
673a394b | 2845 | |
891b48cf | 2846 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2847 | idle = false; |
2848 | if (mutex_trylock(&dev->struct_mutex)) { | |
2849 | idle = i915_gem_retire_requests(dev); | |
2850 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2851 | } |
b29c19b6 | 2852 | if (!idle) |
bcb45086 CW |
2853 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2854 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2855 | } |
0a58705b | 2856 | |
b29c19b6 CW |
2857 | static void |
2858 | i915_gem_idle_work_handler(struct work_struct *work) | |
2859 | { | |
2860 | struct drm_i915_private *dev_priv = | |
2861 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2862 | ||
2863 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2864 | } |
2865 | ||
30dfebf3 DV |
2866 | /** |
2867 | * Ensures that an object will eventually get non-busy by flushing any required | |
2868 | * write domains, emitting any outstanding lazy request and retiring and | |
2869 | * completed requests. | |
2870 | */ | |
2871 | static int | |
2872 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2873 | { | |
2874 | int ret; | |
2875 | ||
2876 | if (obj->active) { | |
b6660d59 | 2877 | ret = i915_gem_check_olr(obj->last_read_req); |
30dfebf3 DV |
2878 | if (ret) |
2879 | return ret; | |
2880 | ||
30dfebf3 DV |
2881 | i915_gem_retire_requests_ring(obj->ring); |
2882 | } | |
2883 | ||
2884 | return 0; | |
2885 | } | |
2886 | ||
23ba4fd0 BW |
2887 | /** |
2888 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2889 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2890 | * | |
2891 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2892 | * the timeout parameter. | |
2893 | * -ETIME: object is still busy after timeout | |
2894 | * -ERESTARTSYS: signal interrupted the wait | |
2895 | * -ENONENT: object doesn't exist | |
2896 | * Also possible, but rare: | |
2897 | * -EAGAIN: GPU wedged | |
2898 | * -ENOMEM: damn | |
2899 | * -ENODEV: Internal IRQ fail | |
2900 | * -E?: The add request failed | |
2901 | * | |
2902 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2903 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2904 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2905 | * without holding struct_mutex the object may become re-busied before this | |
2906 | * function completes. A similar but shorter * race condition exists in the busy | |
2907 | * ioctl | |
2908 | */ | |
2909 | int | |
2910 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2911 | { | |
3e31c6c0 | 2912 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2913 | struct drm_i915_gem_wait *args = data; |
2914 | struct drm_i915_gem_object *obj; | |
ff865885 | 2915 | struct drm_i915_gem_request *req; |
f69061be | 2916 | unsigned reset_counter; |
23ba4fd0 BW |
2917 | int ret = 0; |
2918 | ||
11b5d511 DV |
2919 | if (args->flags != 0) |
2920 | return -EINVAL; | |
2921 | ||
23ba4fd0 BW |
2922 | ret = i915_mutex_lock_interruptible(dev); |
2923 | if (ret) | |
2924 | return ret; | |
2925 | ||
2926 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2927 | if (&obj->base == NULL) { | |
2928 | mutex_unlock(&dev->struct_mutex); | |
2929 | return -ENOENT; | |
2930 | } | |
2931 | ||
30dfebf3 DV |
2932 | /* Need to make sure the object gets inactive eventually. */ |
2933 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2934 | if (ret) |
2935 | goto out; | |
2936 | ||
97b2a6a1 JH |
2937 | if (!obj->active || !obj->last_read_req) |
2938 | goto out; | |
23ba4fd0 | 2939 | |
ff865885 | 2940 | req = obj->last_read_req; |
23ba4fd0 | 2941 | |
23ba4fd0 | 2942 | /* Do this after OLR check to make sure we make forward progress polling |
5ed0bdf2 | 2943 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
23ba4fd0 | 2944 | */ |
5ed0bdf2 | 2945 | if (args->timeout_ns <= 0) { |
23ba4fd0 BW |
2946 | ret = -ETIME; |
2947 | goto out; | |
2948 | } | |
2949 | ||
2950 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2951 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 2952 | i915_gem_request_reference(req); |
23ba4fd0 BW |
2953 | mutex_unlock(&dev->struct_mutex); |
2954 | ||
9c654818 JH |
2955 | ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns, |
2956 | file->driver_priv); | |
ff865885 JH |
2957 | mutex_lock(&dev->struct_mutex); |
2958 | i915_gem_request_unreference(req); | |
2959 | mutex_unlock(&dev->struct_mutex); | |
2960 | return ret; | |
23ba4fd0 BW |
2961 | |
2962 | out: | |
2963 | drm_gem_object_unreference(&obj->base); | |
2964 | mutex_unlock(&dev->struct_mutex); | |
2965 | return ret; | |
2966 | } | |
2967 | ||
5816d648 BW |
2968 | /** |
2969 | * i915_gem_object_sync - sync an object to a ring. | |
2970 | * | |
2971 | * @obj: object which may be in use on another ring. | |
2972 | * @to: ring we wish to use the object on. May be NULL. | |
2973 | * | |
2974 | * This code is meant to abstract object synchronization with the GPU. | |
2975 | * Calling with NULL implies synchronizing the object with the CPU | |
2976 | * rather than a particular GPU ring. | |
2977 | * | |
2978 | * Returns 0 if successful, else propagates up the lower layer error. | |
2979 | */ | |
2911a35b BW |
2980 | int |
2981 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2982 | struct intel_engine_cs *to) |
2911a35b | 2983 | { |
a4872ba6 | 2984 | struct intel_engine_cs *from = obj->ring; |
2911a35b BW |
2985 | u32 seqno; |
2986 | int ret, idx; | |
2987 | ||
2988 | if (from == NULL || to == from) | |
2989 | return 0; | |
2990 | ||
5816d648 | 2991 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2992 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2993 | |
2994 | idx = intel_ring_sync_index(from, to); | |
2995 | ||
97b2a6a1 | 2996 | seqno = i915_gem_request_get_seqno(obj->last_read_req); |
ddd4dbc6 RV |
2997 | /* Optimization: Avoid semaphore sync when we are sure we already |
2998 | * waited for an object with higher seqno */ | |
ebc348b2 | 2999 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
3000 | return 0; |
3001 | ||
b6660d59 | 3002 | ret = i915_gem_check_olr(obj->last_read_req); |
b4aca010 BW |
3003 | if (ret) |
3004 | return ret; | |
2911a35b | 3005 | |
74328ee5 | 3006 | trace_i915_gem_ring_sync_to(from, to, obj->last_read_req); |
ebc348b2 | 3007 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 3008 | if (!ret) |
97b2a6a1 | 3009 | /* We use last_read_req because sync_to() |
7b01e260 MK |
3010 | * might have just caused seqno wrap under |
3011 | * the radar. | |
3012 | */ | |
97b2a6a1 JH |
3013 | from->semaphore.sync_seqno[idx] = |
3014 | i915_gem_request_get_seqno(obj->last_read_req); | |
2911a35b | 3015 | |
e3a5a225 | 3016 | return ret; |
2911a35b BW |
3017 | } |
3018 | ||
b5ffc9bc CW |
3019 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3020 | { | |
3021 | u32 old_write_domain, old_read_domains; | |
3022 | ||
b5ffc9bc CW |
3023 | /* Force a pagefault for domain tracking on next user access */ |
3024 | i915_gem_release_mmap(obj); | |
3025 | ||
b97c3d9c KP |
3026 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3027 | return; | |
3028 | ||
97c809fd CW |
3029 | /* Wait for any direct GTT access to complete */ |
3030 | mb(); | |
3031 | ||
b5ffc9bc CW |
3032 | old_read_domains = obj->base.read_domains; |
3033 | old_write_domain = obj->base.write_domain; | |
3034 | ||
3035 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3036 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3037 | ||
3038 | trace_i915_gem_object_change_domain(obj, | |
3039 | old_read_domains, | |
3040 | old_write_domain); | |
3041 | } | |
3042 | ||
07fe0b12 | 3043 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 3044 | { |
07fe0b12 | 3045 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3046 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3047 | int ret; |
673a394b | 3048 | |
07fe0b12 | 3049 | if (list_empty(&vma->vma_link)) |
673a394b EA |
3050 | return 0; |
3051 | ||
0ff501cb DV |
3052 | if (!drm_mm_node_allocated(&vma->node)) { |
3053 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3054 | return 0; |
3055 | } | |
433544bd | 3056 | |
d7f46fc4 | 3057 | if (vma->pin_count) |
31d8d651 | 3058 | return -EBUSY; |
673a394b | 3059 | |
c4670ad0 CW |
3060 | BUG_ON(obj->pages == NULL); |
3061 | ||
a8198eea | 3062 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 3063 | if (ret) |
a8198eea CW |
3064 | return ret; |
3065 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
3066 | * should be safe and we need to cleanup or else we might | |
3067 | * cause memory corruption through use-after-free. | |
3068 | */ | |
3069 | ||
1d1ef21d CW |
3070 | /* Throw away the active reference before moving to the unbound list */ |
3071 | i915_gem_object_retire(obj); | |
3072 | ||
8b1bc9b4 DV |
3073 | if (i915_is_ggtt(vma->vm)) { |
3074 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 3075 | |
8b1bc9b4 DV |
3076 | /* release the fence reg _after_ flushing */ |
3077 | ret = i915_gem_object_put_fence(obj); | |
3078 | if (ret) | |
3079 | return ret; | |
3080 | } | |
96b47b65 | 3081 | |
07fe0b12 | 3082 | trace_i915_vma_unbind(vma); |
db53a302 | 3083 | |
6f65e29a BW |
3084 | vma->unbind_vma(vma); |
3085 | ||
64bf9303 | 3086 | list_del_init(&vma->mm_list); |
5cacaac7 | 3087 | if (i915_is_ggtt(vma->vm)) |
e6a84468 | 3088 | obj->map_and_fenceable = false; |
673a394b | 3089 | |
2f633156 BW |
3090 | drm_mm_remove_node(&vma->node); |
3091 | i915_gem_vma_destroy(vma); | |
3092 | ||
3093 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3094 | * no more VMAs exist. */ |
9490edb5 AR |
3095 | if (list_empty(&obj->vma_list)) { |
3096 | i915_gem_gtt_finish_object(obj); | |
2f633156 | 3097 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 3098 | } |
673a394b | 3099 | |
70903c3b CW |
3100 | /* And finally now the object is completely decoupled from this vma, |
3101 | * we can drop its hold on the backing storage and allow it to be | |
3102 | * reaped by the shrinker. | |
3103 | */ | |
3104 | i915_gem_object_unpin_pages(obj); | |
3105 | ||
88241785 | 3106 | return 0; |
54cf91dc CW |
3107 | } |
3108 | ||
b2da9fe5 | 3109 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3110 | { |
3e31c6c0 | 3111 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3112 | struct intel_engine_cs *ring; |
1ec14ad3 | 3113 | int ret, i; |
4df2faf4 | 3114 | |
4df2faf4 | 3115 | /* Flush everything onto the inactive list. */ |
b4519513 | 3116 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3117 | if (!i915.enable_execlists) { |
3118 | ret = i915_switch_context(ring, ring->default_context); | |
3119 | if (ret) | |
3120 | return ret; | |
3121 | } | |
b6c7488d | 3122 | |
3e960501 | 3123 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3124 | if (ret) |
3125 | return ret; | |
3126 | } | |
4df2faf4 | 3127 | |
8a1a49f9 | 3128 | return 0; |
4df2faf4 DV |
3129 | } |
3130 | ||
9ce079e4 CW |
3131 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3132 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3133 | { |
3e31c6c0 | 3134 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3135 | int fence_reg; |
3136 | int fence_pitch_shift; | |
de151cf6 | 3137 | |
56c844e5 ID |
3138 | if (INTEL_INFO(dev)->gen >= 6) { |
3139 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3140 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3141 | } else { | |
3142 | fence_reg = FENCE_REG_965_0; | |
3143 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3144 | } | |
3145 | ||
d18b9619 CW |
3146 | fence_reg += reg * 8; |
3147 | ||
3148 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3149 | * we split the 64-bit update into two 32-bit writes. In order | |
3150 | * for a partial fence not to be evaluated between writes, we | |
3151 | * precede the update with write to turn off the fence register, | |
3152 | * and only enable the fence as the last step. | |
3153 | * | |
3154 | * For extra levels of paranoia, we make sure each step lands | |
3155 | * before applying the next step. | |
3156 | */ | |
3157 | I915_WRITE(fence_reg, 0); | |
3158 | POSTING_READ(fence_reg); | |
3159 | ||
9ce079e4 | 3160 | if (obj) { |
f343c5f6 | 3161 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3162 | uint64_t val; |
de151cf6 | 3163 | |
f343c5f6 | 3164 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3165 | 0xfffff000) << 32; |
f343c5f6 | 3166 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3167 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3168 | if (obj->tiling_mode == I915_TILING_Y) |
3169 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3170 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3171 | |
d18b9619 CW |
3172 | I915_WRITE(fence_reg + 4, val >> 32); |
3173 | POSTING_READ(fence_reg + 4); | |
3174 | ||
3175 | I915_WRITE(fence_reg + 0, val); | |
3176 | POSTING_READ(fence_reg); | |
3177 | } else { | |
3178 | I915_WRITE(fence_reg + 4, 0); | |
3179 | POSTING_READ(fence_reg + 4); | |
3180 | } | |
de151cf6 JB |
3181 | } |
3182 | ||
9ce079e4 CW |
3183 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3184 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3185 | { |
3e31c6c0 | 3186 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3187 | u32 val; |
de151cf6 | 3188 | |
9ce079e4 | 3189 | if (obj) { |
f343c5f6 | 3190 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3191 | int pitch_val; |
3192 | int tile_width; | |
c6642782 | 3193 | |
f343c5f6 | 3194 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3195 | (size & -size) != size || |
f343c5f6 BW |
3196 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3197 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3198 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3199 | |
9ce079e4 CW |
3200 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3201 | tile_width = 128; | |
3202 | else | |
3203 | tile_width = 512; | |
3204 | ||
3205 | /* Note: pitch better be a power of two tile widths */ | |
3206 | pitch_val = obj->stride / tile_width; | |
3207 | pitch_val = ffs(pitch_val) - 1; | |
3208 | ||
f343c5f6 | 3209 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3210 | if (obj->tiling_mode == I915_TILING_Y) |
3211 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3212 | val |= I915_FENCE_SIZE_BITS(size); | |
3213 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3214 | val |= I830_FENCE_REG_VALID; | |
3215 | } else | |
3216 | val = 0; | |
3217 | ||
3218 | if (reg < 8) | |
3219 | reg = FENCE_REG_830_0 + reg * 4; | |
3220 | else | |
3221 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3222 | ||
3223 | I915_WRITE(reg, val); | |
3224 | POSTING_READ(reg); | |
de151cf6 JB |
3225 | } |
3226 | ||
9ce079e4 CW |
3227 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3228 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3229 | { |
3e31c6c0 | 3230 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3231 | uint32_t val; |
de151cf6 | 3232 | |
9ce079e4 | 3233 | if (obj) { |
f343c5f6 | 3234 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3235 | uint32_t pitch_val; |
de151cf6 | 3236 | |
f343c5f6 | 3237 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3238 | (size & -size) != size || |
f343c5f6 BW |
3239 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3240 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3241 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3242 | |
9ce079e4 CW |
3243 | pitch_val = obj->stride / 128; |
3244 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3245 | |
f343c5f6 | 3246 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3247 | if (obj->tiling_mode == I915_TILING_Y) |
3248 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3249 | val |= I830_FENCE_SIZE_BITS(size); | |
3250 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3251 | val |= I830_FENCE_REG_VALID; | |
3252 | } else | |
3253 | val = 0; | |
c6642782 | 3254 | |
9ce079e4 CW |
3255 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3256 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3257 | } | |
3258 | ||
d0a57789 CW |
3259 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3260 | { | |
3261 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3262 | } | |
3263 | ||
9ce079e4 CW |
3264 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3265 | struct drm_i915_gem_object *obj) | |
3266 | { | |
d0a57789 CW |
3267 | struct drm_i915_private *dev_priv = dev->dev_private; |
3268 | ||
3269 | /* Ensure that all CPU reads are completed before installing a fence | |
3270 | * and all writes before removing the fence. | |
3271 | */ | |
3272 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3273 | mb(); | |
3274 | ||
94a335db DV |
3275 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3276 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3277 | obj->stride, obj->tiling_mode); | |
3278 | ||
9ce079e4 | 3279 | switch (INTEL_INFO(dev)->gen) { |
01209dd5 | 3280 | case 9: |
5ab31333 | 3281 | case 8: |
9ce079e4 | 3282 | case 7: |
56c844e5 | 3283 | case 6: |
9ce079e4 CW |
3284 | case 5: |
3285 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3286 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3287 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3288 | default: BUG(); |
9ce079e4 | 3289 | } |
d0a57789 CW |
3290 | |
3291 | /* And similarly be paranoid that no direct access to this region | |
3292 | * is reordered to before the fence is installed. | |
3293 | */ | |
3294 | if (i915_gem_object_needs_mb(obj)) | |
3295 | mb(); | |
de151cf6 JB |
3296 | } |
3297 | ||
61050808 CW |
3298 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3299 | struct drm_i915_fence_reg *fence) | |
3300 | { | |
3301 | return fence - dev_priv->fence_regs; | |
3302 | } | |
3303 | ||
3304 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3305 | struct drm_i915_fence_reg *fence, | |
3306 | bool enable) | |
3307 | { | |
2dc8aae0 | 3308 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3309 | int reg = fence_number(dev_priv, fence); |
3310 | ||
3311 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3312 | |
3313 | if (enable) { | |
46a0b638 | 3314 | obj->fence_reg = reg; |
61050808 CW |
3315 | fence->obj = obj; |
3316 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3317 | } else { | |
3318 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3319 | fence->obj = NULL; | |
3320 | list_del_init(&fence->lru_list); | |
3321 | } | |
94a335db | 3322 | obj->fence_dirty = false; |
61050808 CW |
3323 | } |
3324 | ||
d9e86c0e | 3325 | static int |
d0a57789 | 3326 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3327 | { |
97b2a6a1 | 3328 | if (obj->last_fenced_req) { |
a4b3a571 | 3329 | int ret = i915_wait_request(obj->last_fenced_req); |
18991845 CW |
3330 | if (ret) |
3331 | return ret; | |
d9e86c0e | 3332 | |
97b2a6a1 | 3333 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
d9e86c0e CW |
3334 | } |
3335 | ||
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | int | |
3340 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3341 | { | |
61050808 | 3342 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3343 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3344 | int ret; |
3345 | ||
d0a57789 | 3346 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3347 | if (ret) |
3348 | return ret; | |
3349 | ||
61050808 CW |
3350 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3351 | return 0; | |
d9e86c0e | 3352 | |
f9c513e9 CW |
3353 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3354 | ||
aff10b30 DV |
3355 | if (WARN_ON(fence->pin_count)) |
3356 | return -EBUSY; | |
3357 | ||
61050808 | 3358 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3359 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3360 | |
3361 | return 0; | |
3362 | } | |
3363 | ||
3364 | static struct drm_i915_fence_reg * | |
a360bb1a | 3365 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3366 | { |
ae3db24a | 3367 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3368 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3369 | int i; |
ae3db24a DV |
3370 | |
3371 | /* First try to find a free reg */ | |
d9e86c0e | 3372 | avail = NULL; |
ae3db24a DV |
3373 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3374 | reg = &dev_priv->fence_regs[i]; | |
3375 | if (!reg->obj) | |
d9e86c0e | 3376 | return reg; |
ae3db24a | 3377 | |
1690e1eb | 3378 | if (!reg->pin_count) |
d9e86c0e | 3379 | avail = reg; |
ae3db24a DV |
3380 | } |
3381 | ||
d9e86c0e | 3382 | if (avail == NULL) |
5dce5b93 | 3383 | goto deadlock; |
ae3db24a DV |
3384 | |
3385 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3386 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3387 | if (reg->pin_count) |
ae3db24a DV |
3388 | continue; |
3389 | ||
8fe301ad | 3390 | return reg; |
ae3db24a DV |
3391 | } |
3392 | ||
5dce5b93 CW |
3393 | deadlock: |
3394 | /* Wait for completion of pending flips which consume fences */ | |
3395 | if (intel_has_pending_fb_unpin(dev)) | |
3396 | return ERR_PTR(-EAGAIN); | |
3397 | ||
3398 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3399 | } |
3400 | ||
de151cf6 | 3401 | /** |
9a5a53b3 | 3402 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3403 | * @obj: object to map through a fence reg |
3404 | * | |
3405 | * When mapping objects through the GTT, userspace wants to be able to write | |
3406 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3407 | * This function walks the fence regs looking for a free one for @obj, |
3408 | * stealing one if it can't find any. | |
3409 | * | |
3410 | * It then sets up the reg based on the object's properties: address, pitch | |
3411 | * and tiling format. | |
9a5a53b3 CW |
3412 | * |
3413 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3414 | */ |
8c4b8c3f | 3415 | int |
06d98131 | 3416 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3417 | { |
05394f39 | 3418 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3419 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3420 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3421 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3422 | int ret; |
de151cf6 | 3423 | |
14415745 CW |
3424 | /* Have we updated the tiling parameters upon the object and so |
3425 | * will need to serialise the write to the associated fence register? | |
3426 | */ | |
5d82e3e6 | 3427 | if (obj->fence_dirty) { |
d0a57789 | 3428 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3429 | if (ret) |
3430 | return ret; | |
3431 | } | |
9a5a53b3 | 3432 | |
d9e86c0e | 3433 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3434 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3435 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3436 | if (!obj->fence_dirty) { |
14415745 CW |
3437 | list_move_tail(®->lru_list, |
3438 | &dev_priv->mm.fence_list); | |
3439 | return 0; | |
3440 | } | |
3441 | } else if (enable) { | |
e6a84468 CW |
3442 | if (WARN_ON(!obj->map_and_fenceable)) |
3443 | return -EINVAL; | |
3444 | ||
14415745 | 3445 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3446 | if (IS_ERR(reg)) |
3447 | return PTR_ERR(reg); | |
d9e86c0e | 3448 | |
14415745 CW |
3449 | if (reg->obj) { |
3450 | struct drm_i915_gem_object *old = reg->obj; | |
3451 | ||
d0a57789 | 3452 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3453 | if (ret) |
3454 | return ret; | |
3455 | ||
14415745 | 3456 | i915_gem_object_fence_lost(old); |
29c5a587 | 3457 | } |
14415745 | 3458 | } else |
a09ba7fa | 3459 | return 0; |
a09ba7fa | 3460 | |
14415745 | 3461 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3462 | |
9ce079e4 | 3463 | return 0; |
de151cf6 JB |
3464 | } |
3465 | ||
4144f9b5 | 3466 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3467 | unsigned long cache_level) |
3468 | { | |
4144f9b5 | 3469 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3470 | struct drm_mm_node *other; |
3471 | ||
4144f9b5 CW |
3472 | /* |
3473 | * On some machines we have to be careful when putting differing types | |
3474 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3475 | * domains and dying. During vm initialisation, we decide whether or not | |
3476 | * these constraints apply and set the drm_mm.color_adjust | |
3477 | * appropriately. | |
42d6ab48 | 3478 | */ |
4144f9b5 | 3479 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3480 | return true; |
3481 | ||
c6cfb325 | 3482 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3483 | return true; |
3484 | ||
3485 | if (list_empty(>t_space->node_list)) | |
3486 | return true; | |
3487 | ||
3488 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3489 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3490 | return false; | |
3491 | ||
3492 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3493 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3494 | return false; | |
3495 | ||
3496 | return true; | |
3497 | } | |
3498 | ||
673a394b EA |
3499 | /** |
3500 | * Finds free space in the GTT aperture and binds the object there. | |
3501 | */ | |
262de145 | 3502 | static struct i915_vma * |
07fe0b12 BW |
3503 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3504 | struct i915_address_space *vm, | |
3505 | unsigned alignment, | |
d23db88c | 3506 | uint64_t flags) |
673a394b | 3507 | { |
05394f39 | 3508 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3509 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3510 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3511 | unsigned long start = |
3512 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3513 | unsigned long end = | |
1ec9e26d | 3514 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3515 | struct i915_vma *vma; |
07f73f69 | 3516 | int ret; |
673a394b | 3517 | |
e28f8711 CW |
3518 | fence_size = i915_gem_get_gtt_size(dev, |
3519 | obj->base.size, | |
3520 | obj->tiling_mode); | |
3521 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3522 | obj->base.size, | |
d865110c | 3523 | obj->tiling_mode, true); |
e28f8711 | 3524 | unfenced_alignment = |
d865110c | 3525 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3526 | obj->base.size, |
3527 | obj->tiling_mode, false); | |
a00b10c3 | 3528 | |
673a394b | 3529 | if (alignment == 0) |
1ec9e26d | 3530 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3531 | unfenced_alignment; |
1ec9e26d | 3532 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3533 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3534 | return ERR_PTR(-EINVAL); |
673a394b EA |
3535 | } |
3536 | ||
1ec9e26d | 3537 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3538 | |
654fc607 CW |
3539 | /* If the object is bigger than the entire aperture, reject it early |
3540 | * before evicting everything in a vain attempt to find space. | |
3541 | */ | |
d23db88c CW |
3542 | if (obj->base.size > end) { |
3543 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3544 | obj->base.size, |
1ec9e26d | 3545 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3546 | end); |
262de145 | 3547 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3548 | } |
3549 | ||
37e680a1 | 3550 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3551 | if (ret) |
262de145 | 3552 | return ERR_PTR(ret); |
6c085a72 | 3553 | |
fbdda6fb CW |
3554 | i915_gem_object_pin_pages(obj); |
3555 | ||
accfef2e | 3556 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3557 | if (IS_ERR(vma)) |
bc6bc15b | 3558 | goto err_unpin; |
2f633156 | 3559 | |
0a9ae0d7 | 3560 | search_free: |
07fe0b12 | 3561 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3562 | size, alignment, |
d23db88c CW |
3563 | obj->cache_level, |
3564 | start, end, | |
62347f9e LK |
3565 | DRM_MM_SEARCH_DEFAULT, |
3566 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3567 | if (ret) { |
f6cd1f15 | 3568 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3569 | obj->cache_level, |
3570 | start, end, | |
3571 | flags); | |
dc9dd7a2 CW |
3572 | if (ret == 0) |
3573 | goto search_free; | |
9731129c | 3574 | |
bc6bc15b | 3575 | goto err_free_vma; |
673a394b | 3576 | } |
4144f9b5 | 3577 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3578 | ret = -EINVAL; |
bc6bc15b | 3579 | goto err_remove_node; |
673a394b EA |
3580 | } |
3581 | ||
74163907 | 3582 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3583 | if (ret) |
bc6bc15b | 3584 | goto err_remove_node; |
673a394b | 3585 | |
35c20a60 | 3586 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3587 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3588 | |
1ec9e26d | 3589 | trace_i915_vma_bind(vma, flags); |
8ea99c92 | 3590 | vma->bind_vma(vma, obj->cache_level, |
c826c449 | 3591 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); |
8ea99c92 | 3592 | |
262de145 | 3593 | return vma; |
2f633156 | 3594 | |
bc6bc15b | 3595 | err_remove_node: |
6286ef9b | 3596 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3597 | err_free_vma: |
2f633156 | 3598 | i915_gem_vma_destroy(vma); |
262de145 | 3599 | vma = ERR_PTR(ret); |
bc6bc15b | 3600 | err_unpin: |
2f633156 | 3601 | i915_gem_object_unpin_pages(obj); |
262de145 | 3602 | return vma; |
673a394b EA |
3603 | } |
3604 | ||
000433b6 | 3605 | bool |
2c22569b CW |
3606 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3607 | bool force) | |
673a394b | 3608 | { |
673a394b EA |
3609 | /* If we don't have a page list set up, then we're not pinned |
3610 | * to GPU, and we can ignore the cache flush because it'll happen | |
3611 | * again at bind time. | |
3612 | */ | |
05394f39 | 3613 | if (obj->pages == NULL) |
000433b6 | 3614 | return false; |
673a394b | 3615 | |
769ce464 ID |
3616 | /* |
3617 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3618 | * marked as wc by the system, or the system is cache-coherent. | |
3619 | */ | |
6a2c4232 | 3620 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3621 | return false; |
769ce464 | 3622 | |
9c23f7fc CW |
3623 | /* If the GPU is snooping the contents of the CPU cache, |
3624 | * we do not need to manually clear the CPU cache lines. However, | |
3625 | * the caches are only snooped when the render cache is | |
3626 | * flushed/invalidated. As we always have to emit invalidations | |
3627 | * and flushes when moving into and out of the RENDER domain, correct | |
3628 | * snooping behaviour occurs naturally as the result of our domain | |
3629 | * tracking. | |
3630 | */ | |
2c22569b | 3631 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3632 | return false; |
9c23f7fc | 3633 | |
1c5d22f7 | 3634 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3635 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3636 | |
3637 | return true; | |
e47c68e9 EA |
3638 | } |
3639 | ||
3640 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3641 | static void | |
05394f39 | 3642 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3643 | { |
1c5d22f7 CW |
3644 | uint32_t old_write_domain; |
3645 | ||
05394f39 | 3646 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3647 | return; |
3648 | ||
63256ec5 | 3649 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3650 | * to it immediately go to main memory as far as we know, so there's |
3651 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3652 | * |
3653 | * However, we do have to enforce the order so that all writes through | |
3654 | * the GTT land before any writes to the device, such as updates to | |
3655 | * the GATT itself. | |
e47c68e9 | 3656 | */ |
63256ec5 CW |
3657 | wmb(); |
3658 | ||
05394f39 CW |
3659 | old_write_domain = obj->base.write_domain; |
3660 | obj->base.write_domain = 0; | |
1c5d22f7 | 3661 | |
f99d7069 DV |
3662 | intel_fb_obj_flush(obj, false); |
3663 | ||
1c5d22f7 | 3664 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3665 | obj->base.read_domains, |
1c5d22f7 | 3666 | old_write_domain); |
e47c68e9 EA |
3667 | } |
3668 | ||
3669 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3670 | static void | |
2c22569b CW |
3671 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3672 | bool force) | |
e47c68e9 | 3673 | { |
1c5d22f7 | 3674 | uint32_t old_write_domain; |
e47c68e9 | 3675 | |
05394f39 | 3676 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3677 | return; |
3678 | ||
000433b6 CW |
3679 | if (i915_gem_clflush_object(obj, force)) |
3680 | i915_gem_chipset_flush(obj->base.dev); | |
3681 | ||
05394f39 CW |
3682 | old_write_domain = obj->base.write_domain; |
3683 | obj->base.write_domain = 0; | |
1c5d22f7 | 3684 | |
f99d7069 DV |
3685 | intel_fb_obj_flush(obj, false); |
3686 | ||
1c5d22f7 | 3687 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3688 | obj->base.read_domains, |
1c5d22f7 | 3689 | old_write_domain); |
e47c68e9 EA |
3690 | } |
3691 | ||
2ef7eeaa EA |
3692 | /** |
3693 | * Moves a single object to the GTT read, and possibly write domain. | |
3694 | * | |
3695 | * This function returns when the move is complete, including waiting on | |
3696 | * flushes to occur. | |
3697 | */ | |
79e53945 | 3698 | int |
2021746e | 3699 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3700 | { |
3e31c6c0 | 3701 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
dc8cd1e7 | 3702 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
1c5d22f7 | 3703 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3704 | int ret; |
2ef7eeaa | 3705 | |
02354392 | 3706 | /* Not valid to be called on unbound objects. */ |
dc8cd1e7 | 3707 | if (vma == NULL) |
02354392 EA |
3708 | return -EINVAL; |
3709 | ||
8d7e3de1 CW |
3710 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3711 | return 0; | |
3712 | ||
0201f1ec | 3713 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3714 | if (ret) |
3715 | return ret; | |
3716 | ||
c8725f3d | 3717 | i915_gem_object_retire(obj); |
2c22569b | 3718 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3719 | |
d0a57789 CW |
3720 | /* Serialise direct access to this object with the barriers for |
3721 | * coherent writes from the GPU, by effectively invalidating the | |
3722 | * GTT domain upon first access. | |
3723 | */ | |
3724 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3725 | mb(); | |
3726 | ||
05394f39 CW |
3727 | old_write_domain = obj->base.write_domain; |
3728 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3729 | |
e47c68e9 EA |
3730 | /* It should now be out of any other write domains, and we can update |
3731 | * the domain values for our changes. | |
3732 | */ | |
05394f39 CW |
3733 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3734 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3735 | if (write) { |
05394f39 CW |
3736 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3737 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3738 | obj->dirty = 1; | |
2ef7eeaa EA |
3739 | } |
3740 | ||
f99d7069 DV |
3741 | if (write) |
3742 | intel_fb_obj_invalidate(obj, NULL); | |
3743 | ||
1c5d22f7 CW |
3744 | trace_i915_gem_object_change_domain(obj, |
3745 | old_read_domains, | |
3746 | old_write_domain); | |
3747 | ||
8325a09d | 3748 | /* And bump the LRU for this access */ |
dc8cd1e7 CW |
3749 | if (i915_gem_object_is_inactive(obj)) |
3750 | list_move_tail(&vma->mm_list, | |
3751 | &dev_priv->gtt.base.inactive_list); | |
8325a09d | 3752 | |
e47c68e9 EA |
3753 | return 0; |
3754 | } | |
3755 | ||
e4ffd173 CW |
3756 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3757 | enum i915_cache_level cache_level) | |
3758 | { | |
7bddb01f | 3759 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3760 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3761 | int ret; |
3762 | ||
3763 | if (obj->cache_level == cache_level) | |
3764 | return 0; | |
3765 | ||
d7f46fc4 | 3766 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3767 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3768 | return -EBUSY; | |
3769 | } | |
3770 | ||
df6f783a | 3771 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3772 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3773 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3774 | if (ret) |
3775 | return ret; | |
3089c6f2 | 3776 | } |
42d6ab48 CW |
3777 | } |
3778 | ||
3089c6f2 | 3779 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3780 | ret = i915_gem_object_finish_gpu(obj); |
3781 | if (ret) | |
3782 | return ret; | |
3783 | ||
3784 | i915_gem_object_finish_gtt(obj); | |
3785 | ||
3786 | /* Before SandyBridge, you could not use tiling or fence | |
3787 | * registers with snooped memory, so relinquish any fences | |
3788 | * currently pointing to our region in the aperture. | |
3789 | */ | |
42d6ab48 | 3790 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3791 | ret = i915_gem_object_put_fence(obj); |
3792 | if (ret) | |
3793 | return ret; | |
3794 | } | |
3795 | ||
6f65e29a | 3796 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3797 | if (drm_mm_node_allocated(&vma->node)) |
3798 | vma->bind_vma(vma, cache_level, | |
aff43766 | 3799 | vma->bound & GLOBAL_BIND); |
e4ffd173 CW |
3800 | } |
3801 | ||
2c22569b CW |
3802 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3803 | vma->node.color = cache_level; | |
3804 | obj->cache_level = cache_level; | |
3805 | ||
3806 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3807 | u32 old_read_domains, old_write_domain; |
3808 | ||
3809 | /* If we're coming from LLC cached, then we haven't | |
3810 | * actually been tracking whether the data is in the | |
3811 | * CPU cache or not, since we only allow one bit set | |
3812 | * in obj->write_domain and have been skipping the clflushes. | |
3813 | * Just set it to the CPU cache for now. | |
3814 | */ | |
c8725f3d | 3815 | i915_gem_object_retire(obj); |
e4ffd173 | 3816 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3817 | |
3818 | old_read_domains = obj->base.read_domains; | |
3819 | old_write_domain = obj->base.write_domain; | |
3820 | ||
3821 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3822 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3823 | ||
3824 | trace_i915_gem_object_change_domain(obj, | |
3825 | old_read_domains, | |
3826 | old_write_domain); | |
3827 | } | |
3828 | ||
e4ffd173 CW |
3829 | return 0; |
3830 | } | |
3831 | ||
199adf40 BW |
3832 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3833 | struct drm_file *file) | |
e6994aee | 3834 | { |
199adf40 | 3835 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3836 | struct drm_i915_gem_object *obj; |
3837 | int ret; | |
3838 | ||
3839 | ret = i915_mutex_lock_interruptible(dev); | |
3840 | if (ret) | |
3841 | return ret; | |
3842 | ||
3843 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3844 | if (&obj->base == NULL) { | |
3845 | ret = -ENOENT; | |
3846 | goto unlock; | |
3847 | } | |
3848 | ||
651d794f CW |
3849 | switch (obj->cache_level) { |
3850 | case I915_CACHE_LLC: | |
3851 | case I915_CACHE_L3_LLC: | |
3852 | args->caching = I915_CACHING_CACHED; | |
3853 | break; | |
3854 | ||
4257d3ba CW |
3855 | case I915_CACHE_WT: |
3856 | args->caching = I915_CACHING_DISPLAY; | |
3857 | break; | |
3858 | ||
651d794f CW |
3859 | default: |
3860 | args->caching = I915_CACHING_NONE; | |
3861 | break; | |
3862 | } | |
e6994aee CW |
3863 | |
3864 | drm_gem_object_unreference(&obj->base); | |
3865 | unlock: | |
3866 | mutex_unlock(&dev->struct_mutex); | |
3867 | return ret; | |
3868 | } | |
3869 | ||
199adf40 BW |
3870 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3871 | struct drm_file *file) | |
e6994aee | 3872 | { |
199adf40 | 3873 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3874 | struct drm_i915_gem_object *obj; |
3875 | enum i915_cache_level level; | |
3876 | int ret; | |
3877 | ||
199adf40 BW |
3878 | switch (args->caching) { |
3879 | case I915_CACHING_NONE: | |
e6994aee CW |
3880 | level = I915_CACHE_NONE; |
3881 | break; | |
199adf40 | 3882 | case I915_CACHING_CACHED: |
e6994aee CW |
3883 | level = I915_CACHE_LLC; |
3884 | break; | |
4257d3ba CW |
3885 | case I915_CACHING_DISPLAY: |
3886 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3887 | break; | |
e6994aee CW |
3888 | default: |
3889 | return -EINVAL; | |
3890 | } | |
3891 | ||
3bc2913e BW |
3892 | ret = i915_mutex_lock_interruptible(dev); |
3893 | if (ret) | |
3894 | return ret; | |
3895 | ||
e6994aee CW |
3896 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3897 | if (&obj->base == NULL) { | |
3898 | ret = -ENOENT; | |
3899 | goto unlock; | |
3900 | } | |
3901 | ||
3902 | ret = i915_gem_object_set_cache_level(obj, level); | |
3903 | ||
3904 | drm_gem_object_unreference(&obj->base); | |
3905 | unlock: | |
3906 | mutex_unlock(&dev->struct_mutex); | |
3907 | return ret; | |
3908 | } | |
3909 | ||
cc98b413 CW |
3910 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3911 | { | |
19656430 OM |
3912 | struct i915_vma *vma; |
3913 | ||
19656430 OM |
3914 | vma = i915_gem_obj_to_ggtt(obj); |
3915 | if (!vma) | |
3916 | return false; | |
3917 | ||
4feb7659 | 3918 | /* There are 2 sources that pin objects: |
cc98b413 CW |
3919 | * 1. The display engine (scanouts, sprites, cursors); |
3920 | * 2. Reservations for execbuffer; | |
cc98b413 CW |
3921 | * |
3922 | * We can ignore reservations as we hold the struct_mutex and | |
4feb7659 | 3923 | * are only called outside of the reservation path. |
cc98b413 | 3924 | */ |
4feb7659 | 3925 | return vma->pin_count; |
cc98b413 CW |
3926 | } |
3927 | ||
b9241ea3 | 3928 | /* |
2da3b9b9 CW |
3929 | * Prepare buffer for display plane (scanout, cursors, etc). |
3930 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3931 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3932 | */ |
3933 | int | |
2da3b9b9 CW |
3934 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3935 | u32 alignment, | |
a4872ba6 | 3936 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3937 | { |
2da3b9b9 | 3938 | u32 old_read_domains, old_write_domain; |
19656430 | 3939 | bool was_pin_display; |
b9241ea3 ZW |
3940 | int ret; |
3941 | ||
0be73284 | 3942 | if (pipelined != obj->ring) { |
2911a35b BW |
3943 | ret = i915_gem_object_sync(obj, pipelined); |
3944 | if (ret) | |
b9241ea3 ZW |
3945 | return ret; |
3946 | } | |
3947 | ||
cc98b413 CW |
3948 | /* Mark the pin_display early so that we account for the |
3949 | * display coherency whilst setting up the cache domains. | |
3950 | */ | |
19656430 | 3951 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3952 | obj->pin_display = true; |
3953 | ||
a7ef0640 EA |
3954 | /* The display engine is not coherent with the LLC cache on gen6. As |
3955 | * a result, we make sure that the pinning that is about to occur is | |
3956 | * done with uncached PTEs. This is lowest common denominator for all | |
3957 | * chipsets. | |
3958 | * | |
3959 | * However for gen6+, we could do better by using the GFDT bit instead | |
3960 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3961 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3962 | */ | |
651d794f CW |
3963 | ret = i915_gem_object_set_cache_level(obj, |
3964 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3965 | if (ret) |
cc98b413 | 3966 | goto err_unpin_display; |
a7ef0640 | 3967 | |
2da3b9b9 CW |
3968 | /* As the user may map the buffer once pinned in the display plane |
3969 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3970 | * always use map_and_fenceable for all scanout buffers. | |
3971 | */ | |
1ec9e26d | 3972 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3973 | if (ret) |
cc98b413 | 3974 | goto err_unpin_display; |
2da3b9b9 | 3975 | |
2c22569b | 3976 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3977 | |
2da3b9b9 | 3978 | old_write_domain = obj->base.write_domain; |
05394f39 | 3979 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3980 | |
3981 | /* It should now be out of any other write domains, and we can update | |
3982 | * the domain values for our changes. | |
3983 | */ | |
e5f1d962 | 3984 | obj->base.write_domain = 0; |
05394f39 | 3985 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3986 | |
3987 | trace_i915_gem_object_change_domain(obj, | |
3988 | old_read_domains, | |
2da3b9b9 | 3989 | old_write_domain); |
b9241ea3 ZW |
3990 | |
3991 | return 0; | |
cc98b413 CW |
3992 | |
3993 | err_unpin_display: | |
19656430 OM |
3994 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3995 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3996 | return ret; |
3997 | } | |
3998 | ||
3999 | void | |
4000 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
4001 | { | |
d7f46fc4 | 4002 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 4003 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
4004 | } |
4005 | ||
85345517 | 4006 | int |
a8198eea | 4007 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 4008 | { |
88241785 CW |
4009 | int ret; |
4010 | ||
a8198eea | 4011 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
4012 | return 0; |
4013 | ||
0201f1ec | 4014 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
4015 | if (ret) |
4016 | return ret; | |
4017 | ||
a8198eea CW |
4018 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
4019 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 4020 | return 0; |
85345517 CW |
4021 | } |
4022 | ||
e47c68e9 EA |
4023 | /** |
4024 | * Moves a single object to the CPU read, and possibly write domain. | |
4025 | * | |
4026 | * This function returns when the move is complete, including waiting on | |
4027 | * flushes to occur. | |
4028 | */ | |
dabdfe02 | 4029 | int |
919926ae | 4030 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4031 | { |
1c5d22f7 | 4032 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4033 | int ret; |
4034 | ||
8d7e3de1 CW |
4035 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4036 | return 0; | |
4037 | ||
0201f1ec | 4038 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4039 | if (ret) |
4040 | return ret; | |
4041 | ||
c8725f3d | 4042 | i915_gem_object_retire(obj); |
e47c68e9 | 4043 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4044 | |
05394f39 CW |
4045 | old_write_domain = obj->base.write_domain; |
4046 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4047 | |
e47c68e9 | 4048 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4049 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4050 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4051 | |
05394f39 | 4052 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4053 | } |
4054 | ||
4055 | /* It should now be out of any other write domains, and we can update | |
4056 | * the domain values for our changes. | |
4057 | */ | |
05394f39 | 4058 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4059 | |
4060 | /* If we're writing through the CPU, then the GPU read domains will | |
4061 | * need to be invalidated at next use. | |
4062 | */ | |
4063 | if (write) { | |
05394f39 CW |
4064 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4065 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4066 | } |
2ef7eeaa | 4067 | |
f99d7069 DV |
4068 | if (write) |
4069 | intel_fb_obj_invalidate(obj, NULL); | |
4070 | ||
1c5d22f7 CW |
4071 | trace_i915_gem_object_change_domain(obj, |
4072 | old_read_domains, | |
4073 | old_write_domain); | |
4074 | ||
2ef7eeaa EA |
4075 | return 0; |
4076 | } | |
4077 | ||
673a394b EA |
4078 | /* Throttle our rendering by waiting until the ring has completed our requests |
4079 | * emitted over 20 msec ago. | |
4080 | * | |
b962442e EA |
4081 | * Note that if we were to use the current jiffies each time around the loop, |
4082 | * we wouldn't escape the function with any frames outstanding if the time to | |
4083 | * render a frame was over 20ms. | |
4084 | * | |
673a394b EA |
4085 | * This should get us reasonable parallelism between CPU and GPU but also |
4086 | * relatively low latency when blocking on a particular request to finish. | |
4087 | */ | |
40a5f0de | 4088 | static int |
f787a5f5 | 4089 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4090 | { |
f787a5f5 CW |
4091 | struct drm_i915_private *dev_priv = dev->dev_private; |
4092 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 4093 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
54fb2411 | 4094 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4095 | unsigned reset_counter; |
f787a5f5 | 4096 | int ret; |
93533c29 | 4097 | |
308887aa DV |
4098 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4099 | if (ret) | |
4100 | return ret; | |
4101 | ||
4102 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4103 | if (ret) | |
4104 | return ret; | |
e110e8d6 | 4105 | |
1c25595f | 4106 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4107 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4108 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4109 | break; | |
40a5f0de | 4110 | |
54fb2411 | 4111 | target = request; |
b962442e | 4112 | } |
f69061be | 4113 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4114 | if (target) |
4115 | i915_gem_request_reference(target); | |
1c25595f | 4116 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4117 | |
54fb2411 | 4118 | if (target == NULL) |
f787a5f5 | 4119 | return 0; |
2bc43b5c | 4120 | |
9c654818 | 4121 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4122 | if (ret == 0) |
4123 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4124 | |
ff865885 JH |
4125 | mutex_lock(&dev->struct_mutex); |
4126 | i915_gem_request_unreference(target); | |
4127 | mutex_unlock(&dev->struct_mutex); | |
4128 | ||
40a5f0de EA |
4129 | return ret; |
4130 | } | |
4131 | ||
d23db88c CW |
4132 | static bool |
4133 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4134 | { | |
4135 | struct drm_i915_gem_object *obj = vma->obj; | |
4136 | ||
4137 | if (alignment && | |
4138 | vma->node.start & (alignment - 1)) | |
4139 | return true; | |
4140 | ||
4141 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4142 | return true; | |
4143 | ||
4144 | if (flags & PIN_OFFSET_BIAS && | |
4145 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4146 | return true; | |
4147 | ||
4148 | return false; | |
4149 | } | |
4150 | ||
673a394b | 4151 | int |
05394f39 | 4152 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 4153 | struct i915_address_space *vm, |
05394f39 | 4154 | uint32_t alignment, |
d23db88c | 4155 | uint64_t flags) |
673a394b | 4156 | { |
6e7186af | 4157 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4158 | struct i915_vma *vma; |
ef79e17c | 4159 | unsigned bound; |
673a394b EA |
4160 | int ret; |
4161 | ||
6e7186af BW |
4162 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4163 | return -ENODEV; | |
4164 | ||
bf3d149b | 4165 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4166 | return -EINVAL; |
07fe0b12 | 4167 | |
c826c449 CW |
4168 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4169 | return -EINVAL; | |
4170 | ||
07fe0b12 | 4171 | vma = i915_gem_obj_to_vma(obj, vm); |
07fe0b12 | 4172 | if (vma) { |
d7f46fc4 BW |
4173 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4174 | return -EBUSY; | |
4175 | ||
d23db88c | 4176 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4177 | WARN(vma->pin_count, |
ae7d49d8 | 4178 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4179 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4180 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 4181 | i915_gem_obj_offset(obj, vm), alignment, |
d23db88c | 4182 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4183 | obj->map_and_fenceable); |
07fe0b12 | 4184 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4185 | if (ret) |
4186 | return ret; | |
8ea99c92 DV |
4187 | |
4188 | vma = NULL; | |
ac0c6b5a CW |
4189 | } |
4190 | } | |
4191 | ||
ef79e17c | 4192 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4193 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
4194 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
4195 | if (IS_ERR(vma)) | |
4196 | return PTR_ERR(vma); | |
22c344e9 | 4197 | } |
76446cac | 4198 | |
aff43766 | 4199 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) |
8ea99c92 | 4200 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
74898d7e | 4201 | |
ef79e17c CW |
4202 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
4203 | bool mappable, fenceable; | |
4204 | u32 fence_size, fence_alignment; | |
4205 | ||
4206 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4207 | obj->base.size, | |
4208 | obj->tiling_mode); | |
4209 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4210 | obj->base.size, | |
4211 | obj->tiling_mode, | |
4212 | true); | |
4213 | ||
4214 | fenceable = (vma->node.size == fence_size && | |
4215 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4216 | ||
4217 | mappable = (vma->node.start + obj->base.size <= | |
4218 | dev_priv->gtt.mappable_end); | |
4219 | ||
4220 | obj->map_and_fenceable = mappable && fenceable; | |
4221 | } | |
4222 | ||
4223 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); | |
4224 | ||
8ea99c92 | 4225 | vma->pin_count++; |
1ec9e26d DV |
4226 | if (flags & PIN_MAPPABLE) |
4227 | obj->pin_mappable |= true; | |
673a394b EA |
4228 | |
4229 | return 0; | |
4230 | } | |
4231 | ||
4232 | void | |
d7f46fc4 | 4233 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4234 | { |
d7f46fc4 | 4235 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4236 | |
d7f46fc4 BW |
4237 | BUG_ON(!vma); |
4238 | BUG_ON(vma->pin_count == 0); | |
4239 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4240 | ||
4241 | if (--vma->pin_count == 0) | |
6299f992 | 4242 | obj->pin_mappable = false; |
673a394b EA |
4243 | } |
4244 | ||
d8ffa60b DV |
4245 | bool |
4246 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4247 | { | |
4248 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4249 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4250 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4251 | ||
4252 | WARN_ON(!ggtt_vma || | |
4253 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4254 | ggtt_vma->pin_count); | |
4255 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4256 | return true; | |
4257 | } else | |
4258 | return false; | |
4259 | } | |
4260 | ||
4261 | void | |
4262 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4263 | { | |
4264 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4265 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4266 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4267 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4268 | } | |
4269 | } | |
4270 | ||
673a394b EA |
4271 | int |
4272 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4273 | struct drm_file *file) |
673a394b EA |
4274 | { |
4275 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4276 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4277 | int ret; |
4278 | ||
76c1dec1 | 4279 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4280 | if (ret) |
76c1dec1 | 4281 | return ret; |
673a394b | 4282 | |
05394f39 | 4283 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4284 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4285 | ret = -ENOENT; |
4286 | goto unlock; | |
673a394b | 4287 | } |
d1b851fc | 4288 | |
0be555b6 CW |
4289 | /* Count all active objects as busy, even if they are currently not used |
4290 | * by the gpu. Users of this interface expect objects to eventually | |
4291 | * become non-busy without any further actions, therefore emit any | |
4292 | * necessary flushes here. | |
c4de0a5d | 4293 | */ |
30dfebf3 | 4294 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4295 | |
30dfebf3 | 4296 | args->busy = obj->active; |
e9808edd CW |
4297 | if (obj->ring) { |
4298 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4299 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4300 | } | |
673a394b | 4301 | |
05394f39 | 4302 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4303 | unlock: |
673a394b | 4304 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4305 | return ret; |
673a394b EA |
4306 | } |
4307 | ||
4308 | int | |
4309 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4310 | struct drm_file *file_priv) | |
4311 | { | |
0206e353 | 4312 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4313 | } |
4314 | ||
3ef94daa CW |
4315 | int |
4316 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4317 | struct drm_file *file_priv) | |
4318 | { | |
656bfa3a | 4319 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4320 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4321 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4322 | int ret; |
3ef94daa CW |
4323 | |
4324 | switch (args->madv) { | |
4325 | case I915_MADV_DONTNEED: | |
4326 | case I915_MADV_WILLNEED: | |
4327 | break; | |
4328 | default: | |
4329 | return -EINVAL; | |
4330 | } | |
4331 | ||
1d7cfea1 CW |
4332 | ret = i915_mutex_lock_interruptible(dev); |
4333 | if (ret) | |
4334 | return ret; | |
4335 | ||
05394f39 | 4336 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4337 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4338 | ret = -ENOENT; |
4339 | goto unlock; | |
3ef94daa | 4340 | } |
3ef94daa | 4341 | |
d7f46fc4 | 4342 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4343 | ret = -EINVAL; |
4344 | goto out; | |
3ef94daa CW |
4345 | } |
4346 | ||
656bfa3a DV |
4347 | if (obj->pages && |
4348 | obj->tiling_mode != I915_TILING_NONE && | |
4349 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4350 | if (obj->madv == I915_MADV_WILLNEED) | |
4351 | i915_gem_object_unpin_pages(obj); | |
4352 | if (args->madv == I915_MADV_WILLNEED) | |
4353 | i915_gem_object_pin_pages(obj); | |
4354 | } | |
4355 | ||
05394f39 CW |
4356 | if (obj->madv != __I915_MADV_PURGED) |
4357 | obj->madv = args->madv; | |
3ef94daa | 4358 | |
6c085a72 CW |
4359 | /* if the object is no longer attached, discard its backing storage */ |
4360 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4361 | i915_gem_object_truncate(obj); |
4362 | ||
05394f39 | 4363 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4364 | |
1d7cfea1 | 4365 | out: |
05394f39 | 4366 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4367 | unlock: |
3ef94daa | 4368 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4369 | return ret; |
3ef94daa CW |
4370 | } |
4371 | ||
37e680a1 CW |
4372 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4373 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4374 | { |
35c20a60 | 4375 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4376 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4377 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4378 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4379 | |
37e680a1 CW |
4380 | obj->ops = ops; |
4381 | ||
0327d6ba CW |
4382 | obj->fence_reg = I915_FENCE_REG_NONE; |
4383 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4384 | |
4385 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4386 | } | |
4387 | ||
37e680a1 CW |
4388 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4389 | .get_pages = i915_gem_object_get_pages_gtt, | |
4390 | .put_pages = i915_gem_object_put_pages_gtt, | |
4391 | }; | |
4392 | ||
05394f39 CW |
4393 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4394 | size_t size) | |
ac52bc56 | 4395 | { |
c397b908 | 4396 | struct drm_i915_gem_object *obj; |
5949eac4 | 4397 | struct address_space *mapping; |
1a240d4d | 4398 | gfp_t mask; |
ac52bc56 | 4399 | |
42dcedd4 | 4400 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4401 | if (obj == NULL) |
4402 | return NULL; | |
673a394b | 4403 | |
c397b908 | 4404 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4405 | i915_gem_object_free(obj); |
c397b908 DV |
4406 | return NULL; |
4407 | } | |
673a394b | 4408 | |
bed1ea95 CW |
4409 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4410 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4411 | /* 965gm cannot relocate objects above 4GiB. */ | |
4412 | mask &= ~__GFP_HIGHMEM; | |
4413 | mask |= __GFP_DMA32; | |
4414 | } | |
4415 | ||
496ad9aa | 4416 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4417 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4418 | |
37e680a1 | 4419 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4420 | |
c397b908 DV |
4421 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4422 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4423 | |
3d29b842 ED |
4424 | if (HAS_LLC(dev)) { |
4425 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4426 | * cache) for about a 10% performance improvement |
4427 | * compared to uncached. Graphics requests other than | |
4428 | * display scanout are coherent with the CPU in | |
4429 | * accessing this cache. This means in this mode we | |
4430 | * don't need to clflush on the CPU side, and on the | |
4431 | * GPU side we only need to flush internal caches to | |
4432 | * get data visible to the CPU. | |
4433 | * | |
4434 | * However, we maintain the display planes as UC, and so | |
4435 | * need to rebind when first used as such. | |
4436 | */ | |
4437 | obj->cache_level = I915_CACHE_LLC; | |
4438 | } else | |
4439 | obj->cache_level = I915_CACHE_NONE; | |
4440 | ||
d861e338 DV |
4441 | trace_i915_gem_object_create(obj); |
4442 | ||
05394f39 | 4443 | return obj; |
c397b908 DV |
4444 | } |
4445 | ||
340fbd8c CW |
4446 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4447 | { | |
4448 | /* If we are the last user of the backing storage (be it shmemfs | |
4449 | * pages or stolen etc), we know that the pages are going to be | |
4450 | * immediately released. In this case, we can then skip copying | |
4451 | * back the contents from the GPU. | |
4452 | */ | |
4453 | ||
4454 | if (obj->madv != I915_MADV_WILLNEED) | |
4455 | return false; | |
4456 | ||
4457 | if (obj->base.filp == NULL) | |
4458 | return true; | |
4459 | ||
4460 | /* At first glance, this looks racy, but then again so would be | |
4461 | * userspace racing mmap against close. However, the first external | |
4462 | * reference to the filp can only be obtained through the | |
4463 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4464 | * acquiring such a reference whilst we are in the middle of | |
4465 | * freeing the object. | |
4466 | */ | |
4467 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4468 | } | |
4469 | ||
1488fc08 | 4470 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4471 | { |
1488fc08 | 4472 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4473 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4474 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4475 | struct i915_vma *vma, *next; |
673a394b | 4476 | |
f65c9168 PZ |
4477 | intel_runtime_pm_get(dev_priv); |
4478 | ||
26e12f89 CW |
4479 | trace_i915_gem_object_destroy(obj); |
4480 | ||
07fe0b12 | 4481 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4482 | int ret; |
4483 | ||
4484 | vma->pin_count = 0; | |
4485 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4486 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4487 | bool was_interruptible; | |
1488fc08 | 4488 | |
07fe0b12 BW |
4489 | was_interruptible = dev_priv->mm.interruptible; |
4490 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4491 | |
07fe0b12 | 4492 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4493 | |
07fe0b12 BW |
4494 | dev_priv->mm.interruptible = was_interruptible; |
4495 | } | |
1488fc08 CW |
4496 | } |
4497 | ||
1d64ae71 BW |
4498 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4499 | * before progressing. */ | |
4500 | if (obj->stolen) | |
4501 | i915_gem_object_unpin_pages(obj); | |
4502 | ||
a071fa00 DV |
4503 | WARN_ON(obj->frontbuffer_bits); |
4504 | ||
656bfa3a DV |
4505 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4506 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4507 | obj->tiling_mode != I915_TILING_NONE) | |
4508 | i915_gem_object_unpin_pages(obj); | |
4509 | ||
401c29f6 BW |
4510 | if (WARN_ON(obj->pages_pin_count)) |
4511 | obj->pages_pin_count = 0; | |
340fbd8c | 4512 | if (discard_backing_storage(obj)) |
5537252b | 4513 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4514 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4515 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4516 | |
9da3da66 CW |
4517 | BUG_ON(obj->pages); |
4518 | ||
2f745ad3 CW |
4519 | if (obj->base.import_attach) |
4520 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4521 | |
5cc9ed4b CW |
4522 | if (obj->ops->release) |
4523 | obj->ops->release(obj); | |
4524 | ||
05394f39 CW |
4525 | drm_gem_object_release(&obj->base); |
4526 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4527 | |
05394f39 | 4528 | kfree(obj->bit_17); |
42dcedd4 | 4529 | i915_gem_object_free(obj); |
f65c9168 PZ |
4530 | |
4531 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4532 | } |
4533 | ||
e656a6cb | 4534 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4535 | struct i915_address_space *vm) |
e656a6cb DV |
4536 | { |
4537 | struct i915_vma *vma; | |
4538 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4539 | if (vma->vm == vm) | |
4540 | return vma; | |
4541 | ||
4542 | return NULL; | |
4543 | } | |
4544 | ||
2f633156 BW |
4545 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4546 | { | |
b9d06dd9 | 4547 | struct i915_address_space *vm = NULL; |
2f633156 | 4548 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4549 | |
4550 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4551 | if (!list_empty(&vma->exec_list)) | |
4552 | return; | |
4553 | ||
b9d06dd9 | 4554 | vm = vma->vm; |
b9d06dd9 | 4555 | |
841cd773 DV |
4556 | if (!i915_is_ggtt(vm)) |
4557 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4558 | |
8b9c2b94 | 4559 | list_del(&vma->vma_link); |
b93dab6e | 4560 | |
2f633156 BW |
4561 | kfree(vma); |
4562 | } | |
4563 | ||
e3efda49 CW |
4564 | static void |
4565 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4566 | { | |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4568 | struct intel_engine_cs *ring; |
e3efda49 CW |
4569 | int i; |
4570 | ||
4571 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4572 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4573 | } |
4574 | ||
29105ccc | 4575 | int |
45c5f202 | 4576 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4577 | { |
3e31c6c0 | 4578 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4579 | int ret = 0; |
28dfe52a | 4580 | |
45c5f202 | 4581 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4582 | ret = i915_gpu_idle(dev); |
f7403347 | 4583 | if (ret) |
45c5f202 | 4584 | goto err; |
f7403347 | 4585 | |
b2da9fe5 | 4586 | i915_gem_retire_requests(dev); |
673a394b | 4587 | |
29105ccc | 4588 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4589 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4590 | i915_gem_evict_everything(dev); |
29105ccc | 4591 | |
e3efda49 | 4592 | i915_gem_stop_ringbuffers(dev); |
45c5f202 CW |
4593 | mutex_unlock(&dev->struct_mutex); |
4594 | ||
4595 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4596 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4597 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4598 | |
bdcf120b CW |
4599 | /* Assert that we sucessfully flushed all the work and |
4600 | * reset the GPU back to its idle, low power state. | |
4601 | */ | |
4602 | WARN_ON(dev_priv->mm.busy); | |
4603 | ||
673a394b | 4604 | return 0; |
45c5f202 CW |
4605 | |
4606 | err: | |
4607 | mutex_unlock(&dev->struct_mutex); | |
4608 | return ret; | |
673a394b EA |
4609 | } |
4610 | ||
a4872ba6 | 4611 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4612 | { |
c3787e2e | 4613 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4614 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4615 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4616 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4617 | int i, ret; |
b9524a1e | 4618 | |
040d2baa | 4619 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4620 | return 0; |
b9524a1e | 4621 | |
c3787e2e BW |
4622 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4623 | if (ret) | |
4624 | return ret; | |
b9524a1e | 4625 | |
c3787e2e BW |
4626 | /* |
4627 | * Note: We do not worry about the concurrent register cacheline hang | |
4628 | * here because no other code should access these registers other than | |
4629 | * at initialization time. | |
4630 | */ | |
b9524a1e | 4631 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4632 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4633 | intel_ring_emit(ring, reg_base + i); | |
4634 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4635 | } |
4636 | ||
c3787e2e | 4637 | intel_ring_advance(ring); |
b9524a1e | 4638 | |
c3787e2e | 4639 | return ret; |
b9524a1e BW |
4640 | } |
4641 | ||
f691e2f4 DV |
4642 | void i915_gem_init_swizzling(struct drm_device *dev) |
4643 | { | |
3e31c6c0 | 4644 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4645 | |
11782b02 | 4646 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4647 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4648 | return; | |
4649 | ||
4650 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4651 | DISP_TILE_SURFACE_SWIZZLING); | |
4652 | ||
11782b02 DV |
4653 | if (IS_GEN5(dev)) |
4654 | return; | |
4655 | ||
f691e2f4 DV |
4656 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4657 | if (IS_GEN6(dev)) | |
6b26c86d | 4658 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4659 | else if (IS_GEN7(dev)) |
6b26c86d | 4660 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4661 | else if (IS_GEN8(dev)) |
4662 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4663 | else |
4664 | BUG(); | |
f691e2f4 | 4665 | } |
e21af88d | 4666 | |
67b1b571 CW |
4667 | static bool |
4668 | intel_enable_blt(struct drm_device *dev) | |
4669 | { | |
4670 | if (!HAS_BLT(dev)) | |
4671 | return false; | |
4672 | ||
4673 | /* The blitter was dysfunctional on early prototypes */ | |
4674 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4675 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4676 | " graphics performance will be degraded.\n"); | |
4677 | return false; | |
4678 | } | |
4679 | ||
4680 | return true; | |
4681 | } | |
4682 | ||
81e7f200 VS |
4683 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4684 | { | |
4685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4686 | ||
4687 | I915_WRITE(RING_CTL(base), 0); | |
4688 | I915_WRITE(RING_HEAD(base), 0); | |
4689 | I915_WRITE(RING_TAIL(base), 0); | |
4690 | I915_WRITE(RING_START(base), 0); | |
4691 | } | |
4692 | ||
4693 | static void init_unused_rings(struct drm_device *dev) | |
4694 | { | |
4695 | if (IS_I830(dev)) { | |
4696 | init_unused_ring(dev, PRB1_BASE); | |
4697 | init_unused_ring(dev, SRB0_BASE); | |
4698 | init_unused_ring(dev, SRB1_BASE); | |
4699 | init_unused_ring(dev, SRB2_BASE); | |
4700 | init_unused_ring(dev, SRB3_BASE); | |
4701 | } else if (IS_GEN2(dev)) { | |
4702 | init_unused_ring(dev, SRB0_BASE); | |
4703 | init_unused_ring(dev, SRB1_BASE); | |
4704 | } else if (IS_GEN3(dev)) { | |
4705 | init_unused_ring(dev, PRB1_BASE); | |
4706 | init_unused_ring(dev, PRB2_BASE); | |
4707 | } | |
4708 | } | |
4709 | ||
a83014d3 | 4710 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4711 | { |
4fc7c971 | 4712 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4713 | int ret; |
68f95ba9 | 4714 | |
81e7f200 VS |
4715 | /* |
4716 | * At least 830 can leave some of the unused rings | |
4717 | * "active" (ie. head != tail) after resume which | |
4718 | * will prevent c3 entry. Makes sure all unused rings | |
4719 | * are totally idle. | |
4720 | */ | |
4721 | init_unused_rings(dev); | |
4722 | ||
5c1143bb | 4723 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4724 | if (ret) |
b6913e4b | 4725 | return ret; |
68f95ba9 CW |
4726 | |
4727 | if (HAS_BSD(dev)) { | |
5c1143bb | 4728 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4729 | if (ret) |
4730 | goto cleanup_render_ring; | |
d1b851fc | 4731 | } |
68f95ba9 | 4732 | |
67b1b571 | 4733 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4734 | ret = intel_init_blt_ring_buffer(dev); |
4735 | if (ret) | |
4736 | goto cleanup_bsd_ring; | |
4737 | } | |
4738 | ||
9a8a2213 BW |
4739 | if (HAS_VEBOX(dev)) { |
4740 | ret = intel_init_vebox_ring_buffer(dev); | |
4741 | if (ret) | |
4742 | goto cleanup_blt_ring; | |
4743 | } | |
4744 | ||
845f74a7 ZY |
4745 | if (HAS_BSD2(dev)) { |
4746 | ret = intel_init_bsd2_ring_buffer(dev); | |
4747 | if (ret) | |
4748 | goto cleanup_vebox_ring; | |
4749 | } | |
9a8a2213 | 4750 | |
99433931 | 4751 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4752 | if (ret) |
845f74a7 | 4753 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4754 | |
4755 | return 0; | |
4756 | ||
845f74a7 ZY |
4757 | cleanup_bsd2_ring: |
4758 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4759 | cleanup_vebox_ring: |
4760 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4761 | cleanup_blt_ring: |
4762 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4763 | cleanup_bsd_ring: | |
4764 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4765 | cleanup_render_ring: | |
4766 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4767 | ||
4768 | return ret; | |
4769 | } | |
4770 | ||
4771 | int | |
4772 | i915_gem_init_hw(struct drm_device *dev) | |
4773 | { | |
3e31c6c0 | 4774 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4775 | int ret, i; |
4fc7c971 BW |
4776 | |
4777 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4778 | return -EIO; | |
4779 | ||
59124506 | 4780 | if (dev_priv->ellc_size) |
05e21cc4 | 4781 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4782 | |
0bf21347 VS |
4783 | if (IS_HASWELL(dev)) |
4784 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4785 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4786 | |
88a2b2a3 | 4787 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4788 | if (IS_IVYBRIDGE(dev)) { |
4789 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4790 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4791 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4792 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4793 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4794 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4795 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4796 | } | |
88a2b2a3 BW |
4797 | } |
4798 | ||
4fc7c971 BW |
4799 | i915_gem_init_swizzling(dev); |
4800 | ||
a83014d3 | 4801 | ret = dev_priv->gt.init_rings(dev); |
99433931 MK |
4802 | if (ret) |
4803 | return ret; | |
4804 | ||
c3787e2e BW |
4805 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4806 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4807 | ||
254f965c | 4808 | /* |
2fa48d8d BW |
4809 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4810 | * default context switch however is something we'd like to do after | |
4811 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4812 | * goes with our code better). Context switching requires rings (for | |
4813 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4814 | */ |
2fa48d8d | 4815 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4816 | if (ret && ret != -EIO) { |
2fa48d8d | 4817 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4818 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
4819 | |
4820 | return ret; | |
4821 | } | |
4822 | ||
4823 | ret = i915_ppgtt_init_hw(dev); | |
4824 | if (ret && ret != -EIO) { | |
4825 | DRM_ERROR("PPGTT enable failed %d\n", ret); | |
4826 | i915_gem_cleanup_ringbuffer(dev); | |
b7c36d25 | 4827 | } |
e21af88d | 4828 | |
2fa48d8d | 4829 | return ret; |
8187a2b7 ZN |
4830 | } |
4831 | ||
1070a42b CW |
4832 | int i915_gem_init(struct drm_device *dev) |
4833 | { | |
4834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4835 | int ret; |
4836 | ||
127f1003 OM |
4837 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4838 | i915.enable_execlists); | |
4839 | ||
1070a42b | 4840 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4841 | |
4842 | if (IS_VALLEYVIEW(dev)) { | |
4843 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4844 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4845 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4846 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4847 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4848 | } | |
4849 | ||
a83014d3 OM |
4850 | if (!i915.enable_execlists) { |
4851 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; | |
4852 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4853 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4854 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd OM |
4855 | } else { |
4856 | dev_priv->gt.do_execbuf = intel_execlists_submission; | |
4857 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4858 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4859 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4860 | } |
4861 | ||
6c5566a8 DV |
4862 | ret = i915_gem_init_userptr(dev); |
4863 | if (ret) { | |
4864 | mutex_unlock(&dev->struct_mutex); | |
4865 | return ret; | |
4866 | } | |
4867 | ||
d7e5008f | 4868 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4869 | |
2fa48d8d | 4870 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4871 | if (ret) { |
4872 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4873 | return ret; |
e3848694 | 4874 | } |
2fa48d8d | 4875 | |
1070a42b | 4876 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4877 | if (ret == -EIO) { |
4878 | /* Allow ring initialisation to fail by marking the GPU as | |
4879 | * wedged. But we only want to do this where the GPU is angry, | |
4880 | * for all other failure, such as an allocation failure, bail. | |
4881 | */ | |
4882 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4883 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4884 | ret = 0; | |
1070a42b | 4885 | } |
60990320 | 4886 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4887 | |
60990320 | 4888 | return ret; |
1070a42b CW |
4889 | } |
4890 | ||
8187a2b7 ZN |
4891 | void |
4892 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4893 | { | |
3e31c6c0 | 4894 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4895 | struct intel_engine_cs *ring; |
1ec14ad3 | 4896 | int i; |
8187a2b7 | 4897 | |
b4519513 | 4898 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4899 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
4900 | } |
4901 | ||
64193406 | 4902 | static void |
a4872ba6 | 4903 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4904 | { |
4905 | INIT_LIST_HEAD(&ring->active_list); | |
4906 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4907 | } |
4908 | ||
7e0d96bc BW |
4909 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4910 | struct i915_address_space *vm) | |
fc8c067e | 4911 | { |
7e0d96bc BW |
4912 | if (!i915_is_ggtt(vm)) |
4913 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4914 | vm->dev = dev_priv->dev; |
4915 | INIT_LIST_HEAD(&vm->active_list); | |
4916 | INIT_LIST_HEAD(&vm->inactive_list); | |
4917 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4918 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4919 | } |
4920 | ||
673a394b EA |
4921 | void |
4922 | i915_gem_load(struct drm_device *dev) | |
4923 | { | |
3e31c6c0 | 4924 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4925 | int i; |
4926 | ||
4927 | dev_priv->slab = | |
4928 | kmem_cache_create("i915_gem_object", | |
4929 | sizeof(struct drm_i915_gem_object), 0, | |
4930 | SLAB_HWCACHE_ALIGN, | |
4931 | NULL); | |
673a394b | 4932 | |
fc8c067e BW |
4933 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4934 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4935 | ||
a33afea5 | 4936 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4937 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4938 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4939 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4940 | for (i = 0; i < I915_NUM_RINGS; i++) |
4941 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4942 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4943 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4944 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4945 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4946 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4947 | i915_gem_idle_work_handler); | |
1f83fee0 | 4948 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4949 | |
94400120 | 4950 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 4951 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
4952 | I915_WRITE(MI_ARB_STATE, |
4953 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4954 | } |
4955 | ||
72bfa19c CW |
4956 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4957 | ||
de151cf6 | 4958 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4959 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4960 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4961 | |
42b5aeab VS |
4962 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4963 | dev_priv->num_fence_regs = 32; | |
4964 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4965 | dev_priv->num_fence_regs = 16; |
4966 | else | |
4967 | dev_priv->num_fence_regs = 8; | |
4968 | ||
b5aa8a0f | 4969 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4970 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4971 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4972 | |
673a394b | 4973 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4974 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4975 | |
ce453d81 CW |
4976 | dev_priv->mm.interruptible = true; |
4977 | ||
ceabbba5 CW |
4978 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
4979 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
4980 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
4981 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
4982 | |
4983 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
4984 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
f99d7069 DV |
4985 | |
4986 | mutex_init(&dev_priv->fb_tracking.lock); | |
673a394b | 4987 | } |
71acb5eb | 4988 | |
f787a5f5 | 4989 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4990 | { |
f787a5f5 | 4991 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4992 | |
b29c19b6 CW |
4993 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4994 | ||
b962442e EA |
4995 | /* Clean up our request list when the client is going away, so that |
4996 | * later retire_requests won't dereference our soon-to-be-gone | |
4997 | * file_priv. | |
4998 | */ | |
1c25595f | 4999 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5000 | while (!list_empty(&file_priv->mm.request_list)) { |
5001 | struct drm_i915_gem_request *request; | |
5002 | ||
5003 | request = list_first_entry(&file_priv->mm.request_list, | |
5004 | struct drm_i915_gem_request, | |
5005 | client_list); | |
5006 | list_del(&request->client_list); | |
5007 | request->file_priv = NULL; | |
5008 | } | |
1c25595f | 5009 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5010 | } |
31169714 | 5011 | |
b29c19b6 CW |
5012 | static void |
5013 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5014 | { | |
5015 | struct drm_i915_file_private *file_priv = | |
5016 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5017 | ||
5018 | atomic_set(&file_priv->rps_wait_boost, false); | |
5019 | } | |
5020 | ||
5021 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5022 | { | |
5023 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5024 | int ret; |
b29c19b6 CW |
5025 | |
5026 | DRM_DEBUG_DRIVER("\n"); | |
5027 | ||
5028 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5029 | if (!file_priv) | |
5030 | return -ENOMEM; | |
5031 | ||
5032 | file->driver_priv = file_priv; | |
5033 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5034 | file_priv->file = file; |
b29c19b6 CW |
5035 | |
5036 | spin_lock_init(&file_priv->mm.lock); | |
5037 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5038 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5039 | i915_gem_file_idle_work_handler); | |
5040 | ||
e422b888 BW |
5041 | ret = i915_gem_context_open(dev, file); |
5042 | if (ret) | |
5043 | kfree(file_priv); | |
b29c19b6 | 5044 | |
e422b888 | 5045 | return ret; |
b29c19b6 CW |
5046 | } |
5047 | ||
b680c37a DV |
5048 | /** |
5049 | * i915_gem_track_fb - update frontbuffer tracking | |
5050 | * old: current GEM buffer for the frontbuffer slots | |
5051 | * new: new GEM buffer for the frontbuffer slots | |
5052 | * frontbuffer_bits: bitmask of frontbuffer slots | |
5053 | * | |
5054 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5055 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5056 | */ | |
a071fa00 DV |
5057 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5058 | struct drm_i915_gem_object *new, | |
5059 | unsigned frontbuffer_bits) | |
5060 | { | |
5061 | if (old) { | |
5062 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5063 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5064 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5065 | } | |
5066 | ||
5067 | if (new) { | |
5068 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5069 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5070 | new->frontbuffer_bits |= frontbuffer_bits; | |
5071 | } | |
5072 | } | |
5073 | ||
5774506f CW |
5074 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5075 | { | |
5076 | if (!mutex_is_locked(mutex)) | |
5077 | return false; | |
5078 | ||
5079 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
5080 | return mutex->owner == task; | |
5081 | #else | |
5082 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5083 | return false; | |
5084 | #endif | |
5085 | } | |
5086 | ||
b453c4db CW |
5087 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5088 | { | |
5089 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5090 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5091 | return false; | |
5092 | ||
5093 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5094 | return false; | |
5095 | ||
5096 | *unlock = false; | |
5097 | } else | |
5098 | *unlock = true; | |
5099 | ||
5100 | return true; | |
5101 | } | |
5102 | ||
ceabbba5 CW |
5103 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5104 | { | |
5105 | struct i915_vma *vma; | |
5106 | int count = 0; | |
5107 | ||
5108 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5109 | if (drm_mm_node_allocated(&vma->node)) | |
5110 | count++; | |
5111 | ||
5112 | return count; | |
5113 | } | |
5114 | ||
7dc19d5a | 5115 | static unsigned long |
ceabbba5 | 5116 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5117 | { |
17250b71 | 5118 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5119 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5120 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5121 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5122 | unsigned long count; |
b453c4db | 5123 | bool unlock; |
17250b71 | 5124 | |
b453c4db CW |
5125 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5126 | return 0; | |
31169714 | 5127 | |
7dc19d5a | 5128 | count = 0; |
35c20a60 | 5129 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5130 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5131 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5132 | |
5133 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5134 | if (!i915_gem_obj_is_pinned(obj) && |
5135 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5136 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5137 | } |
17250b71 | 5138 | |
5774506f CW |
5139 | if (unlock) |
5140 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5141 | |
7dc19d5a | 5142 | return count; |
31169714 | 5143 | } |
a70a3148 BW |
5144 | |
5145 | /* All the new VM stuff */ | |
5146 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5147 | struct i915_address_space *vm) | |
5148 | { | |
5149 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5150 | struct i915_vma *vma; | |
5151 | ||
896ab1a5 | 5152 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5153 | |
a70a3148 BW |
5154 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5155 | if (vma->vm == vm) | |
5156 | return vma->node.start; | |
5157 | ||
5158 | } | |
f25748ea DV |
5159 | WARN(1, "%s vma for this object not found.\n", |
5160 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5161 | return -1; |
5162 | } | |
5163 | ||
5164 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5165 | struct i915_address_space *vm) | |
5166 | { | |
5167 | struct i915_vma *vma; | |
5168 | ||
5169 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5170 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5171 | return true; |
5172 | ||
5173 | return false; | |
5174 | } | |
5175 | ||
5176 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5177 | { | |
5a1d5eb0 | 5178 | struct i915_vma *vma; |
a70a3148 | 5179 | |
5a1d5eb0 CW |
5180 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5181 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5182 | return true; |
5183 | ||
5184 | return false; | |
5185 | } | |
5186 | ||
5187 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5188 | struct i915_address_space *vm) | |
5189 | { | |
5190 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5191 | struct i915_vma *vma; | |
5192 | ||
896ab1a5 | 5193 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5194 | |
5195 | BUG_ON(list_empty(&o->vma_list)); | |
5196 | ||
5197 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5198 | if (vma->vm == vm) | |
5199 | return vma->node.size; | |
5200 | ||
5201 | return 0; | |
5202 | } | |
5203 | ||
7dc19d5a | 5204 | static unsigned long |
ceabbba5 | 5205 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5206 | { |
5207 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5208 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5209 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5210 | unsigned long freed; |
b453c4db | 5211 | bool unlock; |
7dc19d5a | 5212 | |
b453c4db CW |
5213 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5214 | return SHRINK_STOP; | |
7dc19d5a | 5215 | |
21ab4e74 CW |
5216 | freed = i915_gem_shrink(dev_priv, |
5217 | sc->nr_to_scan, | |
5218 | I915_SHRINK_BOUND | | |
5219 | I915_SHRINK_UNBOUND | | |
5220 | I915_SHRINK_PURGEABLE); | |
d9973b43 | 5221 | if (freed < sc->nr_to_scan) |
21ab4e74 CW |
5222 | freed += i915_gem_shrink(dev_priv, |
5223 | sc->nr_to_scan - freed, | |
5224 | I915_SHRINK_BOUND | | |
5225 | I915_SHRINK_UNBOUND); | |
7dc19d5a DC |
5226 | if (unlock) |
5227 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5228 | |
7dc19d5a DC |
5229 | return freed; |
5230 | } | |
5c2abbea | 5231 | |
2cfcd32a CW |
5232 | static int |
5233 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5234 | { | |
5235 | struct drm_i915_private *dev_priv = | |
5236 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5237 | struct drm_device *dev = dev_priv->dev; | |
5238 | struct drm_i915_gem_object *obj; | |
5239 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
005445c5 | 5240 | unsigned long pinned, bound, unbound, freed_pages; |
2cfcd32a CW |
5241 | bool was_interruptible; |
5242 | bool unlock; | |
5243 | ||
a1db2fa7 | 5244 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
2cfcd32a | 5245 | schedule_timeout_killable(1); |
a1db2fa7 CW |
5246 | if (fatal_signal_pending(current)) |
5247 | return NOTIFY_DONE; | |
5248 | } | |
2cfcd32a CW |
5249 | if (timeout == 0) { |
5250 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5251 | return NOTIFY_DONE; | |
5252 | } | |
5253 | ||
5254 | was_interruptible = dev_priv->mm.interruptible; | |
5255 | dev_priv->mm.interruptible = false; | |
5256 | ||
005445c5 | 5257 | freed_pages = i915_gem_shrink_all(dev_priv); |
2cfcd32a CW |
5258 | |
5259 | dev_priv->mm.interruptible = was_interruptible; | |
5260 | ||
5261 | /* Because we may be allocating inside our own driver, we cannot | |
5262 | * assert that there are no objects with pinned pages that are not | |
5263 | * being pointed to by hardware. | |
5264 | */ | |
5265 | unbound = bound = pinned = 0; | |
5266 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5267 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5268 | continue; | |
5269 | ||
5270 | if (obj->pages_pin_count) | |
5271 | pinned += obj->base.size; | |
5272 | else | |
5273 | unbound += obj->base.size; | |
5274 | } | |
5275 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5276 | if (!obj->base.filp) | |
5277 | continue; | |
5278 | ||
5279 | if (obj->pages_pin_count) | |
5280 | pinned += obj->base.size; | |
5281 | else | |
5282 | bound += obj->base.size; | |
5283 | } | |
5284 | ||
5285 | if (unlock) | |
5286 | mutex_unlock(&dev->struct_mutex); | |
5287 | ||
bb9059d3 CW |
5288 | if (freed_pages || unbound || bound) |
5289 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5290 | freed_pages << PAGE_SHIFT, pinned); | |
2cfcd32a CW |
5291 | if (unbound || bound) |
5292 | pr_err("%lu and %lu bytes still available in the " | |
5293 | "bound and unbound GPU page lists.\n", | |
5294 | bound, unbound); | |
5295 | ||
005445c5 | 5296 | *(unsigned long *)ptr += freed_pages; |
2cfcd32a CW |
5297 | return NOTIFY_DONE; |
5298 | } | |
5299 | ||
5c2abbea BW |
5300 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5301 | { | |
5302 | struct i915_vma *vma; | |
5303 | ||
5c2abbea | 5304 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
5dc383b0 | 5305 | if (vma->vm != i915_obj_to_ggtt(obj)) |
5c2abbea BW |
5306 | return NULL; |
5307 | ||
5308 | return vma; | |
5309 | } |