[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_gem_clflush.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include "i915_drv.h"
#include "intel_frontbuffer.h"
#include "i915_gem_clflush.h"

static DEFINE_SPINLOCK(clflush_lock);

struct clflush {
	struct dma_fence dma; /* Must be first for dma_fence_free() */
	struct i915_sw_fence wait;
	struct work_struct work;
	struct drm_i915_gem_object *obj;
};

static const char *i915_clflush_get_driver_name(struct dma_fence *fence)
{
	return DRIVER_NAME;
}

static const char *i915_clflush_get_timeline_name(struct dma_fence *fence)
{
	return "clflush";
}

static bool i915_clflush_enable_signaling(struct dma_fence *fence)
{
	return true;
}

static void i915_clflush_release(struct dma_fence *fence)
{
	struct clflush *clflush = container_of(fence, typeof(*clflush), dma);

	i915_sw_fence_fini(&clflush->wait);

	BUILD_BUG_ON(offsetof(typeof(*clflush), dma));
	dma_fence_free(&clflush->dma);
}

static const struct dma_fence_ops i915_clflush_ops = {
	.get_driver_name = i915_clflush_get_driver_name,
	.get_timeline_name = i915_clflush_get_timeline_name,
	.enable_signaling = i915_clflush_enable_signaling,
	.wait = dma_fence_default_wait,
	.release = i915_clflush_release,
};

static void __i915_do_clflush(struct drm_i915_gem_object *obj)
{
	drm_clflush_sg(obj->mm.pages);
	intel_fb_obj_flush(obj, ORIGIN_CPU);
}

static void i915_clflush_work(struct work_struct *work)
{
	struct clflush *clflush = container_of(work, typeof(*clflush), work);
	struct drm_i915_gem_object *obj = clflush->obj;

	if (i915_gem_object_pin_pages(obj)) {
		DRM_ERROR("Failed to acquire obj->pages for clflushing\n");
		goto out;
	}

	__i915_do_clflush(obj);

	i915_gem_object_unpin_pages(obj);

out:
	i915_gem_object_put(obj);

	dma_fence_signal(&clflush->dma);
	dma_fence_put(&clflush->dma);
}

static int __i915_sw_fence_call
i915_clflush_notify(struct i915_sw_fence *fence,
		    enum i915_sw_fence_notify state)
{
	struct clflush *clflush = container_of(fence, typeof(*clflush), wait);

	switch (state) {
	case FENCE_COMPLETE:
		schedule_work(&clflush->work);
		break;

	case FENCE_FREE:
		dma_fence_put(&clflush->dma);
		break;
	}

	return NOTIFY_DONE;
}

bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
			     unsigned int flags)
{
	struct clflush *clflush;

	/*
	 * Stolen memory is always coherent with the GPU as it is explicitly
	 * marked as wc by the system, or the system is cache-coherent.
	 * Similarly, we only access struct pages through the CPU cache, so
	 * anything not backed by physical memory we consider to be always
	 * coherent and not need clflushing.
	 */
	if (!i915_gem_object_has_struct_page(obj)) {
		obj->cache_dirty = false;
		return false;
	}

	/* If the GPU is snooping the contents of the CPU cache,
	 * we do not need to manually clear the CPU cache lines.  However,
	 * the caches are only snooped when the render cache is
	 * flushed/invalidated.  As we always have to emit invalidations
	 * and flushes when moving into and out of the RENDER domain, correct
	 * snooping behaviour occurs naturally as the result of our domain
	 * tracking.
	 */
	if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent)
		return false;

	trace_i915_gem_object_clflush(obj);

	clflush = NULL;
	if (!(flags & I915_CLFLUSH_SYNC))
		clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
	if (clflush) {
		GEM_BUG_ON(!obj->cache_dirty);

		dma_fence_init(&clflush->dma,
			       &i915_clflush_ops,
			       &clflush_lock,
			       to_i915(obj->base.dev)->mm.unordered_timeline,
			       0);
		i915_sw_fence_init(&clflush->wait, i915_clflush_notify);

		clflush->obj = i915_gem_object_get(obj);
		INIT_WORK(&clflush->work, i915_clflush_work);

		dma_fence_get(&clflush->dma);

		i915_sw_fence_await_reservation(&clflush->wait,
						obj->resv, NULL,
						true, I915_FENCE_TIMEOUT,
						GFP_KERNEL);

		reservation_object_lock(obj->resv, NULL);
		reservation_object_add_excl_fence(obj->resv, &clflush->dma);
		reservation_object_unlock(obj->resv);

		i915_sw_fence_commit(&clflush->wait);
	} else if (obj->mm.pages) {
		__i915_do_clflush(obj);
	} else {
		GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
	}

	obj->cache_dirty = false;
	return true;
}
Commit	Line	Data
57822dc6 CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#include "i915_drv.h"
	26	#include "intel_frontbuffer.h"
	27	#include "i915_gem_clflush.h"
	28
	29	static DEFINE_SPINLOCK(clflush_lock);
57822dc6 CW	30
	31	struct clflush {
	32	struct dma_fence dma; /* Must be first for dma_fence_free() */
	33	struct i915_sw_fence wait;
	34	struct work_struct work;
	35	struct drm_i915_gem_object *obj;
	36	};
	37
	38	static const char i915_clflush_get_driver_name(struct dma_fence fence)
	39	{
	40	return DRIVER_NAME;
	41	}
	42
	43	static const char i915_clflush_get_timeline_name(struct dma_fence fence)
	44	{
	45	return "clflush";
	46	}
	47
	48	static bool i915_clflush_enable_signaling(struct dma_fence *fence)
	49	{
	50	return true;
	51	}
	52
	53	static void i915_clflush_release(struct dma_fence *fence)
	54	{
	55	struct clflush clflush = container_of(fence, typeof(clflush), dma);
	56
	57	i915_sw_fence_fini(&clflush->wait);
	58
	59	BUILD_BUG_ON(offsetof(typeof(*clflush), dma));
	60	dma_fence_free(&clflush->dma);
	61	}
	62
	63	static const struct dma_fence_ops i915_clflush_ops = {
	64	.get_driver_name = i915_clflush_get_driver_name,
	65	.get_timeline_name = i915_clflush_get_timeline_name,
	66	.enable_signaling = i915_clflush_enable_signaling,
	67	.wait = dma_fence_default_wait,
	68	.release = i915_clflush_release,
	69	};
	70
	71	static void __i915_do_clflush(struct drm_i915_gem_object *obj)
	72	{
	73	drm_clflush_sg(obj->mm.pages);
d59b21ec	74	intel_fb_obj_flush(obj, ORIGIN_CPU);
57822dc6 CW	75	}
	76
	77	static void i915_clflush_work(struct work_struct *work)
	78	{
	79	struct clflush clflush = container_of(work, typeof(clflush), work);
	80	struct drm_i915_gem_object *obj = clflush->obj;
	81
57822dc6 CW	82	if (i915_gem_object_pin_pages(obj)) {
	83	DRM_ERROR("Failed to acquire obj->pages for clflushing\n");
	84	goto out;
	85	}
	86
	87	__i915_do_clflush(obj);
	88
	89	i915_gem_object_unpin_pages(obj);
	90
	91	out:
	92	i915_gem_object_put(obj);
	93
	94	dma_fence_signal(&clflush->dma);
	95	dma_fence_put(&clflush->dma);
	96	}
	97
	98	static int __i915_sw_fence_call
	99	i915_clflush_notify(struct i915_sw_fence *fence,
	100	enum i915_sw_fence_notify state)
	101	{
	102	struct clflush clflush = container_of(fence, typeof(clflush), wait);
	103
	104	switch (state) {
	105	case FENCE_COMPLETE:
	106	schedule_work(&clflush->work);
	107	break;
	108
	109	case FENCE_FREE:
	110	dma_fence_put(&clflush->dma);
	111	break;
	112	}
	113
	114	return NOTIFY_DONE;
	115	}
	116
7b98da66	117	bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
57822dc6 CW	118	unsigned int flags)
	119	{
	120	struct clflush *clflush;
	121
	122	/*
	123	* Stolen memory is always coherent with the GPU as it is explicitly
	124	* marked as wc by the system, or the system is cache-coherent.
	125	* Similarly, we only access struct pages through the CPU cache, so
	126	* anything not backed by physical memory we consider to be always
	127	* coherent and not need clflushing.
	128	*/
e27ab73d CW	129	if (!i915_gem_object_has_struct_page(obj)) {
e27ab73d CW	130	obj->cache_dirty = false;
7b98da66	131	return false;
e27ab73d	132	}
57822dc6 CW	133
	134	/* If the GPU is snooping the contents of the CPU cache,
	135	* we do not need to manually clear the CPU cache lines. However,
	136	* the caches are only snooped when the render cache is
	137	* flushed/invalidated. As we always have to emit invalidations
	138	* and flushes when moving into and out of the RENDER domain, correct
	139	* snooping behaviour occurs naturally as the result of our domain
	140	* tracking.
	141	*/
7fc92e96	142	if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent)
7b98da66	143	return false;
57822dc6 CW	144
	145	trace_i915_gem_object_clflush(obj);
	146
	147	clflush = NULL;
	148	if (!(flags & I915_CLFLUSH_SYNC))
	149	clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
	150	if (clflush) {
e27ab73d CW	151	GEM_BUG_ON(!obj->cache_dirty);
e27ab73d CW	152
57822dc6 CW	153	dma_fence_init(&clflush->dma,
	154	&i915_clflush_ops,
	155	&clflush_lock,
94312828	156	to_i915(obj->base.dev)->mm.unordered_timeline,
57822dc6 CW	157	0);
	158	i915_sw_fence_init(&clflush->wait, i915_clflush_notify);
	159
	160	clflush->obj = i915_gem_object_get(obj);
	161	INIT_WORK(&clflush->work, i915_clflush_work);
	162
	163	dma_fence_get(&clflush->dma);
	164
	165	i915_sw_fence_await_reservation(&clflush->wait,
	166	obj->resv, NULL,
d223760f	167	true, I915_FENCE_TIMEOUT,
57822dc6 CW	168	GFP_KERNEL);
	169
	170	reservation_object_lock(obj->resv, NULL);
	171	reservation_object_add_excl_fence(obj->resv, &clflush->dma);
	172	reservation_object_unlock(obj->resv);
	173
	174	i915_sw_fence_commit(&clflush->wait);
	175	} else if (obj->mm.pages) {
	176	__i915_do_clflush(obj);
	177	} else {
	178	GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
	179	}
e27ab73d CW	180
e27ab73d CW	181	obj->cache_dirty = false;
7b98da66	182	return true;
57822dc6	183	}