]>
Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
b731d33d BW |
96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 BW |
98 | |
99 | static struct i915_hw_context * | |
100 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); | |
67e3d297 BW |
101 | static int do_switch(struct intel_ring_buffer *ring, |
102 | struct i915_hw_context *to); | |
40521054 | 103 | |
b731d33d BW |
104 | static size_t get_context_alignment(struct drm_device *dev) |
105 | { | |
106 | if (IS_GEN6(dev)) | |
107 | return GEN6_CONTEXT_ALIGN; | |
108 | ||
109 | return GEN7_CONTEXT_ALIGN; | |
110 | } | |
111 | ||
254f965c BW |
112 | static int get_context_size(struct drm_device *dev) |
113 | { | |
114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
115 | int ret; | |
116 | u32 reg; | |
117 | ||
118 | switch (INTEL_INFO(dev)->gen) { | |
119 | case 6: | |
120 | reg = I915_READ(CXT_SIZE); | |
121 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
122 | break; | |
123 | case 7: | |
4f91dd6f | 124 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 125 | if (IS_HASWELL(dev)) |
a0de80a0 | 126 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
127 | else |
128 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 129 | break; |
8897644a BW |
130 | case 8: |
131 | ret = GEN8_CXT_TOTAL_SIZE; | |
132 | break; | |
254f965c BW |
133 | default: |
134 | BUG(); | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
dce3271b | 140 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 141 | { |
dce3271b MK |
142 | struct i915_hw_context *ctx = container_of(ctx_ref, |
143 | typeof(*ctx), ref); | |
40521054 | 144 | |
a33afea5 | 145 | list_del(&ctx->link); |
40521054 BW |
146 | drm_gem_object_unreference(&ctx->obj->base); |
147 | kfree(ctx); | |
148 | } | |
149 | ||
146937e5 | 150 | static struct i915_hw_context * |
40521054 | 151 | create_hw_context(struct drm_device *dev, |
146937e5 | 152 | struct drm_i915_file_private *file_priv) |
40521054 BW |
153 | { |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146937e5 | 155 | struct i915_hw_context *ctx; |
c8c470af | 156 | int ret; |
40521054 | 157 | |
f94982b0 | 158 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
159 | if (ctx == NULL) |
160 | return ERR_PTR(-ENOMEM); | |
40521054 | 161 | |
dce3271b | 162 | kref_init(&ctx->ref); |
146937e5 | 163 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
a33afea5 | 164 | INIT_LIST_HEAD(&ctx->link); |
146937e5 BW |
165 | if (ctx->obj == NULL) { |
166 | kfree(ctx); | |
40521054 | 167 | DRM_DEBUG_DRIVER("Context object allocated failed\n"); |
146937e5 | 168 | return ERR_PTR(-ENOMEM); |
40521054 BW |
169 | } |
170 | ||
4615d4c9 CW |
171 | if (INTEL_INFO(dev)->gen >= 7) { |
172 | ret = i915_gem_object_set_cache_level(ctx->obj, | |
350ec881 | 173 | I915_CACHE_L3_LLC); |
bb036413 BW |
174 | /* Failure shouldn't ever happen this early */ |
175 | if (WARN_ON(ret)) | |
4615d4c9 CW |
176 | goto err_out; |
177 | } | |
178 | ||
a33afea5 | 179 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 BW |
180 | |
181 | /* Default context will never have a file_priv */ | |
182 | if (file_priv == NULL) | |
146937e5 | 183 | return ctx; |
40521054 | 184 | |
c8c470af TH |
185 | ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0, |
186 | GFP_KERNEL); | |
187 | if (ret < 0) | |
40521054 | 188 | goto err_out; |
dce3271b MK |
189 | |
190 | ctx->file_priv = file_priv; | |
c8c470af | 191 | ctx->id = ret; |
3ccfd19d BW |
192 | /* NB: Mark all slices as needing a remap so that when the context first |
193 | * loads it will restore whatever remap state already exists. If there | |
194 | * is no remap info, it will be a NOP. */ | |
195 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 196 | |
146937e5 | 197 | return ctx; |
40521054 BW |
198 | |
199 | err_out: | |
dce3271b | 200 | i915_gem_context_unreference(ctx); |
146937e5 | 201 | return ERR_PTR(ret); |
40521054 BW |
202 | } |
203 | ||
e0556841 BW |
204 | static inline bool is_default_context(struct i915_hw_context *ctx) |
205 | { | |
0009e46c BW |
206 | /* Cheap trick to determine default contexts */ |
207 | return ctx->file_priv ? false : true; | |
e0556841 BW |
208 | } |
209 | ||
254f965c BW |
210 | /** |
211 | * The default context needs to exist per ring that uses contexts. It stores the | |
212 | * context state of the GPU for applications that don't utilize HW contexts, as | |
213 | * well as an idle case. | |
214 | */ | |
b731d33d | 215 | static int create_default_context(struct drm_device *dev) |
254f965c | 216 | { |
b731d33d | 217 | struct drm_i915_private *dev_priv = dev->dev_private; |
40521054 BW |
218 | struct i915_hw_context *ctx; |
219 | int ret; | |
220 | ||
b731d33d | 221 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 222 | |
b731d33d | 223 | ctx = create_hw_context(dev, NULL); |
146937e5 BW |
224 | if (IS_ERR(ctx)) |
225 | return PTR_ERR(ctx); | |
40521054 BW |
226 | |
227 | /* We may need to do things with the shrinker which require us to | |
228 | * immediately switch back to the default context. This can cause a | |
229 | * problem as pinning the default context also requires GTT space which | |
230 | * may not be available. To avoid this we always pin the | |
231 | * default context. | |
232 | */ | |
b731d33d BW |
233 | ret = i915_gem_obj_ggtt_pin(ctx->obj, get_context_alignment(dev), |
234 | false, false); | |
bb036413 BW |
235 | if (ret) { |
236 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
9a3b5304 | 237 | goto err_destroy; |
bb036413 | 238 | } |
40521054 | 239 | |
67e3d297 | 240 | ret = do_switch(&dev_priv->ring[RCS], ctx); |
bb036413 BW |
241 | if (ret) { |
242 | DRM_DEBUG_DRIVER("Switch failed %d\n", ret); | |
9a3b5304 | 243 | goto err_unpin; |
bb036413 | 244 | } |
dfabbcb4 | 245 | |
71b76d00 BW |
246 | dev_priv->ring[RCS].default_context = ctx; |
247 | ||
9a3b5304 CW |
248 | DRM_DEBUG_DRIVER("Default HW context loaded\n"); |
249 | return 0; | |
250 | ||
251 | err_unpin: | |
d7f46fc4 | 252 | i915_gem_object_ggtt_unpin(ctx->obj); |
9a3b5304 | 253 | err_destroy: |
dce3271b | 254 | i915_gem_context_unreference(ctx); |
40521054 | 255 | return ret; |
254f965c BW |
256 | } |
257 | ||
8245be31 | 258 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
259 | { |
260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
67e3d297 BW |
261 | struct intel_ring_buffer *ring; |
262 | int i, ret; | |
254f965c | 263 | |
8245be31 BW |
264 | if (!HAS_HW_CONTEXTS(dev)) |
265 | return 0; | |
254f965c BW |
266 | |
267 | /* If called from reset, or thaw... we've been here already */ | |
8245be31 BW |
268 | if (dev_priv->ring[RCS].default_context) |
269 | return 0; | |
254f965c | 270 | |
07ea0d85 | 271 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
254f965c | 272 | |
07ea0d85 | 273 | if (dev_priv->hw_context_size > (1<<20)) { |
bb036413 | 274 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n"); |
8245be31 | 275 | return -E2BIG; |
254f965c BW |
276 | } |
277 | ||
b731d33d | 278 | ret = create_default_context(dev); |
8245be31 BW |
279 | if (ret) { |
280 | DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %d\n", | |
281 | ret); | |
282 | return ret; | |
254f965c BW |
283 | } |
284 | ||
67e3d297 BW |
285 | for (i = RCS + 1; i < I915_NUM_RINGS; i++) { |
286 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
287 | continue; | |
288 | ||
289 | ring = &dev_priv->ring[i]; | |
290 | ||
291 | /* NB: RCS will hold a ref for all rings */ | |
292 | ring->default_context = dev_priv->ring[RCS].default_context; | |
293 | } | |
294 | ||
254f965c | 295 | DRM_DEBUG_DRIVER("HW context support initialized\n"); |
8245be31 | 296 | return 0; |
254f965c BW |
297 | } |
298 | ||
299 | void i915_gem_context_fini(struct drm_device *dev) | |
300 | { | |
301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dce3271b | 302 | struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 303 | int i; |
254f965c | 304 | |
8245be31 | 305 | if (!HAS_HW_CONTEXTS(dev)) |
254f965c | 306 | return; |
40521054 | 307 | |
55a66628 DV |
308 | /* The only known way to stop the gpu from accessing the hw context is |
309 | * to reset it. Do this as the very last operation to avoid confusing | |
310 | * other code, leading to spurious errors. */ | |
311 | intel_gpu_reset(dev); | |
312 | ||
168f8366 MK |
313 | /* When default context is created and switched to, base object refcount |
314 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
315 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
316 | * to default context. So we need to unreference the base object once | |
317 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
318 | * can then free the base object correctly. */ | |
71b76d00 BW |
319 | WARN_ON(!dev_priv->ring[RCS].last_context); |
320 | if (dev_priv->ring[RCS].last_context == dctx) { | |
321 | /* Fake switch to NULL context */ | |
322 | WARN_ON(dctx->obj->active); | |
d7f46fc4 | 323 | i915_gem_object_ggtt_unpin(dctx->obj); |
71b76d00 | 324 | i915_gem_context_unreference(dctx); |
67e3d297 BW |
325 | dev_priv->ring[RCS].last_context = NULL; |
326 | } | |
327 | ||
328 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
329 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
330 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
331 | continue; | |
332 | ||
333 | if (ring->last_context) | |
334 | i915_gem_context_unreference(ring->last_context); | |
335 | ||
336 | ring->default_context = NULL; | |
0009e46c | 337 | ring->last_context = NULL; |
71b76d00 BW |
338 | } |
339 | ||
d7f46fc4 | 340 | i915_gem_object_ggtt_unpin(dctx->obj); |
dce3271b | 341 | i915_gem_context_unreference(dctx); |
254f965c BW |
342 | } |
343 | ||
40521054 BW |
344 | static int context_idr_cleanup(int id, void *p, void *data) |
345 | { | |
73c273eb | 346 | struct i915_hw_context *ctx = p; |
40521054 BW |
347 | |
348 | BUG_ON(id == DEFAULT_CONTEXT_ID); | |
40521054 | 349 | |
dce3271b | 350 | i915_gem_context_unreference(ctx); |
40521054 | 351 | return 0; |
254f965c BW |
352 | } |
353 | ||
c0bb617a | 354 | struct i915_ctx_hang_stats * |
11fa3384 | 355 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
c0bb617a MK |
356 | struct drm_file *file, |
357 | u32 id) | |
358 | { | |
c0bb617a | 359 | struct drm_i915_file_private *file_priv = file->driver_priv; |
11fa3384 | 360 | struct i915_hw_context *ctx; |
c0bb617a MK |
361 | |
362 | if (id == DEFAULT_CONTEXT_ID) | |
363 | return &file_priv->hang_stats; | |
364 | ||
8245be31 BW |
365 | if (!HAS_HW_CONTEXTS(dev)) |
366 | return ERR_PTR(-ENOENT); | |
367 | ||
368 | ctx = i915_gem_context_get(file->driver_priv, id); | |
11fa3384 | 369 | if (ctx == NULL) |
c0bb617a MK |
370 | return ERR_PTR(-ENOENT); |
371 | ||
11fa3384 | 372 | return &ctx->hang_stats; |
c0bb617a MK |
373 | } |
374 | ||
e422b888 BW |
375 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
376 | { | |
377 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
378 | ||
379 | if (!HAS_HW_CONTEXTS(dev)) | |
380 | return 0; | |
381 | ||
382 | idr_init(&file_priv->context_idr); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
254f965c BW |
387 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
388 | { | |
40521054 | 389 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 390 | |
e422b888 BW |
391 | if (!HAS_HW_CONTEXTS(dev)) |
392 | return; | |
393 | ||
40521054 | 394 | mutex_lock(&dev->struct_mutex); |
73c273eb | 395 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 BW |
396 | idr_destroy(&file_priv->context_idr); |
397 | mutex_unlock(&dev->struct_mutex); | |
398 | } | |
399 | ||
e0556841 | 400 | static struct i915_hw_context * |
40521054 BW |
401 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
402 | { | |
403 | return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); | |
254f965c | 404 | } |
e0556841 BW |
405 | |
406 | static inline int | |
407 | mi_set_context(struct intel_ring_buffer *ring, | |
408 | struct i915_hw_context *new_context, | |
409 | u32 hw_flags) | |
410 | { | |
411 | int ret; | |
412 | ||
12b0286f BW |
413 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
414 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
415 | * explicitly, so we rely on the value at ring init, stored in | |
416 | * itlb_before_ctx_switch. | |
417 | */ | |
418 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | |
ac82ea2e | 419 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
420 | if (ret) |
421 | return ret; | |
422 | } | |
423 | ||
e37ec39b | 424 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
425 | if (ret) |
426 | return ret; | |
427 | ||
8693a824 | 428 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */ |
e37ec39b BW |
429 | if (IS_GEN7(ring->dev)) |
430 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
431 | else | |
432 | intel_ring_emit(ring, MI_NOOP); | |
433 | ||
e0556841 BW |
434 | intel_ring_emit(ring, MI_NOOP); |
435 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 436 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) | |
e0556841 BW |
437 | MI_MM_SPACE_GTT | |
438 | MI_SAVE_EXT_STATE_EN | | |
439 | MI_RESTORE_EXT_STATE_EN | | |
440 | hw_flags); | |
441 | /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ | |
442 | intel_ring_emit(ring, MI_NOOP); | |
443 | ||
e37ec39b BW |
444 | if (IS_GEN7(ring->dev)) |
445 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
446 | else | |
447 | intel_ring_emit(ring, MI_NOOP); | |
448 | ||
e0556841 BW |
449 | intel_ring_advance(ring); |
450 | ||
451 | return ret; | |
452 | } | |
453 | ||
67e3d297 BW |
454 | static int do_switch(struct intel_ring_buffer *ring, |
455 | struct i915_hw_context *to) | |
e0556841 | 456 | { |
6f65e29a | 457 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
112522f6 | 458 | struct i915_hw_context *from = ring->last_context; |
e0556841 | 459 | u32 hw_flags = 0; |
3ccfd19d | 460 | int ret, i; |
e0556841 | 461 | |
67e3d297 BW |
462 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
463 | BUG_ON(from->obj == NULL); | |
464 | BUG_ON(!i915_gem_obj_is_pinned(from->obj)); | |
465 | } | |
e0556841 | 466 | |
0009e46c | 467 | if (from == to && from->last_ring == ring && !to->remap_slice) |
9a3b5304 CW |
468 | return 0; |
469 | ||
67e3d297 BW |
470 | if (ring != &dev_priv->ring[RCS]) { |
471 | if (from) | |
472 | i915_gem_context_unreference(from); | |
473 | goto done; | |
474 | } | |
475 | ||
b731d33d BW |
476 | ret = i915_gem_obj_ggtt_pin(to->obj, get_context_alignment(ring->dev), |
477 | false, false); | |
e0556841 BW |
478 | if (ret) |
479 | return ret; | |
480 | ||
d3373a24 CW |
481 | /* Clear this page out of any CPU caches for coherent swap-in/out. Note |
482 | * that thanks to write = false in this call and us not setting any gpu | |
483 | * write domains when putting a context object onto the active list | |
484 | * (when switching away from it), this won't block. | |
485 | * XXX: We need a real interface to do this instead of trickery. */ | |
486 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); | |
487 | if (ret) { | |
d7f46fc4 | 488 | i915_gem_object_ggtt_unpin(to->obj); |
d3373a24 CW |
489 | return ret; |
490 | } | |
491 | ||
6f65e29a BW |
492 | if (!to->obj->has_global_gtt_mapping) { |
493 | struct i915_vma *vma = i915_gem_obj_to_vma(to->obj, | |
494 | &dev_priv->gtt.base); | |
495 | vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND); | |
496 | } | |
3af7b857 | 497 | |
e0556841 BW |
498 | if (!to->is_initialized || is_default_context(to)) |
499 | hw_flags |= MI_RESTORE_INHIBIT; | |
e0556841 | 500 | |
e0556841 BW |
501 | ret = mi_set_context(ring, to, hw_flags); |
502 | if (ret) { | |
d7f46fc4 | 503 | i915_gem_object_ggtt_unpin(to->obj); |
e0556841 BW |
504 | return ret; |
505 | } | |
506 | ||
3ccfd19d BW |
507 | for (i = 0; i < MAX_L3_SLICES; i++) { |
508 | if (!(to->remap_slice & (1<<i))) | |
509 | continue; | |
510 | ||
511 | ret = i915_gem_l3_remap(ring, i); | |
512 | /* If it failed, try again next round */ | |
513 | if (ret) | |
514 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
515 | else | |
516 | to->remap_slice &= ~(1<<i); | |
517 | } | |
518 | ||
e0556841 BW |
519 | /* The backing object for the context is done after switching to the |
520 | * *next* context. Therefore we cannot retire the previous context until | |
521 | * the next context has already started running. In fact, the below code | |
522 | * is a bit suboptimal because the retiring can occur simply after the | |
523 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
524 | */ | |
112522f6 CW |
525 | if (from != NULL) { |
526 | from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; | |
e2d05a8b | 527 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring); |
e0556841 BW |
528 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
529 | * whole damn pipeline, we don't need to explicitly mark the | |
530 | * object dirty. The only exception is that the context must be | |
531 | * correct in case the object gets swapped out. Ideally we'd be | |
532 | * able to defer doing this until we know the object would be | |
533 | * swapped, but there is no way to do that yet. | |
534 | */ | |
112522f6 CW |
535 | from->obj->dirty = 1; |
536 | BUG_ON(from->obj->ring != ring); | |
537 | ||
c0321e2c | 538 | /* obj is kept alive until the next request by its active ref */ |
d7f46fc4 | 539 | i915_gem_object_ggtt_unpin(from->obj); |
112522f6 | 540 | i915_gem_context_unreference(from); |
e0556841 BW |
541 | } |
542 | ||
67e3d297 | 543 | done: |
112522f6 CW |
544 | i915_gem_context_reference(to); |
545 | ring->last_context = to; | |
e0556841 | 546 | to->is_initialized = true; |
0009e46c | 547 | to->last_ring = ring; |
e0556841 BW |
548 | |
549 | return 0; | |
550 | } | |
551 | ||
552 | /** | |
553 | * i915_switch_context() - perform a GPU context switch. | |
554 | * @ring: ring for which we'll execute the context switch | |
555 | * @file_priv: file_priv associated with the context, may be NULL | |
556 | * @id: context id number | |
e0556841 BW |
557 | * |
558 | * The context life cycle is simple. The context refcount is incremented and | |
559 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
560 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
561 | * object while letting the normal object tracking destroy the backing BO. | |
562 | */ | |
563 | int i915_switch_context(struct intel_ring_buffer *ring, | |
564 | struct drm_file *file, | |
565 | int to_id) | |
566 | { | |
567 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 568 | struct i915_hw_context *to; |
e0556841 | 569 | |
8245be31 | 570 | if (!HAS_HW_CONTEXTS(ring->dev)) |
e0556841 BW |
571 | return 0; |
572 | ||
186507e9 BW |
573 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
574 | ||
e0556841 BW |
575 | if (to_id == DEFAULT_CONTEXT_ID) { |
576 | to = ring->default_context; | |
577 | } else { | |
9a3b5304 CW |
578 | if (file == NULL) |
579 | return -EINVAL; | |
580 | ||
581 | to = i915_gem_context_get(file->driver_priv, to_id); | |
e0556841 | 582 | if (to == NULL) |
0d326013 | 583 | return -ENOENT; |
e0556841 BW |
584 | } |
585 | ||
67e3d297 | 586 | return do_switch(ring, to); |
e0556841 | 587 | } |
84624813 BW |
588 | |
589 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
590 | struct drm_file *file) | |
591 | { | |
84624813 BW |
592 | struct drm_i915_gem_context_create *args = data; |
593 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
594 | struct i915_hw_context *ctx; | |
595 | int ret; | |
596 | ||
597 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
598 | return -ENODEV; | |
599 | ||
8245be31 | 600 | if (!HAS_HW_CONTEXTS(dev)) |
5fa8be65 DV |
601 | return -ENODEV; |
602 | ||
84624813 BW |
603 | ret = i915_mutex_lock_interruptible(dev); |
604 | if (ret) | |
605 | return ret; | |
606 | ||
146937e5 | 607 | ctx = create_hw_context(dev, file_priv); |
84624813 | 608 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
609 | if (IS_ERR(ctx)) |
610 | return PTR_ERR(ctx); | |
84624813 BW |
611 | |
612 | args->ctx_id = ctx->id; | |
613 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
614 | ||
be636387 | 615 | return 0; |
84624813 BW |
616 | } |
617 | ||
618 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
619 | struct drm_file *file) | |
620 | { | |
621 | struct drm_i915_gem_context_destroy *args = data; | |
622 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
84624813 BW |
623 | struct i915_hw_context *ctx; |
624 | int ret; | |
625 | ||
626 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
627 | return -ENODEV; | |
628 | ||
629 | ret = i915_mutex_lock_interruptible(dev); | |
630 | if (ret) | |
631 | return ret; | |
632 | ||
633 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
634 | if (!ctx) { | |
635 | mutex_unlock(&dev->struct_mutex); | |
0d326013 | 636 | return -ENOENT; |
84624813 BW |
637 | } |
638 | ||
dce3271b MK |
639 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
640 | i915_gem_context_unreference(ctx); | |
84624813 BW |
641 | mutex_unlock(&dev->struct_mutex); |
642 | ||
643 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
644 | return 0; | |
645 | } |