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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
76 | * GPU. The GPU has loaded it's state already and has stored away the gtt | |
77 | * offset of the BO. The GPU is not actively referencing the data at this | |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
96 | #define CONTEXT_ALIGN (64<<10) | |
97 | ||
98 | static struct i915_hw_context * | |
99 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); | |
9a3b5304 | 100 | static int do_switch(struct i915_hw_context *to); |
40521054 | 101 | |
254f965c BW |
102 | static int get_context_size(struct drm_device *dev) |
103 | { | |
104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
105 | int ret; | |
106 | u32 reg; | |
107 | ||
108 | switch (INTEL_INFO(dev)->gen) { | |
109 | case 6: | |
110 | reg = I915_READ(CXT_SIZE); | |
111 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
112 | break; | |
113 | case 7: | |
4f91dd6f | 114 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 BW |
115 | if (IS_HASWELL(dev)) |
116 | ret = HSW_CXT_TOTAL_SIZE(reg) * 64; | |
117 | else | |
118 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c BW |
119 | break; |
120 | default: | |
121 | BUG(); | |
122 | } | |
123 | ||
124 | return ret; | |
125 | } | |
126 | ||
dce3271b | 127 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 128 | { |
dce3271b MK |
129 | struct i915_hw_context *ctx = container_of(ctx_ref, |
130 | typeof(*ctx), ref); | |
40521054 BW |
131 | |
132 | drm_gem_object_unreference(&ctx->obj->base); | |
133 | kfree(ctx); | |
134 | } | |
135 | ||
146937e5 | 136 | static struct i915_hw_context * |
40521054 | 137 | create_hw_context(struct drm_device *dev, |
146937e5 | 138 | struct drm_i915_file_private *file_priv) |
40521054 BW |
139 | { |
140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146937e5 | 141 | struct i915_hw_context *ctx; |
c8c470af | 142 | int ret; |
40521054 | 143 | |
f94982b0 | 144 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
145 | if (ctx == NULL) |
146 | return ERR_PTR(-ENOMEM); | |
40521054 | 147 | |
dce3271b | 148 | kref_init(&ctx->ref); |
146937e5 BW |
149 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
150 | if (ctx->obj == NULL) { | |
151 | kfree(ctx); | |
40521054 | 152 | DRM_DEBUG_DRIVER("Context object allocated failed\n"); |
146937e5 | 153 | return ERR_PTR(-ENOMEM); |
40521054 BW |
154 | } |
155 | ||
4615d4c9 CW |
156 | if (INTEL_INFO(dev)->gen >= 7) { |
157 | ret = i915_gem_object_set_cache_level(ctx->obj, | |
158 | I915_CACHE_LLC_MLC); | |
159 | if (ret) | |
160 | goto err_out; | |
161 | } | |
162 | ||
40521054 BW |
163 | /* The ring associated with the context object is handled by the normal |
164 | * object tracking code. We give an initial ring value simple to pass an | |
165 | * assertion in the context switch code. | |
166 | */ | |
146937e5 | 167 | ctx->ring = &dev_priv->ring[RCS]; |
40521054 BW |
168 | |
169 | /* Default context will never have a file_priv */ | |
170 | if (file_priv == NULL) | |
146937e5 | 171 | return ctx; |
40521054 | 172 | |
c8c470af TH |
173 | ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0, |
174 | GFP_KERNEL); | |
175 | if (ret < 0) | |
40521054 | 176 | goto err_out; |
dce3271b MK |
177 | |
178 | ctx->file_priv = file_priv; | |
c8c470af | 179 | ctx->id = ret; |
40521054 | 180 | |
146937e5 | 181 | return ctx; |
40521054 BW |
182 | |
183 | err_out: | |
dce3271b | 184 | i915_gem_context_unreference(ctx); |
146937e5 | 185 | return ERR_PTR(ret); |
40521054 BW |
186 | } |
187 | ||
e0556841 BW |
188 | static inline bool is_default_context(struct i915_hw_context *ctx) |
189 | { | |
190 | return (ctx == ctx->ring->default_context); | |
191 | } | |
192 | ||
254f965c BW |
193 | /** |
194 | * The default context needs to exist per ring that uses contexts. It stores the | |
195 | * context state of the GPU for applications that don't utilize HW contexts, as | |
196 | * well as an idle case. | |
197 | */ | |
198 | static int create_default_context(struct drm_i915_private *dev_priv) | |
199 | { | |
40521054 BW |
200 | struct i915_hw_context *ctx; |
201 | int ret; | |
202 | ||
203 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); | |
204 | ||
146937e5 BW |
205 | ctx = create_hw_context(dev_priv->dev, NULL); |
206 | if (IS_ERR(ctx)) | |
207 | return PTR_ERR(ctx); | |
40521054 BW |
208 | |
209 | /* We may need to do things with the shrinker which require us to | |
210 | * immediately switch back to the default context. This can cause a | |
211 | * problem as pinning the default context also requires GTT space which | |
212 | * may not be available. To avoid this we always pin the | |
213 | * default context. | |
214 | */ | |
146937e5 | 215 | dev_priv->ring[RCS].default_context = ctx; |
86a1ee26 | 216 | ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false, false); |
9a3b5304 CW |
217 | if (ret) |
218 | goto err_destroy; | |
40521054 | 219 | |
9a3b5304 CW |
220 | ret = do_switch(ctx); |
221 | if (ret) | |
222 | goto err_unpin; | |
dfabbcb4 | 223 | |
9a3b5304 CW |
224 | DRM_DEBUG_DRIVER("Default HW context loaded\n"); |
225 | return 0; | |
226 | ||
227 | err_unpin: | |
228 | i915_gem_object_unpin(ctx->obj); | |
229 | err_destroy: | |
dce3271b | 230 | i915_gem_context_unreference(ctx); |
40521054 | 231 | return ret; |
254f965c BW |
232 | } |
233 | ||
234 | void i915_gem_context_init(struct drm_device *dev) | |
235 | { | |
236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
254f965c | 237 | |
e158c5aa BW |
238 | if (!HAS_HW_CONTEXTS(dev)) { |
239 | dev_priv->hw_contexts_disabled = true; | |
254f965c | 240 | return; |
e158c5aa | 241 | } |
254f965c BW |
242 | |
243 | /* If called from reset, or thaw... we've been here already */ | |
40521054 BW |
244 | if (dev_priv->hw_contexts_disabled || |
245 | dev_priv->ring[RCS].default_context) | |
254f965c BW |
246 | return; |
247 | ||
07ea0d85 | 248 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
254f965c | 249 | |
07ea0d85 | 250 | if (dev_priv->hw_context_size > (1<<20)) { |
254f965c BW |
251 | dev_priv->hw_contexts_disabled = true; |
252 | return; | |
253 | } | |
254 | ||
255 | if (create_default_context(dev_priv)) { | |
256 | dev_priv->hw_contexts_disabled = true; | |
257 | return; | |
258 | } | |
259 | ||
260 | DRM_DEBUG_DRIVER("HW context support initialized\n"); | |
261 | } | |
262 | ||
263 | void i915_gem_context_fini(struct drm_device *dev) | |
264 | { | |
265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dce3271b | 266 | struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; |
254f965c BW |
267 | |
268 | if (dev_priv->hw_contexts_disabled) | |
269 | return; | |
40521054 | 270 | |
55a66628 DV |
271 | /* The only known way to stop the gpu from accessing the hw context is |
272 | * to reset it. Do this as the very last operation to avoid confusing | |
273 | * other code, leading to spurious errors. */ | |
274 | intel_gpu_reset(dev); | |
275 | ||
dce3271b MK |
276 | i915_gem_object_unpin(dctx->obj); |
277 | i915_gem_context_unreference(dctx); | |
254f965c BW |
278 | } |
279 | ||
40521054 BW |
280 | static int context_idr_cleanup(int id, void *p, void *data) |
281 | { | |
73c273eb | 282 | struct i915_hw_context *ctx = p; |
40521054 BW |
283 | |
284 | BUG_ON(id == DEFAULT_CONTEXT_ID); | |
40521054 | 285 | |
dce3271b | 286 | i915_gem_context_unreference(ctx); |
40521054 | 287 | return 0; |
254f965c BW |
288 | } |
289 | ||
290 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) | |
291 | { | |
40521054 | 292 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 293 | |
40521054 | 294 | mutex_lock(&dev->struct_mutex); |
73c273eb | 295 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 BW |
296 | idr_destroy(&file_priv->context_idr); |
297 | mutex_unlock(&dev->struct_mutex); | |
298 | } | |
299 | ||
e0556841 | 300 | static struct i915_hw_context * |
40521054 BW |
301 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
302 | { | |
303 | return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); | |
254f965c | 304 | } |
e0556841 BW |
305 | |
306 | static inline int | |
307 | mi_set_context(struct intel_ring_buffer *ring, | |
308 | struct i915_hw_context *new_context, | |
309 | u32 hw_flags) | |
310 | { | |
311 | int ret; | |
312 | ||
12b0286f BW |
313 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
314 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
315 | * explicitly, so we rely on the value at ring init, stored in | |
316 | * itlb_before_ctx_switch. | |
317 | */ | |
318 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | |
ac82ea2e | 319 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
320 | if (ret) |
321 | return ret; | |
322 | } | |
323 | ||
e37ec39b | 324 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
325 | if (ret) |
326 | return ret; | |
327 | ||
e37ec39b BW |
328 | if (IS_GEN7(ring->dev)) |
329 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
330 | else | |
331 | intel_ring_emit(ring, MI_NOOP); | |
332 | ||
e0556841 BW |
333 | intel_ring_emit(ring, MI_NOOP); |
334 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
335 | intel_ring_emit(ring, new_context->obj->gtt_offset | | |
336 | MI_MM_SPACE_GTT | | |
337 | MI_SAVE_EXT_STATE_EN | | |
338 | MI_RESTORE_EXT_STATE_EN | | |
339 | hw_flags); | |
340 | /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ | |
341 | intel_ring_emit(ring, MI_NOOP); | |
342 | ||
e37ec39b BW |
343 | if (IS_GEN7(ring->dev)) |
344 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
345 | else | |
346 | intel_ring_emit(ring, MI_NOOP); | |
347 | ||
e0556841 BW |
348 | intel_ring_advance(ring); |
349 | ||
350 | return ret; | |
351 | } | |
352 | ||
9a3b5304 | 353 | static int do_switch(struct i915_hw_context *to) |
e0556841 | 354 | { |
9a3b5304 CW |
355 | struct intel_ring_buffer *ring = to->ring; |
356 | struct drm_i915_gem_object *from_obj = ring->last_context_obj; | |
e0556841 BW |
357 | u32 hw_flags = 0; |
358 | int ret; | |
359 | ||
e0556841 BW |
360 | BUG_ON(from_obj != NULL && from_obj->pin_count == 0); |
361 | ||
9a3b5304 CW |
362 | if (from_obj == to->obj) |
363 | return 0; | |
364 | ||
86a1ee26 | 365 | ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false, false); |
e0556841 BW |
366 | if (ret) |
367 | return ret; | |
368 | ||
d3373a24 CW |
369 | /* Clear this page out of any CPU caches for coherent swap-in/out. Note |
370 | * that thanks to write = false in this call and us not setting any gpu | |
371 | * write domains when putting a context object onto the active list | |
372 | * (when switching away from it), this won't block. | |
373 | * XXX: We need a real interface to do this instead of trickery. */ | |
374 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); | |
375 | if (ret) { | |
376 | i915_gem_object_unpin(to->obj); | |
377 | return ret; | |
378 | } | |
379 | ||
3af7b857 DV |
380 | if (!to->obj->has_global_gtt_mapping) |
381 | i915_gem_gtt_bind_object(to->obj, to->obj->cache_level); | |
382 | ||
e0556841 BW |
383 | if (!to->is_initialized || is_default_context(to)) |
384 | hw_flags |= MI_RESTORE_INHIBIT; | |
385 | else if (WARN_ON_ONCE(from_obj == to->obj)) /* not yet expected */ | |
386 | hw_flags |= MI_FORCE_RESTORE; | |
387 | ||
e0556841 BW |
388 | ret = mi_set_context(ring, to, hw_flags); |
389 | if (ret) { | |
390 | i915_gem_object_unpin(to->obj); | |
391 | return ret; | |
392 | } | |
393 | ||
394 | /* The backing object for the context is done after switching to the | |
395 | * *next* context. Therefore we cannot retire the previous context until | |
396 | * the next context has already started running. In fact, the below code | |
397 | * is a bit suboptimal because the retiring can occur simply after the | |
398 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
399 | */ | |
400 | if (from_obj != NULL) { | |
401 | from_obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; | |
9d773091 | 402 | i915_gem_object_move_to_active(from_obj, ring); |
e0556841 BW |
403 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
404 | * whole damn pipeline, we don't need to explicitly mark the | |
405 | * object dirty. The only exception is that the context must be | |
406 | * correct in case the object gets swapped out. Ideally we'd be | |
407 | * able to defer doing this until we know the object would be | |
408 | * swapped, but there is no way to do that yet. | |
409 | */ | |
410 | from_obj->dirty = 1; | |
9a3b5304 | 411 | BUG_ON(from_obj->ring != ring); |
e0556841 | 412 | i915_gem_object_unpin(from_obj); |
b259b312 CW |
413 | |
414 | drm_gem_object_unreference(&from_obj->base); | |
e0556841 BW |
415 | } |
416 | ||
b259b312 | 417 | drm_gem_object_reference(&to->obj->base); |
e0556841 BW |
418 | ring->last_context_obj = to->obj; |
419 | to->is_initialized = true; | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | /** | |
425 | * i915_switch_context() - perform a GPU context switch. | |
426 | * @ring: ring for which we'll execute the context switch | |
427 | * @file_priv: file_priv associated with the context, may be NULL | |
428 | * @id: context id number | |
429 | * @seqno: sequence number by which the new context will be switched to | |
430 | * @flags: | |
431 | * | |
432 | * The context life cycle is simple. The context refcount is incremented and | |
433 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
434 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
435 | * object while letting the normal object tracking destroy the backing BO. | |
436 | */ | |
437 | int i915_switch_context(struct intel_ring_buffer *ring, | |
438 | struct drm_file *file, | |
439 | int to_id) | |
440 | { | |
441 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 442 | struct i915_hw_context *to; |
e0556841 BW |
443 | |
444 | if (dev_priv->hw_contexts_disabled) | |
445 | return 0; | |
446 | ||
447 | if (ring != &dev_priv->ring[RCS]) | |
448 | return 0; | |
449 | ||
e0556841 BW |
450 | if (to_id == DEFAULT_CONTEXT_ID) { |
451 | to = ring->default_context; | |
452 | } else { | |
9a3b5304 CW |
453 | if (file == NULL) |
454 | return -EINVAL; | |
455 | ||
456 | to = i915_gem_context_get(file->driver_priv, to_id); | |
e0556841 | 457 | if (to == NULL) |
0d326013 | 458 | return -ENOENT; |
e0556841 BW |
459 | } |
460 | ||
9a3b5304 | 461 | return do_switch(to); |
e0556841 | 462 | } |
84624813 BW |
463 | |
464 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
465 | struct drm_file *file) | |
466 | { | |
5fa8be65 | 467 | struct drm_i915_private *dev_priv = dev->dev_private; |
84624813 BW |
468 | struct drm_i915_gem_context_create *args = data; |
469 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
470 | struct i915_hw_context *ctx; | |
471 | int ret; | |
472 | ||
473 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
474 | return -ENODEV; | |
475 | ||
5fa8be65 DV |
476 | if (dev_priv->hw_contexts_disabled) |
477 | return -ENODEV; | |
478 | ||
84624813 BW |
479 | ret = i915_mutex_lock_interruptible(dev); |
480 | if (ret) | |
481 | return ret; | |
482 | ||
146937e5 | 483 | ctx = create_hw_context(dev, file_priv); |
84624813 | 484 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
485 | if (IS_ERR(ctx)) |
486 | return PTR_ERR(ctx); | |
84624813 BW |
487 | |
488 | args->ctx_id = ctx->id; | |
489 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
490 | ||
be636387 | 491 | return 0; |
84624813 BW |
492 | } |
493 | ||
494 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
495 | struct drm_file *file) | |
496 | { | |
497 | struct drm_i915_gem_context_destroy *args = data; | |
498 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
84624813 BW |
499 | struct i915_hw_context *ctx; |
500 | int ret; | |
501 | ||
502 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
503 | return -ENODEV; | |
504 | ||
505 | ret = i915_mutex_lock_interruptible(dev); | |
506 | if (ret) | |
507 | return ret; | |
508 | ||
509 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
510 | if (!ctx) { | |
511 | mutex_unlock(&dev->struct_mutex); | |
0d326013 | 512 | return -ENOENT; |
84624813 BW |
513 | } |
514 | ||
dce3271b MK |
515 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
516 | i915_gem_context_unreference(ctx); | |
84624813 BW |
517 | mutex_unlock(&dev->struct_mutex); |
518 | ||
519 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
520 | return 0; | |
521 | } |