]>
Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
b2e862d0 CW |
93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
94 | ||
40521054 BW |
95 | /* This is a HW constraint. The value below is the largest known requirement |
96 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
97 | * part. It should be safe to decrease this, but it's more future proof as is. | |
98 | */ | |
b731d33d BW |
99 | #define GEN6_CONTEXT_ALIGN (64<<10) |
100 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 101 | |
c033666a | 102 | static size_t get_context_alignment(struct drm_i915_private *dev_priv) |
b731d33d | 103 | { |
c033666a | 104 | if (IS_GEN6(dev_priv)) |
b731d33d BW |
105 | return GEN6_CONTEXT_ALIGN; |
106 | ||
107 | return GEN7_CONTEXT_ALIGN; | |
108 | } | |
109 | ||
c033666a | 110 | static int get_context_size(struct drm_i915_private *dev_priv) |
254f965c | 111 | { |
254f965c BW |
112 | int ret; |
113 | u32 reg; | |
114 | ||
c033666a | 115 | switch (INTEL_GEN(dev_priv)) { |
254f965c BW |
116 | case 6: |
117 | reg = I915_READ(CXT_SIZE); | |
118 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
119 | break; | |
120 | case 7: | |
4f91dd6f | 121 | reg = I915_READ(GEN7_CXT_SIZE); |
c033666a | 122 | if (IS_HASWELL(dev_priv)) |
a0de80a0 | 123 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
124 | else |
125 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 126 | break; |
8897644a BW |
127 | case 8: |
128 | ret = GEN8_CXT_TOTAL_SIZE; | |
129 | break; | |
254f965c BW |
130 | default: |
131 | BUG(); | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
e9f24d5f TU |
137 | static void i915_gem_context_clean(struct intel_context *ctx) |
138 | { | |
139 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; | |
140 | struct i915_vma *vma, *next; | |
141 | ||
61fb5881 | 142 | if (!ppgtt) |
e9f24d5f TU |
143 | return; |
144 | ||
e9f24d5f | 145 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
1c7f4bca | 146 | vm_link) { |
e9f24d5f TU |
147 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
148 | break; | |
149 | } | |
150 | } | |
151 | ||
dce3271b | 152 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 153 | { |
9ea4feec | 154 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
40521054 | 155 | |
198c974d DCS |
156 | trace_i915_context_free(ctx); |
157 | ||
ae6c4806 | 158 | if (i915.enable_execlists) |
ede7d42b | 159 | intel_lr_context_free(ctx); |
c7c48dfd | 160 | |
e9f24d5f TU |
161 | /* |
162 | * This context is going away and we need to remove all VMAs still | |
163 | * around. This is to handle imported shared objects for which | |
164 | * destructor did not run when their handles were closed. | |
165 | */ | |
166 | i915_gem_context_clean(ctx); | |
167 | ||
ae6c4806 DV |
168 | i915_ppgtt_put(ctx->ppgtt); |
169 | ||
2f295791 BW |
170 | if (ctx->legacy_hw_ctx.rcs_state) |
171 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); | |
c7c48dfd | 172 | list_del(&ctx->link); |
5d1808ec CW |
173 | |
174 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); | |
40521054 BW |
175 | kfree(ctx); |
176 | } | |
177 | ||
8c857917 | 178 | struct drm_i915_gem_object * |
aa0c13da OM |
179 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
180 | { | |
181 | struct drm_i915_gem_object *obj; | |
182 | int ret; | |
183 | ||
d37cd8a8 | 184 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
185 | if (IS_ERR(obj)) |
186 | return obj; | |
aa0c13da OM |
187 | |
188 | /* | |
189 | * Try to make the context utilize L3 as well as LLC. | |
190 | * | |
191 | * On VLV we don't have L3 controls in the PTEs so we | |
192 | * shouldn't touch the cache level, especially as that | |
193 | * would make the object snooped which might have a | |
194 | * negative performance impact. | |
4d3e904c WB |
195 | * |
196 | * Snooping is required on non-llc platforms in execlist | |
197 | * mode, but since all GGTT accesses use PAT entry 0 we | |
198 | * get snooping anyway regardless of cache_level. | |
199 | * | |
200 | * This is only applicable for Ivy Bridge devices since | |
201 | * later platforms don't have L3 control bits in the PTE. | |
aa0c13da | 202 | */ |
4d3e904c | 203 | if (IS_IVYBRIDGE(dev)) { |
aa0c13da OM |
204 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
205 | /* Failure shouldn't ever happen this early */ | |
206 | if (WARN_ON(ret)) { | |
207 | drm_gem_object_unreference(&obj->base); | |
208 | return ERR_PTR(ret); | |
209 | } | |
210 | } | |
211 | ||
212 | return obj; | |
213 | } | |
214 | ||
5d1808ec CW |
215 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
216 | { | |
217 | int ret; | |
218 | ||
219 | ret = ida_simple_get(&dev_priv->context_hw_ida, | |
220 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
221 | if (ret < 0) { | |
222 | /* Contexts are only released when no longer active. | |
223 | * Flush any pending retires to hopefully release some | |
224 | * stale contexts and try again. | |
225 | */ | |
c033666a | 226 | i915_gem_retire_requests(dev_priv); |
5d1808ec CW |
227 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
228 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
229 | if (ret < 0) | |
230 | return ret; | |
231 | } | |
232 | ||
233 | *out = ret; | |
234 | return 0; | |
235 | } | |
236 | ||
273497e5 | 237 | static struct intel_context * |
0eea67eb | 238 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 239 | struct drm_i915_file_private *file_priv) |
40521054 BW |
240 | { |
241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 242 | struct intel_context *ctx; |
c8c470af | 243 | int ret; |
40521054 | 244 | |
f94982b0 | 245 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
246 | if (ctx == NULL) |
247 | return ERR_PTR(-ENOMEM); | |
40521054 | 248 | |
5d1808ec CW |
249 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
250 | if (ret) { | |
251 | kfree(ctx); | |
252 | return ERR_PTR(ret); | |
253 | } | |
254 | ||
dce3271b | 255 | kref_init(&ctx->ref); |
691e6415 | 256 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 257 | ctx->i915 = dev_priv; |
40521054 | 258 | |
691e6415 | 259 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
260 | struct drm_i915_gem_object *obj = |
261 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
262 | if (IS_ERR(obj)) { | |
263 | ret = PTR_ERR(obj); | |
4615d4c9 | 264 | goto err_out; |
691e6415 | 265 | } |
ea0c76f8 | 266 | ctx->legacy_hw_ctx.rcs_state = obj; |
691e6415 | 267 | } |
40521054 BW |
268 | |
269 | /* Default context will never have a file_priv */ | |
691e6415 CW |
270 | if (file_priv != NULL) { |
271 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 272 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
273 | if (ret < 0) |
274 | goto err_out; | |
275 | } else | |
821d66dd | 276 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
277 | |
278 | ctx->file_priv = file_priv; | |
821d66dd | 279 | ctx->user_handle = ret; |
3ccfd19d BW |
280 | /* NB: Mark all slices as needing a remap so that when the context first |
281 | * loads it will restore whatever remap state already exists. If there | |
282 | * is no remap info, it will be a NOP. */ | |
b2e862d0 | 283 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
40521054 | 284 | |
676fa572 CW |
285 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
286 | ||
146937e5 | 287 | return ctx; |
40521054 BW |
288 | |
289 | err_out: | |
dce3271b | 290 | i915_gem_context_unreference(ctx); |
146937e5 | 291 | return ERR_PTR(ret); |
40521054 BW |
292 | } |
293 | ||
254f965c BW |
294 | /** |
295 | * The default context needs to exist per ring that uses contexts. It stores the | |
296 | * context state of the GPU for applications that don't utilize HW contexts, as | |
297 | * well as an idle case. | |
298 | */ | |
273497e5 | 299 | static struct intel_context * |
0eea67eb | 300 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 301 | struct drm_i915_file_private *file_priv) |
254f965c | 302 | { |
42c3b603 | 303 | const bool is_global_default_ctx = file_priv == NULL; |
273497e5 | 304 | struct intel_context *ctx; |
bdf4fd7e | 305 | int ret = 0; |
40521054 | 306 | |
b731d33d | 307 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 308 | |
0eea67eb | 309 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 310 | if (IS_ERR(ctx)) |
a45d0f6a | 311 | return ctx; |
40521054 | 312 | |
ea0c76f8 | 313 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
42c3b603 CW |
314 | /* We may need to do things with the shrinker which |
315 | * require us to immediately switch back to the default | |
316 | * context. This can cause a problem as pinning the | |
317 | * default context also requires GTT space which may not | |
318 | * be available. To avoid this we always pin the default | |
319 | * context. | |
320 | */ | |
ea0c76f8 | 321 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
c033666a | 322 | get_context_alignment(to_i915(dev)), 0); |
42c3b603 CW |
323 | if (ret) { |
324 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
325 | goto err_destroy; | |
326 | } | |
327 | } | |
328 | ||
d624d86e | 329 | if (USES_FULL_PPGTT(dev)) { |
4d884705 | 330 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e BW |
331 | |
332 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
333 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
334 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 335 | ret = PTR_ERR(ppgtt); |
42c3b603 | 336 | goto err_unpin; |
ae6c4806 DV |
337 | } |
338 | ||
339 | ctx->ppgtt = ppgtt; | |
340 | } | |
bdf4fd7e | 341 | |
198c974d DCS |
342 | trace_i915_context_create(ctx); |
343 | ||
a45d0f6a | 344 | return ctx; |
9a3b5304 | 345 | |
42c3b603 | 346 | err_unpin: |
ea0c76f8 OM |
347 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
348 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
9a3b5304 | 349 | err_destroy: |
37876df6 | 350 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
dce3271b | 351 | i915_gem_context_unreference(ctx); |
a45d0f6a | 352 | return ERR_PTR(ret); |
254f965c BW |
353 | } |
354 | ||
a0b4a6a8 TU |
355 | static void i915_gem_context_unpin(struct intel_context *ctx, |
356 | struct intel_engine_cs *engine) | |
357 | { | |
f4e2dece TU |
358 | if (i915.enable_execlists) { |
359 | intel_lr_context_unpin(ctx, engine); | |
360 | } else { | |
361 | if (engine->id == RCS && ctx->legacy_hw_ctx.rcs_state) | |
362 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
363 | i915_gem_context_unreference(ctx); | |
364 | } | |
a0b4a6a8 TU |
365 | } |
366 | ||
acce9ffa BW |
367 | void i915_gem_context_reset(struct drm_device *dev) |
368 | { | |
369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa | 370 | |
3e5b6f05 TD |
371 | if (i915.enable_execlists) { |
372 | struct intel_context *ctx; | |
373 | ||
a0b4a6a8 | 374 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
7d774cac | 375 | intel_lr_context_reset(dev_priv, ctx); |
3e5b6f05 | 376 | } |
ecdb5fd8 | 377 | |
b2e862d0 | 378 | i915_gem_context_lost(dev_priv); |
acce9ffa BW |
379 | } |
380 | ||
8245be31 | 381 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
382 | { |
383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 384 | struct intel_context *ctx; |
254f965c | 385 | |
2fa48d8d BW |
386 | /* Init should only be called once per module load. Eventually the |
387 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 388 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 389 | return 0; |
254f965c | 390 | |
c033666a CW |
391 | if (intel_vgpu_active(dev_priv) && |
392 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { | |
a0bd6c31 ZL |
393 | if (!i915.enable_execlists) { |
394 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
395 | return -EINVAL; | |
396 | } | |
397 | } | |
398 | ||
5d1808ec CW |
399 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
400 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); | |
401 | ida_init(&dev_priv->context_hw_ida); | |
402 | ||
ede7d42b OM |
403 | if (i915.enable_execlists) { |
404 | /* NB: intentionally left blank. We will allocate our own | |
405 | * backing objects as we need them, thank you very much */ | |
406 | dev_priv->hw_context_size = 0; | |
c033666a CW |
407 | } else if (HAS_HW_CONTEXTS(dev_priv)) { |
408 | dev_priv->hw_context_size = | |
409 | round_up(get_context_size(dev_priv), 4096); | |
691e6415 CW |
410 | if (dev_priv->hw_context_size > (1<<20)) { |
411 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
412 | dev_priv->hw_context_size); | |
413 | dev_priv->hw_context_size = 0; | |
414 | } | |
254f965c BW |
415 | } |
416 | ||
d624d86e | 417 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
418 | if (IS_ERR(ctx)) { |
419 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
420 | PTR_ERR(ctx)); | |
421 | return PTR_ERR(ctx); | |
254f965c BW |
422 | } |
423 | ||
ed54c1a1 | 424 | dev_priv->kernel_context = ctx; |
67e3d297 | 425 | |
ede7d42b OM |
426 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
427 | i915.enable_execlists ? "LR" : | |
428 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 429 | return 0; |
254f965c BW |
430 | } |
431 | ||
b2e862d0 CW |
432 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
433 | { | |
434 | struct intel_engine_cs *engine; | |
435 | ||
436 | for_each_engine(engine, dev_priv) { | |
437 | if (engine->last_context == NULL) | |
438 | continue; | |
439 | ||
440 | i915_gem_context_unpin(engine->last_context, engine); | |
441 | engine->last_context = NULL; | |
442 | } | |
443 | ||
444 | /* Force the GPU state to be reinitialised on enabling */ | |
445 | dev_priv->kernel_context->legacy_hw_ctx.initialized = false; | |
446 | dev_priv->kernel_context->remap_slice = ALL_L3_SLICES(dev_priv); | |
447 | } | |
448 | ||
254f965c BW |
449 | void i915_gem_context_fini(struct drm_device *dev) |
450 | { | |
451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed54c1a1 | 452 | struct intel_context *dctx = dev_priv->kernel_context; |
b2e862d0 | 453 | |
e7ae86ba | 454 | if (dctx->legacy_hw_ctx.rcs_state) |
ea0c76f8 | 455 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
67e3d297 | 456 | |
dce3271b | 457 | i915_gem_context_unreference(dctx); |
ed54c1a1 | 458 | dev_priv->kernel_context = NULL; |
5d1808ec CW |
459 | |
460 | ida_destroy(&dev_priv->context_hw_ida); | |
254f965c BW |
461 | } |
462 | ||
40521054 BW |
463 | static int context_idr_cleanup(int id, void *p, void *data) |
464 | { | |
273497e5 | 465 | struct intel_context *ctx = p; |
40521054 | 466 | |
dce3271b | 467 | i915_gem_context_unreference(ctx); |
40521054 | 468 | return 0; |
254f965c BW |
469 | } |
470 | ||
e422b888 BW |
471 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
472 | { | |
473 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 474 | struct intel_context *ctx; |
e422b888 BW |
475 | |
476 | idr_init(&file_priv->context_idr); | |
477 | ||
0eea67eb | 478 | mutex_lock(&dev->struct_mutex); |
d624d86e | 479 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
480 | mutex_unlock(&dev->struct_mutex); |
481 | ||
f83d6518 | 482 | if (IS_ERR(ctx)) { |
0eea67eb | 483 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 484 | return PTR_ERR(ctx); |
0eea67eb BW |
485 | } |
486 | ||
e422b888 BW |
487 | return 0; |
488 | } | |
489 | ||
254f965c BW |
490 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
491 | { | |
40521054 | 492 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 493 | |
73c273eb | 494 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 495 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
496 | } |
497 | ||
273497e5 | 498 | struct intel_context * |
40521054 BW |
499 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
500 | { | |
273497e5 | 501 | struct intel_context *ctx; |
72ad5c45 | 502 | |
273497e5 | 503 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
504 | if (!ctx) |
505 | return ERR_PTR(-ENOENT); | |
506 | ||
507 | return ctx; | |
254f965c | 508 | } |
e0556841 BW |
509 | |
510 | static inline int | |
1d719cda | 511 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 512 | { |
c033666a | 513 | struct drm_i915_private *dev_priv = req->i915; |
4a570db5 | 514 | struct intel_engine_cs *engine = req->engine; |
e80f14b6 | 515 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
516 | const int num_rings = |
517 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
c033666a CW |
518 | i915_semaphore_is_enabled(dev_priv) ? |
519 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 : | |
2c550183 | 520 | 0; |
b4ac5afc | 521 | int len, ret; |
e0556841 | 522 | |
12b0286f BW |
523 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
524 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
525 | * explicitly, so we rely on the value at ring init, stored in | |
526 | * itlb_before_ctx_switch. | |
527 | */ | |
c033666a | 528 | if (IS_GEN6(dev_priv)) { |
e2f80391 | 529 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
530 | if (ret) |
531 | return ret; | |
532 | } | |
533 | ||
e80f14b6 | 534 | /* These flags are for resource streamer on HSW+ */ |
c033666a | 535 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
4c436d55 | 536 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
c033666a | 537 | else if (INTEL_GEN(dev_priv) < 8) |
e80f14b6 BW |
538 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
539 | ||
2c550183 CW |
540 | |
541 | len = 4; | |
c033666a | 542 | if (INTEL_GEN(dev_priv) >= 7) |
e9135c4f | 543 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
2c550183 | 544 | |
5fb9de1a | 545 | ret = intel_ring_begin(req, len); |
e0556841 BW |
546 | if (ret) |
547 | return ret; | |
548 | ||
b3f797ac | 549 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
c033666a | 550 | if (INTEL_GEN(dev_priv) >= 7) { |
e2f80391 | 551 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
552 | if (num_rings) { |
553 | struct intel_engine_cs *signaller; | |
554 | ||
e2f80391 TU |
555 | intel_ring_emit(engine, |
556 | MI_LOAD_REGISTER_IMM(num_rings)); | |
c033666a | 557 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 558 | if (signaller == engine) |
2c550183 CW |
559 | continue; |
560 | ||
e2f80391 TU |
561 | intel_ring_emit_reg(engine, |
562 | RING_PSMI_CTL(signaller->mmio_base)); | |
563 | intel_ring_emit(engine, | |
564 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 CW |
565 | } |
566 | } | |
567 | } | |
e37ec39b | 568 | |
e2f80391 TU |
569 | intel_ring_emit(engine, MI_NOOP); |
570 | intel_ring_emit(engine, MI_SET_CONTEXT); | |
571 | intel_ring_emit(engine, | |
572 | i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | | |
e80f14b6 | 573 | flags); |
2b7e8082 VS |
574 | /* |
575 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
576 | * WaMiSetContext_Hang:snb,ivb,vlv | |
577 | */ | |
e2f80391 | 578 | intel_ring_emit(engine, MI_NOOP); |
e0556841 | 579 | |
c033666a | 580 | if (INTEL_GEN(dev_priv) >= 7) { |
2c550183 CW |
581 | if (num_rings) { |
582 | struct intel_engine_cs *signaller; | |
e9135c4f | 583 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
2c550183 | 584 | |
e2f80391 TU |
585 | intel_ring_emit(engine, |
586 | MI_LOAD_REGISTER_IMM(num_rings)); | |
c033666a | 587 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 588 | if (signaller == engine) |
2c550183 CW |
589 | continue; |
590 | ||
e9135c4f CW |
591 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
592 | intel_ring_emit_reg(engine, last_reg); | |
e2f80391 TU |
593 | intel_ring_emit(engine, |
594 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 | 595 | } |
e9135c4f CW |
596 | |
597 | /* Insert a delay before the next switch! */ | |
598 | intel_ring_emit(engine, | |
599 | MI_STORE_REGISTER_MEM | | |
600 | MI_SRM_LRM_GLOBAL_GTT); | |
601 | intel_ring_emit_reg(engine, last_reg); | |
602 | intel_ring_emit(engine, engine->scratch.gtt_offset); | |
603 | intel_ring_emit(engine, MI_NOOP); | |
2c550183 | 604 | } |
e2f80391 | 605 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 606 | } |
e37ec39b | 607 | |
e2f80391 | 608 | intel_ring_advance(engine); |
e0556841 BW |
609 | |
610 | return ret; | |
611 | } | |
612 | ||
d200cda6 | 613 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
b0ebde39 | 614 | { |
ff55b5e8 | 615 | u32 *remap_info = req->i915->l3_parity.remap_info[slice]; |
b0ebde39 | 616 | struct intel_engine_cs *engine = req->engine; |
b0ebde39 CW |
617 | int i, ret; |
618 | ||
ff55b5e8 | 619 | if (!remap_info) |
b0ebde39 CW |
620 | return 0; |
621 | ||
ff55b5e8 | 622 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
b0ebde39 CW |
623 | if (ret) |
624 | return ret; | |
625 | ||
626 | /* | |
627 | * Note: We do not worry about the concurrent register cacheline hang | |
628 | * here because no other code should access these registers other than | |
629 | * at initialization time. | |
630 | */ | |
ff55b5e8 CW |
631 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); |
632 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
b0ebde39 CW |
633 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); |
634 | intel_ring_emit(engine, remap_info[i]); | |
635 | } | |
ff55b5e8 | 636 | intel_ring_emit(engine, MI_NOOP); |
b0ebde39 CW |
637 | intel_ring_advance(engine); |
638 | ||
ff55b5e8 | 639 | return 0; |
b0ebde39 CW |
640 | } |
641 | ||
f9326be5 CW |
642 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
643 | struct intel_engine_cs *engine, | |
e1a8daa2 | 644 | struct intel_context *to) |
317b4e90 | 645 | { |
563222a7 BW |
646 | if (to->remap_slice) |
647 | return false; | |
648 | ||
fcb5106d CW |
649 | if (!to->legacy_hw_ctx.initialized) |
650 | return false; | |
651 | ||
f9326be5 | 652 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
fcb5106d | 653 | return false; |
317b4e90 | 654 | |
fcb5106d | 655 | return to == engine->last_context; |
317b4e90 BW |
656 | } |
657 | ||
658 | static bool | |
f9326be5 CW |
659 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
660 | struct intel_engine_cs *engine, | |
661 | struct intel_context *to) | |
317b4e90 | 662 | { |
f9326be5 | 663 | if (!ppgtt) |
317b4e90 BW |
664 | return false; |
665 | ||
f9326be5 CW |
666 | /* Always load the ppgtt on first use */ |
667 | if (!engine->last_context) | |
668 | return true; | |
669 | ||
670 | /* Same context without new entries, skip */ | |
e1a8daa2 | 671 | if (engine->last_context == to && |
f9326be5 | 672 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
e1a8daa2 CW |
673 | return false; |
674 | ||
675 | if (engine->id != RCS) | |
317b4e90 BW |
676 | return true; |
677 | ||
c033666a | 678 | if (INTEL_GEN(engine->i915) < 8) |
317b4e90 BW |
679 | return true; |
680 | ||
681 | return false; | |
682 | } | |
683 | ||
684 | static bool | |
f9326be5 CW |
685 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
686 | struct intel_context *to, | |
687 | u32 hw_flags) | |
317b4e90 | 688 | { |
f9326be5 | 689 | if (!ppgtt) |
317b4e90 BW |
690 | return false; |
691 | ||
fcb5106d | 692 | if (!IS_GEN8(to->i915)) |
317b4e90 BW |
693 | return false; |
694 | ||
6702cf16 | 695 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
696 | return true; |
697 | ||
698 | return false; | |
699 | } | |
700 | ||
e1a8daa2 | 701 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
e0556841 | 702 | { |
abd68d9e | 703 | struct intel_context *to = req->ctx; |
4a570db5 | 704 | struct intel_engine_cs *engine = req->engine; |
f9326be5 | 705 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
fcb5106d CW |
706 | struct intel_context *from; |
707 | u32 hw_flags; | |
3ccfd19d | 708 | int ret, i; |
e0556841 | 709 | |
f9326be5 | 710 | if (skip_rcs_switch(ppgtt, engine, to)) |
9a3b5304 CW |
711 | return 0; |
712 | ||
7e0d96bc | 713 | /* Trying to pin first makes error handling easier. */ |
e1a8daa2 | 714 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
c033666a | 715 | get_context_alignment(engine->i915), |
e1a8daa2 CW |
716 | 0); |
717 | if (ret) | |
718 | return ret; | |
67e3d297 | 719 | |
acc240d4 DV |
720 | /* |
721 | * Pin can switch back to the default context if we end up calling into | |
722 | * evict_everything - as a last ditch gtt defrag effort that also | |
723 | * switches to the default context. Hence we need to reload from here. | |
fcb5106d CW |
724 | * |
725 | * XXX: Doing so is painfully broken! | |
acc240d4 | 726 | */ |
e2f80391 | 727 | from = engine->last_context; |
acc240d4 DV |
728 | |
729 | /* | |
730 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
731 | * that thanks to write = false in this call and us not setting any gpu |
732 | * write domains when putting a context object onto the active list | |
733 | * (when switching away from it), this won't block. | |
acc240d4 DV |
734 | * |
735 | * XXX: We need a real interface to do this instead of trickery. | |
736 | */ | |
ea0c76f8 | 737 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
7e0d96bc BW |
738 | if (ret) |
739 | goto unpin_out; | |
d3373a24 | 740 | |
f9326be5 | 741 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
fcb5106d CW |
742 | /* Older GENs and non render rings still want the load first, |
743 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
744 | * Register Immediate commands in Ring Buffer before submitting | |
745 | * a context."*/ | |
746 | trace_switch_mm(engine, to); | |
f9326be5 | 747 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
748 | if (ret) |
749 | goto unpin_out; | |
750 | } | |
751 | ||
752 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) | |
6702cf16 BW |
753 | /* NB: If we inhibit the restore, the context is not allowed to |
754 | * die because future work may end up depending on valid address | |
755 | * space. This means we must enforce that a page table load | |
756 | * occur when this occurs. */ | |
fcb5106d | 757 | hw_flags = MI_RESTORE_INHIBIT; |
f9326be5 | 758 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
fcb5106d CW |
759 | hw_flags = MI_FORCE_RESTORE; |
760 | else | |
761 | hw_flags = 0; | |
e0556841 | 762 | |
fcb5106d CW |
763 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
764 | ret = mi_set_context(req, hw_flags); | |
3ccfd19d | 765 | if (ret) |
fcb5106d | 766 | goto unpin_out; |
3ccfd19d BW |
767 | } |
768 | ||
e0556841 BW |
769 | /* The backing object for the context is done after switching to the |
770 | * *next* context. Therefore we cannot retire the previous context until | |
771 | * the next context has already started running. In fact, the below code | |
772 | * is a bit suboptimal because the retiring can occur simply after the | |
773 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
774 | */ | |
112522f6 | 775 | if (from != NULL) { |
ea0c76f8 | 776 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
b2af0376 | 777 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
e0556841 BW |
778 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
779 | * whole damn pipeline, we don't need to explicitly mark the | |
780 | * object dirty. The only exception is that the context must be | |
781 | * correct in case the object gets swapped out. Ideally we'd be | |
782 | * able to defer doing this until we know the object would be | |
783 | * swapped, but there is no way to do that yet. | |
784 | */ | |
ea0c76f8 | 785 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
112522f6 | 786 | |
c0321e2c | 787 | /* obj is kept alive until the next request by its active ref */ |
ea0c76f8 | 788 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
112522f6 | 789 | i915_gem_context_unreference(from); |
e0556841 | 790 | } |
112522f6 | 791 | i915_gem_context_reference(to); |
e2f80391 | 792 | engine->last_context = to; |
e0556841 | 793 | |
fcb5106d CW |
794 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
795 | * setup, and we do not wish to move them. | |
796 | */ | |
f9326be5 | 797 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
fcb5106d | 798 | trace_switch_mm(engine, to); |
f9326be5 | 799 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
800 | /* The hardware context switch is emitted, but we haven't |
801 | * actually changed the state - so it's probably safe to bail | |
802 | * here. Still, let the user know something dangerous has | |
803 | * happened. | |
804 | */ | |
805 | if (ret) | |
806 | return ret; | |
807 | } | |
808 | ||
f9326be5 CW |
809 | if (ppgtt) |
810 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); | |
fcb5106d CW |
811 | |
812 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
813 | if (!(to->remap_slice & (1<<i))) | |
814 | continue; | |
815 | ||
d200cda6 | 816 | ret = remap_l3(req, i); |
fcb5106d CW |
817 | if (ret) |
818 | return ret; | |
819 | ||
820 | to->remap_slice &= ~(1<<i); | |
821 | } | |
822 | ||
823 | if (!to->legacy_hw_ctx.initialized) { | |
e2f80391 TU |
824 | if (engine->init_context) { |
825 | ret = engine->init_context(req); | |
86d7f238 | 826 | if (ret) |
fcb5106d | 827 | return ret; |
86d7f238 | 828 | } |
fcb5106d | 829 | to->legacy_hw_ctx.initialized = true; |
46470fc9 MK |
830 | } |
831 | ||
e0556841 | 832 | return 0; |
7e0d96bc BW |
833 | |
834 | unpin_out: | |
e1a8daa2 | 835 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
7e0d96bc | 836 | return ret; |
e0556841 BW |
837 | } |
838 | ||
839 | /** | |
840 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 841 | * @req: request for which we'll execute the context switch |
e0556841 BW |
842 | * |
843 | * The context life cycle is simple. The context refcount is incremented and | |
844 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 845 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 846 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
847 | * |
848 | * This function should not be used in execlists mode. Instead the context is | |
849 | * switched by writing to the ELSP and requests keep a reference to their | |
850 | * context. | |
e0556841 | 851 | */ |
ba01cc93 | 852 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 853 | { |
4a570db5 | 854 | struct intel_engine_cs *engine = req->engine; |
39dabecd | 855 | struct drm_i915_private *dev_priv = req->i915; |
e0556841 | 856 | |
ecdb5fd8 | 857 | WARN_ON(i915.enable_execlists); |
0eea67eb BW |
858 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
859 | ||
e1a8daa2 CW |
860 | if (engine->id != RCS || |
861 | req->ctx->legacy_hw_ctx.rcs_state == NULL) { | |
862 | struct intel_context *to = req->ctx; | |
f9326be5 CW |
863 | struct i915_hw_ppgtt *ppgtt = |
864 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; | |
e1a8daa2 | 865 | |
f9326be5 | 866 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
e1a8daa2 CW |
867 | int ret; |
868 | ||
869 | trace_switch_mm(engine, to); | |
f9326be5 | 870 | ret = ppgtt->switch_mm(ppgtt, req); |
e1a8daa2 CW |
871 | if (ret) |
872 | return ret; | |
873 | ||
f9326be5 | 874 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
e1a8daa2 CW |
875 | } |
876 | ||
877 | if (to != engine->last_context) { | |
878 | i915_gem_context_reference(to); | |
e2f80391 TU |
879 | if (engine->last_context) |
880 | i915_gem_context_unreference(engine->last_context); | |
e1a8daa2 | 881 | engine->last_context = to; |
691e6415 | 882 | } |
e1a8daa2 | 883 | |
c482972a | 884 | return 0; |
a95f6a00 | 885 | } |
c482972a | 886 | |
e1a8daa2 | 887 | return do_rcs_switch(req); |
e0556841 | 888 | } |
84624813 | 889 | |
ec3e9963 | 890 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 891 | { |
ec3e9963 | 892 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
893 | } |
894 | ||
84624813 BW |
895 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
896 | struct drm_file *file) | |
897 | { | |
84624813 BW |
898 | struct drm_i915_gem_context_create *args = data; |
899 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 900 | struct intel_context *ctx; |
84624813 BW |
901 | int ret; |
902 | ||
ec3e9963 | 903 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
904 | return -ENODEV; |
905 | ||
b31e5136 CW |
906 | if (args->pad != 0) |
907 | return -EINVAL; | |
908 | ||
84624813 BW |
909 | ret = i915_mutex_lock_interruptible(dev); |
910 | if (ret) | |
911 | return ret; | |
912 | ||
d624d86e | 913 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 914 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
915 | if (IS_ERR(ctx)) |
916 | return PTR_ERR(ctx); | |
84624813 | 917 | |
821d66dd | 918 | args->ctx_id = ctx->user_handle; |
84624813 BW |
919 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
920 | ||
be636387 | 921 | return 0; |
84624813 BW |
922 | } |
923 | ||
924 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
925 | struct drm_file *file) | |
926 | { | |
927 | struct drm_i915_gem_context_destroy *args = data; | |
928 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 929 | struct intel_context *ctx; |
84624813 BW |
930 | int ret; |
931 | ||
b31e5136 CW |
932 | if (args->pad != 0) |
933 | return -EINVAL; | |
934 | ||
821d66dd | 935 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 936 | return -ENOENT; |
0eea67eb | 937 | |
84624813 BW |
938 | ret = i915_mutex_lock_interruptible(dev); |
939 | if (ret) | |
940 | return ret; | |
941 | ||
942 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 943 | if (IS_ERR(ctx)) { |
84624813 | 944 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 945 | return PTR_ERR(ctx); |
84624813 BW |
946 | } |
947 | ||
821d66dd | 948 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
dce3271b | 949 | i915_gem_context_unreference(ctx); |
84624813 BW |
950 | mutex_unlock(&dev->struct_mutex); |
951 | ||
952 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
953 | return 0; | |
954 | } | |
c9dc0f35 CW |
955 | |
956 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
957 | struct drm_file *file) | |
958 | { | |
959 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
960 | struct drm_i915_gem_context_param *args = data; | |
961 | struct intel_context *ctx; | |
962 | int ret; | |
963 | ||
964 | ret = i915_mutex_lock_interruptible(dev); | |
965 | if (ret) | |
966 | return ret; | |
967 | ||
968 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
969 | if (IS_ERR(ctx)) { | |
970 | mutex_unlock(&dev->struct_mutex); | |
971 | return PTR_ERR(ctx); | |
972 | } | |
973 | ||
974 | args->size = 0; | |
975 | switch (args->param) { | |
976 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
977 | args->value = ctx->hang_stats.ban_period_seconds; | |
978 | break; | |
b1b38278 DW |
979 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
980 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
981 | break; | |
fa8848f2 CW |
982 | case I915_CONTEXT_PARAM_GTT_SIZE: |
983 | if (ctx->ppgtt) | |
984 | args->value = ctx->ppgtt->base.total; | |
985 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
986 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
987 | else | |
62106b4f | 988 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 989 | break; |
c9dc0f35 CW |
990 | default: |
991 | ret = -EINVAL; | |
992 | break; | |
993 | } | |
994 | mutex_unlock(&dev->struct_mutex); | |
995 | ||
996 | return ret; | |
997 | } | |
998 | ||
999 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
1000 | struct drm_file *file) | |
1001 | { | |
1002 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1003 | struct drm_i915_gem_context_param *args = data; | |
1004 | struct intel_context *ctx; | |
1005 | int ret; | |
1006 | ||
1007 | ret = i915_mutex_lock_interruptible(dev); | |
1008 | if (ret) | |
1009 | return ret; | |
1010 | ||
1011 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
1012 | if (IS_ERR(ctx)) { | |
1013 | mutex_unlock(&dev->struct_mutex); | |
1014 | return PTR_ERR(ctx); | |
1015 | } | |
1016 | ||
1017 | switch (args->param) { | |
1018 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
1019 | if (args->size) | |
1020 | ret = -EINVAL; | |
1021 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
1022 | !capable(CAP_SYS_ADMIN)) | |
1023 | ret = -EPERM; | |
1024 | else | |
1025 | ctx->hang_stats.ban_period_seconds = args->value; | |
1026 | break; | |
b1b38278 DW |
1027 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1028 | if (args->size) { | |
1029 | ret = -EINVAL; | |
1030 | } else { | |
1031 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
1032 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
1033 | } | |
1034 | break; | |
c9dc0f35 CW |
1035 | default: |
1036 | ret = -EINVAL; | |
1037 | break; | |
1038 | } | |
1039 | mutex_unlock(&dev->struct_mutex); | |
1040 | ||
1041 | return ret; | |
1042 | } | |
d538704b CW |
1043 | |
1044 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, | |
1045 | void *data, struct drm_file *file) | |
1046 | { | |
1047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1048 | struct drm_i915_reset_stats *args = data; | |
1049 | struct i915_ctx_hang_stats *hs; | |
1050 | struct intel_context *ctx; | |
1051 | int ret; | |
1052 | ||
1053 | if (args->flags || args->pad) | |
1054 | return -EINVAL; | |
1055 | ||
1056 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) | |
1057 | return -EPERM; | |
1058 | ||
bdb04614 | 1059 | ret = i915_mutex_lock_interruptible(dev); |
d538704b CW |
1060 | if (ret) |
1061 | return ret; | |
1062 | ||
1063 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); | |
1064 | if (IS_ERR(ctx)) { | |
1065 | mutex_unlock(&dev->struct_mutex); | |
1066 | return PTR_ERR(ctx); | |
1067 | } | |
1068 | hs = &ctx->hang_stats; | |
1069 | ||
1070 | if (capable(CAP_SYS_ADMIN)) | |
1071 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1072 | else | |
1073 | args->reset_count = 0; | |
1074 | ||
1075 | args->batch_active = hs->batch_active; | |
1076 | args->batch_pending = hs->batch_pending; | |
1077 | ||
1078 | mutex_unlock(&dev->struct_mutex); | |
1079 | ||
1080 | return 0; | |
1081 | } |