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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
76 | * GPU. The GPU has loaded it's state already and has stored away the gtt | |
77 | * offset of the BO. The GPU is not actively referencing the data at this | |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
88 | #include "drmP.h" | |
89 | #include "i915_drm.h" | |
90 | #include "i915_drv.h" | |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
96 | #define CONTEXT_ALIGN (64<<10) | |
97 | ||
98 | static struct i915_hw_context * | |
99 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); | |
9a3b5304 | 100 | static int do_switch(struct i915_hw_context *to); |
40521054 | 101 | |
254f965c BW |
102 | static int get_context_size(struct drm_device *dev) |
103 | { | |
104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
105 | int ret; | |
106 | u32 reg; | |
107 | ||
108 | switch (INTEL_INFO(dev)->gen) { | |
109 | case 6: | |
110 | reg = I915_READ(CXT_SIZE); | |
111 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
112 | break; | |
113 | case 7: | |
4f91dd6f | 114 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 BW |
115 | if (IS_HASWELL(dev)) |
116 | ret = HSW_CXT_TOTAL_SIZE(reg) * 64; | |
117 | else | |
118 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c BW |
119 | break; |
120 | default: | |
121 | BUG(); | |
122 | } | |
123 | ||
124 | return ret; | |
125 | } | |
126 | ||
40521054 BW |
127 | static void do_destroy(struct i915_hw_context *ctx) |
128 | { | |
129 | struct drm_device *dev = ctx->obj->base.dev; | |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | ||
132 | if (ctx->file_priv) | |
133 | idr_remove(&ctx->file_priv->context_idr, ctx->id); | |
134 | else | |
135 | BUG_ON(ctx != dev_priv->ring[RCS].default_context); | |
136 | ||
137 | drm_gem_object_unreference(&ctx->obj->base); | |
138 | kfree(ctx); | |
139 | } | |
140 | ||
146937e5 | 141 | static struct i915_hw_context * |
40521054 | 142 | create_hw_context(struct drm_device *dev, |
146937e5 | 143 | struct drm_i915_file_private *file_priv) |
40521054 BW |
144 | { |
145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146937e5 | 146 | struct i915_hw_context *ctx; |
40521054 BW |
147 | int ret, id; |
148 | ||
146937e5 BW |
149 | ctx = kzalloc(sizeof(struct drm_i915_file_private), GFP_KERNEL); |
150 | if (ctx == NULL) | |
151 | return ERR_PTR(-ENOMEM); | |
40521054 | 152 | |
146937e5 BW |
153 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
154 | if (ctx->obj == NULL) { | |
155 | kfree(ctx); | |
40521054 | 156 | DRM_DEBUG_DRIVER("Context object allocated failed\n"); |
146937e5 | 157 | return ERR_PTR(-ENOMEM); |
40521054 BW |
158 | } |
159 | ||
160 | /* The ring associated with the context object is handled by the normal | |
161 | * object tracking code. We give an initial ring value simple to pass an | |
162 | * assertion in the context switch code. | |
163 | */ | |
146937e5 | 164 | ctx->ring = &dev_priv->ring[RCS]; |
40521054 BW |
165 | |
166 | /* Default context will never have a file_priv */ | |
167 | if (file_priv == NULL) | |
146937e5 | 168 | return ctx; |
40521054 | 169 | |
146937e5 | 170 | ctx->file_priv = file_priv; |
40521054 BW |
171 | |
172 | again: | |
173 | if (idr_pre_get(&file_priv->context_idr, GFP_KERNEL) == 0) { | |
174 | ret = -ENOMEM; | |
175 | DRM_DEBUG_DRIVER("idr allocation failed\n"); | |
176 | goto err_out; | |
177 | } | |
178 | ||
146937e5 | 179 | ret = idr_get_new_above(&file_priv->context_idr, ctx, |
40521054 BW |
180 | DEFAULT_CONTEXT_ID + 1, &id); |
181 | if (ret == 0) | |
146937e5 | 182 | ctx->id = id; |
40521054 BW |
183 | |
184 | if (ret == -EAGAIN) | |
185 | goto again; | |
186 | else if (ret) | |
187 | goto err_out; | |
188 | ||
146937e5 | 189 | return ctx; |
40521054 BW |
190 | |
191 | err_out: | |
146937e5 BW |
192 | do_destroy(ctx); |
193 | return ERR_PTR(ret); | |
40521054 BW |
194 | } |
195 | ||
e0556841 BW |
196 | static inline bool is_default_context(struct i915_hw_context *ctx) |
197 | { | |
198 | return (ctx == ctx->ring->default_context); | |
199 | } | |
200 | ||
254f965c BW |
201 | /** |
202 | * The default context needs to exist per ring that uses contexts. It stores the | |
203 | * context state of the GPU for applications that don't utilize HW contexts, as | |
204 | * well as an idle case. | |
205 | */ | |
206 | static int create_default_context(struct drm_i915_private *dev_priv) | |
207 | { | |
40521054 BW |
208 | struct i915_hw_context *ctx; |
209 | int ret; | |
210 | ||
211 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); | |
212 | ||
146937e5 BW |
213 | ctx = create_hw_context(dev_priv->dev, NULL); |
214 | if (IS_ERR(ctx)) | |
215 | return PTR_ERR(ctx); | |
40521054 BW |
216 | |
217 | /* We may need to do things with the shrinker which require us to | |
218 | * immediately switch back to the default context. This can cause a | |
219 | * problem as pinning the default context also requires GTT space which | |
220 | * may not be available. To avoid this we always pin the | |
221 | * default context. | |
222 | */ | |
146937e5 | 223 | dev_priv->ring[RCS].default_context = ctx; |
86a1ee26 | 224 | ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false, false); |
9a3b5304 CW |
225 | if (ret) |
226 | goto err_destroy; | |
40521054 | 227 | |
9a3b5304 CW |
228 | ret = do_switch(ctx); |
229 | if (ret) | |
230 | goto err_unpin; | |
dfabbcb4 | 231 | |
9a3b5304 CW |
232 | DRM_DEBUG_DRIVER("Default HW context loaded\n"); |
233 | return 0; | |
234 | ||
235 | err_unpin: | |
236 | i915_gem_object_unpin(ctx->obj); | |
237 | err_destroy: | |
238 | do_destroy(ctx); | |
40521054 | 239 | return ret; |
254f965c BW |
240 | } |
241 | ||
242 | void i915_gem_context_init(struct drm_device *dev) | |
243 | { | |
244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
245 | uint32_t ctx_size; | |
246 | ||
e158c5aa BW |
247 | if (!HAS_HW_CONTEXTS(dev)) { |
248 | dev_priv->hw_contexts_disabled = true; | |
254f965c | 249 | return; |
e158c5aa | 250 | } |
254f965c BW |
251 | |
252 | /* If called from reset, or thaw... we've been here already */ | |
40521054 BW |
253 | if (dev_priv->hw_contexts_disabled || |
254 | dev_priv->ring[RCS].default_context) | |
254f965c BW |
255 | return; |
256 | ||
257 | ctx_size = get_context_size(dev); | |
258 | dev_priv->hw_context_size = get_context_size(dev); | |
259 | dev_priv->hw_context_size = round_up(dev_priv->hw_context_size, 4096); | |
260 | ||
261 | if (ctx_size <= 0 || ctx_size > (1<<20)) { | |
262 | dev_priv->hw_contexts_disabled = true; | |
263 | return; | |
264 | } | |
265 | ||
266 | if (create_default_context(dev_priv)) { | |
267 | dev_priv->hw_contexts_disabled = true; | |
268 | return; | |
269 | } | |
270 | ||
271 | DRM_DEBUG_DRIVER("HW context support initialized\n"); | |
272 | } | |
273 | ||
274 | void i915_gem_context_fini(struct drm_device *dev) | |
275 | { | |
276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
277 | ||
278 | if (dev_priv->hw_contexts_disabled) | |
279 | return; | |
40521054 | 280 | |
55a66628 DV |
281 | /* The only known way to stop the gpu from accessing the hw context is |
282 | * to reset it. Do this as the very last operation to avoid confusing | |
283 | * other code, leading to spurious errors. */ | |
284 | intel_gpu_reset(dev); | |
285 | ||
40521054 BW |
286 | i915_gem_object_unpin(dev_priv->ring[RCS].default_context->obj); |
287 | ||
288 | do_destroy(dev_priv->ring[RCS].default_context); | |
254f965c BW |
289 | } |
290 | ||
40521054 BW |
291 | static int context_idr_cleanup(int id, void *p, void *data) |
292 | { | |
73c273eb | 293 | struct i915_hw_context *ctx = p; |
40521054 BW |
294 | |
295 | BUG_ON(id == DEFAULT_CONTEXT_ID); | |
40521054 BW |
296 | |
297 | do_destroy(ctx); | |
298 | ||
299 | return 0; | |
254f965c BW |
300 | } |
301 | ||
302 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) | |
303 | { | |
40521054 | 304 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 305 | |
40521054 | 306 | mutex_lock(&dev->struct_mutex); |
73c273eb | 307 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 BW |
308 | idr_destroy(&file_priv->context_idr); |
309 | mutex_unlock(&dev->struct_mutex); | |
310 | } | |
311 | ||
e0556841 | 312 | static struct i915_hw_context * |
40521054 BW |
313 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
314 | { | |
315 | return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); | |
254f965c | 316 | } |
e0556841 BW |
317 | |
318 | static inline int | |
319 | mi_set_context(struct intel_ring_buffer *ring, | |
320 | struct i915_hw_context *new_context, | |
321 | u32 hw_flags) | |
322 | { | |
323 | int ret; | |
324 | ||
12b0286f BW |
325 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
326 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
327 | * explicitly, so we rely on the value at ring init, stored in | |
328 | * itlb_before_ctx_switch. | |
329 | */ | |
330 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | |
331 | ret = ring->flush(ring, 0, 0); | |
332 | if (ret) | |
333 | return ret; | |
334 | } | |
335 | ||
e37ec39b | 336 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
337 | if (ret) |
338 | return ret; | |
339 | ||
e37ec39b BW |
340 | if (IS_GEN7(ring->dev)) |
341 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
342 | else | |
343 | intel_ring_emit(ring, MI_NOOP); | |
344 | ||
e0556841 BW |
345 | intel_ring_emit(ring, MI_NOOP); |
346 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
347 | intel_ring_emit(ring, new_context->obj->gtt_offset | | |
348 | MI_MM_SPACE_GTT | | |
349 | MI_SAVE_EXT_STATE_EN | | |
350 | MI_RESTORE_EXT_STATE_EN | | |
351 | hw_flags); | |
352 | /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ | |
353 | intel_ring_emit(ring, MI_NOOP); | |
354 | ||
e37ec39b BW |
355 | if (IS_GEN7(ring->dev)) |
356 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
357 | else | |
358 | intel_ring_emit(ring, MI_NOOP); | |
359 | ||
e0556841 BW |
360 | intel_ring_advance(ring); |
361 | ||
362 | return ret; | |
363 | } | |
364 | ||
9a3b5304 | 365 | static int do_switch(struct i915_hw_context *to) |
e0556841 | 366 | { |
9a3b5304 CW |
367 | struct intel_ring_buffer *ring = to->ring; |
368 | struct drm_i915_gem_object *from_obj = ring->last_context_obj; | |
e0556841 BW |
369 | u32 hw_flags = 0; |
370 | int ret; | |
371 | ||
e0556841 BW |
372 | BUG_ON(from_obj != NULL && from_obj->pin_count == 0); |
373 | ||
9a3b5304 CW |
374 | if (from_obj == to->obj) |
375 | return 0; | |
376 | ||
86a1ee26 | 377 | ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false, false); |
e0556841 BW |
378 | if (ret) |
379 | return ret; | |
380 | ||
d3373a24 CW |
381 | /* Clear this page out of any CPU caches for coherent swap-in/out. Note |
382 | * that thanks to write = false in this call and us not setting any gpu | |
383 | * write domains when putting a context object onto the active list | |
384 | * (when switching away from it), this won't block. | |
385 | * XXX: We need a real interface to do this instead of trickery. */ | |
386 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); | |
387 | if (ret) { | |
388 | i915_gem_object_unpin(to->obj); | |
389 | return ret; | |
390 | } | |
391 | ||
3af7b857 DV |
392 | if (!to->obj->has_global_gtt_mapping) |
393 | i915_gem_gtt_bind_object(to->obj, to->obj->cache_level); | |
394 | ||
e0556841 BW |
395 | if (!to->is_initialized || is_default_context(to)) |
396 | hw_flags |= MI_RESTORE_INHIBIT; | |
397 | else if (WARN_ON_ONCE(from_obj == to->obj)) /* not yet expected */ | |
398 | hw_flags |= MI_FORCE_RESTORE; | |
399 | ||
e0556841 BW |
400 | ret = mi_set_context(ring, to, hw_flags); |
401 | if (ret) { | |
402 | i915_gem_object_unpin(to->obj); | |
403 | return ret; | |
404 | } | |
405 | ||
406 | /* The backing object for the context is done after switching to the | |
407 | * *next* context. Therefore we cannot retire the previous context until | |
408 | * the next context has already started running. In fact, the below code | |
409 | * is a bit suboptimal because the retiring can occur simply after the | |
410 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
411 | */ | |
412 | if (from_obj != NULL) { | |
9a3b5304 | 413 | u32 seqno = i915_gem_next_request_seqno(ring); |
e0556841 BW |
414 | from_obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
415 | i915_gem_object_move_to_active(from_obj, ring, seqno); | |
416 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the | |
417 | * whole damn pipeline, we don't need to explicitly mark the | |
418 | * object dirty. The only exception is that the context must be | |
419 | * correct in case the object gets swapped out. Ideally we'd be | |
420 | * able to defer doing this until we know the object would be | |
421 | * swapped, but there is no way to do that yet. | |
422 | */ | |
423 | from_obj->dirty = 1; | |
9a3b5304 | 424 | BUG_ON(from_obj->ring != ring); |
e0556841 | 425 | i915_gem_object_unpin(from_obj); |
b259b312 CW |
426 | |
427 | drm_gem_object_unreference(&from_obj->base); | |
e0556841 BW |
428 | } |
429 | ||
b259b312 | 430 | drm_gem_object_reference(&to->obj->base); |
e0556841 BW |
431 | ring->last_context_obj = to->obj; |
432 | to->is_initialized = true; | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | /** | |
438 | * i915_switch_context() - perform a GPU context switch. | |
439 | * @ring: ring for which we'll execute the context switch | |
440 | * @file_priv: file_priv associated with the context, may be NULL | |
441 | * @id: context id number | |
442 | * @seqno: sequence number by which the new context will be switched to | |
443 | * @flags: | |
444 | * | |
445 | * The context life cycle is simple. The context refcount is incremented and | |
446 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
447 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
448 | * object while letting the normal object tracking destroy the backing BO. | |
449 | */ | |
450 | int i915_switch_context(struct intel_ring_buffer *ring, | |
451 | struct drm_file *file, | |
452 | int to_id) | |
453 | { | |
454 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 455 | struct i915_hw_context *to; |
e0556841 BW |
456 | |
457 | if (dev_priv->hw_contexts_disabled) | |
458 | return 0; | |
459 | ||
460 | if (ring != &dev_priv->ring[RCS]) | |
461 | return 0; | |
462 | ||
e0556841 BW |
463 | if (to_id == DEFAULT_CONTEXT_ID) { |
464 | to = ring->default_context; | |
465 | } else { | |
9a3b5304 CW |
466 | if (file == NULL) |
467 | return -EINVAL; | |
468 | ||
469 | to = i915_gem_context_get(file->driver_priv, to_id); | |
e0556841 | 470 | if (to == NULL) |
0d326013 | 471 | return -ENOENT; |
e0556841 BW |
472 | } |
473 | ||
9a3b5304 | 474 | return do_switch(to); |
e0556841 | 475 | } |
84624813 BW |
476 | |
477 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
478 | struct drm_file *file) | |
479 | { | |
5fa8be65 | 480 | struct drm_i915_private *dev_priv = dev->dev_private; |
84624813 BW |
481 | struct drm_i915_gem_context_create *args = data; |
482 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
483 | struct i915_hw_context *ctx; | |
484 | int ret; | |
485 | ||
486 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
487 | return -ENODEV; | |
488 | ||
5fa8be65 DV |
489 | if (dev_priv->hw_contexts_disabled) |
490 | return -ENODEV; | |
491 | ||
84624813 BW |
492 | ret = i915_mutex_lock_interruptible(dev); |
493 | if (ret) | |
494 | return ret; | |
495 | ||
146937e5 | 496 | ctx = create_hw_context(dev, file_priv); |
84624813 | 497 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
498 | if (IS_ERR(ctx)) |
499 | return PTR_ERR(ctx); | |
84624813 BW |
500 | |
501 | args->ctx_id = ctx->id; | |
502 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
503 | ||
be636387 | 504 | return 0; |
84624813 BW |
505 | } |
506 | ||
507 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
508 | struct drm_file *file) | |
509 | { | |
510 | struct drm_i915_gem_context_destroy *args = data; | |
511 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
84624813 BW |
512 | struct i915_hw_context *ctx; |
513 | int ret; | |
514 | ||
515 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
516 | return -ENODEV; | |
517 | ||
518 | ret = i915_mutex_lock_interruptible(dev); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
522 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
523 | if (!ctx) { | |
524 | mutex_unlock(&dev->struct_mutex); | |
0d326013 | 525 | return -ENOENT; |
84624813 BW |
526 | } |
527 | ||
528 | do_destroy(ctx); | |
529 | ||
530 | mutex_unlock(&dev->struct_mutex); | |
531 | ||
532 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
533 | return 0; | |
534 | } |