]>
Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
b731d33d BW |
96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 98 | |
67e3d297 BW |
99 | static int do_switch(struct intel_ring_buffer *ring, |
100 | struct i915_hw_context *to); | |
40521054 | 101 | |
b731d33d BW |
102 | static size_t get_context_alignment(struct drm_device *dev) |
103 | { | |
104 | if (IS_GEN6(dev)) | |
105 | return GEN6_CONTEXT_ALIGN; | |
106 | ||
107 | return GEN7_CONTEXT_ALIGN; | |
108 | } | |
109 | ||
254f965c BW |
110 | static int get_context_size(struct drm_device *dev) |
111 | { | |
112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
113 | int ret; | |
114 | u32 reg; | |
115 | ||
116 | switch (INTEL_INFO(dev)->gen) { | |
117 | case 6: | |
118 | reg = I915_READ(CXT_SIZE); | |
119 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
120 | break; | |
121 | case 7: | |
4f91dd6f | 122 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 123 | if (IS_HASWELL(dev)) |
a0de80a0 | 124 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
125 | else |
126 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 127 | break; |
8897644a BW |
128 | case 8: |
129 | ret = GEN8_CXT_TOTAL_SIZE; | |
130 | break; | |
254f965c BW |
131 | default: |
132 | BUG(); | |
133 | } | |
134 | ||
135 | return ret; | |
136 | } | |
137 | ||
dce3271b | 138 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 139 | { |
dce3271b MK |
140 | struct i915_hw_context *ctx = container_of(ctx_ref, |
141 | typeof(*ctx), ref); | |
c7c48dfd | 142 | struct i915_hw_ppgtt *ppgtt = NULL; |
40521054 | 143 | |
c7c48dfd BW |
144 | /* We refcount even the aliasing PPGTT to keep the code symmetric */ |
145 | if (USES_ALIASING_PPGTT(ctx->obj->base.dev)) | |
0eea67eb | 146 | ppgtt = ctx_to_ppgtt(ctx); |
c7c48dfd BW |
147 | |
148 | /* XXX: Free up the object before tearing down the address space, in | |
149 | * case we're bound in the PPGTT */ | |
40521054 | 150 | drm_gem_object_unreference(&ctx->obj->base); |
c7c48dfd BW |
151 | |
152 | if (ppgtt) | |
153 | kref_put(&ppgtt->ref, ppgtt_release); | |
154 | list_del(&ctx->link); | |
40521054 BW |
155 | kfree(ctx); |
156 | } | |
157 | ||
bdf4fd7e BW |
158 | static struct i915_hw_ppgtt * |
159 | create_vm_for_ctx(struct drm_device *dev, struct i915_hw_context *ctx) | |
160 | { | |
161 | struct i915_hw_ppgtt *ppgtt; | |
162 | int ret; | |
163 | ||
164 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
165 | if (!ppgtt) | |
166 | return ERR_PTR(-ENOMEM); | |
167 | ||
168 | ret = i915_gem_init_ppgtt(dev, ppgtt); | |
169 | if (ret) { | |
170 | kfree(ppgtt); | |
171 | return ERR_PTR(ret); | |
172 | } | |
173 | ||
174 | return ppgtt; | |
175 | } | |
176 | ||
146937e5 | 177 | static struct i915_hw_context * |
0eea67eb | 178 | __create_hw_context(struct drm_device *dev, |
146937e5 | 179 | struct drm_i915_file_private *file_priv) |
40521054 BW |
180 | { |
181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146937e5 | 182 | struct i915_hw_context *ctx; |
c8c470af | 183 | int ret; |
40521054 | 184 | |
f94982b0 | 185 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
186 | if (ctx == NULL) |
187 | return ERR_PTR(-ENOMEM); | |
40521054 | 188 | |
dce3271b | 189 | kref_init(&ctx->ref); |
146937e5 | 190 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
a33afea5 | 191 | INIT_LIST_HEAD(&ctx->link); |
146937e5 BW |
192 | if (ctx->obj == NULL) { |
193 | kfree(ctx); | |
40521054 | 194 | DRM_DEBUG_DRIVER("Context object allocated failed\n"); |
146937e5 | 195 | return ERR_PTR(-ENOMEM); |
40521054 BW |
196 | } |
197 | ||
4615d4c9 CW |
198 | if (INTEL_INFO(dev)->gen >= 7) { |
199 | ret = i915_gem_object_set_cache_level(ctx->obj, | |
350ec881 | 200 | I915_CACHE_L3_LLC); |
bb036413 BW |
201 | /* Failure shouldn't ever happen this early */ |
202 | if (WARN_ON(ret)) | |
4615d4c9 CW |
203 | goto err_out; |
204 | } | |
205 | ||
a33afea5 | 206 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 BW |
207 | |
208 | /* Default context will never have a file_priv */ | |
209 | if (file_priv == NULL) | |
146937e5 | 210 | return ctx; |
40521054 | 211 | |
0eea67eb | 212 | ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID, 0, |
c8c470af TH |
213 | GFP_KERNEL); |
214 | if (ret < 0) | |
40521054 | 215 | goto err_out; |
dce3271b MK |
216 | |
217 | ctx->file_priv = file_priv; | |
c8c470af | 218 | ctx->id = ret; |
3ccfd19d BW |
219 | /* NB: Mark all slices as needing a remap so that when the context first |
220 | * loads it will restore whatever remap state already exists. If there | |
221 | * is no remap info, it will be a NOP. */ | |
222 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 223 | |
146937e5 | 224 | return ctx; |
40521054 BW |
225 | |
226 | err_out: | |
dce3271b | 227 | i915_gem_context_unreference(ctx); |
146937e5 | 228 | return ERR_PTR(ret); |
40521054 BW |
229 | } |
230 | ||
e0556841 BW |
231 | static inline bool is_default_context(struct i915_hw_context *ctx) |
232 | { | |
0eea67eb | 233 | return (ctx->id == DEFAULT_CONTEXT_ID); |
e0556841 BW |
234 | } |
235 | ||
254f965c BW |
236 | /** |
237 | * The default context needs to exist per ring that uses contexts. It stores the | |
238 | * context state of the GPU for applications that don't utilize HW contexts, as | |
239 | * well as an idle case. | |
240 | */ | |
a45d0f6a | 241 | static struct i915_hw_context * |
0eea67eb BW |
242 | i915_gem_create_context(struct drm_device *dev, |
243 | struct drm_i915_file_private *file_priv, | |
244 | bool create_vm) | |
254f965c | 245 | { |
bdf4fd7e | 246 | struct drm_i915_private *dev_priv = dev->dev_private; |
40521054 | 247 | struct i915_hw_context *ctx; |
bdf4fd7e | 248 | int ret = 0; |
40521054 | 249 | |
b731d33d | 250 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 251 | |
0eea67eb | 252 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 253 | if (IS_ERR(ctx)) |
a45d0f6a | 254 | return ctx; |
40521054 | 255 | |
bdf4fd7e BW |
256 | if (create_vm) { |
257 | struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx); | |
258 | ||
259 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
260 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
261 | PTR_ERR(ppgtt)); | |
bdf4fd7e BW |
262 | ret = PTR_ERR(ppgtt); |
263 | goto err_destroy; | |
264 | } else | |
265 | ctx->vm = &ppgtt->base; | |
266 | ||
267 | /* This case is reserved for the global default context and | |
268 | * should only happen once. */ | |
269 | if (!file_priv) { | |
270 | if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) { | |
271 | ret = -EEXIST; | |
272 | goto err_destroy; | |
273 | } | |
274 | ||
275 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
276 | ||
277 | /* We may need to do things with the shrinker which | |
278 | * require us to immediately switch back to the default | |
279 | * context. This can cause a problem as pinning the | |
280 | * default context also requires GTT space which may not | |
281 | * be available. To avoid this we always pin the default | |
282 | * context. | |
283 | */ | |
284 | ret = i915_gem_obj_ggtt_pin(ctx->obj, | |
285 | get_context_alignment(dev), | |
286 | false, false); | |
287 | if (ret) { | |
288 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
289 | goto err_destroy; | |
290 | } | |
291 | } | |
292 | } else if (USES_ALIASING_PPGTT(dev)) { | |
293 | /* For platforms which only have aliasing PPGTT, we fake the | |
294 | * address space and refcounting. */ | |
295 | kref_get(&dev_priv->mm.aliasing_ppgtt->ref); | |
bb036413 | 296 | } |
40521054 | 297 | |
bdf4fd7e BW |
298 | /* TODO: Until full ppgtt... */ |
299 | if (USES_ALIASING_PPGTT(dev)) | |
300 | ctx->vm = &dev_priv->mm.aliasing_ppgtt->base; | |
301 | else | |
302 | ctx->vm = &dev_priv->gtt.base; | |
303 | ||
a45d0f6a | 304 | return ctx; |
9a3b5304 | 305 | |
9a3b5304 | 306 | err_destroy: |
dce3271b | 307 | i915_gem_context_unreference(ctx); |
a45d0f6a | 308 | return ERR_PTR(ret); |
254f965c BW |
309 | } |
310 | ||
acce9ffa BW |
311 | void i915_gem_context_reset(struct drm_device *dev) |
312 | { | |
313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
314 | struct intel_ring_buffer *ring; | |
315 | int i; | |
316 | ||
317 | if (!HAS_HW_CONTEXTS(dev)) | |
318 | return; | |
319 | ||
320 | /* Prevent the hardware from restoring the last context (which hung) on | |
321 | * the next switch */ | |
322 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
323 | struct i915_hw_context *dctx; | |
324 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
325 | continue; | |
326 | ||
327 | /* Do a fake switch to the default context */ | |
328 | ring = &dev_priv->ring[i]; | |
329 | dctx = ring->default_context; | |
330 | if (WARN_ON(!dctx)) | |
331 | continue; | |
332 | ||
333 | if (!ring->last_context) | |
334 | continue; | |
335 | ||
336 | if (ring->last_context == dctx) | |
337 | continue; | |
338 | ||
339 | if (i == RCS) { | |
340 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj, | |
341 | get_context_alignment(dev), | |
342 | false, false)); | |
343 | /* Fake a finish/inactive */ | |
344 | dctx->obj->base.write_domain = 0; | |
345 | dctx->obj->active = 0; | |
346 | } | |
347 | ||
348 | i915_gem_context_unreference(ring->last_context); | |
349 | i915_gem_context_reference(dctx); | |
350 | ring->last_context = dctx; | |
351 | } | |
352 | } | |
353 | ||
8245be31 | 354 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
355 | { |
356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
67e3d297 | 357 | struct intel_ring_buffer *ring; |
a45d0f6a | 358 | int i; |
254f965c | 359 | |
8245be31 BW |
360 | if (!HAS_HW_CONTEXTS(dev)) |
361 | return 0; | |
254f965c | 362 | |
2fa48d8d BW |
363 | /* Init should only be called once per module load. Eventually the |
364 | * restriction on the context_disabled check can be loosened. */ | |
365 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 366 | return 0; |
254f965c | 367 | |
07ea0d85 | 368 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
254f965c | 369 | |
07ea0d85 | 370 | if (dev_priv->hw_context_size > (1<<20)) { |
bb036413 | 371 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n"); |
8245be31 | 372 | return -E2BIG; |
254f965c BW |
373 | } |
374 | ||
bdf4fd7e | 375 | dev_priv->ring[RCS].default_context = |
0eea67eb | 376 | i915_gem_create_context(dev, NULL, USES_ALIASING_PPGTT(dev)); |
a45d0f6a | 377 | |
a45d0f6a BW |
378 | if (IS_ERR_OR_NULL(dev_priv->ring[RCS].default_context)) { |
379 | DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %ld\n", | |
380 | PTR_ERR(dev_priv->ring[RCS].default_context)); | |
381 | return PTR_ERR(dev_priv->ring[RCS].default_context); | |
254f965c BW |
382 | } |
383 | ||
67e3d297 BW |
384 | for (i = RCS + 1; i < I915_NUM_RINGS; i++) { |
385 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
386 | continue; | |
387 | ||
388 | ring = &dev_priv->ring[i]; | |
389 | ||
390 | /* NB: RCS will hold a ref for all rings */ | |
391 | ring->default_context = dev_priv->ring[RCS].default_context; | |
392 | } | |
393 | ||
254f965c | 394 | DRM_DEBUG_DRIVER("HW context support initialized\n"); |
8245be31 | 395 | return 0; |
254f965c BW |
396 | } |
397 | ||
398 | void i915_gem_context_fini(struct drm_device *dev) | |
399 | { | |
400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dce3271b | 401 | struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 402 | int i; |
254f965c | 403 | |
8245be31 | 404 | if (!HAS_HW_CONTEXTS(dev)) |
254f965c | 405 | return; |
40521054 | 406 | |
55a66628 DV |
407 | /* The only known way to stop the gpu from accessing the hw context is |
408 | * to reset it. Do this as the very last operation to avoid confusing | |
409 | * other code, leading to spurious errors. */ | |
410 | intel_gpu_reset(dev); | |
411 | ||
168f8366 MK |
412 | /* When default context is created and switched to, base object refcount |
413 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
414 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
415 | * to default context. So we need to unreference the base object once | |
416 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
417 | * can then free the base object correctly. */ | |
71b76d00 BW |
418 | WARN_ON(!dev_priv->ring[RCS].last_context); |
419 | if (dev_priv->ring[RCS].last_context == dctx) { | |
420 | /* Fake switch to NULL context */ | |
421 | WARN_ON(dctx->obj->active); | |
d7f46fc4 | 422 | i915_gem_object_ggtt_unpin(dctx->obj); |
71b76d00 | 423 | i915_gem_context_unreference(dctx); |
67e3d297 BW |
424 | dev_priv->ring[RCS].last_context = NULL; |
425 | } | |
426 | ||
427 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
428 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
429 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
430 | continue; | |
431 | ||
432 | if (ring->last_context) | |
433 | i915_gem_context_unreference(ring->last_context); | |
434 | ||
435 | ring->default_context = NULL; | |
0009e46c | 436 | ring->last_context = NULL; |
71b76d00 BW |
437 | } |
438 | ||
d7f46fc4 | 439 | i915_gem_object_ggtt_unpin(dctx->obj); |
dce3271b | 440 | i915_gem_context_unreference(dctx); |
bdf4fd7e | 441 | dev_priv->mm.aliasing_ppgtt = NULL; |
254f965c BW |
442 | } |
443 | ||
2fa48d8d BW |
444 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
445 | { | |
446 | struct intel_ring_buffer *ring; | |
447 | int ret, i; | |
448 | ||
449 | if (!HAS_HW_CONTEXTS(dev_priv->dev)) | |
450 | return 0; | |
451 | ||
bdf4fd7e BW |
452 | /* This is the only place the aliasing PPGTT gets enabled, which means |
453 | * it has to happen before we bail on reset */ | |
454 | if (dev_priv->mm.aliasing_ppgtt) { | |
455 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
456 | ppgtt->enable(ppgtt); | |
457 | } | |
458 | ||
2fa48d8d BW |
459 | /* FIXME: We should make this work, even in reset */ |
460 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
461 | return 0; | |
462 | ||
463 | BUG_ON(!dev_priv->ring[RCS].default_context); | |
bdf4fd7e | 464 | |
2fa48d8d BW |
465 | for_each_ring(ring, dev_priv, i) { |
466 | ret = do_switch(ring, ring->default_context); | |
467 | if (ret) | |
468 | return ret; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
40521054 BW |
474 | static int context_idr_cleanup(int id, void *p, void *data) |
475 | { | |
73c273eb | 476 | struct i915_hw_context *ctx = p; |
40521054 | 477 | |
0eea67eb BW |
478 | /* Ignore the default context because close will handle it */ |
479 | if (is_default_context(ctx)) | |
480 | return 0; | |
40521054 | 481 | |
dce3271b | 482 | i915_gem_context_unreference(ctx); |
40521054 | 483 | return 0; |
254f965c BW |
484 | } |
485 | ||
e422b888 BW |
486 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
487 | { | |
488 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
c482972a | 489 | struct drm_i915_private *dev_priv = dev->dev_private; |
e422b888 | 490 | |
c482972a BW |
491 | if (!HAS_HW_CONTEXTS(dev)) { |
492 | /* Cheat for hang stats */ | |
493 | file_priv->private_default_ctx = | |
494 | kzalloc(sizeof(struct i915_hw_context), GFP_KERNEL); | |
495 | file_priv->private_default_ctx->vm = &dev_priv->gtt.base; | |
e422b888 | 496 | return 0; |
c482972a | 497 | } |
e422b888 BW |
498 | |
499 | idr_init(&file_priv->context_idr); | |
500 | ||
0eea67eb BW |
501 | mutex_lock(&dev->struct_mutex); |
502 | file_priv->private_default_ctx = | |
503 | i915_gem_create_context(dev, file_priv, false); | |
504 | mutex_unlock(&dev->struct_mutex); | |
505 | ||
506 | if (IS_ERR(file_priv->private_default_ctx)) { | |
507 | idr_destroy(&file_priv->context_idr); | |
508 | return PTR_ERR(file_priv->private_default_ctx); | |
509 | } | |
510 | ||
e422b888 BW |
511 | return 0; |
512 | } | |
513 | ||
254f965c BW |
514 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
515 | { | |
40521054 | 516 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 517 | |
c482972a BW |
518 | if (!HAS_HW_CONTEXTS(dev)) { |
519 | kfree(file_priv->private_default_ctx); | |
e422b888 | 520 | return; |
c482972a | 521 | } |
e422b888 | 522 | |
73c273eb | 523 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
0eea67eb | 524 | i915_gem_context_unreference(file_priv->private_default_ctx); |
40521054 | 525 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
526 | } |
527 | ||
41bde553 | 528 | struct i915_hw_context * |
40521054 BW |
529 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
530 | { | |
41bde553 BW |
531 | if (!HAS_HW_CONTEXTS(file_priv->dev_priv->dev)) |
532 | return file_priv->private_default_ctx; | |
533 | ||
40521054 | 534 | return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); |
254f965c | 535 | } |
e0556841 BW |
536 | |
537 | static inline int | |
538 | mi_set_context(struct intel_ring_buffer *ring, | |
539 | struct i915_hw_context *new_context, | |
540 | u32 hw_flags) | |
541 | { | |
542 | int ret; | |
543 | ||
12b0286f BW |
544 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
545 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
546 | * explicitly, so we rely on the value at ring init, stored in | |
547 | * itlb_before_ctx_switch. | |
548 | */ | |
549 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | |
ac82ea2e | 550 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
551 | if (ret) |
552 | return ret; | |
553 | } | |
554 | ||
e37ec39b | 555 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
556 | if (ret) |
557 | return ret; | |
558 | ||
8693a824 | 559 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */ |
e37ec39b BW |
560 | if (IS_GEN7(ring->dev)) |
561 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
562 | else | |
563 | intel_ring_emit(ring, MI_NOOP); | |
564 | ||
e0556841 BW |
565 | intel_ring_emit(ring, MI_NOOP); |
566 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 567 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) | |
e0556841 BW |
568 | MI_MM_SPACE_GTT | |
569 | MI_SAVE_EXT_STATE_EN | | |
570 | MI_RESTORE_EXT_STATE_EN | | |
571 | hw_flags); | |
572 | /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ | |
573 | intel_ring_emit(ring, MI_NOOP); | |
574 | ||
e37ec39b BW |
575 | if (IS_GEN7(ring->dev)) |
576 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
577 | else | |
578 | intel_ring_emit(ring, MI_NOOP); | |
579 | ||
e0556841 BW |
580 | intel_ring_advance(ring); |
581 | ||
582 | return ret; | |
583 | } | |
584 | ||
67e3d297 BW |
585 | static int do_switch(struct intel_ring_buffer *ring, |
586 | struct i915_hw_context *to) | |
e0556841 | 587 | { |
6f65e29a | 588 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
112522f6 | 589 | struct i915_hw_context *from = ring->last_context; |
e0556841 | 590 | u32 hw_flags = 0; |
3ccfd19d | 591 | int ret, i; |
e0556841 | 592 | |
67e3d297 BW |
593 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
594 | BUG_ON(from->obj == NULL); | |
595 | BUG_ON(!i915_gem_obj_is_pinned(from->obj)); | |
596 | } | |
e0556841 | 597 | |
0009e46c | 598 | if (from == to && from->last_ring == ring && !to->remap_slice) |
9a3b5304 CW |
599 | return 0; |
600 | ||
67e3d297 BW |
601 | if (ring != &dev_priv->ring[RCS]) { |
602 | if (from) | |
603 | i915_gem_context_unreference(from); | |
604 | goto done; | |
605 | } | |
606 | ||
b731d33d BW |
607 | ret = i915_gem_obj_ggtt_pin(to->obj, get_context_alignment(ring->dev), |
608 | false, false); | |
e0556841 BW |
609 | if (ret) |
610 | return ret; | |
611 | ||
acc240d4 DV |
612 | /* |
613 | * Pin can switch back to the default context if we end up calling into | |
614 | * evict_everything - as a last ditch gtt defrag effort that also | |
615 | * switches to the default context. Hence we need to reload from here. | |
616 | */ | |
617 | from = ring->last_context; | |
618 | ||
619 | /* | |
620 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
621 | * that thanks to write = false in this call and us not setting any gpu |
622 | * write domains when putting a context object onto the active list | |
623 | * (when switching away from it), this won't block. | |
acc240d4 DV |
624 | * |
625 | * XXX: We need a real interface to do this instead of trickery. | |
626 | */ | |
d3373a24 CW |
627 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); |
628 | if (ret) { | |
d7f46fc4 | 629 | i915_gem_object_ggtt_unpin(to->obj); |
d3373a24 CW |
630 | return ret; |
631 | } | |
632 | ||
6f65e29a BW |
633 | if (!to->obj->has_global_gtt_mapping) { |
634 | struct i915_vma *vma = i915_gem_obj_to_vma(to->obj, | |
635 | &dev_priv->gtt.base); | |
636 | vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND); | |
637 | } | |
3af7b857 | 638 | |
e0556841 BW |
639 | if (!to->is_initialized || is_default_context(to)) |
640 | hw_flags |= MI_RESTORE_INHIBIT; | |
e0556841 | 641 | |
e0556841 BW |
642 | ret = mi_set_context(ring, to, hw_flags); |
643 | if (ret) { | |
d7f46fc4 | 644 | i915_gem_object_ggtt_unpin(to->obj); |
e0556841 BW |
645 | return ret; |
646 | } | |
647 | ||
3ccfd19d BW |
648 | for (i = 0; i < MAX_L3_SLICES; i++) { |
649 | if (!(to->remap_slice & (1<<i))) | |
650 | continue; | |
651 | ||
652 | ret = i915_gem_l3_remap(ring, i); | |
653 | /* If it failed, try again next round */ | |
654 | if (ret) | |
655 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
656 | else | |
657 | to->remap_slice &= ~(1<<i); | |
658 | } | |
659 | ||
e0556841 BW |
660 | /* The backing object for the context is done after switching to the |
661 | * *next* context. Therefore we cannot retire the previous context until | |
662 | * the next context has already started running. In fact, the below code | |
663 | * is a bit suboptimal because the retiring can occur simply after the | |
664 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
665 | */ | |
112522f6 CW |
666 | if (from != NULL) { |
667 | from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; | |
e2d05a8b | 668 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring); |
e0556841 BW |
669 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
670 | * whole damn pipeline, we don't need to explicitly mark the | |
671 | * object dirty. The only exception is that the context must be | |
672 | * correct in case the object gets swapped out. Ideally we'd be | |
673 | * able to defer doing this until we know the object would be | |
674 | * swapped, but there is no way to do that yet. | |
675 | */ | |
112522f6 CW |
676 | from->obj->dirty = 1; |
677 | BUG_ON(from->obj->ring != ring); | |
678 | ||
c0321e2c | 679 | /* obj is kept alive until the next request by its active ref */ |
d7f46fc4 | 680 | i915_gem_object_ggtt_unpin(from->obj); |
112522f6 | 681 | i915_gem_context_unreference(from); |
e0556841 BW |
682 | } |
683 | ||
67e3d297 | 684 | done: |
112522f6 CW |
685 | i915_gem_context_reference(to); |
686 | ring->last_context = to; | |
e0556841 | 687 | to->is_initialized = true; |
0009e46c | 688 | to->last_ring = ring; |
e0556841 BW |
689 | |
690 | return 0; | |
691 | } | |
692 | ||
693 | /** | |
694 | * i915_switch_context() - perform a GPU context switch. | |
695 | * @ring: ring for which we'll execute the context switch | |
696 | * @file_priv: file_priv associated with the context, may be NULL | |
697 | * @id: context id number | |
e0556841 BW |
698 | * |
699 | * The context life cycle is simple. The context refcount is incremented and | |
700 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
701 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
702 | * object while letting the normal object tracking destroy the backing BO. | |
703 | */ | |
704 | int i915_switch_context(struct intel_ring_buffer *ring, | |
705 | struct drm_file *file, | |
41bde553 | 706 | struct i915_hw_context *to) |
e0556841 BW |
707 | { |
708 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 709 | |
0eea67eb BW |
710 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
711 | ||
41bde553 | 712 | BUG_ON(file && to == NULL); |
e0556841 | 713 | |
c482972a BW |
714 | /* We have the fake context, but don't supports switching. */ |
715 | if (!HAS_HW_CONTEXTS(ring->dev)) | |
716 | return 0; | |
717 | ||
67e3d297 | 718 | return do_switch(ring, to); |
e0556841 | 719 | } |
84624813 BW |
720 | |
721 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
722 | struct drm_file *file) | |
723 | { | |
84624813 BW |
724 | struct drm_i915_gem_context_create *args = data; |
725 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
726 | struct i915_hw_context *ctx; | |
727 | int ret; | |
728 | ||
729 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
730 | return -ENODEV; | |
731 | ||
8245be31 | 732 | if (!HAS_HW_CONTEXTS(dev)) |
5fa8be65 DV |
733 | return -ENODEV; |
734 | ||
84624813 BW |
735 | ret = i915_mutex_lock_interruptible(dev); |
736 | if (ret) | |
737 | return ret; | |
738 | ||
0eea67eb | 739 | ctx = i915_gem_create_context(dev, file_priv, false); |
84624813 | 740 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
741 | if (IS_ERR(ctx)) |
742 | return PTR_ERR(ctx); | |
84624813 BW |
743 | |
744 | args->ctx_id = ctx->id; | |
745 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
746 | ||
be636387 | 747 | return 0; |
84624813 BW |
748 | } |
749 | ||
750 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
751 | struct drm_file *file) | |
752 | { | |
753 | struct drm_i915_gem_context_destroy *args = data; | |
754 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
84624813 BW |
755 | struct i915_hw_context *ctx; |
756 | int ret; | |
757 | ||
758 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
759 | return -ENODEV; | |
760 | ||
0eea67eb BW |
761 | if (args->ctx_id == DEFAULT_CONTEXT_ID) |
762 | return -EPERM; | |
763 | ||
84624813 BW |
764 | ret = i915_mutex_lock_interruptible(dev); |
765 | if (ret) | |
766 | return ret; | |
767 | ||
768 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
769 | if (!ctx) { | |
770 | mutex_unlock(&dev->struct_mutex); | |
0d326013 | 771 | return -ENOENT; |
84624813 BW |
772 | } |
773 | ||
dce3271b MK |
774 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
775 | i915_gem_context_unreference(ctx); | |
84624813 BW |
776 | mutex_unlock(&dev->struct_mutex); |
777 | ||
778 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
779 | return 0; | |
780 | } |