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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
40521054 BW |
93 | /* This is a HW constraint. The value below is the largest known requirement |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
95 | * part. It should be safe to decrease this, but it's more future proof as is. | |
96 | */ | |
b731d33d BW |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
98 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 99 | |
b731d33d BW |
100 | static size_t get_context_alignment(struct drm_device *dev) |
101 | { | |
102 | if (IS_GEN6(dev)) | |
103 | return GEN6_CONTEXT_ALIGN; | |
104 | ||
105 | return GEN7_CONTEXT_ALIGN; | |
106 | } | |
107 | ||
254f965c BW |
108 | static int get_context_size(struct drm_device *dev) |
109 | { | |
110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
111 | int ret; | |
112 | u32 reg; | |
113 | ||
114 | switch (INTEL_INFO(dev)->gen) { | |
115 | case 6: | |
116 | reg = I915_READ(CXT_SIZE); | |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
118 | break; | |
119 | case 7: | |
4f91dd6f | 120 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 121 | if (IS_HASWELL(dev)) |
a0de80a0 | 122 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
123 | else |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 125 | break; |
8897644a BW |
126 | case 8: |
127 | ret = GEN8_CXT_TOTAL_SIZE; | |
128 | break; | |
254f965c BW |
129 | default: |
130 | BUG(); | |
131 | } | |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
dce3271b | 136 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 137 | { |
273497e5 | 138 | struct intel_context *ctx = container_of(ctx_ref, |
ae6c4806 | 139 | typeof(*ctx), ref); |
40521054 | 140 | |
198c974d DCS |
141 | trace_i915_context_free(ctx); |
142 | ||
ae6c4806 | 143 | if (i915.enable_execlists) |
ede7d42b | 144 | intel_lr_context_free(ctx); |
c7c48dfd | 145 | |
ae6c4806 DV |
146 | i915_ppgtt_put(ctx->ppgtt); |
147 | ||
2f295791 BW |
148 | if (ctx->legacy_hw_ctx.rcs_state) |
149 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); | |
c7c48dfd | 150 | list_del(&ctx->link); |
40521054 BW |
151 | kfree(ctx); |
152 | } | |
153 | ||
8c857917 | 154 | struct drm_i915_gem_object * |
aa0c13da OM |
155 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
156 | { | |
157 | struct drm_i915_gem_object *obj; | |
158 | int ret; | |
159 | ||
149c86e7 CW |
160 | obj = i915_gem_object_create_stolen(dev, size); |
161 | if (obj == NULL) | |
162 | obj = i915_gem_alloc_object(dev, size); | |
aa0c13da OM |
163 | if (obj == NULL) |
164 | return ERR_PTR(-ENOMEM); | |
165 | ||
166 | /* | |
167 | * Try to make the context utilize L3 as well as LLC. | |
168 | * | |
169 | * On VLV we don't have L3 controls in the PTEs so we | |
170 | * shouldn't touch the cache level, especially as that | |
171 | * would make the object snooped which might have a | |
172 | * negative performance impact. | |
173 | */ | |
174 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { | |
175 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
176 | /* Failure shouldn't ever happen this early */ | |
177 | if (WARN_ON(ret)) { | |
178 | drm_gem_object_unreference(&obj->base); | |
179 | return ERR_PTR(ret); | |
180 | } | |
181 | } | |
182 | ||
183 | return obj; | |
184 | } | |
185 | ||
273497e5 | 186 | static struct intel_context * |
0eea67eb | 187 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 188 | struct drm_i915_file_private *file_priv) |
40521054 BW |
189 | { |
190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 191 | struct intel_context *ctx; |
c8c470af | 192 | int ret; |
40521054 | 193 | |
f94982b0 | 194 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
195 | if (ctx == NULL) |
196 | return ERR_PTR(-ENOMEM); | |
40521054 | 197 | |
dce3271b | 198 | kref_init(&ctx->ref); |
691e6415 | 199 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 | 200 | |
691e6415 | 201 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
202 | struct drm_i915_gem_object *obj = |
203 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
204 | if (IS_ERR(obj)) { | |
205 | ret = PTR_ERR(obj); | |
4615d4c9 | 206 | goto err_out; |
691e6415 | 207 | } |
ea0c76f8 | 208 | ctx->legacy_hw_ctx.rcs_state = obj; |
691e6415 | 209 | } |
40521054 BW |
210 | |
211 | /* Default context will never have a file_priv */ | |
691e6415 CW |
212 | if (file_priv != NULL) { |
213 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 214 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
215 | if (ret < 0) |
216 | goto err_out; | |
217 | } else | |
821d66dd | 218 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
219 | |
220 | ctx->file_priv = file_priv; | |
821d66dd | 221 | ctx->user_handle = ret; |
3ccfd19d BW |
222 | /* NB: Mark all slices as needing a remap so that when the context first |
223 | * loads it will restore whatever remap state already exists. If there | |
224 | * is no remap info, it will be a NOP. */ | |
225 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 226 | |
676fa572 CW |
227 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
228 | ||
146937e5 | 229 | return ctx; |
40521054 BW |
230 | |
231 | err_out: | |
dce3271b | 232 | i915_gem_context_unreference(ctx); |
146937e5 | 233 | return ERR_PTR(ret); |
40521054 BW |
234 | } |
235 | ||
254f965c BW |
236 | /** |
237 | * The default context needs to exist per ring that uses contexts. It stores the | |
238 | * context state of the GPU for applications that don't utilize HW contexts, as | |
239 | * well as an idle case. | |
240 | */ | |
273497e5 | 241 | static struct intel_context * |
0eea67eb | 242 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 243 | struct drm_i915_file_private *file_priv) |
254f965c | 244 | { |
42c3b603 | 245 | const bool is_global_default_ctx = file_priv == NULL; |
273497e5 | 246 | struct intel_context *ctx; |
bdf4fd7e | 247 | int ret = 0; |
40521054 | 248 | |
b731d33d | 249 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 250 | |
0eea67eb | 251 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 252 | if (IS_ERR(ctx)) |
a45d0f6a | 253 | return ctx; |
40521054 | 254 | |
ea0c76f8 | 255 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
42c3b603 CW |
256 | /* We may need to do things with the shrinker which |
257 | * require us to immediately switch back to the default | |
258 | * context. This can cause a problem as pinning the | |
259 | * default context also requires GTT space which may not | |
260 | * be available. To avoid this we always pin the default | |
261 | * context. | |
262 | */ | |
ea0c76f8 | 263 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
1ec9e26d | 264 | get_context_alignment(dev), 0); |
42c3b603 CW |
265 | if (ret) { |
266 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
267 | goto err_destroy; | |
268 | } | |
269 | } | |
270 | ||
d624d86e | 271 | if (USES_FULL_PPGTT(dev)) { |
4d884705 | 272 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e BW |
273 | |
274 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
275 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
276 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 277 | ret = PTR_ERR(ppgtt); |
42c3b603 | 278 | goto err_unpin; |
ae6c4806 DV |
279 | } |
280 | ||
281 | ctx->ppgtt = ppgtt; | |
282 | } | |
bdf4fd7e | 283 | |
198c974d DCS |
284 | trace_i915_context_create(ctx); |
285 | ||
a45d0f6a | 286 | return ctx; |
9a3b5304 | 287 | |
42c3b603 | 288 | err_unpin: |
ea0c76f8 OM |
289 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
290 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
9a3b5304 | 291 | err_destroy: |
dce3271b | 292 | i915_gem_context_unreference(ctx); |
a45d0f6a | 293 | return ERR_PTR(ret); |
254f965c BW |
294 | } |
295 | ||
acce9ffa BW |
296 | void i915_gem_context_reset(struct drm_device *dev) |
297 | { | |
298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa BW |
299 | int i; |
300 | ||
3e5b6f05 TD |
301 | if (i915.enable_execlists) { |
302 | struct intel_context *ctx; | |
303 | ||
304 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
305 | intel_lr_context_reset(dev, ctx); | |
306 | } | |
307 | ||
ecdb5fd8 | 308 | return; |
3e5b6f05 | 309 | } |
ecdb5fd8 | 310 | |
acce9ffa | 311 | for (i = 0; i < I915_NUM_RINGS; i++) { |
a4872ba6 | 312 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
ea0c76f8 | 313 | struct intel_context *lctx = ring->last_context; |
acce9ffa | 314 | |
6689c167 MA |
315 | if (lctx) { |
316 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) | |
317 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); | |
acce9ffa | 318 | |
6689c167 MA |
319 | i915_gem_context_unreference(lctx); |
320 | ring->last_context = NULL; | |
acce9ffa | 321 | } |
acce9ffa BW |
322 | } |
323 | } | |
324 | ||
8245be31 | 325 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
326 | { |
327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 328 | struct intel_context *ctx; |
a45d0f6a | 329 | int i; |
254f965c | 330 | |
2fa48d8d BW |
331 | /* Init should only be called once per module load. Eventually the |
332 | * restriction on the context_disabled check can be loosened. */ | |
333 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 334 | return 0; |
254f965c | 335 | |
ede7d42b OM |
336 | if (i915.enable_execlists) { |
337 | /* NB: intentionally left blank. We will allocate our own | |
338 | * backing objects as we need them, thank you very much */ | |
339 | dev_priv->hw_context_size = 0; | |
340 | } else if (HAS_HW_CONTEXTS(dev)) { | |
691e6415 CW |
341 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
342 | if (dev_priv->hw_context_size > (1<<20)) { | |
343 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
344 | dev_priv->hw_context_size); | |
345 | dev_priv->hw_context_size = 0; | |
346 | } | |
254f965c BW |
347 | } |
348 | ||
d624d86e | 349 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
350 | if (IS_ERR(ctx)) { |
351 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
352 | PTR_ERR(ctx)); | |
353 | return PTR_ERR(ctx); | |
254f965c BW |
354 | } |
355 | ||
ede7d42b OM |
356 | for (i = 0; i < I915_NUM_RINGS; i++) { |
357 | struct intel_engine_cs *ring = &dev_priv->ring[i]; | |
358 | ||
359 | /* NB: RCS will hold a ref for all rings */ | |
360 | ring->default_context = ctx; | |
ede7d42b | 361 | } |
67e3d297 | 362 | |
ede7d42b OM |
363 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
364 | i915.enable_execlists ? "LR" : | |
365 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 366 | return 0; |
254f965c BW |
367 | } |
368 | ||
369 | void i915_gem_context_fini(struct drm_device *dev) | |
370 | { | |
371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 372 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 373 | int i; |
254f965c | 374 | |
ea0c76f8 | 375 | if (dctx->legacy_hw_ctx.rcs_state) { |
691e6415 CW |
376 | /* The only known way to stop the gpu from accessing the hw context is |
377 | * to reset it. Do this as the very last operation to avoid confusing | |
378 | * other code, leading to spurious errors. */ | |
379 | intel_gpu_reset(dev); | |
380 | ||
381 | /* When default context is created and switched to, base object refcount | |
382 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
383 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
384 | * to default context. So we need to unreference the base object once | |
385 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
386 | * can then free the base object correctly. */ | |
387 | WARN_ON(!dev_priv->ring[RCS].last_context); | |
388 | if (dev_priv->ring[RCS].last_context == dctx) { | |
389 | /* Fake switch to NULL context */ | |
ea0c76f8 OM |
390 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
391 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); | |
691e6415 CW |
392 | i915_gem_context_unreference(dctx); |
393 | dev_priv->ring[RCS].last_context = NULL; | |
394 | } | |
d3b448d9 | 395 | |
ea0c76f8 | 396 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
67e3d297 BW |
397 | } |
398 | ||
399 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 400 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
67e3d297 BW |
401 | |
402 | if (ring->last_context) | |
403 | i915_gem_context_unreference(ring->last_context); | |
404 | ||
405 | ring->default_context = NULL; | |
0009e46c | 406 | ring->last_context = NULL; |
71b76d00 BW |
407 | } |
408 | ||
dce3271b | 409 | i915_gem_context_unreference(dctx); |
254f965c BW |
410 | } |
411 | ||
2fa48d8d BW |
412 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
413 | { | |
a4872ba6 | 414 | struct intel_engine_cs *ring; |
2fa48d8d BW |
415 | int ret, i; |
416 | ||
2fa48d8d | 417 | BUG_ON(!dev_priv->ring[RCS].default_context); |
bdf4fd7e | 418 | |
e7778be1 TD |
419 | if (i915.enable_execlists) { |
420 | for_each_ring(ring, dev_priv, i) { | |
421 | if (ring->init_context) { | |
422 | ret = ring->init_context(ring, | |
423 | ring->default_context); | |
424 | if (ret) { | |
425 | DRM_ERROR("ring init context: %d\n", | |
426 | ret); | |
427 | return ret; | |
428 | } | |
429 | } | |
430 | } | |
ecdb5fd8 | 431 | |
e7778be1 TD |
432 | } else |
433 | for_each_ring(ring, dev_priv, i) { | |
434 | ret = i915_switch_context(ring, ring->default_context); | |
435 | if (ret) | |
436 | return ret; | |
437 | } | |
2fa48d8d BW |
438 | |
439 | return 0; | |
440 | } | |
441 | ||
40521054 BW |
442 | static int context_idr_cleanup(int id, void *p, void *data) |
443 | { | |
273497e5 | 444 | struct intel_context *ctx = p; |
40521054 | 445 | |
dce3271b | 446 | i915_gem_context_unreference(ctx); |
40521054 | 447 | return 0; |
254f965c BW |
448 | } |
449 | ||
e422b888 BW |
450 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
451 | { | |
452 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 453 | struct intel_context *ctx; |
e422b888 BW |
454 | |
455 | idr_init(&file_priv->context_idr); | |
456 | ||
0eea67eb | 457 | mutex_lock(&dev->struct_mutex); |
d624d86e | 458 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
459 | mutex_unlock(&dev->struct_mutex); |
460 | ||
f83d6518 | 461 | if (IS_ERR(ctx)) { |
0eea67eb | 462 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 463 | return PTR_ERR(ctx); |
0eea67eb BW |
464 | } |
465 | ||
e422b888 BW |
466 | return 0; |
467 | } | |
468 | ||
254f965c BW |
469 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
470 | { | |
40521054 | 471 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 472 | |
73c273eb | 473 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 474 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
475 | } |
476 | ||
273497e5 | 477 | struct intel_context * |
40521054 BW |
478 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
479 | { | |
273497e5 | 480 | struct intel_context *ctx; |
72ad5c45 | 481 | |
273497e5 | 482 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
483 | if (!ctx) |
484 | return ERR_PTR(-ENOENT); | |
485 | ||
486 | return ctx; | |
254f965c | 487 | } |
e0556841 BW |
488 | |
489 | static inline int | |
a4872ba6 | 490 | mi_set_context(struct intel_engine_cs *ring, |
273497e5 | 491 | struct intel_context *new_context, |
e0556841 BW |
492 | u32 hw_flags) |
493 | { | |
e80f14b6 | 494 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
495 | const int num_rings = |
496 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
497 | i915_semaphore_is_enabled(ring->dev) ? | |
498 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : | |
499 | 0; | |
500 | int len, i, ret; | |
e0556841 | 501 | |
12b0286f BW |
502 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
503 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
504 | * explicitly, so we rely on the value at ring init, stored in | |
505 | * itlb_before_ctx_switch. | |
506 | */ | |
057f6a8a | 507 | if (IS_GEN6(ring->dev)) { |
ac82ea2e | 508 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
509 | if (ret) |
510 | return ret; | |
511 | } | |
512 | ||
e80f14b6 BW |
513 | /* These flags are for resource streamer on HSW+ */ |
514 | if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8) | |
515 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); | |
516 | ||
2c550183 CW |
517 | |
518 | len = 4; | |
519 | if (INTEL_INFO(ring->dev)->gen >= 7) | |
520 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); | |
521 | ||
522 | ret = intel_ring_begin(ring, len); | |
e0556841 BW |
523 | if (ret) |
524 | return ret; | |
525 | ||
b3f797ac | 526 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
2c550183 | 527 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
e37ec39b | 528 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
529 | if (num_rings) { |
530 | struct intel_engine_cs *signaller; | |
531 | ||
532 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); | |
533 | for_each_ring(signaller, to_i915(ring->dev), i) { | |
534 | if (signaller == ring) | |
535 | continue; | |
536 | ||
537 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); | |
538 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
539 | } | |
540 | } | |
541 | } | |
e37ec39b | 542 | |
e0556841 BW |
543 | intel_ring_emit(ring, MI_NOOP); |
544 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
ea0c76f8 | 545 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) | |
e80f14b6 | 546 | flags); |
2b7e8082 VS |
547 | /* |
548 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
549 | * WaMiSetContext_Hang:snb,ivb,vlv | |
550 | */ | |
e0556841 BW |
551 | intel_ring_emit(ring, MI_NOOP); |
552 | ||
2c550183 CW |
553 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
554 | if (num_rings) { | |
555 | struct intel_engine_cs *signaller; | |
556 | ||
557 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); | |
558 | for_each_ring(signaller, to_i915(ring->dev), i) { | |
559 | if (signaller == ring) | |
560 | continue; | |
561 | ||
562 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); | |
563 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
564 | } | |
565 | } | |
e37ec39b | 566 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 567 | } |
e37ec39b | 568 | |
e0556841 BW |
569 | intel_ring_advance(ring); |
570 | ||
571 | return ret; | |
572 | } | |
573 | ||
317b4e90 BW |
574 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
575 | struct intel_context *from, | |
576 | struct intel_context *to) | |
577 | { | |
563222a7 BW |
578 | if (to->remap_slice) |
579 | return false; | |
580 | ||
9258811c DV |
581 | if (to->ppgtt && from == to && |
582 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) | |
583 | return true; | |
317b4e90 BW |
584 | |
585 | return false; | |
586 | } | |
587 | ||
588 | static bool | |
589 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) | |
590 | { | |
591 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
592 | ||
593 | if (!to->ppgtt) | |
594 | return false; | |
595 | ||
596 | if (INTEL_INFO(ring->dev)->gen < 8) | |
597 | return true; | |
598 | ||
599 | if (ring != &dev_priv->ring[RCS]) | |
600 | return true; | |
601 | ||
602 | return false; | |
603 | } | |
604 | ||
605 | static bool | |
6702cf16 BW |
606 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
607 | u32 hw_flags) | |
317b4e90 BW |
608 | { |
609 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
610 | ||
611 | if (!to->ppgtt) | |
612 | return false; | |
613 | ||
614 | if (!IS_GEN8(ring->dev)) | |
615 | return false; | |
616 | ||
617 | if (ring != &dev_priv->ring[RCS]) | |
618 | return false; | |
619 | ||
6702cf16 | 620 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
621 | return true; |
622 | ||
623 | return false; | |
624 | } | |
625 | ||
a4872ba6 | 626 | static int do_switch(struct intel_engine_cs *ring, |
273497e5 | 627 | struct intel_context *to) |
e0556841 | 628 | { |
6f65e29a | 629 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
273497e5 | 630 | struct intel_context *from = ring->last_context; |
e0556841 | 631 | u32 hw_flags = 0; |
967ab6b1 | 632 | bool uninitialized = false; |
3ccfd19d | 633 | int ret, i; |
e0556841 | 634 | |
67e3d297 | 635 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
ea0c76f8 OM |
636 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
637 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); | |
67e3d297 | 638 | } |
e0556841 | 639 | |
317b4e90 | 640 | if (should_skip_switch(ring, from, to)) |
9a3b5304 CW |
641 | return 0; |
642 | ||
7e0d96bc BW |
643 | /* Trying to pin first makes error handling easier. */ |
644 | if (ring == &dev_priv->ring[RCS]) { | |
ea0c76f8 | 645 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
1ec9e26d | 646 | get_context_alignment(ring->dev), 0); |
7e0d96bc BW |
647 | if (ret) |
648 | return ret; | |
67e3d297 BW |
649 | } |
650 | ||
acc240d4 DV |
651 | /* |
652 | * Pin can switch back to the default context if we end up calling into | |
653 | * evict_everything - as a last ditch gtt defrag effort that also | |
654 | * switches to the default context. Hence we need to reload from here. | |
655 | */ | |
656 | from = ring->last_context; | |
657 | ||
317b4e90 BW |
658 | if (needs_pd_load_pre(ring, to)) { |
659 | /* Older GENs and non render rings still want the load first, | |
660 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
661 | * Register Immediate commands in Ring Buffer before submitting | |
662 | * a context."*/ | |
198c974d | 663 | trace_switch_mm(ring, to); |
6689c167 | 664 | ret = to->ppgtt->switch_mm(to->ppgtt, ring); |
7e0d96bc BW |
665 | if (ret) |
666 | goto unpin_out; | |
563222a7 BW |
667 | |
668 | /* Doing a PD load always reloads the page dirs */ | |
9258811c | 669 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
7e0d96bc BW |
670 | } |
671 | ||
672 | if (ring != &dev_priv->ring[RCS]) { | |
673 | if (from) | |
674 | i915_gem_context_unreference(from); | |
675 | goto done; | |
676 | } | |
677 | ||
acc240d4 DV |
678 | /* |
679 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
680 | * that thanks to write = false in this call and us not setting any gpu |
681 | * write domains when putting a context object onto the active list | |
682 | * (when switching away from it), this won't block. | |
acc240d4 DV |
683 | * |
684 | * XXX: We need a real interface to do this instead of trickery. | |
685 | */ | |
ea0c76f8 | 686 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
7e0d96bc BW |
687 | if (ret) |
688 | goto unpin_out; | |
d3373a24 | 689 | |
6702cf16 | 690 | if (!to->legacy_hw_ctx.initialized) { |
e0556841 | 691 | hw_flags |= MI_RESTORE_INHIBIT; |
6702cf16 BW |
692 | /* NB: If we inhibit the restore, the context is not allowed to |
693 | * die because future work may end up depending on valid address | |
694 | * space. This means we must enforce that a page table load | |
695 | * occur when this occurs. */ | |
696 | } else if (to->ppgtt && | |
9258811c | 697 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
563222a7 | 698 | hw_flags |= MI_FORCE_RESTORE; |
9258811c DV |
699 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
700 | } | |
e0556841 | 701 | |
6702cf16 BW |
702 | /* We should never emit switch_mm more than once */ |
703 | WARN_ON(needs_pd_load_pre(ring, to) && | |
9258811c | 704 | needs_pd_load_post(ring, to, hw_flags)); |
6702cf16 | 705 | |
e0556841 | 706 | ret = mi_set_context(ring, to, hw_flags); |
7e0d96bc BW |
707 | if (ret) |
708 | goto unpin_out; | |
e0556841 | 709 | |
6702cf16 BW |
710 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
711 | * setup, and we do not wish to move them. | |
712 | */ | |
713 | if (needs_pd_load_post(ring, to, hw_flags)) { | |
317b4e90 BW |
714 | trace_switch_mm(ring, to); |
715 | ret = to->ppgtt->switch_mm(to->ppgtt, ring); | |
716 | /* The hardware context switch is emitted, but we haven't | |
717 | * actually changed the state - so it's probably safe to bail | |
718 | * here. Still, let the user know something dangerous has | |
719 | * happened. | |
720 | */ | |
721 | if (ret) { | |
722 | DRM_ERROR("Failed to change address space on context switch\n"); | |
723 | goto unpin_out; | |
724 | } | |
725 | } | |
726 | ||
3ccfd19d BW |
727 | for (i = 0; i < MAX_L3_SLICES; i++) { |
728 | if (!(to->remap_slice & (1<<i))) | |
729 | continue; | |
730 | ||
731 | ret = i915_gem_l3_remap(ring, i); | |
732 | /* If it failed, try again next round */ | |
733 | if (ret) | |
734 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
735 | else | |
736 | to->remap_slice &= ~(1<<i); | |
737 | } | |
738 | ||
e0556841 BW |
739 | /* The backing object for the context is done after switching to the |
740 | * *next* context. Therefore we cannot retire the previous context until | |
741 | * the next context has already started running. In fact, the below code | |
742 | * is a bit suboptimal because the retiring can occur simply after the | |
743 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
744 | */ | |
112522f6 | 745 | if (from != NULL) { |
ea0c76f8 OM |
746 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
747 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), ring); | |
e0556841 BW |
748 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
749 | * whole damn pipeline, we don't need to explicitly mark the | |
750 | * object dirty. The only exception is that the context must be | |
751 | * correct in case the object gets swapped out. Ideally we'd be | |
752 | * able to defer doing this until we know the object would be | |
753 | * swapped, but there is no way to do that yet. | |
754 | */ | |
ea0c76f8 | 755 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
112522f6 | 756 | |
c0321e2c | 757 | /* obj is kept alive until the next request by its active ref */ |
ea0c76f8 | 758 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
112522f6 | 759 | i915_gem_context_unreference(from); |
e0556841 BW |
760 | } |
761 | ||
6702cf16 | 762 | uninitialized = !to->legacy_hw_ctx.initialized; |
ea0c76f8 | 763 | to->legacy_hw_ctx.initialized = true; |
967ab6b1 | 764 | |
67e3d297 | 765 | done: |
112522f6 CW |
766 | i915_gem_context_reference(to); |
767 | ring->last_context = to; | |
e0556841 | 768 | |
967ab6b1 | 769 | if (uninitialized) { |
86d7f238 | 770 | if (ring->init_context) { |
771b9a53 | 771 | ret = ring->init_context(ring, to); |
86d7f238 AS |
772 | if (ret) |
773 | DRM_ERROR("ring init context: %d\n", ret); | |
774 | } | |
46470fc9 MK |
775 | } |
776 | ||
e0556841 | 777 | return 0; |
7e0d96bc BW |
778 | |
779 | unpin_out: | |
780 | if (ring->id == RCS) | |
ea0c76f8 | 781 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
7e0d96bc | 782 | return ret; |
e0556841 BW |
783 | } |
784 | ||
785 | /** | |
786 | * i915_switch_context() - perform a GPU context switch. | |
787 | * @ring: ring for which we'll execute the context switch | |
96a6f0f1 | 788 | * @to: the context to switch to |
e0556841 BW |
789 | * |
790 | * The context life cycle is simple. The context refcount is incremented and | |
791 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 792 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 793 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
794 | * |
795 | * This function should not be used in execlists mode. Instead the context is | |
796 | * switched by writing to the ELSP and requests keep a reference to their | |
797 | * context. | |
e0556841 | 798 | */ |
a4872ba6 | 799 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 | 800 | struct intel_context *to) |
e0556841 BW |
801 | { |
802 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 803 | |
ecdb5fd8 | 804 | WARN_ON(i915.enable_execlists); |
0eea67eb BW |
805 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
806 | ||
ea0c76f8 | 807 | if (to->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
691e6415 CW |
808 | if (to != ring->last_context) { |
809 | i915_gem_context_reference(to); | |
810 | if (ring->last_context) | |
811 | i915_gem_context_unreference(ring->last_context); | |
812 | ring->last_context = to; | |
813 | } | |
c482972a | 814 | return 0; |
a95f6a00 | 815 | } |
c482972a | 816 | |
67e3d297 | 817 | return do_switch(ring, to); |
e0556841 | 818 | } |
84624813 | 819 | |
ec3e9963 | 820 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 821 | { |
ec3e9963 | 822 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
823 | } |
824 | ||
84624813 BW |
825 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
826 | struct drm_file *file) | |
827 | { | |
84624813 BW |
828 | struct drm_i915_gem_context_create *args = data; |
829 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 830 | struct intel_context *ctx; |
84624813 BW |
831 | int ret; |
832 | ||
ec3e9963 | 833 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
834 | return -ENODEV; |
835 | ||
84624813 BW |
836 | ret = i915_mutex_lock_interruptible(dev); |
837 | if (ret) | |
838 | return ret; | |
839 | ||
d624d86e | 840 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 841 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
842 | if (IS_ERR(ctx)) |
843 | return PTR_ERR(ctx); | |
84624813 | 844 | |
821d66dd | 845 | args->ctx_id = ctx->user_handle; |
84624813 BW |
846 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
847 | ||
be636387 | 848 | return 0; |
84624813 BW |
849 | } |
850 | ||
851 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
852 | struct drm_file *file) | |
853 | { | |
854 | struct drm_i915_gem_context_destroy *args = data; | |
855 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 856 | struct intel_context *ctx; |
84624813 BW |
857 | int ret; |
858 | ||
821d66dd | 859 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 860 | return -ENOENT; |
0eea67eb | 861 | |
84624813 BW |
862 | ret = i915_mutex_lock_interruptible(dev); |
863 | if (ret) | |
864 | return ret; | |
865 | ||
866 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 867 | if (IS_ERR(ctx)) { |
84624813 | 868 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 869 | return PTR_ERR(ctx); |
84624813 BW |
870 | } |
871 | ||
821d66dd | 872 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
dce3271b | 873 | i915_gem_context_unreference(ctx); |
84624813 BW |
874 | mutex_unlock(&dev->struct_mutex); |
875 | ||
876 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
877 | return 0; | |
878 | } | |
c9dc0f35 CW |
879 | |
880 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
881 | struct drm_file *file) | |
882 | { | |
883 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
884 | struct drm_i915_gem_context_param *args = data; | |
885 | struct intel_context *ctx; | |
886 | int ret; | |
887 | ||
888 | ret = i915_mutex_lock_interruptible(dev); | |
889 | if (ret) | |
890 | return ret; | |
891 | ||
892 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
893 | if (IS_ERR(ctx)) { | |
894 | mutex_unlock(&dev->struct_mutex); | |
895 | return PTR_ERR(ctx); | |
896 | } | |
897 | ||
898 | args->size = 0; | |
899 | switch (args->param) { | |
900 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
901 | args->value = ctx->hang_stats.ban_period_seconds; | |
902 | break; | |
903 | default: | |
904 | ret = -EINVAL; | |
905 | break; | |
906 | } | |
907 | mutex_unlock(&dev->struct_mutex); | |
908 | ||
909 | return ret; | |
910 | } | |
911 | ||
912 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
913 | struct drm_file *file) | |
914 | { | |
915 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
916 | struct drm_i915_gem_context_param *args = data; | |
917 | struct intel_context *ctx; | |
918 | int ret; | |
919 | ||
920 | ret = i915_mutex_lock_interruptible(dev); | |
921 | if (ret) | |
922 | return ret; | |
923 | ||
924 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
925 | if (IS_ERR(ctx)) { | |
926 | mutex_unlock(&dev->struct_mutex); | |
927 | return PTR_ERR(ctx); | |
928 | } | |
929 | ||
930 | switch (args->param) { | |
931 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
932 | if (args->size) | |
933 | ret = -EINVAL; | |
934 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
935 | !capable(CAP_SYS_ADMIN)) | |
936 | ret = -EPERM; | |
937 | else | |
938 | ctx->hang_stats.ban_period_seconds = args->value; | |
939 | break; | |
940 | default: | |
941 | ret = -EINVAL; | |
942 | break; | |
943 | } | |
944 | mutex_unlock(&dev->struct_mutex); | |
945 | ||
946 | return ret; | |
947 | } |