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drm/i915: Provide a cheap ggtt vma lookup
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1/*
2 * Copyright © 2011-2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 *
26 */
27
28/*
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
35 *
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
46 *
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
51 *
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
63 *
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
73 *
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
508842a0 76 * GPU. The GPU has loaded its state already and has stored away the gtt
254f965c
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77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
80 *
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
85 *
86 */
87
760285e7
DH
88#include <drm/drmP.h>
89#include <drm/i915_drm.h>
254f965c
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90#include "i915_drv.h"
91
40521054
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92/* This is a HW constraint. The value below is the largest known requirement
93 * I've seen in a spec to date, and that was a workaround for a non-shipping
94 * part. It should be safe to decrease this, but it's more future proof as is.
95 */
96#define CONTEXT_ALIGN (64<<10)
97
98static struct i915_hw_context *
99i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
9a3b5304 100static int do_switch(struct i915_hw_context *to);
40521054 101
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102static int get_context_size(struct drm_device *dev)
103{
104 struct drm_i915_private *dev_priv = dev->dev_private;
105 int ret;
106 u32 reg;
107
108 switch (INTEL_INFO(dev)->gen) {
109 case 6:
110 reg = I915_READ(CXT_SIZE);
111 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
112 break;
113 case 7:
4f91dd6f 114 reg = I915_READ(GEN7_CXT_SIZE);
2e4291e0 115 if (IS_HASWELL(dev))
a0de80a0 116 ret = HSW_CXT_TOTAL_SIZE;
2e4291e0
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117 else
118 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
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119 break;
120 default:
121 BUG();
122 }
123
124 return ret;
125}
126
dce3271b 127void i915_gem_context_free(struct kref *ctx_ref)
40521054 128{
dce3271b
MK
129 struct i915_hw_context *ctx = container_of(ctx_ref,
130 typeof(*ctx), ref);
40521054 131
a33afea5 132 list_del(&ctx->link);
40521054
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133 drm_gem_object_unreference(&ctx->obj->base);
134 kfree(ctx);
135}
136
146937e5 137static struct i915_hw_context *
40521054 138create_hw_context(struct drm_device *dev,
146937e5 139 struct drm_i915_file_private *file_priv)
40521054
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140{
141 struct drm_i915_private *dev_priv = dev->dev_private;
146937e5 142 struct i915_hw_context *ctx;
c8c470af 143 int ret;
40521054 144
f94982b0 145 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
146937e5
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146 if (ctx == NULL)
147 return ERR_PTR(-ENOMEM);
40521054 148
dce3271b 149 kref_init(&ctx->ref);
146937e5 150 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
a33afea5 151 INIT_LIST_HEAD(&ctx->link);
146937e5
BW
152 if (ctx->obj == NULL) {
153 kfree(ctx);
40521054 154 DRM_DEBUG_DRIVER("Context object allocated failed\n");
146937e5 155 return ERR_PTR(-ENOMEM);
40521054
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156 }
157
4615d4c9
CW
158 if (INTEL_INFO(dev)->gen >= 7) {
159 ret = i915_gem_object_set_cache_level(ctx->obj,
350ec881 160 I915_CACHE_L3_LLC);
bb036413
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161 /* Failure shouldn't ever happen this early */
162 if (WARN_ON(ret))
4615d4c9
CW
163 goto err_out;
164 }
165
40521054
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166 /* The ring associated with the context object is handled by the normal
167 * object tracking code. We give an initial ring value simple to pass an
168 * assertion in the context switch code.
169 */
146937e5 170 ctx->ring = &dev_priv->ring[RCS];
a33afea5 171 list_add_tail(&ctx->link, &dev_priv->context_list);
40521054
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172
173 /* Default context will never have a file_priv */
174 if (file_priv == NULL)
146937e5 175 return ctx;
40521054 176
c8c470af
TH
177 ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0,
178 GFP_KERNEL);
179 if (ret < 0)
40521054 180 goto err_out;
dce3271b
MK
181
182 ctx->file_priv = file_priv;
c8c470af 183 ctx->id = ret;
3ccfd19d
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184 /* NB: Mark all slices as needing a remap so that when the context first
185 * loads it will restore whatever remap state already exists. If there
186 * is no remap info, it will be a NOP. */
187 ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
40521054 188
146937e5 189 return ctx;
40521054
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190
191err_out:
dce3271b 192 i915_gem_context_unreference(ctx);
146937e5 193 return ERR_PTR(ret);
40521054
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194}
195
e0556841
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196static inline bool is_default_context(struct i915_hw_context *ctx)
197{
198 return (ctx == ctx->ring->default_context);
199}
200
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201/**
202 * The default context needs to exist per ring that uses contexts. It stores the
203 * context state of the GPU for applications that don't utilize HW contexts, as
204 * well as an idle case.
205 */
206static int create_default_context(struct drm_i915_private *dev_priv)
207{
40521054
BW
208 struct i915_hw_context *ctx;
209 int ret;
210
211 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
212
146937e5
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213 ctx = create_hw_context(dev_priv->dev, NULL);
214 if (IS_ERR(ctx))
215 return PTR_ERR(ctx);
40521054
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216
217 /* We may need to do things with the shrinker which require us to
218 * immediately switch back to the default context. This can cause a
219 * problem as pinning the default context also requires GTT space which
220 * may not be available. To avoid this we always pin the
221 * default context.
222 */
146937e5 223 dev_priv->ring[RCS].default_context = ctx;
c37e2204 224 ret = i915_gem_obj_ggtt_pin(ctx->obj, CONTEXT_ALIGN, false, false);
bb036413
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225 if (ret) {
226 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
9a3b5304 227 goto err_destroy;
bb036413 228 }
40521054 229
9a3b5304 230 ret = do_switch(ctx);
bb036413
BW
231 if (ret) {
232 DRM_DEBUG_DRIVER("Switch failed %d\n", ret);
9a3b5304 233 goto err_unpin;
bb036413 234 }
dfabbcb4 235
9a3b5304
CW
236 DRM_DEBUG_DRIVER("Default HW context loaded\n");
237 return 0;
238
239err_unpin:
240 i915_gem_object_unpin(ctx->obj);
241err_destroy:
dce3271b 242 i915_gem_context_unreference(ctx);
40521054 243 return ret;
254f965c
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244}
245
246void i915_gem_context_init(struct drm_device *dev)
247{
248 struct drm_i915_private *dev_priv = dev->dev_private;
254f965c 249
e158c5aa
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250 if (!HAS_HW_CONTEXTS(dev)) {
251 dev_priv->hw_contexts_disabled = true;
bb036413 252 DRM_DEBUG_DRIVER("Disabling HW Contexts; old hardware\n");
254f965c 253 return;
e158c5aa 254 }
254f965c
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255
256 /* If called from reset, or thaw... we've been here already */
40521054
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257 if (dev_priv->hw_contexts_disabled ||
258 dev_priv->ring[RCS].default_context)
254f965c
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259 return;
260
07ea0d85 261 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
254f965c 262
07ea0d85 263 if (dev_priv->hw_context_size > (1<<20)) {
254f965c 264 dev_priv->hw_contexts_disabled = true;
bb036413 265 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
254f965c
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266 return;
267 }
268
269 if (create_default_context(dev_priv)) {
270 dev_priv->hw_contexts_disabled = true;
bb036413 271 DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed\n");
254f965c
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272 return;
273 }
274
275 DRM_DEBUG_DRIVER("HW context support initialized\n");
276}
277
278void i915_gem_context_fini(struct drm_device *dev)
279{
280 struct drm_i915_private *dev_priv = dev->dev_private;
dce3271b 281 struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
254f965c
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282
283 if (dev_priv->hw_contexts_disabled)
284 return;
40521054 285
55a66628
DV
286 /* The only known way to stop the gpu from accessing the hw context is
287 * to reset it. Do this as the very last operation to avoid confusing
288 * other code, leading to spurious errors. */
289 intel_gpu_reset(dev);
290
dce3271b 291 i915_gem_object_unpin(dctx->obj);
168f8366
MK
292
293 /* When default context is created and switched to, base object refcount
294 * will be 2 (+1 from object creation and +1 from do_switch()).
295 * i915_gem_context_fini() will be called after gpu_idle() has switched
296 * to default context. So we need to unreference the base object once
297 * to offset the do_switch part, so that i915_gem_context_unreference()
298 * can then free the base object correctly. */
299 drm_gem_object_unreference(&dctx->obj->base);
dce3271b 300 i915_gem_context_unreference(dctx);
254f965c
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301}
302
40521054
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303static int context_idr_cleanup(int id, void *p, void *data)
304{
73c273eb 305 struct i915_hw_context *ctx = p;
40521054
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306
307 BUG_ON(id == DEFAULT_CONTEXT_ID);
40521054 308
dce3271b 309 i915_gem_context_unreference(ctx);
40521054 310 return 0;
254f965c
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311}
312
c0bb617a 313struct i915_ctx_hang_stats *
11fa3384 314i915_gem_context_get_hang_stats(struct drm_device *dev,
c0bb617a
MK
315 struct drm_file *file,
316 u32 id)
317{
11fa3384 318 struct drm_i915_private *dev_priv = dev->dev_private;
c0bb617a 319 struct drm_i915_file_private *file_priv = file->driver_priv;
11fa3384 320 struct i915_hw_context *ctx;
c0bb617a
MK
321
322 if (id == DEFAULT_CONTEXT_ID)
323 return &file_priv->hang_stats;
324
11fa3384
CW
325 ctx = NULL;
326 if (!dev_priv->hw_contexts_disabled)
327 ctx = i915_gem_context_get(file->driver_priv, id);
328 if (ctx == NULL)
c0bb617a
MK
329 return ERR_PTR(-ENOENT);
330
11fa3384 331 return &ctx->hang_stats;
c0bb617a
MK
332}
333
254f965c
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334void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
335{
40521054 336 struct drm_i915_file_private *file_priv = file->driver_priv;
254f965c 337
40521054 338 mutex_lock(&dev->struct_mutex);
73c273eb 339 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
40521054
BW
340 idr_destroy(&file_priv->context_idr);
341 mutex_unlock(&dev->struct_mutex);
342}
343
e0556841 344static struct i915_hw_context *
40521054
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345i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
346{
347 return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
254f965c 348}
e0556841
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349
350static inline int
351mi_set_context(struct intel_ring_buffer *ring,
352 struct i915_hw_context *new_context,
353 u32 hw_flags)
354{
355 int ret;
356
12b0286f
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357 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
358 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
359 * explicitly, so we rely on the value at ring init, stored in
360 * itlb_before_ctx_switch.
361 */
362 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
ac82ea2e 363 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
12b0286f
BW
364 if (ret)
365 return ret;
366 }
367
e37ec39b 368 ret = intel_ring_begin(ring, 6);
e0556841
BW
369 if (ret)
370 return ret;
371
8693a824 372 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
e37ec39b
BW
373 if (IS_GEN7(ring->dev))
374 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
375 else
376 intel_ring_emit(ring, MI_NOOP);
377
e0556841
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378 intel_ring_emit(ring, MI_NOOP);
379 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 380 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
e0556841
BW
381 MI_MM_SPACE_GTT |
382 MI_SAVE_EXT_STATE_EN |
383 MI_RESTORE_EXT_STATE_EN |
384 hw_flags);
385 /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
386 intel_ring_emit(ring, MI_NOOP);
387
e37ec39b
BW
388 if (IS_GEN7(ring->dev))
389 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
390 else
391 intel_ring_emit(ring, MI_NOOP);
392
e0556841
BW
393 intel_ring_advance(ring);
394
395 return ret;
396}
397
9a3b5304 398static int do_switch(struct i915_hw_context *to)
e0556841 399{
9a3b5304 400 struct intel_ring_buffer *ring = to->ring;
112522f6 401 struct i915_hw_context *from = ring->last_context;
e0556841 402 u32 hw_flags = 0;
3ccfd19d 403 int ret, i;
e0556841 404
112522f6 405 BUG_ON(from != NULL && from->obj != NULL && from->obj->pin_count == 0);
e0556841 406
3ccfd19d 407 if (from == to && !to->remap_slice)
9a3b5304
CW
408 return 0;
409
c37e2204 410 ret = i915_gem_obj_ggtt_pin(to->obj, CONTEXT_ALIGN, false, false);
e0556841
BW
411 if (ret)
412 return ret;
413
d3373a24
CW
414 /* Clear this page out of any CPU caches for coherent swap-in/out. Note
415 * that thanks to write = false in this call and us not setting any gpu
416 * write domains when putting a context object onto the active list
417 * (when switching away from it), this won't block.
418 * XXX: We need a real interface to do this instead of trickery. */
419 ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
420 if (ret) {
421 i915_gem_object_unpin(to->obj);
422 return ret;
423 }
424
3af7b857
DV
425 if (!to->obj->has_global_gtt_mapping)
426 i915_gem_gtt_bind_object(to->obj, to->obj->cache_level);
427
e0556841
BW
428 if (!to->is_initialized || is_default_context(to))
429 hw_flags |= MI_RESTORE_INHIBIT;
e0556841 430
e0556841
BW
431 ret = mi_set_context(ring, to, hw_flags);
432 if (ret) {
433 i915_gem_object_unpin(to->obj);
434 return ret;
435 }
436
3ccfd19d
BW
437 for (i = 0; i < MAX_L3_SLICES; i++) {
438 if (!(to->remap_slice & (1<<i)))
439 continue;
440
441 ret = i915_gem_l3_remap(ring, i);
442 /* If it failed, try again next round */
443 if (ret)
444 DRM_DEBUG_DRIVER("L3 remapping failed\n");
445 else
446 to->remap_slice &= ~(1<<i);
447 }
448
e0556841
BW
449 /* The backing object for the context is done after switching to the
450 * *next* context. Therefore we cannot retire the previous context until
451 * the next context has already started running. In fact, the below code
452 * is a bit suboptimal because the retiring can occur simply after the
453 * MI_SET_CONTEXT instead of when the next seqno has completed.
454 */
112522f6 455 if (from != NULL) {
ca191b13
BW
456 struct drm_i915_private *dev_priv = from->obj->base.dev->dev_private;
457 struct i915_address_space *ggtt = &dev_priv->gtt.base;
112522f6 458 from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
ca191b13 459 list_move_tail(&i915_gem_obj_to_vma(from->obj, ggtt)->mm_list, &ggtt->active_list);
112522f6 460 i915_gem_object_move_to_active(from->obj, ring);
e0556841
BW
461 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
462 * whole damn pipeline, we don't need to explicitly mark the
463 * object dirty. The only exception is that the context must be
464 * correct in case the object gets swapped out. Ideally we'd be
465 * able to defer doing this until we know the object would be
466 * swapped, but there is no way to do that yet.
467 */
112522f6
CW
468 from->obj->dirty = 1;
469 BUG_ON(from->obj->ring != ring);
470
c0321e2c 471 /* obj is kept alive until the next request by its active ref */
112522f6
CW
472 i915_gem_object_unpin(from->obj);
473 i915_gem_context_unreference(from);
e0556841
BW
474 }
475
112522f6
CW
476 i915_gem_context_reference(to);
477 ring->last_context = to;
e0556841
BW
478 to->is_initialized = true;
479
480 return 0;
481}
482
483/**
484 * i915_switch_context() - perform a GPU context switch.
485 * @ring: ring for which we'll execute the context switch
486 * @file_priv: file_priv associated with the context, may be NULL
487 * @id: context id number
488 * @seqno: sequence number by which the new context will be switched to
489 * @flags:
490 *
491 * The context life cycle is simple. The context refcount is incremented and
492 * decremented by 1 and create and destroy. If the context is in use by the GPU,
493 * it will have a refoucnt > 1. This allows us to destroy the context abstract
494 * object while letting the normal object tracking destroy the backing BO.
495 */
496int i915_switch_context(struct intel_ring_buffer *ring,
497 struct drm_file *file,
498 int to_id)
499{
500 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e0556841 501 struct i915_hw_context *to;
e0556841
BW
502
503 if (dev_priv->hw_contexts_disabled)
504 return 0;
505
186507e9
BW
506 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
507
e0556841
BW
508 if (ring != &dev_priv->ring[RCS])
509 return 0;
510
e0556841
BW
511 if (to_id == DEFAULT_CONTEXT_ID) {
512 to = ring->default_context;
513 } else {
9a3b5304
CW
514 if (file == NULL)
515 return -EINVAL;
516
517 to = i915_gem_context_get(file->driver_priv, to_id);
e0556841 518 if (to == NULL)
0d326013 519 return -ENOENT;
e0556841
BW
520 }
521
9a3b5304 522 return do_switch(to);
e0556841 523}
84624813
BW
524
525int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
526 struct drm_file *file)
527{
5fa8be65 528 struct drm_i915_private *dev_priv = dev->dev_private;
84624813
BW
529 struct drm_i915_gem_context_create *args = data;
530 struct drm_i915_file_private *file_priv = file->driver_priv;
531 struct i915_hw_context *ctx;
532 int ret;
533
534 if (!(dev->driver->driver_features & DRIVER_GEM))
535 return -ENODEV;
536
5fa8be65
DV
537 if (dev_priv->hw_contexts_disabled)
538 return -ENODEV;
539
84624813
BW
540 ret = i915_mutex_lock_interruptible(dev);
541 if (ret)
542 return ret;
543
146937e5 544 ctx = create_hw_context(dev, file_priv);
84624813 545 mutex_unlock(&dev->struct_mutex);
be636387
DC
546 if (IS_ERR(ctx))
547 return PTR_ERR(ctx);
84624813
BW
548
549 args->ctx_id = ctx->id;
550 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
551
be636387 552 return 0;
84624813
BW
553}
554
555int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
556 struct drm_file *file)
557{
558 struct drm_i915_gem_context_destroy *args = data;
559 struct drm_i915_file_private *file_priv = file->driver_priv;
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560 struct i915_hw_context *ctx;
561 int ret;
562
563 if (!(dev->driver->driver_features & DRIVER_GEM))
564 return -ENODEV;
565
566 ret = i915_mutex_lock_interruptible(dev);
567 if (ret)
568 return ret;
569
570 ctx = i915_gem_context_get(file_priv, args->ctx_id);
571 if (!ctx) {
572 mutex_unlock(&dev->struct_mutex);
0d326013 573 return -ENOENT;
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574 }
575
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576 idr_remove(&ctx->file_priv->context_idr, ctx->id);
577 i915_gem_context_unreference(ctx);
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578 mutex_unlock(&dev->struct_mutex);
579
580 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
581 return 0;
582}