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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
b2e862d0 CW |
93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
94 | ||
40521054 BW |
95 | /* This is a HW constraint. The value below is the largest known requirement |
96 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
97 | * part. It should be safe to decrease this, but it's more future proof as is. | |
98 | */ | |
b731d33d BW |
99 | #define GEN6_CONTEXT_ALIGN (64<<10) |
100 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 101 | |
c033666a | 102 | static size_t get_context_alignment(struct drm_i915_private *dev_priv) |
b731d33d | 103 | { |
c033666a | 104 | if (IS_GEN6(dev_priv)) |
b731d33d BW |
105 | return GEN6_CONTEXT_ALIGN; |
106 | ||
107 | return GEN7_CONTEXT_ALIGN; | |
108 | } | |
109 | ||
c033666a | 110 | static int get_context_size(struct drm_i915_private *dev_priv) |
254f965c | 111 | { |
254f965c BW |
112 | int ret; |
113 | u32 reg; | |
114 | ||
c033666a | 115 | switch (INTEL_GEN(dev_priv)) { |
254f965c BW |
116 | case 6: |
117 | reg = I915_READ(CXT_SIZE); | |
118 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
119 | break; | |
120 | case 7: | |
4f91dd6f | 121 | reg = I915_READ(GEN7_CXT_SIZE); |
c033666a | 122 | if (IS_HASWELL(dev_priv)) |
a0de80a0 | 123 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
124 | else |
125 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 126 | break; |
8897644a BW |
127 | case 8: |
128 | ret = GEN8_CXT_TOTAL_SIZE; | |
129 | break; | |
254f965c BW |
130 | default: |
131 | BUG(); | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
e2efd130 | 137 | static void i915_gem_context_clean(struct i915_gem_context *ctx) |
e9f24d5f TU |
138 | { |
139 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; | |
140 | struct i915_vma *vma, *next; | |
141 | ||
61fb5881 | 142 | if (!ppgtt) |
e9f24d5f TU |
143 | return; |
144 | ||
e9f24d5f | 145 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
1c7f4bca | 146 | vm_link) { |
e9f24d5f TU |
147 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
148 | break; | |
149 | } | |
150 | } | |
151 | ||
dce3271b | 152 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 153 | { |
e2efd130 | 154 | struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
bca44d80 | 155 | int i; |
40521054 | 156 | |
91c8a326 | 157 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
198c974d DCS |
158 | trace_i915_context_free(ctx); |
159 | ||
e9f24d5f TU |
160 | /* |
161 | * This context is going away and we need to remove all VMAs still | |
162 | * around. This is to handle imported shared objects for which | |
163 | * destructor did not run when their handles were closed. | |
164 | */ | |
165 | i915_gem_context_clean(ctx); | |
166 | ||
ae6c4806 DV |
167 | i915_ppgtt_put(ctx->ppgtt); |
168 | ||
bca44d80 CW |
169 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
170 | struct intel_context *ce = &ctx->engine[i]; | |
171 | ||
172 | if (!ce->state) | |
173 | continue; | |
174 | ||
175 | WARN_ON(ce->pin_count); | |
176 | if (ce->ringbuf) | |
177 | intel_ringbuffer_free(ce->ringbuf); | |
178 | ||
179 | drm_gem_object_unreference(&ce->state->base); | |
180 | } | |
181 | ||
c7c48dfd | 182 | list_del(&ctx->link); |
5d1808ec CW |
183 | |
184 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); | |
40521054 BW |
185 | kfree(ctx); |
186 | } | |
187 | ||
8c857917 | 188 | struct drm_i915_gem_object * |
aa0c13da OM |
189 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
190 | { | |
191 | struct drm_i915_gem_object *obj; | |
192 | int ret; | |
193 | ||
499f2697 CW |
194 | lockdep_assert_held(&dev->struct_mutex); |
195 | ||
d37cd8a8 | 196 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
197 | if (IS_ERR(obj)) |
198 | return obj; | |
aa0c13da OM |
199 | |
200 | /* | |
201 | * Try to make the context utilize L3 as well as LLC. | |
202 | * | |
203 | * On VLV we don't have L3 controls in the PTEs so we | |
204 | * shouldn't touch the cache level, especially as that | |
205 | * would make the object snooped which might have a | |
206 | * negative performance impact. | |
4d3e904c WB |
207 | * |
208 | * Snooping is required on non-llc platforms in execlist | |
209 | * mode, but since all GGTT accesses use PAT entry 0 we | |
210 | * get snooping anyway regardless of cache_level. | |
211 | * | |
212 | * This is only applicable for Ivy Bridge devices since | |
213 | * later platforms don't have L3 control bits in the PTE. | |
aa0c13da | 214 | */ |
4d3e904c | 215 | if (IS_IVYBRIDGE(dev)) { |
aa0c13da OM |
216 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
217 | /* Failure shouldn't ever happen this early */ | |
218 | if (WARN_ON(ret)) { | |
219 | drm_gem_object_unreference(&obj->base); | |
220 | return ERR_PTR(ret); | |
221 | } | |
222 | } | |
223 | ||
224 | return obj; | |
225 | } | |
226 | ||
5d1808ec CW |
227 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
228 | { | |
229 | int ret; | |
230 | ||
231 | ret = ida_simple_get(&dev_priv->context_hw_ida, | |
232 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
233 | if (ret < 0) { | |
234 | /* Contexts are only released when no longer active. | |
235 | * Flush any pending retires to hopefully release some | |
236 | * stale contexts and try again. | |
237 | */ | |
c033666a | 238 | i915_gem_retire_requests(dev_priv); |
5d1808ec CW |
239 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
240 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
241 | if (ret < 0) | |
242 | return ret; | |
243 | } | |
244 | ||
245 | *out = ret; | |
246 | return 0; | |
247 | } | |
248 | ||
e2efd130 | 249 | static struct i915_gem_context * |
0eea67eb | 250 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 251 | struct drm_i915_file_private *file_priv) |
40521054 | 252 | { |
fac5e23e | 253 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 254 | struct i915_gem_context *ctx; |
c8c470af | 255 | int ret; |
40521054 | 256 | |
f94982b0 | 257 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
258 | if (ctx == NULL) |
259 | return ERR_PTR(-ENOMEM); | |
40521054 | 260 | |
5d1808ec CW |
261 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
262 | if (ret) { | |
263 | kfree(ctx); | |
264 | return ERR_PTR(ret); | |
265 | } | |
266 | ||
dce3271b | 267 | kref_init(&ctx->ref); |
691e6415 | 268 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 269 | ctx->i915 = dev_priv; |
40521054 | 270 | |
0cb26a8e CW |
271 | ctx->ggtt_alignment = get_context_alignment(dev_priv); |
272 | ||
691e6415 | 273 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
274 | struct drm_i915_gem_object *obj = |
275 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
276 | if (IS_ERR(obj)) { | |
277 | ret = PTR_ERR(obj); | |
4615d4c9 | 278 | goto err_out; |
691e6415 | 279 | } |
bca44d80 | 280 | ctx->engine[RCS].state = obj; |
691e6415 | 281 | } |
40521054 BW |
282 | |
283 | /* Default context will never have a file_priv */ | |
691e6415 CW |
284 | if (file_priv != NULL) { |
285 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 286 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
287 | if (ret < 0) |
288 | goto err_out; | |
289 | } else | |
821d66dd | 290 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
291 | |
292 | ctx->file_priv = file_priv; | |
821d66dd | 293 | ctx->user_handle = ret; |
3ccfd19d BW |
294 | /* NB: Mark all slices as needing a remap so that when the context first |
295 | * loads it will restore whatever remap state already exists. If there | |
296 | * is no remap info, it will be a NOP. */ | |
b2e862d0 | 297 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
40521054 | 298 | |
676fa572 | 299 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
bcd794c2 | 300 | ctx->ring_size = 4 * PAGE_SIZE; |
c01fc532 ZW |
301 | ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) << |
302 | GEN8_CTX_ADDRESSING_MODE_SHIFT; | |
3c7ba635 | 303 | ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier); |
676fa572 | 304 | |
146937e5 | 305 | return ctx; |
40521054 BW |
306 | |
307 | err_out: | |
dce3271b | 308 | i915_gem_context_unreference(ctx); |
146937e5 | 309 | return ERR_PTR(ret); |
40521054 BW |
310 | } |
311 | ||
254f965c BW |
312 | /** |
313 | * The default context needs to exist per ring that uses contexts. It stores the | |
314 | * context state of the GPU for applications that don't utilize HW contexts, as | |
315 | * well as an idle case. | |
316 | */ | |
e2efd130 | 317 | static struct i915_gem_context * |
0eea67eb | 318 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 319 | struct drm_i915_file_private *file_priv) |
254f965c | 320 | { |
e2efd130 | 321 | struct i915_gem_context *ctx; |
40521054 | 322 | |
499f2697 | 323 | lockdep_assert_held(&dev->struct_mutex); |
40521054 | 324 | |
0eea67eb | 325 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 326 | if (IS_ERR(ctx)) |
a45d0f6a | 327 | return ctx; |
40521054 | 328 | |
d624d86e | 329 | if (USES_FULL_PPGTT(dev)) { |
4d884705 | 330 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e | 331 | |
c6aab916 | 332 | if (IS_ERR(ppgtt)) { |
0eea67eb BW |
333 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
334 | PTR_ERR(ppgtt)); | |
c6aab916 CW |
335 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
336 | i915_gem_context_unreference(ctx); | |
337 | return ERR_CAST(ppgtt); | |
ae6c4806 DV |
338 | } |
339 | ||
340 | ctx->ppgtt = ppgtt; | |
341 | } | |
bdf4fd7e | 342 | |
198c974d DCS |
343 | trace_i915_context_create(ctx); |
344 | ||
a45d0f6a | 345 | return ctx; |
254f965c BW |
346 | } |
347 | ||
c8c35799 ZW |
348 | /** |
349 | * i915_gem_context_create_gvt - create a GVT GEM context | |
350 | * @dev: drm device * | |
351 | * | |
352 | * This function is used to create a GVT specific GEM context. | |
353 | * | |
354 | * Returns: | |
355 | * pointer to i915_gem_context on success, error pointer if failed | |
356 | * | |
357 | */ | |
358 | struct i915_gem_context * | |
359 | i915_gem_context_create_gvt(struct drm_device *dev) | |
360 | { | |
361 | struct i915_gem_context *ctx; | |
362 | int ret; | |
363 | ||
364 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
365 | return ERR_PTR(-ENODEV); | |
366 | ||
367 | ret = i915_mutex_lock_interruptible(dev); | |
368 | if (ret) | |
369 | return ERR_PTR(ret); | |
370 | ||
371 | ctx = i915_gem_create_context(dev, NULL); | |
372 | if (IS_ERR(ctx)) | |
373 | goto out; | |
374 | ||
375 | ctx->execlists_force_single_submission = true; | |
376 | ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */ | |
377 | out: | |
378 | mutex_unlock(&dev->struct_mutex); | |
379 | return ctx; | |
380 | } | |
381 | ||
e2efd130 | 382 | static void i915_gem_context_unpin(struct i915_gem_context *ctx, |
a0b4a6a8 TU |
383 | struct intel_engine_cs *engine) |
384 | { | |
f4e2dece TU |
385 | if (i915.enable_execlists) { |
386 | intel_lr_context_unpin(ctx, engine); | |
387 | } else { | |
bca44d80 CW |
388 | struct intel_context *ce = &ctx->engine[engine->id]; |
389 | ||
390 | if (ce->state) | |
391 | i915_gem_object_ggtt_unpin(ce->state); | |
392 | ||
f4e2dece TU |
393 | i915_gem_context_unreference(ctx); |
394 | } | |
a0b4a6a8 TU |
395 | } |
396 | ||
acce9ffa BW |
397 | void i915_gem_context_reset(struct drm_device *dev) |
398 | { | |
fac5e23e | 399 | struct drm_i915_private *dev_priv = to_i915(dev); |
acce9ffa | 400 | |
499f2697 CW |
401 | lockdep_assert_held(&dev->struct_mutex); |
402 | ||
3e5b6f05 | 403 | if (i915.enable_execlists) { |
e2efd130 | 404 | struct i915_gem_context *ctx; |
3e5b6f05 | 405 | |
a0b4a6a8 | 406 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
7d774cac | 407 | intel_lr_context_reset(dev_priv, ctx); |
3e5b6f05 | 408 | } |
ecdb5fd8 | 409 | |
b2e862d0 | 410 | i915_gem_context_lost(dev_priv); |
acce9ffa BW |
411 | } |
412 | ||
8245be31 | 413 | int i915_gem_context_init(struct drm_device *dev) |
254f965c | 414 | { |
fac5e23e | 415 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 416 | struct i915_gem_context *ctx; |
254f965c | 417 | |
2fa48d8d BW |
418 | /* Init should only be called once per module load. Eventually the |
419 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 420 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 421 | return 0; |
254f965c | 422 | |
c033666a CW |
423 | if (intel_vgpu_active(dev_priv) && |
424 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { | |
a0bd6c31 ZL |
425 | if (!i915.enable_execlists) { |
426 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
427 | return -EINVAL; | |
428 | } | |
429 | } | |
430 | ||
5d1808ec CW |
431 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
432 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); | |
433 | ida_init(&dev_priv->context_hw_ida); | |
434 | ||
ede7d42b OM |
435 | if (i915.enable_execlists) { |
436 | /* NB: intentionally left blank. We will allocate our own | |
437 | * backing objects as we need them, thank you very much */ | |
438 | dev_priv->hw_context_size = 0; | |
c033666a CW |
439 | } else if (HAS_HW_CONTEXTS(dev_priv)) { |
440 | dev_priv->hw_context_size = | |
441 | round_up(get_context_size(dev_priv), 4096); | |
691e6415 CW |
442 | if (dev_priv->hw_context_size > (1<<20)) { |
443 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
444 | dev_priv->hw_context_size); | |
445 | dev_priv->hw_context_size = 0; | |
446 | } | |
254f965c BW |
447 | } |
448 | ||
d624d86e | 449 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
450 | if (IS_ERR(ctx)) { |
451 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
452 | PTR_ERR(ctx)); | |
453 | return PTR_ERR(ctx); | |
254f965c BW |
454 | } |
455 | ||
ed54c1a1 | 456 | dev_priv->kernel_context = ctx; |
67e3d297 | 457 | |
ede7d42b OM |
458 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
459 | i915.enable_execlists ? "LR" : | |
460 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 461 | return 0; |
254f965c BW |
462 | } |
463 | ||
b2e862d0 CW |
464 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
465 | { | |
466 | struct intel_engine_cs *engine; | |
467 | ||
91c8a326 | 468 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 469 | |
b2e862d0 | 470 | for_each_engine(engine, dev_priv) { |
bca44d80 CW |
471 | if (engine->last_context) { |
472 | i915_gem_context_unpin(engine->last_context, engine); | |
473 | engine->last_context = NULL; | |
474 | } | |
b2e862d0 CW |
475 | } |
476 | ||
c7c3c07d CW |
477 | /* Force the GPU state to be restored on enabling */ |
478 | if (!i915.enable_execlists) { | |
a168b2d8 CW |
479 | struct i915_gem_context *ctx; |
480 | ||
481 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
482 | if (!i915_gem_context_is_default(ctx)) | |
483 | continue; | |
484 | ||
485 | for_each_engine(engine, dev_priv) | |
486 | ctx->engine[engine->id].initialised = false; | |
487 | ||
488 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); | |
489 | } | |
490 | ||
c7c3c07d CW |
491 | for_each_engine(engine, dev_priv) { |
492 | struct intel_context *kce = | |
493 | &dev_priv->kernel_context->engine[engine->id]; | |
494 | ||
495 | kce->initialised = true; | |
496 | } | |
497 | } | |
b2e862d0 CW |
498 | } |
499 | ||
254f965c BW |
500 | void i915_gem_context_fini(struct drm_device *dev) |
501 | { | |
fac5e23e | 502 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 503 | struct i915_gem_context *dctx = dev_priv->kernel_context; |
b2e862d0 | 504 | |
499f2697 CW |
505 | lockdep_assert_held(&dev->struct_mutex); |
506 | ||
dce3271b | 507 | i915_gem_context_unreference(dctx); |
ed54c1a1 | 508 | dev_priv->kernel_context = NULL; |
5d1808ec CW |
509 | |
510 | ida_destroy(&dev_priv->context_hw_ida); | |
254f965c BW |
511 | } |
512 | ||
40521054 BW |
513 | static int context_idr_cleanup(int id, void *p, void *data) |
514 | { | |
e2efd130 | 515 | struct i915_gem_context *ctx = p; |
40521054 | 516 | |
d28b99ab | 517 | ctx->file_priv = ERR_PTR(-EBADF); |
dce3271b | 518 | i915_gem_context_unreference(ctx); |
40521054 | 519 | return 0; |
254f965c BW |
520 | } |
521 | ||
e422b888 BW |
522 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
523 | { | |
524 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 525 | struct i915_gem_context *ctx; |
e422b888 BW |
526 | |
527 | idr_init(&file_priv->context_idr); | |
528 | ||
0eea67eb | 529 | mutex_lock(&dev->struct_mutex); |
d624d86e | 530 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
531 | mutex_unlock(&dev->struct_mutex); |
532 | ||
f83d6518 | 533 | if (IS_ERR(ctx)) { |
0eea67eb | 534 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 535 | return PTR_ERR(ctx); |
0eea67eb BW |
536 | } |
537 | ||
e422b888 BW |
538 | return 0; |
539 | } | |
540 | ||
254f965c BW |
541 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
542 | { | |
40521054 | 543 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 544 | |
499f2697 CW |
545 | lockdep_assert_held(&dev->struct_mutex); |
546 | ||
73c273eb | 547 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 548 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
549 | } |
550 | ||
e0556841 | 551 | static inline int |
1d719cda | 552 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 553 | { |
c033666a | 554 | struct drm_i915_private *dev_priv = req->i915; |
4a570db5 | 555 | struct intel_engine_cs *engine = req->engine; |
e80f14b6 | 556 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
557 | const int num_rings = |
558 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
c033666a CW |
559 | i915_semaphore_is_enabled(dev_priv) ? |
560 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 : | |
2c550183 | 561 | 0; |
b4ac5afc | 562 | int len, ret; |
e0556841 | 563 | |
12b0286f BW |
564 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
565 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
566 | * explicitly, so we rely on the value at ring init, stored in | |
567 | * itlb_before_ctx_switch. | |
568 | */ | |
c033666a | 569 | if (IS_GEN6(dev_priv)) { |
e2f80391 | 570 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
571 | if (ret) |
572 | return ret; | |
573 | } | |
574 | ||
e80f14b6 | 575 | /* These flags are for resource streamer on HSW+ */ |
c033666a | 576 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
4c436d55 | 577 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
c033666a | 578 | else if (INTEL_GEN(dev_priv) < 8) |
e80f14b6 BW |
579 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
580 | ||
2c550183 CW |
581 | |
582 | len = 4; | |
c033666a | 583 | if (INTEL_GEN(dev_priv) >= 7) |
e9135c4f | 584 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
2c550183 | 585 | |
5fb9de1a | 586 | ret = intel_ring_begin(req, len); |
e0556841 BW |
587 | if (ret) |
588 | return ret; | |
589 | ||
b3f797ac | 590 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
c033666a | 591 | if (INTEL_GEN(dev_priv) >= 7) { |
e2f80391 | 592 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
593 | if (num_rings) { |
594 | struct intel_engine_cs *signaller; | |
595 | ||
e2f80391 TU |
596 | intel_ring_emit(engine, |
597 | MI_LOAD_REGISTER_IMM(num_rings)); | |
c033666a | 598 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 599 | if (signaller == engine) |
2c550183 CW |
600 | continue; |
601 | ||
e2f80391 TU |
602 | intel_ring_emit_reg(engine, |
603 | RING_PSMI_CTL(signaller->mmio_base)); | |
604 | intel_ring_emit(engine, | |
605 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 CW |
606 | } |
607 | } | |
608 | } | |
e37ec39b | 609 | |
e2f80391 TU |
610 | intel_ring_emit(engine, MI_NOOP); |
611 | intel_ring_emit(engine, MI_SET_CONTEXT); | |
612 | intel_ring_emit(engine, | |
bca44d80 | 613 | i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) | |
e80f14b6 | 614 | flags); |
2b7e8082 VS |
615 | /* |
616 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
617 | * WaMiSetContext_Hang:snb,ivb,vlv | |
618 | */ | |
e2f80391 | 619 | intel_ring_emit(engine, MI_NOOP); |
e0556841 | 620 | |
c033666a | 621 | if (INTEL_GEN(dev_priv) >= 7) { |
2c550183 CW |
622 | if (num_rings) { |
623 | struct intel_engine_cs *signaller; | |
e9135c4f | 624 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
2c550183 | 625 | |
e2f80391 TU |
626 | intel_ring_emit(engine, |
627 | MI_LOAD_REGISTER_IMM(num_rings)); | |
c033666a | 628 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 629 | if (signaller == engine) |
2c550183 CW |
630 | continue; |
631 | ||
e9135c4f CW |
632 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
633 | intel_ring_emit_reg(engine, last_reg); | |
e2f80391 TU |
634 | intel_ring_emit(engine, |
635 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 | 636 | } |
e9135c4f CW |
637 | |
638 | /* Insert a delay before the next switch! */ | |
639 | intel_ring_emit(engine, | |
640 | MI_STORE_REGISTER_MEM | | |
641 | MI_SRM_LRM_GLOBAL_GTT); | |
642 | intel_ring_emit_reg(engine, last_reg); | |
643 | intel_ring_emit(engine, engine->scratch.gtt_offset); | |
644 | intel_ring_emit(engine, MI_NOOP); | |
2c550183 | 645 | } |
e2f80391 | 646 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 647 | } |
e37ec39b | 648 | |
e2f80391 | 649 | intel_ring_advance(engine); |
e0556841 BW |
650 | |
651 | return ret; | |
652 | } | |
653 | ||
d200cda6 | 654 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
b0ebde39 | 655 | { |
ff55b5e8 | 656 | u32 *remap_info = req->i915->l3_parity.remap_info[slice]; |
b0ebde39 | 657 | struct intel_engine_cs *engine = req->engine; |
b0ebde39 CW |
658 | int i, ret; |
659 | ||
ff55b5e8 | 660 | if (!remap_info) |
b0ebde39 CW |
661 | return 0; |
662 | ||
ff55b5e8 | 663 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
b0ebde39 CW |
664 | if (ret) |
665 | return ret; | |
666 | ||
667 | /* | |
668 | * Note: We do not worry about the concurrent register cacheline hang | |
669 | * here because no other code should access these registers other than | |
670 | * at initialization time. | |
671 | */ | |
ff55b5e8 CW |
672 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); |
673 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
b0ebde39 CW |
674 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); |
675 | intel_ring_emit(engine, remap_info[i]); | |
676 | } | |
ff55b5e8 | 677 | intel_ring_emit(engine, MI_NOOP); |
b0ebde39 CW |
678 | intel_ring_advance(engine); |
679 | ||
ff55b5e8 | 680 | return 0; |
b0ebde39 CW |
681 | } |
682 | ||
f9326be5 CW |
683 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
684 | struct intel_engine_cs *engine, | |
e2efd130 | 685 | struct i915_gem_context *to) |
317b4e90 | 686 | { |
563222a7 BW |
687 | if (to->remap_slice) |
688 | return false; | |
689 | ||
bca44d80 | 690 | if (!to->engine[RCS].initialised) |
fcb5106d CW |
691 | return false; |
692 | ||
f9326be5 | 693 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
fcb5106d | 694 | return false; |
317b4e90 | 695 | |
fcb5106d | 696 | return to == engine->last_context; |
317b4e90 BW |
697 | } |
698 | ||
699 | static bool | |
f9326be5 CW |
700 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
701 | struct intel_engine_cs *engine, | |
e2efd130 | 702 | struct i915_gem_context *to) |
317b4e90 | 703 | { |
f9326be5 | 704 | if (!ppgtt) |
317b4e90 BW |
705 | return false; |
706 | ||
f9326be5 CW |
707 | /* Always load the ppgtt on first use */ |
708 | if (!engine->last_context) | |
709 | return true; | |
710 | ||
711 | /* Same context without new entries, skip */ | |
e1a8daa2 | 712 | if (engine->last_context == to && |
f9326be5 | 713 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
e1a8daa2 CW |
714 | return false; |
715 | ||
716 | if (engine->id != RCS) | |
317b4e90 BW |
717 | return true; |
718 | ||
c033666a | 719 | if (INTEL_GEN(engine->i915) < 8) |
317b4e90 BW |
720 | return true; |
721 | ||
722 | return false; | |
723 | } | |
724 | ||
725 | static bool | |
f9326be5 | 726 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
e2efd130 | 727 | struct i915_gem_context *to, |
f9326be5 | 728 | u32 hw_flags) |
317b4e90 | 729 | { |
f9326be5 | 730 | if (!ppgtt) |
317b4e90 BW |
731 | return false; |
732 | ||
fcb5106d | 733 | if (!IS_GEN8(to->i915)) |
317b4e90 BW |
734 | return false; |
735 | ||
6702cf16 | 736 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
737 | return true; |
738 | ||
739 | return false; | |
740 | } | |
741 | ||
e1a8daa2 | 742 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
e0556841 | 743 | { |
e2efd130 | 744 | struct i915_gem_context *to = req->ctx; |
4a570db5 | 745 | struct intel_engine_cs *engine = req->engine; |
f9326be5 | 746 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
e2efd130 | 747 | struct i915_gem_context *from; |
fcb5106d | 748 | u32 hw_flags; |
3ccfd19d | 749 | int ret, i; |
e0556841 | 750 | |
f9326be5 | 751 | if (skip_rcs_switch(ppgtt, engine, to)) |
9a3b5304 CW |
752 | return 0; |
753 | ||
7e0d96bc | 754 | /* Trying to pin first makes error handling easier. */ |
bca44d80 | 755 | ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state, |
0cb26a8e | 756 | to->ggtt_alignment, |
e1a8daa2 CW |
757 | 0); |
758 | if (ret) | |
759 | return ret; | |
67e3d297 | 760 | |
acc240d4 DV |
761 | /* |
762 | * Pin can switch back to the default context if we end up calling into | |
763 | * evict_everything - as a last ditch gtt defrag effort that also | |
764 | * switches to the default context. Hence we need to reload from here. | |
fcb5106d CW |
765 | * |
766 | * XXX: Doing so is painfully broken! | |
acc240d4 | 767 | */ |
e2f80391 | 768 | from = engine->last_context; |
acc240d4 DV |
769 | |
770 | /* | |
771 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
772 | * that thanks to write = false in this call and us not setting any gpu |
773 | * write domains when putting a context object onto the active list | |
774 | * (when switching away from it), this won't block. | |
acc240d4 DV |
775 | * |
776 | * XXX: We need a real interface to do this instead of trickery. | |
777 | */ | |
bca44d80 | 778 | ret = i915_gem_object_set_to_gtt_domain(to->engine[RCS].state, false); |
7e0d96bc BW |
779 | if (ret) |
780 | goto unpin_out; | |
d3373a24 | 781 | |
f9326be5 | 782 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
fcb5106d CW |
783 | /* Older GENs and non render rings still want the load first, |
784 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
785 | * Register Immediate commands in Ring Buffer before submitting | |
786 | * a context."*/ | |
787 | trace_switch_mm(engine, to); | |
f9326be5 | 788 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
789 | if (ret) |
790 | goto unpin_out; | |
791 | } | |
792 | ||
bca44d80 | 793 | if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) |
6702cf16 BW |
794 | /* NB: If we inhibit the restore, the context is not allowed to |
795 | * die because future work may end up depending on valid address | |
796 | * space. This means we must enforce that a page table load | |
797 | * occur when this occurs. */ | |
fcb5106d | 798 | hw_flags = MI_RESTORE_INHIBIT; |
f9326be5 | 799 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
fcb5106d CW |
800 | hw_flags = MI_FORCE_RESTORE; |
801 | else | |
802 | hw_flags = 0; | |
e0556841 | 803 | |
fcb5106d CW |
804 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
805 | ret = mi_set_context(req, hw_flags); | |
3ccfd19d | 806 | if (ret) |
fcb5106d | 807 | goto unpin_out; |
3ccfd19d BW |
808 | } |
809 | ||
e0556841 BW |
810 | /* The backing object for the context is done after switching to the |
811 | * *next* context. Therefore we cannot retire the previous context until | |
812 | * the next context has already started running. In fact, the below code | |
813 | * is a bit suboptimal because the retiring can occur simply after the | |
814 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
815 | */ | |
112522f6 | 816 | if (from != NULL) { |
bca44d80 CW |
817 | from->engine[RCS].state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
818 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req); | |
e0556841 BW |
819 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
820 | * whole damn pipeline, we don't need to explicitly mark the | |
821 | * object dirty. The only exception is that the context must be | |
822 | * correct in case the object gets swapped out. Ideally we'd be | |
823 | * able to defer doing this until we know the object would be | |
824 | * swapped, but there is no way to do that yet. | |
825 | */ | |
bca44d80 | 826 | from->engine[RCS].state->dirty = 1; |
112522f6 | 827 | |
c0321e2c | 828 | /* obj is kept alive until the next request by its active ref */ |
bca44d80 | 829 | i915_gem_object_ggtt_unpin(from->engine[RCS].state); |
112522f6 | 830 | i915_gem_context_unreference(from); |
e0556841 | 831 | } |
112522f6 | 832 | i915_gem_context_reference(to); |
e2f80391 | 833 | engine->last_context = to; |
e0556841 | 834 | |
fcb5106d CW |
835 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
836 | * setup, and we do not wish to move them. | |
837 | */ | |
f9326be5 | 838 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
fcb5106d | 839 | trace_switch_mm(engine, to); |
f9326be5 | 840 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
841 | /* The hardware context switch is emitted, but we haven't |
842 | * actually changed the state - so it's probably safe to bail | |
843 | * here. Still, let the user know something dangerous has | |
844 | * happened. | |
845 | */ | |
846 | if (ret) | |
847 | return ret; | |
848 | } | |
849 | ||
f9326be5 CW |
850 | if (ppgtt) |
851 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); | |
fcb5106d CW |
852 | |
853 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
854 | if (!(to->remap_slice & (1<<i))) | |
855 | continue; | |
856 | ||
d200cda6 | 857 | ret = remap_l3(req, i); |
fcb5106d CW |
858 | if (ret) |
859 | return ret; | |
860 | ||
861 | to->remap_slice &= ~(1<<i); | |
862 | } | |
863 | ||
bca44d80 | 864 | if (!to->engine[RCS].initialised) { |
e2f80391 TU |
865 | if (engine->init_context) { |
866 | ret = engine->init_context(req); | |
86d7f238 | 867 | if (ret) |
fcb5106d | 868 | return ret; |
86d7f238 | 869 | } |
bca44d80 | 870 | to->engine[RCS].initialised = true; |
46470fc9 MK |
871 | } |
872 | ||
e0556841 | 873 | return 0; |
7e0d96bc BW |
874 | |
875 | unpin_out: | |
bca44d80 | 876 | i915_gem_object_ggtt_unpin(to->engine[RCS].state); |
7e0d96bc | 877 | return ret; |
e0556841 BW |
878 | } |
879 | ||
880 | /** | |
881 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 882 | * @req: request for which we'll execute the context switch |
e0556841 BW |
883 | * |
884 | * The context life cycle is simple. The context refcount is incremented and | |
885 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 886 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 887 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
888 | * |
889 | * This function should not be used in execlists mode. Instead the context is | |
890 | * switched by writing to the ELSP and requests keep a reference to their | |
891 | * context. | |
e0556841 | 892 | */ |
ba01cc93 | 893 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 894 | { |
4a570db5 | 895 | struct intel_engine_cs *engine = req->engine; |
e0556841 | 896 | |
ecdb5fd8 | 897 | WARN_ON(i915.enable_execlists); |
91c8a326 | 898 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
0eea67eb | 899 | |
bca44d80 | 900 | if (!req->ctx->engine[engine->id].state) { |
e2efd130 | 901 | struct i915_gem_context *to = req->ctx; |
f9326be5 CW |
902 | struct i915_hw_ppgtt *ppgtt = |
903 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; | |
e1a8daa2 | 904 | |
f9326be5 | 905 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
e1a8daa2 CW |
906 | int ret; |
907 | ||
908 | trace_switch_mm(engine, to); | |
f9326be5 | 909 | ret = ppgtt->switch_mm(ppgtt, req); |
e1a8daa2 CW |
910 | if (ret) |
911 | return ret; | |
912 | ||
f9326be5 | 913 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
e1a8daa2 CW |
914 | } |
915 | ||
916 | if (to != engine->last_context) { | |
917 | i915_gem_context_reference(to); | |
e2f80391 TU |
918 | if (engine->last_context) |
919 | i915_gem_context_unreference(engine->last_context); | |
e1a8daa2 | 920 | engine->last_context = to; |
691e6415 | 921 | } |
e1a8daa2 | 922 | |
c482972a | 923 | return 0; |
a95f6a00 | 924 | } |
c482972a | 925 | |
e1a8daa2 | 926 | return do_rcs_switch(req); |
e0556841 | 927 | } |
84624813 | 928 | |
ec3e9963 | 929 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 930 | { |
ec3e9963 | 931 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
932 | } |
933 | ||
84624813 BW |
934 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
935 | struct drm_file *file) | |
936 | { | |
84624813 BW |
937 | struct drm_i915_gem_context_create *args = data; |
938 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 939 | struct i915_gem_context *ctx; |
84624813 BW |
940 | int ret; |
941 | ||
ec3e9963 | 942 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
943 | return -ENODEV; |
944 | ||
b31e5136 CW |
945 | if (args->pad != 0) |
946 | return -EINVAL; | |
947 | ||
84624813 BW |
948 | ret = i915_mutex_lock_interruptible(dev); |
949 | if (ret) | |
950 | return ret; | |
951 | ||
d624d86e | 952 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 953 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
954 | if (IS_ERR(ctx)) |
955 | return PTR_ERR(ctx); | |
84624813 | 956 | |
821d66dd | 957 | args->ctx_id = ctx->user_handle; |
84624813 BW |
958 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
959 | ||
be636387 | 960 | return 0; |
84624813 BW |
961 | } |
962 | ||
963 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
964 | struct drm_file *file) | |
965 | { | |
966 | struct drm_i915_gem_context_destroy *args = data; | |
967 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 968 | struct i915_gem_context *ctx; |
84624813 BW |
969 | int ret; |
970 | ||
b31e5136 CW |
971 | if (args->pad != 0) |
972 | return -EINVAL; | |
973 | ||
821d66dd | 974 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 975 | return -ENOENT; |
0eea67eb | 976 | |
84624813 BW |
977 | ret = i915_mutex_lock_interruptible(dev); |
978 | if (ret) | |
979 | return ret; | |
980 | ||
ca585b5d | 981 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
72ad5c45 | 982 | if (IS_ERR(ctx)) { |
84624813 | 983 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 984 | return PTR_ERR(ctx); |
84624813 BW |
985 | } |
986 | ||
d28b99ab | 987 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
dce3271b | 988 | i915_gem_context_unreference(ctx); |
84624813 BW |
989 | mutex_unlock(&dev->struct_mutex); |
990 | ||
991 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
992 | return 0; | |
993 | } | |
c9dc0f35 CW |
994 | |
995 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
996 | struct drm_file *file) | |
997 | { | |
998 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
999 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1000 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1001 | int ret; |
1002 | ||
1003 | ret = i915_mutex_lock_interruptible(dev); | |
1004 | if (ret) | |
1005 | return ret; | |
1006 | ||
ca585b5d | 1007 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1008 | if (IS_ERR(ctx)) { |
1009 | mutex_unlock(&dev->struct_mutex); | |
1010 | return PTR_ERR(ctx); | |
1011 | } | |
1012 | ||
1013 | args->size = 0; | |
1014 | switch (args->param) { | |
1015 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
1016 | args->value = ctx->hang_stats.ban_period_seconds; | |
1017 | break; | |
b1b38278 DW |
1018 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1019 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
1020 | break; | |
fa8848f2 CW |
1021 | case I915_CONTEXT_PARAM_GTT_SIZE: |
1022 | if (ctx->ppgtt) | |
1023 | args->value = ctx->ppgtt->base.total; | |
1024 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
1025 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
1026 | else | |
62106b4f | 1027 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 1028 | break; |
bc3d6744 CW |
1029 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: |
1030 | args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE); | |
1031 | break; | |
c9dc0f35 CW |
1032 | default: |
1033 | ret = -EINVAL; | |
1034 | break; | |
1035 | } | |
1036 | mutex_unlock(&dev->struct_mutex); | |
1037 | ||
1038 | return ret; | |
1039 | } | |
1040 | ||
1041 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
1042 | struct drm_file *file) | |
1043 | { | |
1044 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1045 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1046 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1047 | int ret; |
1048 | ||
1049 | ret = i915_mutex_lock_interruptible(dev); | |
1050 | if (ret) | |
1051 | return ret; | |
1052 | ||
ca585b5d | 1053 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1054 | if (IS_ERR(ctx)) { |
1055 | mutex_unlock(&dev->struct_mutex); | |
1056 | return PTR_ERR(ctx); | |
1057 | } | |
1058 | ||
1059 | switch (args->param) { | |
1060 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
1061 | if (args->size) | |
1062 | ret = -EINVAL; | |
1063 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
1064 | !capable(CAP_SYS_ADMIN)) | |
1065 | ret = -EPERM; | |
1066 | else | |
1067 | ctx->hang_stats.ban_period_seconds = args->value; | |
1068 | break; | |
b1b38278 DW |
1069 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1070 | if (args->size) { | |
1071 | ret = -EINVAL; | |
1072 | } else { | |
1073 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
1074 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
bc3d6744 CW |
1075 | } |
1076 | break; | |
1077 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: | |
1078 | if (args->size) { | |
1079 | ret = -EINVAL; | |
1080 | } else { | |
1081 | if (args->value) | |
1082 | ctx->flags |= CONTEXT_NO_ERROR_CAPTURE; | |
1083 | else | |
1084 | ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE; | |
b1b38278 DW |
1085 | } |
1086 | break; | |
c9dc0f35 CW |
1087 | default: |
1088 | ret = -EINVAL; | |
1089 | break; | |
1090 | } | |
1091 | mutex_unlock(&dev->struct_mutex); | |
1092 | ||
1093 | return ret; | |
1094 | } | |
d538704b CW |
1095 | |
1096 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, | |
1097 | void *data, struct drm_file *file) | |
1098 | { | |
fac5e23e | 1099 | struct drm_i915_private *dev_priv = to_i915(dev); |
d538704b CW |
1100 | struct drm_i915_reset_stats *args = data; |
1101 | struct i915_ctx_hang_stats *hs; | |
e2efd130 | 1102 | struct i915_gem_context *ctx; |
d538704b CW |
1103 | int ret; |
1104 | ||
1105 | if (args->flags || args->pad) | |
1106 | return -EINVAL; | |
1107 | ||
1108 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) | |
1109 | return -EPERM; | |
1110 | ||
bdb04614 | 1111 | ret = i915_mutex_lock_interruptible(dev); |
d538704b CW |
1112 | if (ret) |
1113 | return ret; | |
1114 | ||
ca585b5d | 1115 | ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id); |
d538704b CW |
1116 | if (IS_ERR(ctx)) { |
1117 | mutex_unlock(&dev->struct_mutex); | |
1118 | return PTR_ERR(ctx); | |
1119 | } | |
1120 | hs = &ctx->hang_stats; | |
1121 | ||
1122 | if (capable(CAP_SYS_ADMIN)) | |
1123 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1124 | else | |
1125 | args->reset_count = 0; | |
1126 | ||
1127 | args->batch_active = hs->batch_active; | |
1128 | args->batch_pending = hs->batch_pending; | |
1129 | ||
1130 | mutex_unlock(&dev->struct_mutex); | |
1131 | ||
1132 | return 0; | |
1133 | } |