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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
b2e862d0 CW |
93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
94 | ||
40521054 BW |
95 | /* This is a HW constraint. The value below is the largest known requirement |
96 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
97 | * part. It should be safe to decrease this, but it's more future proof as is. | |
98 | */ | |
b731d33d BW |
99 | #define GEN6_CONTEXT_ALIGN (64<<10) |
100 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 101 | |
c033666a | 102 | static size_t get_context_alignment(struct drm_i915_private *dev_priv) |
b731d33d | 103 | { |
c033666a | 104 | if (IS_GEN6(dev_priv)) |
b731d33d BW |
105 | return GEN6_CONTEXT_ALIGN; |
106 | ||
107 | return GEN7_CONTEXT_ALIGN; | |
108 | } | |
109 | ||
c033666a | 110 | static int get_context_size(struct drm_i915_private *dev_priv) |
254f965c | 111 | { |
254f965c BW |
112 | int ret; |
113 | u32 reg; | |
114 | ||
c033666a | 115 | switch (INTEL_GEN(dev_priv)) { |
254f965c BW |
116 | case 6: |
117 | reg = I915_READ(CXT_SIZE); | |
118 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
119 | break; | |
120 | case 7: | |
4f91dd6f | 121 | reg = I915_READ(GEN7_CXT_SIZE); |
c033666a | 122 | if (IS_HASWELL(dev_priv)) |
a0de80a0 | 123 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
124 | else |
125 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 126 | break; |
8897644a BW |
127 | case 8: |
128 | ret = GEN8_CXT_TOTAL_SIZE; | |
129 | break; | |
254f965c BW |
130 | default: |
131 | BUG(); | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
dce3271b | 137 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 138 | { |
e2efd130 | 139 | struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
bca44d80 | 140 | int i; |
40521054 | 141 | |
91c8a326 | 142 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
198c974d | 143 | trace_i915_context_free(ctx); |
50e046b6 | 144 | GEM_BUG_ON(!ctx->closed); |
198c974d | 145 | |
ae6c4806 DV |
146 | i915_ppgtt_put(ctx->ppgtt); |
147 | ||
bca44d80 CW |
148 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
149 | struct intel_context *ce = &ctx->engine[i]; | |
150 | ||
151 | if (!ce->state) | |
152 | continue; | |
153 | ||
154 | WARN_ON(ce->pin_count); | |
dca33ecc | 155 | if (ce->ring) |
7e37f889 | 156 | intel_ring_free(ce->ring); |
bca44d80 | 157 | |
f8a7fde4 | 158 | __i915_gem_object_release_unless_active(ce->state->obj); |
bca44d80 CW |
159 | } |
160 | ||
562f5d45 | 161 | kfree(ctx->name); |
c84455b4 | 162 | put_pid(ctx->pid); |
c7c48dfd | 163 | list_del(&ctx->link); |
5d1808ec CW |
164 | |
165 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); | |
40521054 BW |
166 | kfree(ctx); |
167 | } | |
168 | ||
8c857917 | 169 | struct drm_i915_gem_object * |
aa0c13da OM |
170 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
171 | { | |
172 | struct drm_i915_gem_object *obj; | |
173 | int ret; | |
174 | ||
499f2697 CW |
175 | lockdep_assert_held(&dev->struct_mutex); |
176 | ||
d37cd8a8 | 177 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
178 | if (IS_ERR(obj)) |
179 | return obj; | |
aa0c13da OM |
180 | |
181 | /* | |
182 | * Try to make the context utilize L3 as well as LLC. | |
183 | * | |
184 | * On VLV we don't have L3 controls in the PTEs so we | |
185 | * shouldn't touch the cache level, especially as that | |
186 | * would make the object snooped which might have a | |
187 | * negative performance impact. | |
4d3e904c WB |
188 | * |
189 | * Snooping is required on non-llc platforms in execlist | |
190 | * mode, but since all GGTT accesses use PAT entry 0 we | |
191 | * get snooping anyway regardless of cache_level. | |
192 | * | |
193 | * This is only applicable for Ivy Bridge devices since | |
194 | * later platforms don't have L3 control bits in the PTE. | |
aa0c13da | 195 | */ |
fd6b8f43 | 196 | if (IS_IVYBRIDGE(to_i915(dev))) { |
aa0c13da OM |
197 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
198 | /* Failure shouldn't ever happen this early */ | |
199 | if (WARN_ON(ret)) { | |
f8c417cd | 200 | i915_gem_object_put(obj); |
aa0c13da OM |
201 | return ERR_PTR(ret); |
202 | } | |
203 | } | |
204 | ||
205 | return obj; | |
206 | } | |
207 | ||
50e046b6 CW |
208 | static void i915_ppgtt_close(struct i915_address_space *vm) |
209 | { | |
210 | struct list_head *phases[] = { | |
211 | &vm->active_list, | |
212 | &vm->inactive_list, | |
213 | &vm->unbound_list, | |
214 | NULL, | |
215 | }, **phase; | |
216 | ||
217 | GEM_BUG_ON(vm->closed); | |
218 | vm->closed = true; | |
219 | ||
220 | for (phase = phases; *phase; phase++) { | |
221 | struct i915_vma *vma, *vn; | |
222 | ||
223 | list_for_each_entry_safe(vma, vn, *phase, vm_link) | |
3272db53 | 224 | if (!i915_vma_is_closed(vma)) |
50e046b6 CW |
225 | i915_vma_close(vma); |
226 | } | |
227 | } | |
228 | ||
229 | static void context_close(struct i915_gem_context *ctx) | |
230 | { | |
231 | GEM_BUG_ON(ctx->closed); | |
232 | ctx->closed = true; | |
233 | if (ctx->ppgtt) | |
234 | i915_ppgtt_close(&ctx->ppgtt->base); | |
235 | ctx->file_priv = ERR_PTR(-EBADF); | |
236 | i915_gem_context_put(ctx); | |
237 | } | |
238 | ||
5d1808ec CW |
239 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
240 | { | |
241 | int ret; | |
242 | ||
243 | ret = ida_simple_get(&dev_priv->context_hw_ida, | |
244 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
245 | if (ret < 0) { | |
246 | /* Contexts are only released when no longer active. | |
247 | * Flush any pending retires to hopefully release some | |
248 | * stale contexts and try again. | |
249 | */ | |
c033666a | 250 | i915_gem_retire_requests(dev_priv); |
5d1808ec CW |
251 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
252 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
253 | if (ret < 0) | |
254 | return ret; | |
255 | } | |
256 | ||
257 | *out = ret; | |
258 | return 0; | |
259 | } | |
260 | ||
e2efd130 | 261 | static struct i915_gem_context * |
0eea67eb | 262 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 263 | struct drm_i915_file_private *file_priv) |
40521054 | 264 | { |
fac5e23e | 265 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 266 | struct i915_gem_context *ctx; |
c8c470af | 267 | int ret; |
40521054 | 268 | |
f94982b0 | 269 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
270 | if (ctx == NULL) |
271 | return ERR_PTR(-ENOMEM); | |
40521054 | 272 | |
5d1808ec CW |
273 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
274 | if (ret) { | |
275 | kfree(ctx); | |
276 | return ERR_PTR(ret); | |
277 | } | |
278 | ||
dce3271b | 279 | kref_init(&ctx->ref); |
691e6415 | 280 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 281 | ctx->i915 = dev_priv; |
40521054 | 282 | |
0cb26a8e CW |
283 | ctx->ggtt_alignment = get_context_alignment(dev_priv); |
284 | ||
691e6415 | 285 | if (dev_priv->hw_context_size) { |
bf3783e5 CW |
286 | struct drm_i915_gem_object *obj; |
287 | struct i915_vma *vma; | |
288 | ||
289 | obj = i915_gem_alloc_context_obj(dev, | |
290 | dev_priv->hw_context_size); | |
aa0c13da OM |
291 | if (IS_ERR(obj)) { |
292 | ret = PTR_ERR(obj); | |
4615d4c9 | 293 | goto err_out; |
691e6415 | 294 | } |
bf3783e5 CW |
295 | |
296 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); | |
297 | if (IS_ERR(vma)) { | |
298 | i915_gem_object_put(obj); | |
299 | ret = PTR_ERR(vma); | |
300 | goto err_out; | |
301 | } | |
302 | ||
303 | ctx->engine[RCS].state = vma; | |
691e6415 | 304 | } |
40521054 BW |
305 | |
306 | /* Default context will never have a file_priv */ | |
562f5d45 CW |
307 | ret = DEFAULT_CONTEXT_HANDLE; |
308 | if (file_priv) { | |
691e6415 | 309 | ret = idr_alloc(&file_priv->context_idr, ctx, |
821d66dd | 310 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
311 | if (ret < 0) |
312 | goto err_out; | |
562f5d45 CW |
313 | } |
314 | ctx->user_handle = ret; | |
dce3271b MK |
315 | |
316 | ctx->file_priv = file_priv; | |
562f5d45 | 317 | if (file_priv) { |
c84455b4 | 318 | ctx->pid = get_task_pid(current, PIDTYPE_PID); |
562f5d45 CW |
319 | ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x", |
320 | current->comm, | |
321 | pid_nr(ctx->pid), | |
322 | ctx->user_handle); | |
323 | if (!ctx->name) { | |
324 | ret = -ENOMEM; | |
325 | goto err_pid; | |
326 | } | |
327 | } | |
c84455b4 | 328 | |
3ccfd19d BW |
329 | /* NB: Mark all slices as needing a remap so that when the context first |
330 | * loads it will restore whatever remap state already exists. If there | |
331 | * is no remap info, it will be a NOP. */ | |
b2e862d0 | 332 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
40521054 | 333 | |
84102171 | 334 | ctx->hang_stats.bannable = true; |
bcd794c2 | 335 | ctx->ring_size = 4 * PAGE_SIZE; |
c01fc532 ZW |
336 | ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) << |
337 | GEN8_CTX_ADDRESSING_MODE_SHIFT; | |
3c7ba635 | 338 | ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier); |
676fa572 | 339 | |
146937e5 | 340 | return ctx; |
40521054 | 341 | |
562f5d45 CW |
342 | err_pid: |
343 | put_pid(ctx->pid); | |
344 | idr_remove(&file_priv->context_idr, ctx->user_handle); | |
40521054 | 345 | err_out: |
50e046b6 | 346 | context_close(ctx); |
146937e5 | 347 | return ERR_PTR(ret); |
40521054 BW |
348 | } |
349 | ||
254f965c BW |
350 | /** |
351 | * The default context needs to exist per ring that uses contexts. It stores the | |
352 | * context state of the GPU for applications that don't utilize HW contexts, as | |
353 | * well as an idle case. | |
354 | */ | |
e2efd130 | 355 | static struct i915_gem_context * |
0eea67eb | 356 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 357 | struct drm_i915_file_private *file_priv) |
254f965c | 358 | { |
e2efd130 | 359 | struct i915_gem_context *ctx; |
40521054 | 360 | |
499f2697 | 361 | lockdep_assert_held(&dev->struct_mutex); |
40521054 | 362 | |
0eea67eb | 363 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 364 | if (IS_ERR(ctx)) |
a45d0f6a | 365 | return ctx; |
40521054 | 366 | |
d624d86e | 367 | if (USES_FULL_PPGTT(dev)) { |
80b204bc | 368 | struct i915_hw_ppgtt *ppgtt; |
bdf4fd7e | 369 | |
80b204bc | 370 | ppgtt = i915_ppgtt_create(to_i915(dev), file_priv, ctx->name); |
c6aab916 | 371 | if (IS_ERR(ppgtt)) { |
0eea67eb BW |
372 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
373 | PTR_ERR(ppgtt)); | |
c6aab916 | 374 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
50e046b6 | 375 | context_close(ctx); |
c6aab916 | 376 | return ERR_CAST(ppgtt); |
ae6c4806 DV |
377 | } |
378 | ||
379 | ctx->ppgtt = ppgtt; | |
380 | } | |
bdf4fd7e | 381 | |
198c974d DCS |
382 | trace_i915_context_create(ctx); |
383 | ||
a45d0f6a | 384 | return ctx; |
254f965c BW |
385 | } |
386 | ||
c8c35799 ZW |
387 | /** |
388 | * i915_gem_context_create_gvt - create a GVT GEM context | |
389 | * @dev: drm device * | |
390 | * | |
391 | * This function is used to create a GVT specific GEM context. | |
392 | * | |
393 | * Returns: | |
394 | * pointer to i915_gem_context on success, error pointer if failed | |
395 | * | |
396 | */ | |
397 | struct i915_gem_context * | |
398 | i915_gem_context_create_gvt(struct drm_device *dev) | |
399 | { | |
400 | struct i915_gem_context *ctx; | |
401 | int ret; | |
402 | ||
403 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
404 | return ERR_PTR(-ENODEV); | |
405 | ||
406 | ret = i915_mutex_lock_interruptible(dev); | |
407 | if (ret) | |
408 | return ERR_PTR(ret); | |
409 | ||
410 | ctx = i915_gem_create_context(dev, NULL); | |
411 | if (IS_ERR(ctx)) | |
412 | goto out; | |
413 | ||
414 | ctx->execlists_force_single_submission = true; | |
415 | ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */ | |
416 | out: | |
417 | mutex_unlock(&dev->struct_mutex); | |
418 | return ctx; | |
419 | } | |
420 | ||
e2efd130 | 421 | static void i915_gem_context_unpin(struct i915_gem_context *ctx, |
a0b4a6a8 TU |
422 | struct intel_engine_cs *engine) |
423 | { | |
f4e2dece TU |
424 | if (i915.enable_execlists) { |
425 | intel_lr_context_unpin(ctx, engine); | |
426 | } else { | |
bca44d80 CW |
427 | struct intel_context *ce = &ctx->engine[engine->id]; |
428 | ||
429 | if (ce->state) | |
bf3783e5 | 430 | i915_vma_unpin(ce->state); |
bca44d80 | 431 | |
9a6feaf0 | 432 | i915_gem_context_put(ctx); |
f4e2dece | 433 | } |
a0b4a6a8 TU |
434 | } |
435 | ||
8245be31 | 436 | int i915_gem_context_init(struct drm_device *dev) |
254f965c | 437 | { |
fac5e23e | 438 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 439 | struct i915_gem_context *ctx; |
254f965c | 440 | |
2fa48d8d BW |
441 | /* Init should only be called once per module load. Eventually the |
442 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 443 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 444 | return 0; |
254f965c | 445 | |
c033666a CW |
446 | if (intel_vgpu_active(dev_priv) && |
447 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { | |
a0bd6c31 ZL |
448 | if (!i915.enable_execlists) { |
449 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
450 | return -EINVAL; | |
451 | } | |
452 | } | |
453 | ||
5d1808ec CW |
454 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
455 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); | |
456 | ida_init(&dev_priv->context_hw_ida); | |
457 | ||
ede7d42b OM |
458 | if (i915.enable_execlists) { |
459 | /* NB: intentionally left blank. We will allocate our own | |
460 | * backing objects as we need them, thank you very much */ | |
461 | dev_priv->hw_context_size = 0; | |
c033666a CW |
462 | } else if (HAS_HW_CONTEXTS(dev_priv)) { |
463 | dev_priv->hw_context_size = | |
464 | round_up(get_context_size(dev_priv), 4096); | |
691e6415 CW |
465 | if (dev_priv->hw_context_size > (1<<20)) { |
466 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
467 | dev_priv->hw_context_size); | |
468 | dev_priv->hw_context_size = 0; | |
469 | } | |
254f965c BW |
470 | } |
471 | ||
d624d86e | 472 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
473 | if (IS_ERR(ctx)) { |
474 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
475 | PTR_ERR(ctx)); | |
476 | return PTR_ERR(ctx); | |
254f965c BW |
477 | } |
478 | ||
9f792eba | 479 | ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */ |
ed54c1a1 | 480 | dev_priv->kernel_context = ctx; |
67e3d297 | 481 | |
ede7d42b OM |
482 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
483 | i915.enable_execlists ? "LR" : | |
484 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 485 | return 0; |
254f965c BW |
486 | } |
487 | ||
b2e862d0 CW |
488 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
489 | { | |
490 | struct intel_engine_cs *engine; | |
3b3f1650 | 491 | enum intel_engine_id id; |
b2e862d0 | 492 | |
91c8a326 | 493 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 494 | |
3b3f1650 | 495 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
496 | if (engine->last_context) { |
497 | i915_gem_context_unpin(engine->last_context, engine); | |
498 | engine->last_context = NULL; | |
499 | } | |
b2e862d0 CW |
500 | } |
501 | ||
c7c3c07d CW |
502 | /* Force the GPU state to be restored on enabling */ |
503 | if (!i915.enable_execlists) { | |
a168b2d8 CW |
504 | struct i915_gem_context *ctx; |
505 | ||
506 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
507 | if (!i915_gem_context_is_default(ctx)) | |
508 | continue; | |
509 | ||
3b3f1650 | 510 | for_each_engine(engine, dev_priv, id) |
a168b2d8 CW |
511 | ctx->engine[engine->id].initialised = false; |
512 | ||
513 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); | |
514 | } | |
515 | ||
3b3f1650 | 516 | for_each_engine(engine, dev_priv, id) { |
c7c3c07d CW |
517 | struct intel_context *kce = |
518 | &dev_priv->kernel_context->engine[engine->id]; | |
519 | ||
520 | kce->initialised = true; | |
521 | } | |
522 | } | |
b2e862d0 CW |
523 | } |
524 | ||
254f965c BW |
525 | void i915_gem_context_fini(struct drm_device *dev) |
526 | { | |
fac5e23e | 527 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 528 | struct i915_gem_context *dctx = dev_priv->kernel_context; |
b2e862d0 | 529 | |
499f2697 CW |
530 | lockdep_assert_held(&dev->struct_mutex); |
531 | ||
50e046b6 | 532 | context_close(dctx); |
ed54c1a1 | 533 | dev_priv->kernel_context = NULL; |
5d1808ec CW |
534 | |
535 | ida_destroy(&dev_priv->context_hw_ida); | |
254f965c BW |
536 | } |
537 | ||
40521054 BW |
538 | static int context_idr_cleanup(int id, void *p, void *data) |
539 | { | |
e2efd130 | 540 | struct i915_gem_context *ctx = p; |
40521054 | 541 | |
50e046b6 | 542 | context_close(ctx); |
40521054 | 543 | return 0; |
254f965c BW |
544 | } |
545 | ||
e422b888 BW |
546 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
547 | { | |
548 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 549 | struct i915_gem_context *ctx; |
e422b888 BW |
550 | |
551 | idr_init(&file_priv->context_idr); | |
552 | ||
0eea67eb | 553 | mutex_lock(&dev->struct_mutex); |
d624d86e | 554 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
555 | mutex_unlock(&dev->struct_mutex); |
556 | ||
f83d6518 | 557 | if (IS_ERR(ctx)) { |
0eea67eb | 558 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 559 | return PTR_ERR(ctx); |
0eea67eb BW |
560 | } |
561 | ||
e422b888 BW |
562 | return 0; |
563 | } | |
564 | ||
254f965c BW |
565 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
566 | { | |
40521054 | 567 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 568 | |
499f2697 CW |
569 | lockdep_assert_held(&dev->struct_mutex); |
570 | ||
73c273eb | 571 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 572 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
573 | } |
574 | ||
e0556841 | 575 | static inline int |
1d719cda | 576 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 577 | { |
c033666a | 578 | struct drm_i915_private *dev_priv = req->i915; |
7e37f889 | 579 | struct intel_ring *ring = req->ring; |
4a570db5 | 580 | struct intel_engine_cs *engine = req->engine; |
3b3f1650 | 581 | enum intel_engine_id id; |
e80f14b6 | 582 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
583 | const int num_rings = |
584 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
39df9190 | 585 | i915.semaphores ? |
c1bb1145 | 586 | INTEL_INFO(dev_priv)->num_rings - 1 : |
2c550183 | 587 | 0; |
b4ac5afc | 588 | int len, ret; |
e0556841 | 589 | |
12b0286f BW |
590 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
591 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
592 | * explicitly, so we rely on the value at ring init, stored in | |
593 | * itlb_before_ctx_switch. | |
594 | */ | |
c033666a | 595 | if (IS_GEN6(dev_priv)) { |
7c9cf4e3 | 596 | ret = engine->emit_flush(req, EMIT_INVALIDATE); |
12b0286f BW |
597 | if (ret) |
598 | return ret; | |
599 | } | |
600 | ||
e80f14b6 | 601 | /* These flags are for resource streamer on HSW+ */ |
c033666a | 602 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
4c436d55 | 603 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
c033666a | 604 | else if (INTEL_GEN(dev_priv) < 8) |
e80f14b6 BW |
605 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
606 | ||
2c550183 CW |
607 | |
608 | len = 4; | |
c033666a | 609 | if (INTEL_GEN(dev_priv) >= 7) |
e9135c4f | 610 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
2c550183 | 611 | |
5fb9de1a | 612 | ret = intel_ring_begin(req, len); |
e0556841 BW |
613 | if (ret) |
614 | return ret; | |
615 | ||
b3f797ac | 616 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
c033666a | 617 | if (INTEL_GEN(dev_priv) >= 7) { |
b5321f30 | 618 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
619 | if (num_rings) { |
620 | struct intel_engine_cs *signaller; | |
621 | ||
b5321f30 | 622 | intel_ring_emit(ring, |
e2f80391 | 623 | MI_LOAD_REGISTER_IMM(num_rings)); |
3b3f1650 | 624 | for_each_engine(signaller, dev_priv, id) { |
e2f80391 | 625 | if (signaller == engine) |
2c550183 CW |
626 | continue; |
627 | ||
b5321f30 | 628 | intel_ring_emit_reg(ring, |
e2f80391 | 629 | RING_PSMI_CTL(signaller->mmio_base)); |
b5321f30 | 630 | intel_ring_emit(ring, |
e2f80391 | 631 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
2c550183 CW |
632 | } |
633 | } | |
634 | } | |
e37ec39b | 635 | |
b5321f30 CW |
636 | intel_ring_emit(ring, MI_NOOP); |
637 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
bde13ebd CW |
638 | intel_ring_emit(ring, |
639 | i915_ggtt_offset(req->ctx->engine[RCS].state) | flags); | |
2b7e8082 VS |
640 | /* |
641 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
642 | * WaMiSetContext_Hang:snb,ivb,vlv | |
643 | */ | |
b5321f30 | 644 | intel_ring_emit(ring, MI_NOOP); |
e0556841 | 645 | |
c033666a | 646 | if (INTEL_GEN(dev_priv) >= 7) { |
2c550183 CW |
647 | if (num_rings) { |
648 | struct intel_engine_cs *signaller; | |
e9135c4f | 649 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
2c550183 | 650 | |
b5321f30 | 651 | intel_ring_emit(ring, |
e2f80391 | 652 | MI_LOAD_REGISTER_IMM(num_rings)); |
3b3f1650 | 653 | for_each_engine(signaller, dev_priv, id) { |
e2f80391 | 654 | if (signaller == engine) |
2c550183 CW |
655 | continue; |
656 | ||
e9135c4f | 657 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
b5321f30 CW |
658 | intel_ring_emit_reg(ring, last_reg); |
659 | intel_ring_emit(ring, | |
e2f80391 | 660 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
2c550183 | 661 | } |
e9135c4f CW |
662 | |
663 | /* Insert a delay before the next switch! */ | |
b5321f30 | 664 | intel_ring_emit(ring, |
e9135c4f CW |
665 | MI_STORE_REGISTER_MEM | |
666 | MI_SRM_LRM_GLOBAL_GTT); | |
b5321f30 | 667 | intel_ring_emit_reg(ring, last_reg); |
bde13ebd CW |
668 | intel_ring_emit(ring, |
669 | i915_ggtt_offset(engine->scratch)); | |
b5321f30 | 670 | intel_ring_emit(ring, MI_NOOP); |
2c550183 | 671 | } |
b5321f30 | 672 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 673 | } |
e37ec39b | 674 | |
b5321f30 | 675 | intel_ring_advance(ring); |
e0556841 BW |
676 | |
677 | return ret; | |
678 | } | |
679 | ||
d200cda6 | 680 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
b0ebde39 | 681 | { |
ff55b5e8 | 682 | u32 *remap_info = req->i915->l3_parity.remap_info[slice]; |
7e37f889 | 683 | struct intel_ring *ring = req->ring; |
b0ebde39 CW |
684 | int i, ret; |
685 | ||
ff55b5e8 | 686 | if (!remap_info) |
b0ebde39 CW |
687 | return 0; |
688 | ||
ff55b5e8 | 689 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
b0ebde39 CW |
690 | if (ret) |
691 | return ret; | |
692 | ||
693 | /* | |
694 | * Note: We do not worry about the concurrent register cacheline hang | |
695 | * here because no other code should access these registers other than | |
696 | * at initialization time. | |
697 | */ | |
b5321f30 | 698 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); |
ff55b5e8 | 699 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { |
b5321f30 CW |
700 | intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i)); |
701 | intel_ring_emit(ring, remap_info[i]); | |
b0ebde39 | 702 | } |
b5321f30 CW |
703 | intel_ring_emit(ring, MI_NOOP); |
704 | intel_ring_advance(ring); | |
b0ebde39 | 705 | |
ff55b5e8 | 706 | return 0; |
b0ebde39 CW |
707 | } |
708 | ||
f9326be5 CW |
709 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
710 | struct intel_engine_cs *engine, | |
e2efd130 | 711 | struct i915_gem_context *to) |
317b4e90 | 712 | { |
563222a7 BW |
713 | if (to->remap_slice) |
714 | return false; | |
715 | ||
bca44d80 | 716 | if (!to->engine[RCS].initialised) |
fcb5106d CW |
717 | return false; |
718 | ||
f9326be5 | 719 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
fcb5106d | 720 | return false; |
317b4e90 | 721 | |
fcb5106d | 722 | return to == engine->last_context; |
317b4e90 BW |
723 | } |
724 | ||
725 | static bool | |
f9326be5 CW |
726 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
727 | struct intel_engine_cs *engine, | |
e2efd130 | 728 | struct i915_gem_context *to) |
317b4e90 | 729 | { |
f9326be5 | 730 | if (!ppgtt) |
317b4e90 BW |
731 | return false; |
732 | ||
f9326be5 CW |
733 | /* Always load the ppgtt on first use */ |
734 | if (!engine->last_context) | |
735 | return true; | |
736 | ||
737 | /* Same context without new entries, skip */ | |
e1a8daa2 | 738 | if (engine->last_context == to && |
f9326be5 | 739 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
e1a8daa2 CW |
740 | return false; |
741 | ||
742 | if (engine->id != RCS) | |
317b4e90 BW |
743 | return true; |
744 | ||
c033666a | 745 | if (INTEL_GEN(engine->i915) < 8) |
317b4e90 BW |
746 | return true; |
747 | ||
748 | return false; | |
749 | } | |
750 | ||
751 | static bool | |
f9326be5 | 752 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
e2efd130 | 753 | struct i915_gem_context *to, |
f9326be5 | 754 | u32 hw_flags) |
317b4e90 | 755 | { |
f9326be5 | 756 | if (!ppgtt) |
317b4e90 BW |
757 | return false; |
758 | ||
fcb5106d | 759 | if (!IS_GEN8(to->i915)) |
317b4e90 BW |
760 | return false; |
761 | ||
6702cf16 | 762 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
763 | return true; |
764 | ||
765 | return false; | |
766 | } | |
767 | ||
07c9a21a CW |
768 | struct i915_vma * |
769 | i915_gem_context_pin_legacy(struct i915_gem_context *ctx, | |
770 | unsigned int flags) | |
771 | { | |
772 | struct i915_vma *vma = ctx->engine[RCS].state; | |
773 | int ret; | |
774 | ||
775 | /* Clear this page out of any CPU caches for coherent swap-in/out. | |
776 | * We only want to do this on the first bind so that we do not stall | |
777 | * on an active context (which by nature is already on the GPU). | |
778 | */ | |
779 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
780 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, false); | |
781 | if (ret) | |
782 | return ERR_PTR(ret); | |
783 | } | |
784 | ||
785 | ret = i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | flags); | |
786 | if (ret) | |
787 | return ERR_PTR(ret); | |
788 | ||
789 | return vma; | |
790 | } | |
791 | ||
e1a8daa2 | 792 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
e0556841 | 793 | { |
e2efd130 | 794 | struct i915_gem_context *to = req->ctx; |
4a570db5 | 795 | struct intel_engine_cs *engine = req->engine; |
f9326be5 | 796 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
07c9a21a | 797 | struct i915_vma *vma; |
e2efd130 | 798 | struct i915_gem_context *from; |
fcb5106d | 799 | u32 hw_flags; |
3ccfd19d | 800 | int ret, i; |
e0556841 | 801 | |
f9326be5 | 802 | if (skip_rcs_switch(ppgtt, engine, to)) |
9a3b5304 CW |
803 | return 0; |
804 | ||
7e0d96bc | 805 | /* Trying to pin first makes error handling easier. */ |
07c9a21a CW |
806 | vma = i915_gem_context_pin_legacy(to, 0); |
807 | if (IS_ERR(vma)) | |
808 | return PTR_ERR(vma); | |
67e3d297 | 809 | |
acc240d4 DV |
810 | /* |
811 | * Pin can switch back to the default context if we end up calling into | |
812 | * evict_everything - as a last ditch gtt defrag effort that also | |
813 | * switches to the default context. Hence we need to reload from here. | |
fcb5106d CW |
814 | * |
815 | * XXX: Doing so is painfully broken! | |
acc240d4 | 816 | */ |
e2f80391 | 817 | from = engine->last_context; |
acc240d4 | 818 | |
f9326be5 | 819 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
fcb5106d CW |
820 | /* Older GENs and non render rings still want the load first, |
821 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
822 | * Register Immediate commands in Ring Buffer before submitting | |
823 | * a context."*/ | |
824 | trace_switch_mm(engine, to); | |
f9326be5 | 825 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d | 826 | if (ret) |
bf3783e5 | 827 | goto err; |
fcb5106d CW |
828 | } |
829 | ||
bca44d80 | 830 | if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) |
6702cf16 BW |
831 | /* NB: If we inhibit the restore, the context is not allowed to |
832 | * die because future work may end up depending on valid address | |
833 | * space. This means we must enforce that a page table load | |
834 | * occur when this occurs. */ | |
fcb5106d | 835 | hw_flags = MI_RESTORE_INHIBIT; |
f9326be5 | 836 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
fcb5106d CW |
837 | hw_flags = MI_FORCE_RESTORE; |
838 | else | |
839 | hw_flags = 0; | |
e0556841 | 840 | |
fcb5106d CW |
841 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
842 | ret = mi_set_context(req, hw_flags); | |
3ccfd19d | 843 | if (ret) |
bf3783e5 | 844 | goto err; |
3ccfd19d BW |
845 | } |
846 | ||
e0556841 BW |
847 | /* The backing object for the context is done after switching to the |
848 | * *next* context. Therefore we cannot retire the previous context until | |
849 | * the next context has already started running. In fact, the below code | |
850 | * is a bit suboptimal because the retiring can occur simply after the | |
851 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
852 | */ | |
112522f6 | 853 | if (from != NULL) { |
e0556841 BW |
854 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
855 | * whole damn pipeline, we don't need to explicitly mark the | |
856 | * object dirty. The only exception is that the context must be | |
857 | * correct in case the object gets swapped out. Ideally we'd be | |
858 | * able to defer doing this until we know the object would be | |
859 | * swapped, but there is no way to do that yet. | |
860 | */ | |
bf3783e5 CW |
861 | i915_vma_move_to_active(from->engine[RCS].state, req, 0); |
862 | /* state is kept alive until the next request */ | |
863 | i915_vma_unpin(from->engine[RCS].state); | |
9a6feaf0 | 864 | i915_gem_context_put(from); |
e0556841 | 865 | } |
9a6feaf0 | 866 | engine->last_context = i915_gem_context_get(to); |
e0556841 | 867 | |
fcb5106d CW |
868 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
869 | * setup, and we do not wish to move them. | |
870 | */ | |
f9326be5 | 871 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
fcb5106d | 872 | trace_switch_mm(engine, to); |
f9326be5 | 873 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
874 | /* The hardware context switch is emitted, but we haven't |
875 | * actually changed the state - so it's probably safe to bail | |
876 | * here. Still, let the user know something dangerous has | |
877 | * happened. | |
878 | */ | |
879 | if (ret) | |
880 | return ret; | |
881 | } | |
882 | ||
f9326be5 CW |
883 | if (ppgtt) |
884 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); | |
fcb5106d CW |
885 | |
886 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
887 | if (!(to->remap_slice & (1<<i))) | |
888 | continue; | |
889 | ||
d200cda6 | 890 | ret = remap_l3(req, i); |
fcb5106d CW |
891 | if (ret) |
892 | return ret; | |
893 | ||
894 | to->remap_slice &= ~(1<<i); | |
895 | } | |
896 | ||
bca44d80 | 897 | if (!to->engine[RCS].initialised) { |
e2f80391 TU |
898 | if (engine->init_context) { |
899 | ret = engine->init_context(req); | |
86d7f238 | 900 | if (ret) |
fcb5106d | 901 | return ret; |
86d7f238 | 902 | } |
bca44d80 | 903 | to->engine[RCS].initialised = true; |
46470fc9 MK |
904 | } |
905 | ||
e0556841 | 906 | return 0; |
7e0d96bc | 907 | |
bf3783e5 CW |
908 | err: |
909 | i915_vma_unpin(vma); | |
7e0d96bc | 910 | return ret; |
e0556841 BW |
911 | } |
912 | ||
913 | /** | |
914 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 915 | * @req: request for which we'll execute the context switch |
e0556841 BW |
916 | * |
917 | * The context life cycle is simple. The context refcount is incremented and | |
918 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 919 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 920 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
921 | * |
922 | * This function should not be used in execlists mode. Instead the context is | |
923 | * switched by writing to the ELSP and requests keep a reference to their | |
924 | * context. | |
e0556841 | 925 | */ |
ba01cc93 | 926 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 927 | { |
4a570db5 | 928 | struct intel_engine_cs *engine = req->engine; |
e0556841 | 929 | |
91c8a326 | 930 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5b043f4e CW |
931 | if (i915.enable_execlists) |
932 | return 0; | |
0eea67eb | 933 | |
bca44d80 | 934 | if (!req->ctx->engine[engine->id].state) { |
e2efd130 | 935 | struct i915_gem_context *to = req->ctx; |
f9326be5 CW |
936 | struct i915_hw_ppgtt *ppgtt = |
937 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; | |
e1a8daa2 | 938 | |
f9326be5 | 939 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
e1a8daa2 CW |
940 | int ret; |
941 | ||
942 | trace_switch_mm(engine, to); | |
f9326be5 | 943 | ret = ppgtt->switch_mm(ppgtt, req); |
e1a8daa2 CW |
944 | if (ret) |
945 | return ret; | |
946 | ||
f9326be5 | 947 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
e1a8daa2 CW |
948 | } |
949 | ||
950 | if (to != engine->last_context) { | |
e2f80391 | 951 | if (engine->last_context) |
9a6feaf0 CW |
952 | i915_gem_context_put(engine->last_context); |
953 | engine->last_context = i915_gem_context_get(to); | |
691e6415 | 954 | } |
e1a8daa2 | 955 | |
c482972a | 956 | return 0; |
a95f6a00 | 957 | } |
c482972a | 958 | |
e1a8daa2 | 959 | return do_rcs_switch(req); |
e0556841 | 960 | } |
84624813 | 961 | |
945657b4 CW |
962 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) |
963 | { | |
964 | struct intel_engine_cs *engine; | |
3033acab | 965 | struct i915_gem_timeline *timeline; |
3b3f1650 | 966 | enum intel_engine_id id; |
945657b4 | 967 | |
3033acab CW |
968 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
969 | ||
3b3f1650 | 970 | for_each_engine(engine, dev_priv, id) { |
945657b4 CW |
971 | struct drm_i915_gem_request *req; |
972 | int ret; | |
973 | ||
945657b4 CW |
974 | req = i915_gem_request_alloc(engine, dev_priv->kernel_context); |
975 | if (IS_ERR(req)) | |
976 | return PTR_ERR(req); | |
977 | ||
3033acab CW |
978 | /* Queue this switch after all other activity */ |
979 | list_for_each_entry(timeline, &dev_priv->gt.timelines, link) { | |
980 | struct drm_i915_gem_request *prev; | |
981 | struct intel_timeline *tl; | |
982 | ||
983 | tl = &timeline->engine[engine->id]; | |
984 | prev = i915_gem_active_raw(&tl->last_request, | |
985 | &dev_priv->drm.struct_mutex); | |
986 | if (prev) | |
987 | i915_sw_fence_await_sw_fence_gfp(&req->submit, | |
988 | &prev->submit, | |
989 | GFP_KERNEL); | |
990 | } | |
991 | ||
5b043f4e | 992 | ret = i915_switch_context(req); |
945657b4 CW |
993 | i915_add_request_no_flush(req); |
994 | if (ret) | |
995 | return ret; | |
996 | } | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
ec3e9963 | 1001 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 1002 | { |
ec3e9963 | 1003 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
1004 | } |
1005 | ||
84624813 BW |
1006 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1007 | struct drm_file *file) | |
1008 | { | |
84624813 BW |
1009 | struct drm_i915_gem_context_create *args = data; |
1010 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 1011 | struct i915_gem_context *ctx; |
84624813 BW |
1012 | int ret; |
1013 | ||
ec3e9963 | 1014 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
1015 | return -ENODEV; |
1016 | ||
b31e5136 CW |
1017 | if (args->pad != 0) |
1018 | return -EINVAL; | |
1019 | ||
84624813 BW |
1020 | ret = i915_mutex_lock_interruptible(dev); |
1021 | if (ret) | |
1022 | return ret; | |
1023 | ||
d624d86e | 1024 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 1025 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
1026 | if (IS_ERR(ctx)) |
1027 | return PTR_ERR(ctx); | |
84624813 | 1028 | |
821d66dd | 1029 | args->ctx_id = ctx->user_handle; |
b84cf536 | 1030 | DRM_DEBUG("HW context %d created\n", args->ctx_id); |
84624813 | 1031 | |
be636387 | 1032 | return 0; |
84624813 BW |
1033 | } |
1034 | ||
1035 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
1036 | struct drm_file *file) | |
1037 | { | |
1038 | struct drm_i915_gem_context_destroy *args = data; | |
1039 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 1040 | struct i915_gem_context *ctx; |
84624813 BW |
1041 | int ret; |
1042 | ||
b31e5136 CW |
1043 | if (args->pad != 0) |
1044 | return -EINVAL; | |
1045 | ||
821d66dd | 1046 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 1047 | return -ENOENT; |
0eea67eb | 1048 | |
84624813 BW |
1049 | ret = i915_mutex_lock_interruptible(dev); |
1050 | if (ret) | |
1051 | return ret; | |
1052 | ||
ca585b5d | 1053 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
72ad5c45 | 1054 | if (IS_ERR(ctx)) { |
84624813 | 1055 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 1056 | return PTR_ERR(ctx); |
84624813 BW |
1057 | } |
1058 | ||
d28b99ab | 1059 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
50e046b6 | 1060 | context_close(ctx); |
84624813 BW |
1061 | mutex_unlock(&dev->struct_mutex); |
1062 | ||
b84cf536 | 1063 | DRM_DEBUG("HW context %d destroyed\n", args->ctx_id); |
84624813 BW |
1064 | return 0; |
1065 | } | |
c9dc0f35 CW |
1066 | |
1067 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
1068 | struct drm_file *file) | |
1069 | { | |
1070 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1071 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1072 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1073 | int ret; |
1074 | ||
1075 | ret = i915_mutex_lock_interruptible(dev); | |
1076 | if (ret) | |
1077 | return ret; | |
1078 | ||
ca585b5d | 1079 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1080 | if (IS_ERR(ctx)) { |
1081 | mutex_unlock(&dev->struct_mutex); | |
1082 | return PTR_ERR(ctx); | |
1083 | } | |
1084 | ||
1085 | args->size = 0; | |
1086 | switch (args->param) { | |
1087 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
84102171 | 1088 | ret = -EINVAL; |
c9dc0f35 | 1089 | break; |
b1b38278 DW |
1090 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1091 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
1092 | break; | |
fa8848f2 CW |
1093 | case I915_CONTEXT_PARAM_GTT_SIZE: |
1094 | if (ctx->ppgtt) | |
1095 | args->value = ctx->ppgtt->base.total; | |
1096 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
1097 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
1098 | else | |
62106b4f | 1099 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 1100 | break; |
bc3d6744 CW |
1101 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: |
1102 | args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE); | |
1103 | break; | |
84102171 MK |
1104 | case I915_CONTEXT_PARAM_BANNABLE: |
1105 | args->value = ctx->hang_stats.bannable; | |
1106 | break; | |
c9dc0f35 CW |
1107 | default: |
1108 | ret = -EINVAL; | |
1109 | break; | |
1110 | } | |
1111 | mutex_unlock(&dev->struct_mutex); | |
1112 | ||
1113 | return ret; | |
1114 | } | |
1115 | ||
1116 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
1117 | struct drm_file *file) | |
1118 | { | |
1119 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1120 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1121 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1122 | int ret; |
1123 | ||
1124 | ret = i915_mutex_lock_interruptible(dev); | |
1125 | if (ret) | |
1126 | return ret; | |
1127 | ||
ca585b5d | 1128 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1129 | if (IS_ERR(ctx)) { |
1130 | mutex_unlock(&dev->struct_mutex); | |
1131 | return PTR_ERR(ctx); | |
1132 | } | |
1133 | ||
1134 | switch (args->param) { | |
1135 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
84102171 | 1136 | ret = -EINVAL; |
c9dc0f35 | 1137 | break; |
b1b38278 DW |
1138 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1139 | if (args->size) { | |
1140 | ret = -EINVAL; | |
1141 | } else { | |
1142 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
1143 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
bc3d6744 CW |
1144 | } |
1145 | break; | |
1146 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: | |
1147 | if (args->size) { | |
1148 | ret = -EINVAL; | |
1149 | } else { | |
1150 | if (args->value) | |
1151 | ctx->flags |= CONTEXT_NO_ERROR_CAPTURE; | |
1152 | else | |
1153 | ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE; | |
b1b38278 DW |
1154 | } |
1155 | break; | |
84102171 MK |
1156 | case I915_CONTEXT_PARAM_BANNABLE: |
1157 | if (args->size) | |
1158 | ret = -EINVAL; | |
1159 | else if (!capable(CAP_SYS_ADMIN) && !args->value) | |
1160 | ret = -EPERM; | |
1161 | else | |
1162 | ctx->hang_stats.bannable = args->value; | |
1163 | break; | |
c9dc0f35 CW |
1164 | default: |
1165 | ret = -EINVAL; | |
1166 | break; | |
1167 | } | |
1168 | mutex_unlock(&dev->struct_mutex); | |
1169 | ||
1170 | return ret; | |
1171 | } | |
d538704b CW |
1172 | |
1173 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, | |
1174 | void *data, struct drm_file *file) | |
1175 | { | |
fac5e23e | 1176 | struct drm_i915_private *dev_priv = to_i915(dev); |
d538704b CW |
1177 | struct drm_i915_reset_stats *args = data; |
1178 | struct i915_ctx_hang_stats *hs; | |
e2efd130 | 1179 | struct i915_gem_context *ctx; |
d538704b CW |
1180 | int ret; |
1181 | ||
1182 | if (args->flags || args->pad) | |
1183 | return -EINVAL; | |
1184 | ||
1185 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) | |
1186 | return -EPERM; | |
1187 | ||
bdb04614 | 1188 | ret = i915_mutex_lock_interruptible(dev); |
d538704b CW |
1189 | if (ret) |
1190 | return ret; | |
1191 | ||
ca585b5d | 1192 | ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id); |
d538704b CW |
1193 | if (IS_ERR(ctx)) { |
1194 | mutex_unlock(&dev->struct_mutex); | |
1195 | return PTR_ERR(ctx); | |
1196 | } | |
1197 | hs = &ctx->hang_stats; | |
1198 | ||
1199 | if (capable(CAP_SYS_ADMIN)) | |
1200 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1201 | else | |
1202 | args->reset_count = 0; | |
1203 | ||
1204 | args->batch_active = hs->batch_active; | |
1205 | args->batch_pending = hs->batch_pending; | |
1206 | ||
1207 | mutex_unlock(&dev->struct_mutex); | |
1208 | ||
1209 | return 0; | |
1210 | } |