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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
b731d33d BW |
96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 98 | |
b18b6bde | 99 | static void do_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
321f2ada | 100 | { |
321f2ada BW |
101 | struct drm_device *dev = ppgtt->base.dev; |
102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
103 | struct i915_address_space *vm = &ppgtt->base; | |
104 | ||
105 | if (ppgtt == dev_priv->mm.aliasing_ppgtt || | |
106 | (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) { | |
107 | ppgtt->base.cleanup(&ppgtt->base); | |
108 | return; | |
109 | } | |
110 | ||
111 | /* | |
112 | * Make sure vmas are unbound before we take down the drm_mm | |
113 | * | |
114 | * FIXME: Proper refcounting should take care of this, this shouldn't be | |
115 | * needed at all. | |
116 | */ | |
117 | if (!list_empty(&vm->active_list)) { | |
118 | struct i915_vma *vma; | |
119 | ||
120 | list_for_each_entry(vma, &vm->active_list, mm_list) | |
121 | if (WARN_ON(list_empty(&vma->vma_link) || | |
122 | list_is_singular(&vma->vma_link))) | |
123 | break; | |
124 | ||
125 | i915_gem_evict_vm(&ppgtt->base, true); | |
126 | } else { | |
127 | i915_gem_retire_requests(dev); | |
128 | i915_gem_evict_vm(&ppgtt->base, false); | |
129 | } | |
130 | ||
131 | ppgtt->base.cleanup(&ppgtt->base); | |
132 | } | |
133 | ||
b18b6bde BW |
134 | static void ppgtt_release(struct kref *kref) |
135 | { | |
136 | struct i915_hw_ppgtt *ppgtt = | |
137 | container_of(kref, struct i915_hw_ppgtt, ref); | |
138 | ||
139 | do_ppgtt_cleanup(ppgtt); | |
140 | kfree(ppgtt); | |
141 | } | |
142 | ||
b731d33d BW |
143 | static size_t get_context_alignment(struct drm_device *dev) |
144 | { | |
145 | if (IS_GEN6(dev)) | |
146 | return GEN6_CONTEXT_ALIGN; | |
147 | ||
148 | return GEN7_CONTEXT_ALIGN; | |
149 | } | |
150 | ||
254f965c BW |
151 | static int get_context_size(struct drm_device *dev) |
152 | { | |
153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
154 | int ret; | |
155 | u32 reg; | |
156 | ||
157 | switch (INTEL_INFO(dev)->gen) { | |
158 | case 6: | |
159 | reg = I915_READ(CXT_SIZE); | |
160 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
161 | break; | |
162 | case 7: | |
4f91dd6f | 163 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 164 | if (IS_HASWELL(dev)) |
a0de80a0 | 165 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
166 | else |
167 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 168 | break; |
8897644a BW |
169 | case 8: |
170 | ret = GEN8_CXT_TOTAL_SIZE; | |
171 | break; | |
254f965c BW |
172 | default: |
173 | BUG(); | |
174 | } | |
175 | ||
176 | return ret; | |
177 | } | |
178 | ||
dce3271b | 179 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 180 | { |
273497e5 | 181 | struct intel_context *ctx = container_of(ctx_ref, |
dce3271b | 182 | typeof(*ctx), ref); |
c7c48dfd | 183 | struct i915_hw_ppgtt *ppgtt = NULL; |
40521054 | 184 | |
691e6415 CW |
185 | if (ctx->obj) { |
186 | /* We refcount even the aliasing PPGTT to keep the code symmetric */ | |
187 | if (USES_PPGTT(ctx->obj->base.dev)) | |
188 | ppgtt = ctx_to_ppgtt(ctx); | |
c7c48dfd | 189 | |
691e6415 CW |
190 | /* XXX: Free up the object before tearing down the address space, in |
191 | * case we're bound in the PPGTT */ | |
192 | drm_gem_object_unreference(&ctx->obj->base); | |
193 | } | |
c7c48dfd BW |
194 | |
195 | if (ppgtt) | |
196 | kref_put(&ppgtt->ref, ppgtt_release); | |
197 | list_del(&ctx->link); | |
40521054 BW |
198 | kfree(ctx); |
199 | } | |
200 | ||
bdf4fd7e | 201 | static struct i915_hw_ppgtt * |
273497e5 | 202 | create_vm_for_ctx(struct drm_device *dev, struct intel_context *ctx) |
bdf4fd7e BW |
203 | { |
204 | struct i915_hw_ppgtt *ppgtt; | |
205 | int ret; | |
206 | ||
207 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
208 | if (!ppgtt) | |
209 | return ERR_PTR(-ENOMEM); | |
210 | ||
211 | ret = i915_gem_init_ppgtt(dev, ppgtt); | |
212 | if (ret) { | |
213 | kfree(ppgtt); | |
214 | return ERR_PTR(ret); | |
215 | } | |
216 | ||
6313c204 | 217 | ppgtt->ctx = ctx; |
bdf4fd7e BW |
218 | return ppgtt; |
219 | } | |
220 | ||
273497e5 | 221 | static struct intel_context * |
0eea67eb | 222 | __create_hw_context(struct drm_device *dev, |
146937e5 | 223 | struct drm_i915_file_private *file_priv) |
40521054 BW |
224 | { |
225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 226 | struct intel_context *ctx; |
c8c470af | 227 | int ret; |
40521054 | 228 | |
f94982b0 | 229 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
230 | if (ctx == NULL) |
231 | return ERR_PTR(-ENOMEM); | |
40521054 | 232 | |
dce3271b | 233 | kref_init(&ctx->ref); |
691e6415 | 234 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 | 235 | |
691e6415 CW |
236 | if (dev_priv->hw_context_size) { |
237 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); | |
238 | if (ctx->obj == NULL) { | |
239 | ret = -ENOMEM; | |
4615d4c9 | 240 | goto err_out; |
691e6415 | 241 | } |
4615d4c9 | 242 | |
885ac04a DA |
243 | /* |
244 | * Try to make the context utilize L3 as well as LLC. | |
245 | * | |
246 | * On VLV we don't have L3 controls in the PTEs so we | |
247 | * shouldn't touch the cache level, especially as that | |
248 | * would make the object snooped which might have a | |
249 | * negative performance impact. | |
250 | */ | |
251 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { | |
691e6415 CW |
252 | ret = i915_gem_object_set_cache_level(ctx->obj, |
253 | I915_CACHE_L3_LLC); | |
254 | /* Failure shouldn't ever happen this early */ | |
255 | if (WARN_ON(ret)) | |
256 | goto err_out; | |
257 | } | |
258 | } | |
40521054 BW |
259 | |
260 | /* Default context will never have a file_priv */ | |
691e6415 CW |
261 | if (file_priv != NULL) { |
262 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
263 | DEFAULT_CONTEXT_ID, 0, GFP_KERNEL); | |
264 | if (ret < 0) | |
265 | goto err_out; | |
266 | } else | |
267 | ret = DEFAULT_CONTEXT_ID; | |
dce3271b MK |
268 | |
269 | ctx->file_priv = file_priv; | |
c8c470af | 270 | ctx->id = ret; |
3ccfd19d BW |
271 | /* NB: Mark all slices as needing a remap so that when the context first |
272 | * loads it will restore whatever remap state already exists. If there | |
273 | * is no remap info, it will be a NOP. */ | |
274 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 275 | |
146937e5 | 276 | return ctx; |
40521054 BW |
277 | |
278 | err_out: | |
dce3271b | 279 | i915_gem_context_unreference(ctx); |
146937e5 | 280 | return ERR_PTR(ret); |
40521054 BW |
281 | } |
282 | ||
254f965c BW |
283 | /** |
284 | * The default context needs to exist per ring that uses contexts. It stores the | |
285 | * context state of the GPU for applications that don't utilize HW contexts, as | |
286 | * well as an idle case. | |
287 | */ | |
273497e5 | 288 | static struct intel_context * |
0eea67eb BW |
289 | i915_gem_create_context(struct drm_device *dev, |
290 | struct drm_i915_file_private *file_priv, | |
291 | bool create_vm) | |
254f965c | 292 | { |
42c3b603 | 293 | const bool is_global_default_ctx = file_priv == NULL; |
bdf4fd7e | 294 | struct drm_i915_private *dev_priv = dev->dev_private; |
273497e5 | 295 | struct intel_context *ctx; |
bdf4fd7e | 296 | int ret = 0; |
40521054 | 297 | |
b731d33d | 298 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 299 | |
0eea67eb | 300 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 301 | if (IS_ERR(ctx)) |
a45d0f6a | 302 | return ctx; |
40521054 | 303 | |
691e6415 | 304 | if (is_global_default_ctx && ctx->obj) { |
42c3b603 CW |
305 | /* We may need to do things with the shrinker which |
306 | * require us to immediately switch back to the default | |
307 | * context. This can cause a problem as pinning the | |
308 | * default context also requires GTT space which may not | |
309 | * be available. To avoid this we always pin the default | |
310 | * context. | |
311 | */ | |
312 | ret = i915_gem_obj_ggtt_pin(ctx->obj, | |
1ec9e26d | 313 | get_context_alignment(dev), 0); |
42c3b603 CW |
314 | if (ret) { |
315 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
316 | goto err_destroy; | |
317 | } | |
318 | } | |
319 | ||
bdf4fd7e BW |
320 | if (create_vm) { |
321 | struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx); | |
322 | ||
323 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
324 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
325 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 326 | ret = PTR_ERR(ppgtt); |
42c3b603 | 327 | goto err_unpin; |
bdf4fd7e BW |
328 | } else |
329 | ctx->vm = &ppgtt->base; | |
330 | ||
331 | /* This case is reserved for the global default context and | |
332 | * should only happen once. */ | |
42c3b603 | 333 | if (is_global_default_ctx) { |
bdf4fd7e BW |
334 | if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) { |
335 | ret = -EEXIST; | |
42c3b603 | 336 | goto err_unpin; |
bdf4fd7e BW |
337 | } |
338 | ||
339 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
bdf4fd7e | 340 | } |
c5dc5cec | 341 | } else if (USES_PPGTT(dev)) { |
bdf4fd7e BW |
342 | /* For platforms which only have aliasing PPGTT, we fake the |
343 | * address space and refcounting. */ | |
bdf4fd7e | 344 | ctx->vm = &dev_priv->mm.aliasing_ppgtt->base; |
7e0d96bc BW |
345 | kref_get(&dev_priv->mm.aliasing_ppgtt->ref); |
346 | } else | |
bdf4fd7e BW |
347 | ctx->vm = &dev_priv->gtt.base; |
348 | ||
a45d0f6a | 349 | return ctx; |
9a3b5304 | 350 | |
42c3b603 | 351 | err_unpin: |
691e6415 | 352 | if (is_global_default_ctx && ctx->obj) |
42c3b603 | 353 | i915_gem_object_ggtt_unpin(ctx->obj); |
9a3b5304 | 354 | err_destroy: |
dce3271b | 355 | i915_gem_context_unreference(ctx); |
a45d0f6a | 356 | return ERR_PTR(ret); |
254f965c BW |
357 | } |
358 | ||
acce9ffa BW |
359 | void i915_gem_context_reset(struct drm_device *dev) |
360 | { | |
361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa BW |
362 | int i; |
363 | ||
acce9ffa BW |
364 | /* Prevent the hardware from restoring the last context (which hung) on |
365 | * the next switch */ | |
366 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 367 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
273497e5 | 368 | struct intel_context *dctx = ring->default_context; |
acce9ffa BW |
369 | |
370 | /* Do a fake switch to the default context */ | |
691e6415 | 371 | if (ring->last_context == dctx) |
acce9ffa BW |
372 | continue; |
373 | ||
374 | if (!ring->last_context) | |
375 | continue; | |
376 | ||
691e6415 | 377 | if (dctx->obj && i == RCS) { |
acce9ffa | 378 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj, |
1ec9e26d | 379 | get_context_alignment(dev), 0)); |
acce9ffa BW |
380 | /* Fake a finish/inactive */ |
381 | dctx->obj->base.write_domain = 0; | |
382 | dctx->obj->active = 0; | |
383 | } | |
384 | ||
4bfad3dd VS |
385 | if (ring->last_context->obj && i == RCS) |
386 | i915_gem_object_ggtt_unpin(ring->last_context->obj); | |
387 | ||
acce9ffa BW |
388 | i915_gem_context_unreference(ring->last_context); |
389 | i915_gem_context_reference(dctx); | |
390 | ring->last_context = dctx; | |
391 | } | |
392 | } | |
393 | ||
8245be31 | 394 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
395 | { |
396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 397 | struct intel_context *ctx; |
a45d0f6a | 398 | int i; |
254f965c | 399 | |
2fa48d8d BW |
400 | /* Init should only be called once per module load. Eventually the |
401 | * restriction on the context_disabled check can be loosened. */ | |
402 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 403 | return 0; |
254f965c | 404 | |
691e6415 CW |
405 | if (HAS_HW_CONTEXTS(dev)) { |
406 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); | |
407 | if (dev_priv->hw_context_size > (1<<20)) { | |
408 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
409 | dev_priv->hw_context_size); | |
410 | dev_priv->hw_context_size = 0; | |
411 | } | |
254f965c BW |
412 | } |
413 | ||
691e6415 CW |
414 | ctx = i915_gem_create_context(dev, NULL, USES_PPGTT(dev)); |
415 | if (IS_ERR(ctx)) { | |
416 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
417 | PTR_ERR(ctx)); | |
418 | return PTR_ERR(ctx); | |
254f965c BW |
419 | } |
420 | ||
691e6415 CW |
421 | /* NB: RCS will hold a ref for all rings */ |
422 | for (i = 0; i < I915_NUM_RINGS; i++) | |
423 | dev_priv->ring[i].default_context = ctx; | |
67e3d297 | 424 | |
691e6415 | 425 | DRM_DEBUG_DRIVER("%s context support initialized\n", dev_priv->hw_context_size ? "HW" : "fake"); |
8245be31 | 426 | return 0; |
254f965c BW |
427 | } |
428 | ||
429 | void i915_gem_context_fini(struct drm_device *dev) | |
430 | { | |
431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 432 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 433 | int i; |
254f965c | 434 | |
691e6415 CW |
435 | if (dctx->obj) { |
436 | /* The only known way to stop the gpu from accessing the hw context is | |
437 | * to reset it. Do this as the very last operation to avoid confusing | |
438 | * other code, leading to spurious errors. */ | |
439 | intel_gpu_reset(dev); | |
440 | ||
441 | /* When default context is created and switched to, base object refcount | |
442 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
443 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
444 | * to default context. So we need to unreference the base object once | |
445 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
446 | * can then free the base object correctly. */ | |
447 | WARN_ON(!dev_priv->ring[RCS].last_context); | |
448 | if (dev_priv->ring[RCS].last_context == dctx) { | |
449 | /* Fake switch to NULL context */ | |
450 | WARN_ON(dctx->obj->active); | |
451 | i915_gem_object_ggtt_unpin(dctx->obj); | |
452 | i915_gem_context_unreference(dctx); | |
453 | dev_priv->ring[RCS].last_context = NULL; | |
454 | } | |
d3b448d9 CW |
455 | |
456 | i915_gem_object_ggtt_unpin(dctx->obj); | |
67e3d297 BW |
457 | } |
458 | ||
459 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 460 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
67e3d297 BW |
461 | |
462 | if (ring->last_context) | |
463 | i915_gem_context_unreference(ring->last_context); | |
464 | ||
465 | ring->default_context = NULL; | |
0009e46c | 466 | ring->last_context = NULL; |
71b76d00 BW |
467 | } |
468 | ||
dce3271b | 469 | i915_gem_context_unreference(dctx); |
254f965c BW |
470 | } |
471 | ||
2fa48d8d BW |
472 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
473 | { | |
a4872ba6 | 474 | struct intel_engine_cs *ring; |
2fa48d8d BW |
475 | int ret, i; |
476 | ||
bdf4fd7e BW |
477 | /* This is the only place the aliasing PPGTT gets enabled, which means |
478 | * it has to happen before we bail on reset */ | |
479 | if (dev_priv->mm.aliasing_ppgtt) { | |
480 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
481 | ppgtt->enable(ppgtt); | |
482 | } | |
483 | ||
2fa48d8d BW |
484 | /* FIXME: We should make this work, even in reset */ |
485 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
486 | return 0; | |
487 | ||
488 | BUG_ON(!dev_priv->ring[RCS].default_context); | |
bdf4fd7e | 489 | |
2fa48d8d | 490 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 491 | ret = i915_switch_context(ring, ring->default_context); |
2fa48d8d BW |
492 | if (ret) |
493 | return ret; | |
494 | } | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
40521054 BW |
499 | static int context_idr_cleanup(int id, void *p, void *data) |
500 | { | |
273497e5 | 501 | struct intel_context *ctx = p; |
40521054 | 502 | |
dce3271b | 503 | i915_gem_context_unreference(ctx); |
40521054 | 504 | return 0; |
254f965c BW |
505 | } |
506 | ||
e422b888 BW |
507 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
508 | { | |
509 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 510 | struct intel_context *ctx; |
e422b888 BW |
511 | |
512 | idr_init(&file_priv->context_idr); | |
513 | ||
0eea67eb | 514 | mutex_lock(&dev->struct_mutex); |
f83d6518 | 515 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
0eea67eb BW |
516 | mutex_unlock(&dev->struct_mutex); |
517 | ||
f83d6518 | 518 | if (IS_ERR(ctx)) { |
0eea67eb | 519 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 520 | return PTR_ERR(ctx); |
0eea67eb BW |
521 | } |
522 | ||
e422b888 BW |
523 | return 0; |
524 | } | |
525 | ||
254f965c BW |
526 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
527 | { | |
40521054 | 528 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 529 | |
73c273eb | 530 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 531 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
532 | } |
533 | ||
273497e5 | 534 | struct intel_context * |
40521054 BW |
535 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
536 | { | |
273497e5 | 537 | struct intel_context *ctx; |
72ad5c45 | 538 | |
273497e5 | 539 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
540 | if (!ctx) |
541 | return ERR_PTR(-ENOENT); | |
542 | ||
543 | return ctx; | |
254f965c | 544 | } |
e0556841 BW |
545 | |
546 | static inline int | |
a4872ba6 | 547 | mi_set_context(struct intel_engine_cs *ring, |
273497e5 | 548 | struct intel_context *new_context, |
e0556841 BW |
549 | u32 hw_flags) |
550 | { | |
551 | int ret; | |
552 | ||
12b0286f BW |
553 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
554 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
555 | * explicitly, so we rely on the value at ring init, stored in | |
556 | * itlb_before_ctx_switch. | |
557 | */ | |
057f6a8a | 558 | if (IS_GEN6(ring->dev)) { |
ac82ea2e | 559 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
560 | if (ret) |
561 | return ret; | |
562 | } | |
563 | ||
e37ec39b | 564 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
565 | if (ret) |
566 | return ret; | |
567 | ||
b3f797ac | 568 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
64bed788 | 569 | if (INTEL_INFO(ring->dev)->gen >= 7) |
e37ec39b BW |
570 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
571 | else | |
572 | intel_ring_emit(ring, MI_NOOP); | |
573 | ||
e0556841 BW |
574 | intel_ring_emit(ring, MI_NOOP); |
575 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 576 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) | |
e0556841 BW |
577 | MI_MM_SPACE_GTT | |
578 | MI_SAVE_EXT_STATE_EN | | |
579 | MI_RESTORE_EXT_STATE_EN | | |
580 | hw_flags); | |
2b7e8082 VS |
581 | /* |
582 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
583 | * WaMiSetContext_Hang:snb,ivb,vlv | |
584 | */ | |
e0556841 BW |
585 | intel_ring_emit(ring, MI_NOOP); |
586 | ||
64bed788 | 587 | if (INTEL_INFO(ring->dev)->gen >= 7) |
e37ec39b BW |
588 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
589 | else | |
590 | intel_ring_emit(ring, MI_NOOP); | |
591 | ||
e0556841 BW |
592 | intel_ring_advance(ring); |
593 | ||
594 | return ret; | |
595 | } | |
596 | ||
a4872ba6 | 597 | static int do_switch(struct intel_engine_cs *ring, |
273497e5 | 598 | struct intel_context *to) |
e0556841 | 599 | { |
6f65e29a | 600 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
273497e5 | 601 | struct intel_context *from = ring->last_context; |
7e0d96bc | 602 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to); |
e0556841 | 603 | u32 hw_flags = 0; |
967ab6b1 | 604 | bool uninitialized = false; |
3ccfd19d | 605 | int ret, i; |
e0556841 | 606 | |
67e3d297 BW |
607 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
608 | BUG_ON(from->obj == NULL); | |
609 | BUG_ON(!i915_gem_obj_is_pinned(from->obj)); | |
610 | } | |
e0556841 | 611 | |
14d8ec54 | 612 | if (from == to && !to->remap_slice) |
9a3b5304 CW |
613 | return 0; |
614 | ||
7e0d96bc BW |
615 | /* Trying to pin first makes error handling easier. */ |
616 | if (ring == &dev_priv->ring[RCS]) { | |
617 | ret = i915_gem_obj_ggtt_pin(to->obj, | |
1ec9e26d | 618 | get_context_alignment(ring->dev), 0); |
7e0d96bc BW |
619 | if (ret) |
620 | return ret; | |
67e3d297 BW |
621 | } |
622 | ||
acc240d4 DV |
623 | /* |
624 | * Pin can switch back to the default context if we end up calling into | |
625 | * evict_everything - as a last ditch gtt defrag effort that also | |
626 | * switches to the default context. Hence we need to reload from here. | |
627 | */ | |
628 | from = ring->last_context; | |
629 | ||
7e0d96bc BW |
630 | if (USES_FULL_PPGTT(ring->dev)) { |
631 | ret = ppgtt->switch_mm(ppgtt, ring, false); | |
632 | if (ret) | |
633 | goto unpin_out; | |
634 | } | |
635 | ||
636 | if (ring != &dev_priv->ring[RCS]) { | |
637 | if (from) | |
638 | i915_gem_context_unreference(from); | |
639 | goto done; | |
640 | } | |
641 | ||
acc240d4 DV |
642 | /* |
643 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
644 | * that thanks to write = false in this call and us not setting any gpu |
645 | * write domains when putting a context object onto the active list | |
646 | * (when switching away from it), this won't block. | |
acc240d4 DV |
647 | * |
648 | * XXX: We need a real interface to do this instead of trickery. | |
649 | */ | |
d3373a24 | 650 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); |
7e0d96bc BW |
651 | if (ret) |
652 | goto unpin_out; | |
d3373a24 | 653 | |
6f65e29a BW |
654 | if (!to->obj->has_global_gtt_mapping) { |
655 | struct i915_vma *vma = i915_gem_obj_to_vma(to->obj, | |
656 | &dev_priv->gtt.base); | |
657 | vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND); | |
658 | } | |
3af7b857 | 659 | |
3fac8978 | 660 | if (!to->is_initialized || i915_gem_context_is_default(to)) |
e0556841 | 661 | hw_flags |= MI_RESTORE_INHIBIT; |
e0556841 | 662 | |
e0556841 | 663 | ret = mi_set_context(ring, to, hw_flags); |
7e0d96bc BW |
664 | if (ret) |
665 | goto unpin_out; | |
e0556841 | 666 | |
3ccfd19d BW |
667 | for (i = 0; i < MAX_L3_SLICES; i++) { |
668 | if (!(to->remap_slice & (1<<i))) | |
669 | continue; | |
670 | ||
671 | ret = i915_gem_l3_remap(ring, i); | |
672 | /* If it failed, try again next round */ | |
673 | if (ret) | |
674 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
675 | else | |
676 | to->remap_slice &= ~(1<<i); | |
677 | } | |
678 | ||
e0556841 BW |
679 | /* The backing object for the context is done after switching to the |
680 | * *next* context. Therefore we cannot retire the previous context until | |
681 | * the next context has already started running. In fact, the below code | |
682 | * is a bit suboptimal because the retiring can occur simply after the | |
683 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
684 | */ | |
112522f6 CW |
685 | if (from != NULL) { |
686 | from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; | |
e2d05a8b | 687 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring); |
e0556841 BW |
688 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
689 | * whole damn pipeline, we don't need to explicitly mark the | |
690 | * object dirty. The only exception is that the context must be | |
691 | * correct in case the object gets swapped out. Ideally we'd be | |
692 | * able to defer doing this until we know the object would be | |
693 | * swapped, but there is no way to do that yet. | |
694 | */ | |
112522f6 CW |
695 | from->obj->dirty = 1; |
696 | BUG_ON(from->obj->ring != ring); | |
697 | ||
c0321e2c | 698 | /* obj is kept alive until the next request by its active ref */ |
d7f46fc4 | 699 | i915_gem_object_ggtt_unpin(from->obj); |
112522f6 | 700 | i915_gem_context_unreference(from); |
e0556841 BW |
701 | } |
702 | ||
967ab6b1 CW |
703 | uninitialized = !to->is_initialized && from == NULL; |
704 | to->is_initialized = true; | |
705 | ||
67e3d297 | 706 | done: |
112522f6 CW |
707 | i915_gem_context_reference(to); |
708 | ring->last_context = to; | |
e0556841 | 709 | |
967ab6b1 | 710 | if (uninitialized) { |
46470fc9 MK |
711 | ret = i915_gem_render_state_init(ring); |
712 | if (ret) | |
713 | DRM_ERROR("init render state: %d\n", ret); | |
714 | } | |
715 | ||
e0556841 | 716 | return 0; |
7e0d96bc BW |
717 | |
718 | unpin_out: | |
719 | if (ring->id == RCS) | |
720 | i915_gem_object_ggtt_unpin(to->obj); | |
721 | return ret; | |
e0556841 BW |
722 | } |
723 | ||
724 | /** | |
725 | * i915_switch_context() - perform a GPU context switch. | |
726 | * @ring: ring for which we'll execute the context switch | |
96a6f0f1 | 727 | * @to: the context to switch to |
e0556841 BW |
728 | * |
729 | * The context life cycle is simple. The context refcount is incremented and | |
730 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
731 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
732 | * object while letting the normal object tracking destroy the backing BO. | |
733 | */ | |
a4872ba6 | 734 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 | 735 | struct intel_context *to) |
e0556841 BW |
736 | { |
737 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 738 | |
0eea67eb BW |
739 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
740 | ||
691e6415 CW |
741 | if (to->obj == NULL) { /* We have the fake context */ |
742 | if (to != ring->last_context) { | |
743 | i915_gem_context_reference(to); | |
744 | if (ring->last_context) | |
745 | i915_gem_context_unreference(ring->last_context); | |
746 | ring->last_context = to; | |
747 | } | |
c482972a | 748 | return 0; |
a95f6a00 | 749 | } |
c482972a | 750 | |
67e3d297 | 751 | return do_switch(ring, to); |
e0556841 | 752 | } |
84624813 | 753 | |
691e6415 CW |
754 | static bool hw_context_enabled(struct drm_device *dev) |
755 | { | |
756 | return to_i915(dev)->hw_context_size; | |
757 | } | |
758 | ||
84624813 BW |
759 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
760 | struct drm_file *file) | |
761 | { | |
84624813 BW |
762 | struct drm_i915_gem_context_create *args = data; |
763 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 764 | struct intel_context *ctx; |
84624813 BW |
765 | int ret; |
766 | ||
691e6415 | 767 | if (!hw_context_enabled(dev)) |
5fa8be65 DV |
768 | return -ENODEV; |
769 | ||
84624813 BW |
770 | ret = i915_mutex_lock_interruptible(dev); |
771 | if (ret) | |
772 | return ret; | |
773 | ||
7e0d96bc | 774 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
84624813 | 775 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
776 | if (IS_ERR(ctx)) |
777 | return PTR_ERR(ctx); | |
84624813 BW |
778 | |
779 | args->ctx_id = ctx->id; | |
780 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
781 | ||
be636387 | 782 | return 0; |
84624813 BW |
783 | } |
784 | ||
785 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
786 | struct drm_file *file) | |
787 | { | |
788 | struct drm_i915_gem_context_destroy *args = data; | |
789 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 790 | struct intel_context *ctx; |
84624813 BW |
791 | int ret; |
792 | ||
0eea67eb | 793 | if (args->ctx_id == DEFAULT_CONTEXT_ID) |
c2cf2416 | 794 | return -ENOENT; |
0eea67eb | 795 | |
84624813 BW |
796 | ret = i915_mutex_lock_interruptible(dev); |
797 | if (ret) | |
798 | return ret; | |
799 | ||
800 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 801 | if (IS_ERR(ctx)) { |
84624813 | 802 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 803 | return PTR_ERR(ctx); |
84624813 BW |
804 | } |
805 | ||
dce3271b MK |
806 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
807 | i915_gem_context_unreference(ctx); | |
84624813 BW |
808 | mutex_unlock(&dev->struct_mutex); |
809 | ||
810 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
811 | return 0; | |
812 | } |