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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
b2e862d0 CW |
93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
94 | ||
40521054 BW |
95 | /* This is a HW constraint. The value below is the largest known requirement |
96 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
97 | * part. It should be safe to decrease this, but it's more future proof as is. | |
98 | */ | |
b731d33d | 99 | #define GEN6_CONTEXT_ALIGN (64<<10) |
f51455d4 | 100 | #define GEN7_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT |
40521054 | 101 | |
c033666a | 102 | static size_t get_context_alignment(struct drm_i915_private *dev_priv) |
b731d33d | 103 | { |
c033666a | 104 | if (IS_GEN6(dev_priv)) |
b731d33d BW |
105 | return GEN6_CONTEXT_ALIGN; |
106 | ||
107 | return GEN7_CONTEXT_ALIGN; | |
108 | } | |
109 | ||
c033666a | 110 | static int get_context_size(struct drm_i915_private *dev_priv) |
254f965c | 111 | { |
254f965c BW |
112 | int ret; |
113 | u32 reg; | |
114 | ||
c033666a | 115 | switch (INTEL_GEN(dev_priv)) { |
254f965c BW |
116 | case 6: |
117 | reg = I915_READ(CXT_SIZE); | |
118 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
119 | break; | |
120 | case 7: | |
4f91dd6f | 121 | reg = I915_READ(GEN7_CXT_SIZE); |
c033666a | 122 | if (IS_HASWELL(dev_priv)) |
a0de80a0 | 123 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
124 | else |
125 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 126 | break; |
8897644a BW |
127 | case 8: |
128 | ret = GEN8_CXT_TOTAL_SIZE; | |
129 | break; | |
254f965c BW |
130 | default: |
131 | BUG(); | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
dce3271b | 137 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 138 | { |
e2efd130 | 139 | struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
bca44d80 | 140 | int i; |
40521054 | 141 | |
91c8a326 | 142 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
198c974d | 143 | trace_i915_context_free(ctx); |
6095868a | 144 | GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); |
198c974d | 145 | |
ae6c4806 DV |
146 | i915_ppgtt_put(ctx->ppgtt); |
147 | ||
bca44d80 CW |
148 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
149 | struct intel_context *ce = &ctx->engine[i]; | |
150 | ||
151 | if (!ce->state) | |
152 | continue; | |
153 | ||
154 | WARN_ON(ce->pin_count); | |
dca33ecc | 155 | if (ce->ring) |
7e37f889 | 156 | intel_ring_free(ce->ring); |
bca44d80 | 157 | |
f8a7fde4 | 158 | __i915_gem_object_release_unless_active(ce->state->obj); |
bca44d80 CW |
159 | } |
160 | ||
562f5d45 | 161 | kfree(ctx->name); |
c84455b4 | 162 | put_pid(ctx->pid); |
c7c48dfd | 163 | list_del(&ctx->link); |
5d1808ec CW |
164 | |
165 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); | |
40521054 BW |
166 | kfree(ctx); |
167 | } | |
168 | ||
793b61ea | 169 | static struct drm_i915_gem_object * |
bf9e8429 | 170 | alloc_context_obj(struct drm_i915_private *dev_priv, u64 size) |
aa0c13da OM |
171 | { |
172 | struct drm_i915_gem_object *obj; | |
173 | int ret; | |
174 | ||
bf9e8429 | 175 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 176 | |
12d79d78 | 177 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
178 | if (IS_ERR(obj)) |
179 | return obj; | |
aa0c13da OM |
180 | |
181 | /* | |
182 | * Try to make the context utilize L3 as well as LLC. | |
183 | * | |
184 | * On VLV we don't have L3 controls in the PTEs so we | |
185 | * shouldn't touch the cache level, especially as that | |
186 | * would make the object snooped which might have a | |
187 | * negative performance impact. | |
4d3e904c WB |
188 | * |
189 | * Snooping is required on non-llc platforms in execlist | |
190 | * mode, but since all GGTT accesses use PAT entry 0 we | |
191 | * get snooping anyway regardless of cache_level. | |
192 | * | |
193 | * This is only applicable for Ivy Bridge devices since | |
194 | * later platforms don't have L3 control bits in the PTE. | |
aa0c13da | 195 | */ |
12d79d78 | 196 | if (IS_IVYBRIDGE(dev_priv)) { |
aa0c13da OM |
197 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
198 | /* Failure shouldn't ever happen this early */ | |
199 | if (WARN_ON(ret)) { | |
f8c417cd | 200 | i915_gem_object_put(obj); |
aa0c13da OM |
201 | return ERR_PTR(ret); |
202 | } | |
203 | } | |
204 | ||
205 | return obj; | |
206 | } | |
207 | ||
50e046b6 CW |
208 | static void context_close(struct i915_gem_context *ctx) |
209 | { | |
6095868a | 210 | i915_gem_context_set_closed(ctx); |
50e046b6 CW |
211 | if (ctx->ppgtt) |
212 | i915_ppgtt_close(&ctx->ppgtt->base); | |
213 | ctx->file_priv = ERR_PTR(-EBADF); | |
214 | i915_gem_context_put(ctx); | |
215 | } | |
216 | ||
5d1808ec CW |
217 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
218 | { | |
219 | int ret; | |
220 | ||
221 | ret = ida_simple_get(&dev_priv->context_hw_ida, | |
222 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
223 | if (ret < 0) { | |
224 | /* Contexts are only released when no longer active. | |
225 | * Flush any pending retires to hopefully release some | |
226 | * stale contexts and try again. | |
227 | */ | |
c033666a | 228 | i915_gem_retire_requests(dev_priv); |
5d1808ec CW |
229 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
230 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
231 | if (ret < 0) | |
232 | return ret; | |
233 | } | |
234 | ||
235 | *out = ret; | |
236 | return 0; | |
237 | } | |
238 | ||
e2efd130 | 239 | static struct i915_gem_context * |
bf9e8429 | 240 | __create_hw_context(struct drm_i915_private *dev_priv, |
ee960be7 | 241 | struct drm_i915_file_private *file_priv) |
40521054 | 242 | { |
e2efd130 | 243 | struct i915_gem_context *ctx; |
c8c470af | 244 | int ret; |
40521054 | 245 | |
f94982b0 | 246 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
247 | if (ctx == NULL) |
248 | return ERR_PTR(-ENOMEM); | |
40521054 | 249 | |
5d1808ec CW |
250 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
251 | if (ret) { | |
252 | kfree(ctx); | |
253 | return ERR_PTR(ret); | |
254 | } | |
255 | ||
dce3271b | 256 | kref_init(&ctx->ref); |
691e6415 | 257 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 258 | ctx->i915 = dev_priv; |
40521054 | 259 | |
0cb26a8e CW |
260 | ctx->ggtt_alignment = get_context_alignment(dev_priv); |
261 | ||
691e6415 | 262 | if (dev_priv->hw_context_size) { |
bf3783e5 CW |
263 | struct drm_i915_gem_object *obj; |
264 | struct i915_vma *vma; | |
265 | ||
bf9e8429 | 266 | obj = alloc_context_obj(dev_priv, dev_priv->hw_context_size); |
aa0c13da OM |
267 | if (IS_ERR(obj)) { |
268 | ret = PTR_ERR(obj); | |
4615d4c9 | 269 | goto err_out; |
691e6415 | 270 | } |
bf3783e5 | 271 | |
a01cb37a | 272 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
bf3783e5 CW |
273 | if (IS_ERR(vma)) { |
274 | i915_gem_object_put(obj); | |
275 | ret = PTR_ERR(vma); | |
276 | goto err_out; | |
277 | } | |
278 | ||
279 | ctx->engine[RCS].state = vma; | |
691e6415 | 280 | } |
40521054 BW |
281 | |
282 | /* Default context will never have a file_priv */ | |
562f5d45 CW |
283 | ret = DEFAULT_CONTEXT_HANDLE; |
284 | if (file_priv) { | |
691e6415 | 285 | ret = idr_alloc(&file_priv->context_idr, ctx, |
821d66dd | 286 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
287 | if (ret < 0) |
288 | goto err_out; | |
562f5d45 CW |
289 | } |
290 | ctx->user_handle = ret; | |
dce3271b MK |
291 | |
292 | ctx->file_priv = file_priv; | |
562f5d45 | 293 | if (file_priv) { |
c84455b4 | 294 | ctx->pid = get_task_pid(current, PIDTYPE_PID); |
562f5d45 CW |
295 | ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x", |
296 | current->comm, | |
297 | pid_nr(ctx->pid), | |
298 | ctx->user_handle); | |
299 | if (!ctx->name) { | |
300 | ret = -ENOMEM; | |
301 | goto err_pid; | |
302 | } | |
303 | } | |
c84455b4 | 304 | |
3ccfd19d BW |
305 | /* NB: Mark all slices as needing a remap so that when the context first |
306 | * loads it will restore whatever remap state already exists. If there | |
307 | * is no remap info, it will be a NOP. */ | |
b2e862d0 | 308 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
40521054 | 309 | |
6095868a | 310 | i915_gem_context_set_bannable(ctx); |
bcd794c2 | 311 | ctx->ring_size = 4 * PAGE_SIZE; |
c01fc532 ZW |
312 | ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) << |
313 | GEN8_CTX_ADDRESSING_MODE_SHIFT; | |
676fa572 | 314 | |
d3ef1af6 DCS |
315 | /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not |
316 | * present or not in use we still need a small bias as ring wraparound | |
317 | * at offset 0 sometimes hangs. No idea why. | |
318 | */ | |
319 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) | |
320 | ctx->ggtt_offset_bias = GUC_WOPCM_TOP; | |
321 | else | |
f51455d4 | 322 | ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE; |
d3ef1af6 | 323 | |
146937e5 | 324 | return ctx; |
40521054 | 325 | |
562f5d45 CW |
326 | err_pid: |
327 | put_pid(ctx->pid); | |
328 | idr_remove(&file_priv->context_idr, ctx->user_handle); | |
40521054 | 329 | err_out: |
50e046b6 | 330 | context_close(ctx); |
146937e5 | 331 | return ERR_PTR(ret); |
40521054 BW |
332 | } |
333 | ||
254f965c BW |
334 | /** |
335 | * The default context needs to exist per ring that uses contexts. It stores the | |
336 | * context state of the GPU for applications that don't utilize HW contexts, as | |
337 | * well as an idle case. | |
338 | */ | |
e2efd130 | 339 | static struct i915_gem_context * |
bf9e8429 | 340 | i915_gem_create_context(struct drm_i915_private *dev_priv, |
d624d86e | 341 | struct drm_i915_file_private *file_priv) |
254f965c | 342 | { |
e2efd130 | 343 | struct i915_gem_context *ctx; |
40521054 | 344 | |
bf9e8429 | 345 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
40521054 | 346 | |
bf9e8429 | 347 | ctx = __create_hw_context(dev_priv, file_priv); |
146937e5 | 348 | if (IS_ERR(ctx)) |
a45d0f6a | 349 | return ctx; |
40521054 | 350 | |
bf9e8429 | 351 | if (USES_FULL_PPGTT(dev_priv)) { |
80b204bc | 352 | struct i915_hw_ppgtt *ppgtt; |
bdf4fd7e | 353 | |
bf9e8429 | 354 | ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name); |
c6aab916 | 355 | if (IS_ERR(ppgtt)) { |
0eea67eb BW |
356 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
357 | PTR_ERR(ppgtt)); | |
c6aab916 | 358 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
50e046b6 | 359 | context_close(ctx); |
c6aab916 | 360 | return ERR_CAST(ppgtt); |
ae6c4806 DV |
361 | } |
362 | ||
363 | ctx->ppgtt = ppgtt; | |
364 | } | |
bdf4fd7e | 365 | |
198c974d DCS |
366 | trace_i915_context_create(ctx); |
367 | ||
a45d0f6a | 368 | return ctx; |
254f965c BW |
369 | } |
370 | ||
c8c35799 ZW |
371 | /** |
372 | * i915_gem_context_create_gvt - create a GVT GEM context | |
373 | * @dev: drm device * | |
374 | * | |
375 | * This function is used to create a GVT specific GEM context. | |
376 | * | |
377 | * Returns: | |
378 | * pointer to i915_gem_context on success, error pointer if failed | |
379 | * | |
380 | */ | |
381 | struct i915_gem_context * | |
382 | i915_gem_context_create_gvt(struct drm_device *dev) | |
383 | { | |
384 | struct i915_gem_context *ctx; | |
385 | int ret; | |
386 | ||
387 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
388 | return ERR_PTR(-ENODEV); | |
389 | ||
390 | ret = i915_mutex_lock_interruptible(dev); | |
391 | if (ret) | |
392 | return ERR_PTR(ret); | |
393 | ||
984ff29f | 394 | ctx = __create_hw_context(to_i915(dev), NULL); |
c8c35799 ZW |
395 | if (IS_ERR(ctx)) |
396 | goto out; | |
397 | ||
984ff29f | 398 | ctx->file_priv = ERR_PTR(-EBADF); |
6095868a CW |
399 | i915_gem_context_set_closed(ctx); /* not user accessible */ |
400 | i915_gem_context_clear_bannable(ctx); | |
401 | i915_gem_context_set_force_single_submission(ctx); | |
c8c35799 | 402 | ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */ |
984ff29f CW |
403 | |
404 | GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); | |
c8c35799 ZW |
405 | out: |
406 | mutex_unlock(&dev->struct_mutex); | |
407 | return ctx; | |
408 | } | |
409 | ||
bf9e8429 | 410 | int i915_gem_context_init(struct drm_i915_private *dev_priv) |
254f965c | 411 | { |
e2efd130 | 412 | struct i915_gem_context *ctx; |
254f965c | 413 | |
2fa48d8d BW |
414 | /* Init should only be called once per module load. Eventually the |
415 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 416 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 417 | return 0; |
254f965c | 418 | |
c033666a CW |
419 | if (intel_vgpu_active(dev_priv) && |
420 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { | |
a0bd6c31 ZL |
421 | if (!i915.enable_execlists) { |
422 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
423 | return -EINVAL; | |
424 | } | |
425 | } | |
426 | ||
5d1808ec CW |
427 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
428 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); | |
429 | ida_init(&dev_priv->context_hw_ida); | |
430 | ||
ede7d42b OM |
431 | if (i915.enable_execlists) { |
432 | /* NB: intentionally left blank. We will allocate our own | |
433 | * backing objects as we need them, thank you very much */ | |
434 | dev_priv->hw_context_size = 0; | |
c033666a CW |
435 | } else if (HAS_HW_CONTEXTS(dev_priv)) { |
436 | dev_priv->hw_context_size = | |
f51455d4 CW |
437 | round_up(get_context_size(dev_priv), |
438 | I915_GTT_PAGE_SIZE); | |
691e6415 CW |
439 | if (dev_priv->hw_context_size > (1<<20)) { |
440 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
441 | dev_priv->hw_context_size); | |
442 | dev_priv->hw_context_size = 0; | |
443 | } | |
254f965c BW |
444 | } |
445 | ||
bf9e8429 | 446 | ctx = i915_gem_create_context(dev_priv, NULL); |
691e6415 CW |
447 | if (IS_ERR(ctx)) { |
448 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
449 | PTR_ERR(ctx)); | |
450 | return PTR_ERR(ctx); | |
254f965c BW |
451 | } |
452 | ||
6095868a | 453 | i915_gem_context_clear_bannable(ctx); |
9f792eba | 454 | ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */ |
ed54c1a1 | 455 | dev_priv->kernel_context = ctx; |
67e3d297 | 456 | |
984ff29f CW |
457 | GEM_BUG_ON(!i915_gem_context_is_kernel(ctx)); |
458 | ||
ede7d42b OM |
459 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
460 | i915.enable_execlists ? "LR" : | |
461 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 462 | return 0; |
254f965c BW |
463 | } |
464 | ||
b2e862d0 CW |
465 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
466 | { | |
467 | struct intel_engine_cs *engine; | |
3b3f1650 | 468 | enum intel_engine_id id; |
b2e862d0 | 469 | |
91c8a326 | 470 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 471 | |
3b3f1650 | 472 | for_each_engine(engine, dev_priv, id) { |
e8a9c58f CW |
473 | engine->legacy_active_context = NULL; |
474 | ||
475 | if (!engine->last_retired_context) | |
476 | continue; | |
477 | ||
478 | engine->context_unpin(engine, engine->last_retired_context); | |
479 | engine->last_retired_context = NULL; | |
b2e862d0 CW |
480 | } |
481 | ||
c7c3c07d CW |
482 | /* Force the GPU state to be restored on enabling */ |
483 | if (!i915.enable_execlists) { | |
a168b2d8 CW |
484 | struct i915_gem_context *ctx; |
485 | ||
486 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
487 | if (!i915_gem_context_is_default(ctx)) | |
488 | continue; | |
489 | ||
3b3f1650 | 490 | for_each_engine(engine, dev_priv, id) |
a168b2d8 CW |
491 | ctx->engine[engine->id].initialised = false; |
492 | ||
493 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); | |
494 | } | |
495 | ||
3b3f1650 | 496 | for_each_engine(engine, dev_priv, id) { |
c7c3c07d CW |
497 | struct intel_context *kce = |
498 | &dev_priv->kernel_context->engine[engine->id]; | |
499 | ||
500 | kce->initialised = true; | |
501 | } | |
502 | } | |
b2e862d0 CW |
503 | } |
504 | ||
cb15d9f8 | 505 | void i915_gem_context_fini(struct drm_i915_private *dev_priv) |
254f965c | 506 | { |
e2efd130 | 507 | struct i915_gem_context *dctx = dev_priv->kernel_context; |
b2e862d0 | 508 | |
cb15d9f8 | 509 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 510 | |
984ff29f CW |
511 | GEM_BUG_ON(!i915_gem_context_is_kernel(dctx)); |
512 | ||
50e046b6 | 513 | context_close(dctx); |
ed54c1a1 | 514 | dev_priv->kernel_context = NULL; |
5d1808ec CW |
515 | |
516 | ida_destroy(&dev_priv->context_hw_ida); | |
254f965c BW |
517 | } |
518 | ||
40521054 BW |
519 | static int context_idr_cleanup(int id, void *p, void *data) |
520 | { | |
e2efd130 | 521 | struct i915_gem_context *ctx = p; |
40521054 | 522 | |
50e046b6 | 523 | context_close(ctx); |
40521054 | 524 | return 0; |
254f965c BW |
525 | } |
526 | ||
e422b888 BW |
527 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
528 | { | |
529 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 530 | struct i915_gem_context *ctx; |
e422b888 BW |
531 | |
532 | idr_init(&file_priv->context_idr); | |
533 | ||
0eea67eb | 534 | mutex_lock(&dev->struct_mutex); |
bf9e8429 | 535 | ctx = i915_gem_create_context(to_i915(dev), file_priv); |
0eea67eb BW |
536 | mutex_unlock(&dev->struct_mutex); |
537 | ||
984ff29f CW |
538 | GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); |
539 | ||
f83d6518 | 540 | if (IS_ERR(ctx)) { |
0eea67eb | 541 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 542 | return PTR_ERR(ctx); |
0eea67eb BW |
543 | } |
544 | ||
e422b888 BW |
545 | return 0; |
546 | } | |
547 | ||
254f965c BW |
548 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
549 | { | |
40521054 | 550 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 551 | |
499f2697 CW |
552 | lockdep_assert_held(&dev->struct_mutex); |
553 | ||
73c273eb | 554 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 555 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
556 | } |
557 | ||
e0556841 | 558 | static inline int |
1d719cda | 559 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 560 | { |
c033666a | 561 | struct drm_i915_private *dev_priv = req->i915; |
7e37f889 | 562 | struct intel_ring *ring = req->ring; |
4a570db5 | 563 | struct intel_engine_cs *engine = req->engine; |
3b3f1650 | 564 | enum intel_engine_id id; |
e80f14b6 | 565 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
566 | const int num_rings = |
567 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
39df9190 | 568 | i915.semaphores ? |
c1bb1145 | 569 | INTEL_INFO(dev_priv)->num_rings - 1 : |
2c550183 | 570 | 0; |
b4ac5afc | 571 | int len, ret; |
e0556841 | 572 | |
12b0286f BW |
573 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
574 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
575 | * explicitly, so we rely on the value at ring init, stored in | |
576 | * itlb_before_ctx_switch. | |
577 | */ | |
c033666a | 578 | if (IS_GEN6(dev_priv)) { |
7c9cf4e3 | 579 | ret = engine->emit_flush(req, EMIT_INVALIDATE); |
12b0286f BW |
580 | if (ret) |
581 | return ret; | |
582 | } | |
583 | ||
e80f14b6 | 584 | /* These flags are for resource streamer on HSW+ */ |
c033666a | 585 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
4c436d55 | 586 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
c033666a | 587 | else if (INTEL_GEN(dev_priv) < 8) |
e80f14b6 BW |
588 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
589 | ||
2c550183 CW |
590 | |
591 | len = 4; | |
c033666a | 592 | if (INTEL_GEN(dev_priv) >= 7) |
e9135c4f | 593 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
2c550183 | 594 | |
5fb9de1a | 595 | ret = intel_ring_begin(req, len); |
e0556841 BW |
596 | if (ret) |
597 | return ret; | |
598 | ||
b3f797ac | 599 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
c033666a | 600 | if (INTEL_GEN(dev_priv) >= 7) { |
b5321f30 | 601 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
602 | if (num_rings) { |
603 | struct intel_engine_cs *signaller; | |
604 | ||
b5321f30 | 605 | intel_ring_emit(ring, |
e2f80391 | 606 | MI_LOAD_REGISTER_IMM(num_rings)); |
3b3f1650 | 607 | for_each_engine(signaller, dev_priv, id) { |
e2f80391 | 608 | if (signaller == engine) |
2c550183 CW |
609 | continue; |
610 | ||
b5321f30 | 611 | intel_ring_emit_reg(ring, |
e2f80391 | 612 | RING_PSMI_CTL(signaller->mmio_base)); |
b5321f30 | 613 | intel_ring_emit(ring, |
e2f80391 | 614 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
2c550183 CW |
615 | } |
616 | } | |
617 | } | |
e37ec39b | 618 | |
b5321f30 CW |
619 | intel_ring_emit(ring, MI_NOOP); |
620 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
bde13ebd CW |
621 | intel_ring_emit(ring, |
622 | i915_ggtt_offset(req->ctx->engine[RCS].state) | flags); | |
2b7e8082 VS |
623 | /* |
624 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
625 | * WaMiSetContext_Hang:snb,ivb,vlv | |
626 | */ | |
b5321f30 | 627 | intel_ring_emit(ring, MI_NOOP); |
e0556841 | 628 | |
c033666a | 629 | if (INTEL_GEN(dev_priv) >= 7) { |
2c550183 CW |
630 | if (num_rings) { |
631 | struct intel_engine_cs *signaller; | |
e9135c4f | 632 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
2c550183 | 633 | |
b5321f30 | 634 | intel_ring_emit(ring, |
e2f80391 | 635 | MI_LOAD_REGISTER_IMM(num_rings)); |
3b3f1650 | 636 | for_each_engine(signaller, dev_priv, id) { |
e2f80391 | 637 | if (signaller == engine) |
2c550183 CW |
638 | continue; |
639 | ||
e9135c4f | 640 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
b5321f30 CW |
641 | intel_ring_emit_reg(ring, last_reg); |
642 | intel_ring_emit(ring, | |
e2f80391 | 643 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
2c550183 | 644 | } |
e9135c4f CW |
645 | |
646 | /* Insert a delay before the next switch! */ | |
b5321f30 | 647 | intel_ring_emit(ring, |
e9135c4f CW |
648 | MI_STORE_REGISTER_MEM | |
649 | MI_SRM_LRM_GLOBAL_GTT); | |
b5321f30 | 650 | intel_ring_emit_reg(ring, last_reg); |
bde13ebd CW |
651 | intel_ring_emit(ring, |
652 | i915_ggtt_offset(engine->scratch)); | |
b5321f30 | 653 | intel_ring_emit(ring, MI_NOOP); |
2c550183 | 654 | } |
b5321f30 | 655 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 656 | } |
e37ec39b | 657 | |
b5321f30 | 658 | intel_ring_advance(ring); |
e0556841 BW |
659 | |
660 | return ret; | |
661 | } | |
662 | ||
d200cda6 | 663 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
b0ebde39 | 664 | { |
ff55b5e8 | 665 | u32 *remap_info = req->i915->l3_parity.remap_info[slice]; |
7e37f889 | 666 | struct intel_ring *ring = req->ring; |
b0ebde39 CW |
667 | int i, ret; |
668 | ||
ff55b5e8 | 669 | if (!remap_info) |
b0ebde39 CW |
670 | return 0; |
671 | ||
ff55b5e8 | 672 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
b0ebde39 CW |
673 | if (ret) |
674 | return ret; | |
675 | ||
676 | /* | |
677 | * Note: We do not worry about the concurrent register cacheline hang | |
678 | * here because no other code should access these registers other than | |
679 | * at initialization time. | |
680 | */ | |
b5321f30 | 681 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); |
ff55b5e8 | 682 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { |
b5321f30 CW |
683 | intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i)); |
684 | intel_ring_emit(ring, remap_info[i]); | |
b0ebde39 | 685 | } |
b5321f30 CW |
686 | intel_ring_emit(ring, MI_NOOP); |
687 | intel_ring_advance(ring); | |
b0ebde39 | 688 | |
ff55b5e8 | 689 | return 0; |
b0ebde39 CW |
690 | } |
691 | ||
f9326be5 CW |
692 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
693 | struct intel_engine_cs *engine, | |
e2efd130 | 694 | struct i915_gem_context *to) |
317b4e90 | 695 | { |
563222a7 BW |
696 | if (to->remap_slice) |
697 | return false; | |
698 | ||
bca44d80 | 699 | if (!to->engine[RCS].initialised) |
fcb5106d CW |
700 | return false; |
701 | ||
f9326be5 | 702 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
fcb5106d | 703 | return false; |
317b4e90 | 704 | |
e8a9c58f | 705 | return to == engine->legacy_active_context; |
317b4e90 BW |
706 | } |
707 | ||
708 | static bool | |
f9326be5 CW |
709 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
710 | struct intel_engine_cs *engine, | |
e2efd130 | 711 | struct i915_gem_context *to) |
317b4e90 | 712 | { |
f9326be5 | 713 | if (!ppgtt) |
317b4e90 BW |
714 | return false; |
715 | ||
f9326be5 | 716 | /* Always load the ppgtt on first use */ |
e8a9c58f | 717 | if (!engine->legacy_active_context) |
f9326be5 CW |
718 | return true; |
719 | ||
720 | /* Same context without new entries, skip */ | |
e8a9c58f | 721 | if (engine->legacy_active_context == to && |
f9326be5 | 722 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
e1a8daa2 CW |
723 | return false; |
724 | ||
725 | if (engine->id != RCS) | |
317b4e90 BW |
726 | return true; |
727 | ||
c033666a | 728 | if (INTEL_GEN(engine->i915) < 8) |
317b4e90 BW |
729 | return true; |
730 | ||
731 | return false; | |
732 | } | |
733 | ||
734 | static bool | |
f9326be5 | 735 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
e2efd130 | 736 | struct i915_gem_context *to, |
f9326be5 | 737 | u32 hw_flags) |
317b4e90 | 738 | { |
f9326be5 | 739 | if (!ppgtt) |
317b4e90 BW |
740 | return false; |
741 | ||
fcb5106d | 742 | if (!IS_GEN8(to->i915)) |
317b4e90 BW |
743 | return false; |
744 | ||
6702cf16 | 745 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
746 | return true; |
747 | ||
748 | return false; | |
749 | } | |
750 | ||
e1a8daa2 | 751 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
e0556841 | 752 | { |
e2efd130 | 753 | struct i915_gem_context *to = req->ctx; |
4a570db5 | 754 | struct intel_engine_cs *engine = req->engine; |
f9326be5 | 755 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
e8a9c58f | 756 | struct i915_gem_context *from = engine->legacy_active_context; |
fcb5106d | 757 | u32 hw_flags; |
3ccfd19d | 758 | int ret, i; |
e0556841 | 759 | |
e8a9c58f CW |
760 | GEM_BUG_ON(engine->id != RCS); |
761 | ||
f9326be5 | 762 | if (skip_rcs_switch(ppgtt, engine, to)) |
9a3b5304 CW |
763 | return 0; |
764 | ||
f9326be5 | 765 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
fcb5106d CW |
766 | /* Older GENs and non render rings still want the load first, |
767 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
768 | * Register Immediate commands in Ring Buffer before submitting | |
769 | * a context."*/ | |
770 | trace_switch_mm(engine, to); | |
f9326be5 | 771 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d | 772 | if (ret) |
e8a9c58f | 773 | return ret; |
fcb5106d CW |
774 | } |
775 | ||
bca44d80 | 776 | if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) |
6702cf16 BW |
777 | /* NB: If we inhibit the restore, the context is not allowed to |
778 | * die because future work may end up depending on valid address | |
779 | * space. This means we must enforce that a page table load | |
780 | * occur when this occurs. */ | |
fcb5106d | 781 | hw_flags = MI_RESTORE_INHIBIT; |
f9326be5 | 782 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
fcb5106d CW |
783 | hw_flags = MI_FORCE_RESTORE; |
784 | else | |
785 | hw_flags = 0; | |
e0556841 | 786 | |
fcb5106d CW |
787 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
788 | ret = mi_set_context(req, hw_flags); | |
3ccfd19d | 789 | if (ret) |
e8a9c58f | 790 | return ret; |
3ccfd19d | 791 | |
e8a9c58f | 792 | engine->legacy_active_context = to; |
e0556841 | 793 | } |
e0556841 | 794 | |
fcb5106d CW |
795 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
796 | * setup, and we do not wish to move them. | |
797 | */ | |
f9326be5 | 798 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
fcb5106d | 799 | trace_switch_mm(engine, to); |
f9326be5 | 800 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
801 | /* The hardware context switch is emitted, but we haven't |
802 | * actually changed the state - so it's probably safe to bail | |
803 | * here. Still, let the user know something dangerous has | |
804 | * happened. | |
805 | */ | |
806 | if (ret) | |
807 | return ret; | |
808 | } | |
809 | ||
f9326be5 CW |
810 | if (ppgtt) |
811 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); | |
fcb5106d CW |
812 | |
813 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
814 | if (!(to->remap_slice & (1<<i))) | |
815 | continue; | |
816 | ||
d200cda6 | 817 | ret = remap_l3(req, i); |
fcb5106d CW |
818 | if (ret) |
819 | return ret; | |
820 | ||
821 | to->remap_slice &= ~(1<<i); | |
822 | } | |
823 | ||
bca44d80 | 824 | if (!to->engine[RCS].initialised) { |
e2f80391 TU |
825 | if (engine->init_context) { |
826 | ret = engine->init_context(req); | |
86d7f238 | 827 | if (ret) |
fcb5106d | 828 | return ret; |
86d7f238 | 829 | } |
bca44d80 | 830 | to->engine[RCS].initialised = true; |
46470fc9 MK |
831 | } |
832 | ||
e0556841 BW |
833 | return 0; |
834 | } | |
835 | ||
836 | /** | |
837 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 838 | * @req: request for which we'll execute the context switch |
e0556841 BW |
839 | * |
840 | * The context life cycle is simple. The context refcount is incremented and | |
841 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 842 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 843 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
844 | * |
845 | * This function should not be used in execlists mode. Instead the context is | |
846 | * switched by writing to the ELSP and requests keep a reference to their | |
847 | * context. | |
e0556841 | 848 | */ |
ba01cc93 | 849 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 850 | { |
4a570db5 | 851 | struct intel_engine_cs *engine = req->engine; |
e0556841 | 852 | |
91c8a326 | 853 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5b043f4e CW |
854 | if (i915.enable_execlists) |
855 | return 0; | |
0eea67eb | 856 | |
bca44d80 | 857 | if (!req->ctx->engine[engine->id].state) { |
e2efd130 | 858 | struct i915_gem_context *to = req->ctx; |
f9326be5 CW |
859 | struct i915_hw_ppgtt *ppgtt = |
860 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; | |
e1a8daa2 | 861 | |
f9326be5 | 862 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
e1a8daa2 CW |
863 | int ret; |
864 | ||
865 | trace_switch_mm(engine, to); | |
f9326be5 | 866 | ret = ppgtt->switch_mm(ppgtt, req); |
e1a8daa2 CW |
867 | if (ret) |
868 | return ret; | |
869 | ||
f9326be5 | 870 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
e1a8daa2 CW |
871 | } |
872 | ||
c482972a | 873 | return 0; |
a95f6a00 | 874 | } |
c482972a | 875 | |
e1a8daa2 | 876 | return do_rcs_switch(req); |
e0556841 | 877 | } |
84624813 | 878 | |
f131e356 CW |
879 | static bool engine_has_kernel_context(struct intel_engine_cs *engine) |
880 | { | |
881 | struct i915_gem_timeline *timeline; | |
882 | ||
883 | list_for_each_entry(timeline, &engine->i915->gt.timelines, link) { | |
884 | struct intel_timeline *tl; | |
885 | ||
886 | if (timeline == &engine->i915->gt.global_timeline) | |
887 | continue; | |
888 | ||
889 | tl = &timeline->engine[engine->id]; | |
890 | if (i915_gem_active_peek(&tl->last_request, | |
891 | &engine->i915->drm.struct_mutex)) | |
892 | return false; | |
893 | } | |
894 | ||
895 | return (!engine->last_retired_context || | |
896 | i915_gem_context_is_kernel(engine->last_retired_context)); | |
897 | } | |
898 | ||
945657b4 CW |
899 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) |
900 | { | |
901 | struct intel_engine_cs *engine; | |
3033acab | 902 | struct i915_gem_timeline *timeline; |
3b3f1650 | 903 | enum intel_engine_id id; |
945657b4 | 904 | |
3033acab CW |
905 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
906 | ||
f131e356 CW |
907 | i915_gem_retire_requests(dev_priv); |
908 | ||
3b3f1650 | 909 | for_each_engine(engine, dev_priv, id) { |
945657b4 CW |
910 | struct drm_i915_gem_request *req; |
911 | int ret; | |
912 | ||
f131e356 CW |
913 | if (engine_has_kernel_context(engine)) |
914 | continue; | |
915 | ||
945657b4 CW |
916 | req = i915_gem_request_alloc(engine, dev_priv->kernel_context); |
917 | if (IS_ERR(req)) | |
918 | return PTR_ERR(req); | |
919 | ||
3033acab CW |
920 | /* Queue this switch after all other activity */ |
921 | list_for_each_entry(timeline, &dev_priv->gt.timelines, link) { | |
922 | struct drm_i915_gem_request *prev; | |
923 | struct intel_timeline *tl; | |
924 | ||
925 | tl = &timeline->engine[engine->id]; | |
926 | prev = i915_gem_active_raw(&tl->last_request, | |
927 | &dev_priv->drm.struct_mutex); | |
928 | if (prev) | |
929 | i915_sw_fence_await_sw_fence_gfp(&req->submit, | |
930 | &prev->submit, | |
931 | GFP_KERNEL); | |
932 | } | |
933 | ||
5b043f4e | 934 | ret = i915_switch_context(req); |
945657b4 CW |
935 | i915_add_request_no_flush(req); |
936 | if (ret) | |
937 | return ret; | |
938 | } | |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
ec3e9963 | 943 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 944 | { |
ec3e9963 | 945 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
946 | } |
947 | ||
b083a087 MK |
948 | static bool client_is_banned(struct drm_i915_file_private *file_priv) |
949 | { | |
950 | return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS; | |
951 | } | |
952 | ||
84624813 BW |
953 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
954 | struct drm_file *file) | |
955 | { | |
84624813 BW |
956 | struct drm_i915_gem_context_create *args = data; |
957 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 958 | struct i915_gem_context *ctx; |
84624813 BW |
959 | int ret; |
960 | ||
ec3e9963 | 961 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
962 | return -ENODEV; |
963 | ||
b31e5136 CW |
964 | if (args->pad != 0) |
965 | return -EINVAL; | |
966 | ||
b083a087 MK |
967 | if (client_is_banned(file_priv)) { |
968 | DRM_DEBUG("client %s[%d] banned from creating ctx\n", | |
969 | current->comm, | |
970 | pid_nr(get_task_pid(current, PIDTYPE_PID))); | |
971 | ||
972 | return -EIO; | |
973 | } | |
974 | ||
84624813 BW |
975 | ret = i915_mutex_lock_interruptible(dev); |
976 | if (ret) | |
977 | return ret; | |
978 | ||
bf9e8429 | 979 | ctx = i915_gem_create_context(to_i915(dev), file_priv); |
84624813 | 980 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
981 | if (IS_ERR(ctx)) |
982 | return PTR_ERR(ctx); | |
84624813 | 983 | |
984ff29f CW |
984 | GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); |
985 | ||
821d66dd | 986 | args->ctx_id = ctx->user_handle; |
b84cf536 | 987 | DRM_DEBUG("HW context %d created\n", args->ctx_id); |
84624813 | 988 | |
be636387 | 989 | return 0; |
84624813 BW |
990 | } |
991 | ||
992 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
993 | struct drm_file *file) | |
994 | { | |
995 | struct drm_i915_gem_context_destroy *args = data; | |
996 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 997 | struct i915_gem_context *ctx; |
84624813 BW |
998 | int ret; |
999 | ||
b31e5136 CW |
1000 | if (args->pad != 0) |
1001 | return -EINVAL; | |
1002 | ||
821d66dd | 1003 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 1004 | return -ENOENT; |
0eea67eb | 1005 | |
84624813 BW |
1006 | ret = i915_mutex_lock_interruptible(dev); |
1007 | if (ret) | |
1008 | return ret; | |
1009 | ||
ca585b5d | 1010 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
72ad5c45 | 1011 | if (IS_ERR(ctx)) { |
84624813 | 1012 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 1013 | return PTR_ERR(ctx); |
84624813 BW |
1014 | } |
1015 | ||
d28b99ab | 1016 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
50e046b6 | 1017 | context_close(ctx); |
84624813 BW |
1018 | mutex_unlock(&dev->struct_mutex); |
1019 | ||
b84cf536 | 1020 | DRM_DEBUG("HW context %d destroyed\n", args->ctx_id); |
84624813 BW |
1021 | return 0; |
1022 | } | |
c9dc0f35 CW |
1023 | |
1024 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
1025 | struct drm_file *file) | |
1026 | { | |
1027 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1028 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1029 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1030 | int ret; |
1031 | ||
1032 | ret = i915_mutex_lock_interruptible(dev); | |
1033 | if (ret) | |
1034 | return ret; | |
1035 | ||
ca585b5d | 1036 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1037 | if (IS_ERR(ctx)) { |
1038 | mutex_unlock(&dev->struct_mutex); | |
1039 | return PTR_ERR(ctx); | |
1040 | } | |
1041 | ||
1042 | args->size = 0; | |
1043 | switch (args->param) { | |
1044 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
84102171 | 1045 | ret = -EINVAL; |
c9dc0f35 | 1046 | break; |
b1b38278 DW |
1047 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1048 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
1049 | break; | |
fa8848f2 CW |
1050 | case I915_CONTEXT_PARAM_GTT_SIZE: |
1051 | if (ctx->ppgtt) | |
1052 | args->value = ctx->ppgtt->base.total; | |
1053 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
1054 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
1055 | else | |
62106b4f | 1056 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 1057 | break; |
bc3d6744 | 1058 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: |
6095868a | 1059 | args->value = i915_gem_context_no_error_capture(ctx); |
bc3d6744 | 1060 | break; |
84102171 | 1061 | case I915_CONTEXT_PARAM_BANNABLE: |
6095868a | 1062 | args->value = i915_gem_context_is_bannable(ctx); |
84102171 | 1063 | break; |
c9dc0f35 CW |
1064 | default: |
1065 | ret = -EINVAL; | |
1066 | break; | |
1067 | } | |
1068 | mutex_unlock(&dev->struct_mutex); | |
1069 | ||
1070 | return ret; | |
1071 | } | |
1072 | ||
1073 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
1074 | struct drm_file *file) | |
1075 | { | |
1076 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1077 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1078 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1079 | int ret; |
1080 | ||
1081 | ret = i915_mutex_lock_interruptible(dev); | |
1082 | if (ret) | |
1083 | return ret; | |
1084 | ||
ca585b5d | 1085 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1086 | if (IS_ERR(ctx)) { |
1087 | mutex_unlock(&dev->struct_mutex); | |
1088 | return PTR_ERR(ctx); | |
1089 | } | |
1090 | ||
1091 | switch (args->param) { | |
1092 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
84102171 | 1093 | ret = -EINVAL; |
c9dc0f35 | 1094 | break; |
b1b38278 DW |
1095 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1096 | if (args->size) { | |
1097 | ret = -EINVAL; | |
1098 | } else { | |
1099 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
1100 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
bc3d6744 CW |
1101 | } |
1102 | break; | |
1103 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: | |
6095868a | 1104 | if (args->size) |
bc3d6744 | 1105 | ret = -EINVAL; |
6095868a CW |
1106 | else if (args->value) |
1107 | i915_gem_context_set_no_error_capture(ctx); | |
1108 | else | |
1109 | i915_gem_context_clear_no_error_capture(ctx); | |
b1b38278 | 1110 | break; |
84102171 MK |
1111 | case I915_CONTEXT_PARAM_BANNABLE: |
1112 | if (args->size) | |
1113 | ret = -EINVAL; | |
1114 | else if (!capable(CAP_SYS_ADMIN) && !args->value) | |
1115 | ret = -EPERM; | |
6095868a CW |
1116 | else if (args->value) |
1117 | i915_gem_context_set_bannable(ctx); | |
84102171 | 1118 | else |
6095868a | 1119 | i915_gem_context_clear_bannable(ctx); |
84102171 | 1120 | break; |
c9dc0f35 CW |
1121 | default: |
1122 | ret = -EINVAL; | |
1123 | break; | |
1124 | } | |
1125 | mutex_unlock(&dev->struct_mutex); | |
1126 | ||
1127 | return ret; | |
1128 | } | |
d538704b CW |
1129 | |
1130 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, | |
1131 | void *data, struct drm_file *file) | |
1132 | { | |
fac5e23e | 1133 | struct drm_i915_private *dev_priv = to_i915(dev); |
d538704b | 1134 | struct drm_i915_reset_stats *args = data; |
e2efd130 | 1135 | struct i915_gem_context *ctx; |
d538704b CW |
1136 | int ret; |
1137 | ||
1138 | if (args->flags || args->pad) | |
1139 | return -EINVAL; | |
1140 | ||
1141 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) | |
1142 | return -EPERM; | |
1143 | ||
bdb04614 | 1144 | ret = i915_mutex_lock_interruptible(dev); |
d538704b CW |
1145 | if (ret) |
1146 | return ret; | |
1147 | ||
ca585b5d | 1148 | ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id); |
d538704b CW |
1149 | if (IS_ERR(ctx)) { |
1150 | mutex_unlock(&dev->struct_mutex); | |
1151 | return PTR_ERR(ctx); | |
1152 | } | |
d538704b CW |
1153 | |
1154 | if (capable(CAP_SYS_ADMIN)) | |
1155 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1156 | else | |
1157 | args->reset_count = 0; | |
1158 | ||
bc1d53c6 MK |
1159 | args->batch_active = ctx->guilty_count; |
1160 | args->batch_pending = ctx->active_count; | |
d538704b CW |
1161 | |
1162 | mutex_unlock(&dev->struct_mutex); | |
1163 | ||
1164 | return 0; | |
1165 | } |