]>
Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
b731d33d BW |
96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 BW |
98 | |
99 | static struct i915_hw_context * | |
100 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); | |
67e3d297 BW |
101 | static int do_switch(struct intel_ring_buffer *ring, |
102 | struct i915_hw_context *to); | |
40521054 | 103 | |
b731d33d BW |
104 | static size_t get_context_alignment(struct drm_device *dev) |
105 | { | |
106 | if (IS_GEN6(dev)) | |
107 | return GEN6_CONTEXT_ALIGN; | |
108 | ||
109 | return GEN7_CONTEXT_ALIGN; | |
110 | } | |
111 | ||
254f965c BW |
112 | static int get_context_size(struct drm_device *dev) |
113 | { | |
114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
115 | int ret; | |
116 | u32 reg; | |
117 | ||
118 | switch (INTEL_INFO(dev)->gen) { | |
119 | case 6: | |
120 | reg = I915_READ(CXT_SIZE); | |
121 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
122 | break; | |
123 | case 7: | |
4f91dd6f | 124 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 125 | if (IS_HASWELL(dev)) |
a0de80a0 | 126 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
127 | else |
128 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 129 | break; |
8897644a BW |
130 | case 8: |
131 | ret = GEN8_CXT_TOTAL_SIZE; | |
132 | break; | |
254f965c BW |
133 | default: |
134 | BUG(); | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
dce3271b | 140 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 141 | { |
dce3271b MK |
142 | struct i915_hw_context *ctx = container_of(ctx_ref, |
143 | typeof(*ctx), ref); | |
40521054 | 144 | |
a33afea5 | 145 | list_del(&ctx->link); |
40521054 BW |
146 | drm_gem_object_unreference(&ctx->obj->base); |
147 | kfree(ctx); | |
148 | } | |
149 | ||
146937e5 | 150 | static struct i915_hw_context * |
40521054 | 151 | create_hw_context(struct drm_device *dev, |
146937e5 | 152 | struct drm_i915_file_private *file_priv) |
40521054 BW |
153 | { |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146937e5 | 155 | struct i915_hw_context *ctx; |
c8c470af | 156 | int ret; |
40521054 | 157 | |
f94982b0 | 158 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
159 | if (ctx == NULL) |
160 | return ERR_PTR(-ENOMEM); | |
40521054 | 161 | |
dce3271b | 162 | kref_init(&ctx->ref); |
146937e5 | 163 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
a33afea5 | 164 | INIT_LIST_HEAD(&ctx->link); |
146937e5 BW |
165 | if (ctx->obj == NULL) { |
166 | kfree(ctx); | |
40521054 | 167 | DRM_DEBUG_DRIVER("Context object allocated failed\n"); |
146937e5 | 168 | return ERR_PTR(-ENOMEM); |
40521054 BW |
169 | } |
170 | ||
4615d4c9 CW |
171 | if (INTEL_INFO(dev)->gen >= 7) { |
172 | ret = i915_gem_object_set_cache_level(ctx->obj, | |
350ec881 | 173 | I915_CACHE_L3_LLC); |
bb036413 BW |
174 | /* Failure shouldn't ever happen this early */ |
175 | if (WARN_ON(ret)) | |
4615d4c9 CW |
176 | goto err_out; |
177 | } | |
178 | ||
a33afea5 | 179 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 BW |
180 | |
181 | /* Default context will never have a file_priv */ | |
182 | if (file_priv == NULL) | |
146937e5 | 183 | return ctx; |
40521054 | 184 | |
c8c470af TH |
185 | ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0, |
186 | GFP_KERNEL); | |
187 | if (ret < 0) | |
40521054 | 188 | goto err_out; |
dce3271b MK |
189 | |
190 | ctx->file_priv = file_priv; | |
c8c470af | 191 | ctx->id = ret; |
3ccfd19d BW |
192 | /* NB: Mark all slices as needing a remap so that when the context first |
193 | * loads it will restore whatever remap state already exists. If there | |
194 | * is no remap info, it will be a NOP. */ | |
195 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 196 | |
146937e5 | 197 | return ctx; |
40521054 BW |
198 | |
199 | err_out: | |
dce3271b | 200 | i915_gem_context_unreference(ctx); |
146937e5 | 201 | return ERR_PTR(ret); |
40521054 BW |
202 | } |
203 | ||
e0556841 BW |
204 | static inline bool is_default_context(struct i915_hw_context *ctx) |
205 | { | |
0009e46c BW |
206 | /* Cheap trick to determine default contexts */ |
207 | return ctx->file_priv ? false : true; | |
e0556841 BW |
208 | } |
209 | ||
254f965c BW |
210 | /** |
211 | * The default context needs to exist per ring that uses contexts. It stores the | |
212 | * context state of the GPU for applications that don't utilize HW contexts, as | |
213 | * well as an idle case. | |
214 | */ | |
b731d33d | 215 | static int create_default_context(struct drm_device *dev) |
254f965c | 216 | { |
b731d33d | 217 | struct drm_i915_private *dev_priv = dev->dev_private; |
40521054 BW |
218 | struct i915_hw_context *ctx; |
219 | int ret; | |
220 | ||
b731d33d | 221 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 222 | |
b731d33d | 223 | ctx = create_hw_context(dev, NULL); |
146937e5 BW |
224 | if (IS_ERR(ctx)) |
225 | return PTR_ERR(ctx); | |
40521054 BW |
226 | |
227 | /* We may need to do things with the shrinker which require us to | |
228 | * immediately switch back to the default context. This can cause a | |
229 | * problem as pinning the default context also requires GTT space which | |
230 | * may not be available. To avoid this we always pin the | |
231 | * default context. | |
232 | */ | |
b731d33d BW |
233 | ret = i915_gem_obj_ggtt_pin(ctx->obj, get_context_alignment(dev), |
234 | false, false); | |
bb036413 BW |
235 | if (ret) { |
236 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
9a3b5304 | 237 | goto err_destroy; |
bb036413 | 238 | } |
40521054 | 239 | |
67e3d297 | 240 | ret = do_switch(&dev_priv->ring[RCS], ctx); |
bb036413 BW |
241 | if (ret) { |
242 | DRM_DEBUG_DRIVER("Switch failed %d\n", ret); | |
9a3b5304 | 243 | goto err_unpin; |
bb036413 | 244 | } |
dfabbcb4 | 245 | |
71b76d00 BW |
246 | dev_priv->ring[RCS].default_context = ctx; |
247 | ||
9a3b5304 CW |
248 | DRM_DEBUG_DRIVER("Default HW context loaded\n"); |
249 | return 0; | |
250 | ||
251 | err_unpin: | |
d7f46fc4 | 252 | i915_gem_object_ggtt_unpin(ctx->obj); |
9a3b5304 | 253 | err_destroy: |
dce3271b | 254 | i915_gem_context_unreference(ctx); |
40521054 | 255 | return ret; |
254f965c BW |
256 | } |
257 | ||
acce9ffa BW |
258 | void i915_gem_context_reset(struct drm_device *dev) |
259 | { | |
260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
261 | struct intel_ring_buffer *ring; | |
262 | int i; | |
263 | ||
264 | if (!HAS_HW_CONTEXTS(dev)) | |
265 | return; | |
266 | ||
267 | /* Prevent the hardware from restoring the last context (which hung) on | |
268 | * the next switch */ | |
269 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
270 | struct i915_hw_context *dctx; | |
271 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
272 | continue; | |
273 | ||
274 | /* Do a fake switch to the default context */ | |
275 | ring = &dev_priv->ring[i]; | |
276 | dctx = ring->default_context; | |
277 | if (WARN_ON(!dctx)) | |
278 | continue; | |
279 | ||
280 | if (!ring->last_context) | |
281 | continue; | |
282 | ||
283 | if (ring->last_context == dctx) | |
284 | continue; | |
285 | ||
286 | if (i == RCS) { | |
287 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj, | |
288 | get_context_alignment(dev), | |
289 | false, false)); | |
290 | /* Fake a finish/inactive */ | |
291 | dctx->obj->base.write_domain = 0; | |
292 | dctx->obj->active = 0; | |
293 | } | |
294 | ||
295 | i915_gem_context_unreference(ring->last_context); | |
296 | i915_gem_context_reference(dctx); | |
297 | ring->last_context = dctx; | |
298 | } | |
299 | } | |
300 | ||
8245be31 | 301 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
302 | { |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
67e3d297 BW |
304 | struct intel_ring_buffer *ring; |
305 | int i, ret; | |
254f965c | 306 | |
8245be31 BW |
307 | if (!HAS_HW_CONTEXTS(dev)) |
308 | return 0; | |
254f965c BW |
309 | |
310 | /* If called from reset, or thaw... we've been here already */ | |
8245be31 BW |
311 | if (dev_priv->ring[RCS].default_context) |
312 | return 0; | |
254f965c | 313 | |
07ea0d85 | 314 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
254f965c | 315 | |
07ea0d85 | 316 | if (dev_priv->hw_context_size > (1<<20)) { |
bb036413 | 317 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n"); |
8245be31 | 318 | return -E2BIG; |
254f965c BW |
319 | } |
320 | ||
b731d33d | 321 | ret = create_default_context(dev); |
8245be31 BW |
322 | if (ret) { |
323 | DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %d\n", | |
324 | ret); | |
325 | return ret; | |
254f965c BW |
326 | } |
327 | ||
67e3d297 BW |
328 | for (i = RCS + 1; i < I915_NUM_RINGS; i++) { |
329 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
330 | continue; | |
331 | ||
332 | ring = &dev_priv->ring[i]; | |
333 | ||
334 | /* NB: RCS will hold a ref for all rings */ | |
335 | ring->default_context = dev_priv->ring[RCS].default_context; | |
336 | } | |
337 | ||
254f965c | 338 | DRM_DEBUG_DRIVER("HW context support initialized\n"); |
8245be31 | 339 | return 0; |
254f965c BW |
340 | } |
341 | ||
342 | void i915_gem_context_fini(struct drm_device *dev) | |
343 | { | |
344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dce3271b | 345 | struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 346 | int i; |
254f965c | 347 | |
8245be31 | 348 | if (!HAS_HW_CONTEXTS(dev)) |
254f965c | 349 | return; |
40521054 | 350 | |
55a66628 DV |
351 | /* The only known way to stop the gpu from accessing the hw context is |
352 | * to reset it. Do this as the very last operation to avoid confusing | |
353 | * other code, leading to spurious errors. */ | |
354 | intel_gpu_reset(dev); | |
355 | ||
168f8366 MK |
356 | /* When default context is created and switched to, base object refcount |
357 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
358 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
359 | * to default context. So we need to unreference the base object once | |
360 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
361 | * can then free the base object correctly. */ | |
71b76d00 BW |
362 | WARN_ON(!dev_priv->ring[RCS].last_context); |
363 | if (dev_priv->ring[RCS].last_context == dctx) { | |
364 | /* Fake switch to NULL context */ | |
365 | WARN_ON(dctx->obj->active); | |
d7f46fc4 | 366 | i915_gem_object_ggtt_unpin(dctx->obj); |
71b76d00 | 367 | i915_gem_context_unreference(dctx); |
67e3d297 BW |
368 | dev_priv->ring[RCS].last_context = NULL; |
369 | } | |
370 | ||
371 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
372 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
373 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
374 | continue; | |
375 | ||
376 | if (ring->last_context) | |
377 | i915_gem_context_unreference(ring->last_context); | |
378 | ||
379 | ring->default_context = NULL; | |
0009e46c | 380 | ring->last_context = NULL; |
71b76d00 BW |
381 | } |
382 | ||
d7f46fc4 | 383 | i915_gem_object_ggtt_unpin(dctx->obj); |
dce3271b | 384 | i915_gem_context_unreference(dctx); |
254f965c BW |
385 | } |
386 | ||
40521054 BW |
387 | static int context_idr_cleanup(int id, void *p, void *data) |
388 | { | |
73c273eb | 389 | struct i915_hw_context *ctx = p; |
40521054 BW |
390 | |
391 | BUG_ON(id == DEFAULT_CONTEXT_ID); | |
40521054 | 392 | |
dce3271b | 393 | i915_gem_context_unreference(ctx); |
40521054 | 394 | return 0; |
254f965c BW |
395 | } |
396 | ||
c0bb617a | 397 | struct i915_ctx_hang_stats * |
11fa3384 | 398 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
c0bb617a MK |
399 | struct drm_file *file, |
400 | u32 id) | |
401 | { | |
c0bb617a | 402 | struct drm_i915_file_private *file_priv = file->driver_priv; |
11fa3384 | 403 | struct i915_hw_context *ctx; |
c0bb617a MK |
404 | |
405 | if (id == DEFAULT_CONTEXT_ID) | |
406 | return &file_priv->hang_stats; | |
407 | ||
8245be31 BW |
408 | if (!HAS_HW_CONTEXTS(dev)) |
409 | return ERR_PTR(-ENOENT); | |
410 | ||
411 | ctx = i915_gem_context_get(file->driver_priv, id); | |
11fa3384 | 412 | if (ctx == NULL) |
c0bb617a MK |
413 | return ERR_PTR(-ENOENT); |
414 | ||
11fa3384 | 415 | return &ctx->hang_stats; |
c0bb617a MK |
416 | } |
417 | ||
e422b888 BW |
418 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
419 | { | |
420 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
421 | ||
422 | if (!HAS_HW_CONTEXTS(dev)) | |
423 | return 0; | |
424 | ||
425 | idr_init(&file_priv->context_idr); | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
254f965c BW |
430 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
431 | { | |
40521054 | 432 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 433 | |
e422b888 BW |
434 | if (!HAS_HW_CONTEXTS(dev)) |
435 | return; | |
436 | ||
40521054 | 437 | mutex_lock(&dev->struct_mutex); |
73c273eb | 438 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 BW |
439 | idr_destroy(&file_priv->context_idr); |
440 | mutex_unlock(&dev->struct_mutex); | |
441 | } | |
442 | ||
e0556841 | 443 | static struct i915_hw_context * |
40521054 BW |
444 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
445 | { | |
446 | return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); | |
254f965c | 447 | } |
e0556841 BW |
448 | |
449 | static inline int | |
450 | mi_set_context(struct intel_ring_buffer *ring, | |
451 | struct i915_hw_context *new_context, | |
452 | u32 hw_flags) | |
453 | { | |
454 | int ret; | |
455 | ||
12b0286f BW |
456 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
457 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
458 | * explicitly, so we rely on the value at ring init, stored in | |
459 | * itlb_before_ctx_switch. | |
460 | */ | |
461 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | |
ac82ea2e | 462 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
463 | if (ret) |
464 | return ret; | |
465 | } | |
466 | ||
e37ec39b | 467 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
468 | if (ret) |
469 | return ret; | |
470 | ||
8693a824 | 471 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */ |
e37ec39b BW |
472 | if (IS_GEN7(ring->dev)) |
473 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
474 | else | |
475 | intel_ring_emit(ring, MI_NOOP); | |
476 | ||
e0556841 BW |
477 | intel_ring_emit(ring, MI_NOOP); |
478 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 479 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) | |
e0556841 BW |
480 | MI_MM_SPACE_GTT | |
481 | MI_SAVE_EXT_STATE_EN | | |
482 | MI_RESTORE_EXT_STATE_EN | | |
483 | hw_flags); | |
484 | /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ | |
485 | intel_ring_emit(ring, MI_NOOP); | |
486 | ||
e37ec39b BW |
487 | if (IS_GEN7(ring->dev)) |
488 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
489 | else | |
490 | intel_ring_emit(ring, MI_NOOP); | |
491 | ||
e0556841 BW |
492 | intel_ring_advance(ring); |
493 | ||
494 | return ret; | |
495 | } | |
496 | ||
67e3d297 BW |
497 | static int do_switch(struct intel_ring_buffer *ring, |
498 | struct i915_hw_context *to) | |
e0556841 | 499 | { |
6f65e29a | 500 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
112522f6 | 501 | struct i915_hw_context *from = ring->last_context; |
e0556841 | 502 | u32 hw_flags = 0; |
3ccfd19d | 503 | int ret, i; |
e0556841 | 504 | |
67e3d297 BW |
505 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
506 | BUG_ON(from->obj == NULL); | |
507 | BUG_ON(!i915_gem_obj_is_pinned(from->obj)); | |
508 | } | |
e0556841 | 509 | |
0009e46c | 510 | if (from == to && from->last_ring == ring && !to->remap_slice) |
9a3b5304 CW |
511 | return 0; |
512 | ||
67e3d297 BW |
513 | if (ring != &dev_priv->ring[RCS]) { |
514 | if (from) | |
515 | i915_gem_context_unreference(from); | |
516 | goto done; | |
517 | } | |
518 | ||
b731d33d BW |
519 | ret = i915_gem_obj_ggtt_pin(to->obj, get_context_alignment(ring->dev), |
520 | false, false); | |
e0556841 BW |
521 | if (ret) |
522 | return ret; | |
523 | ||
d3373a24 CW |
524 | /* Clear this page out of any CPU caches for coherent swap-in/out. Note |
525 | * that thanks to write = false in this call and us not setting any gpu | |
526 | * write domains when putting a context object onto the active list | |
527 | * (when switching away from it), this won't block. | |
528 | * XXX: We need a real interface to do this instead of trickery. */ | |
529 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); | |
530 | if (ret) { | |
d7f46fc4 | 531 | i915_gem_object_ggtt_unpin(to->obj); |
d3373a24 CW |
532 | return ret; |
533 | } | |
534 | ||
6f65e29a BW |
535 | if (!to->obj->has_global_gtt_mapping) { |
536 | struct i915_vma *vma = i915_gem_obj_to_vma(to->obj, | |
537 | &dev_priv->gtt.base); | |
538 | vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND); | |
539 | } | |
3af7b857 | 540 | |
e0556841 BW |
541 | if (!to->is_initialized || is_default_context(to)) |
542 | hw_flags |= MI_RESTORE_INHIBIT; | |
e0556841 | 543 | |
e0556841 BW |
544 | ret = mi_set_context(ring, to, hw_flags); |
545 | if (ret) { | |
d7f46fc4 | 546 | i915_gem_object_ggtt_unpin(to->obj); |
e0556841 BW |
547 | return ret; |
548 | } | |
549 | ||
3ccfd19d BW |
550 | for (i = 0; i < MAX_L3_SLICES; i++) { |
551 | if (!(to->remap_slice & (1<<i))) | |
552 | continue; | |
553 | ||
554 | ret = i915_gem_l3_remap(ring, i); | |
555 | /* If it failed, try again next round */ | |
556 | if (ret) | |
557 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
558 | else | |
559 | to->remap_slice &= ~(1<<i); | |
560 | } | |
561 | ||
e0556841 BW |
562 | /* The backing object for the context is done after switching to the |
563 | * *next* context. Therefore we cannot retire the previous context until | |
564 | * the next context has already started running. In fact, the below code | |
565 | * is a bit suboptimal because the retiring can occur simply after the | |
566 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
567 | */ | |
112522f6 CW |
568 | if (from != NULL) { |
569 | from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; | |
e2d05a8b | 570 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring); |
e0556841 BW |
571 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
572 | * whole damn pipeline, we don't need to explicitly mark the | |
573 | * object dirty. The only exception is that the context must be | |
574 | * correct in case the object gets swapped out. Ideally we'd be | |
575 | * able to defer doing this until we know the object would be | |
576 | * swapped, but there is no way to do that yet. | |
577 | */ | |
112522f6 CW |
578 | from->obj->dirty = 1; |
579 | BUG_ON(from->obj->ring != ring); | |
580 | ||
c0321e2c | 581 | /* obj is kept alive until the next request by its active ref */ |
d7f46fc4 | 582 | i915_gem_object_ggtt_unpin(from->obj); |
112522f6 | 583 | i915_gem_context_unreference(from); |
e0556841 BW |
584 | } |
585 | ||
67e3d297 | 586 | done: |
112522f6 CW |
587 | i915_gem_context_reference(to); |
588 | ring->last_context = to; | |
e0556841 | 589 | to->is_initialized = true; |
0009e46c | 590 | to->last_ring = ring; |
e0556841 BW |
591 | |
592 | return 0; | |
593 | } | |
594 | ||
595 | /** | |
596 | * i915_switch_context() - perform a GPU context switch. | |
597 | * @ring: ring for which we'll execute the context switch | |
598 | * @file_priv: file_priv associated with the context, may be NULL | |
599 | * @id: context id number | |
e0556841 BW |
600 | * |
601 | * The context life cycle is simple. The context refcount is incremented and | |
602 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
603 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
604 | * object while letting the normal object tracking destroy the backing BO. | |
605 | */ | |
606 | int i915_switch_context(struct intel_ring_buffer *ring, | |
607 | struct drm_file *file, | |
608 | int to_id) | |
609 | { | |
610 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 611 | struct i915_hw_context *to; |
e0556841 | 612 | |
8245be31 | 613 | if (!HAS_HW_CONTEXTS(ring->dev)) |
e0556841 BW |
614 | return 0; |
615 | ||
186507e9 BW |
616 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
617 | ||
e0556841 BW |
618 | if (to_id == DEFAULT_CONTEXT_ID) { |
619 | to = ring->default_context; | |
620 | } else { | |
9a3b5304 CW |
621 | if (file == NULL) |
622 | return -EINVAL; | |
623 | ||
624 | to = i915_gem_context_get(file->driver_priv, to_id); | |
e0556841 | 625 | if (to == NULL) |
0d326013 | 626 | return -ENOENT; |
e0556841 BW |
627 | } |
628 | ||
67e3d297 | 629 | return do_switch(ring, to); |
e0556841 | 630 | } |
84624813 BW |
631 | |
632 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
633 | struct drm_file *file) | |
634 | { | |
84624813 BW |
635 | struct drm_i915_gem_context_create *args = data; |
636 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
637 | struct i915_hw_context *ctx; | |
638 | int ret; | |
639 | ||
640 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
641 | return -ENODEV; | |
642 | ||
8245be31 | 643 | if (!HAS_HW_CONTEXTS(dev)) |
5fa8be65 DV |
644 | return -ENODEV; |
645 | ||
84624813 BW |
646 | ret = i915_mutex_lock_interruptible(dev); |
647 | if (ret) | |
648 | return ret; | |
649 | ||
146937e5 | 650 | ctx = create_hw_context(dev, file_priv); |
84624813 | 651 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
652 | if (IS_ERR(ctx)) |
653 | return PTR_ERR(ctx); | |
84624813 BW |
654 | |
655 | args->ctx_id = ctx->id; | |
656 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
657 | ||
be636387 | 658 | return 0; |
84624813 BW |
659 | } |
660 | ||
661 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
662 | struct drm_file *file) | |
663 | { | |
664 | struct drm_i915_gem_context_destroy *args = data; | |
665 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
84624813 BW |
666 | struct i915_hw_context *ctx; |
667 | int ret; | |
668 | ||
669 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
670 | return -ENODEV; | |
671 | ||
672 | ret = i915_mutex_lock_interruptible(dev); | |
673 | if (ret) | |
674 | return ret; | |
675 | ||
676 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
677 | if (!ctx) { | |
678 | mutex_unlock(&dev->struct_mutex); | |
0d326013 | 679 | return -ENOENT; |
84624813 BW |
680 | } |
681 | ||
dce3271b MK |
682 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
683 | i915_gem_context_unreference(ctx); | |
84624813 BW |
684 | mutex_unlock(&dev->struct_mutex); |
685 | ||
686 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
687 | return 0; | |
688 | } |