]>
Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
b2e862d0 CW |
93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
94 | ||
40521054 BW |
95 | /* This is a HW constraint. The value below is the largest known requirement |
96 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
97 | * part. It should be safe to decrease this, but it's more future proof as is. | |
98 | */ | |
b731d33d BW |
99 | #define GEN6_CONTEXT_ALIGN (64<<10) |
100 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 101 | |
c033666a | 102 | static size_t get_context_alignment(struct drm_i915_private *dev_priv) |
b731d33d | 103 | { |
c033666a | 104 | if (IS_GEN6(dev_priv)) |
b731d33d BW |
105 | return GEN6_CONTEXT_ALIGN; |
106 | ||
107 | return GEN7_CONTEXT_ALIGN; | |
108 | } | |
109 | ||
c033666a | 110 | static int get_context_size(struct drm_i915_private *dev_priv) |
254f965c | 111 | { |
254f965c BW |
112 | int ret; |
113 | u32 reg; | |
114 | ||
c033666a | 115 | switch (INTEL_GEN(dev_priv)) { |
254f965c BW |
116 | case 6: |
117 | reg = I915_READ(CXT_SIZE); | |
118 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
119 | break; | |
120 | case 7: | |
4f91dd6f | 121 | reg = I915_READ(GEN7_CXT_SIZE); |
c033666a | 122 | if (IS_HASWELL(dev_priv)) |
a0de80a0 | 123 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
124 | else |
125 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 126 | break; |
8897644a BW |
127 | case 8: |
128 | ret = GEN8_CXT_TOTAL_SIZE; | |
129 | break; | |
254f965c BW |
130 | default: |
131 | BUG(); | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
e2efd130 | 137 | static void i915_gem_context_clean(struct i915_gem_context *ctx) |
e9f24d5f TU |
138 | { |
139 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; | |
140 | struct i915_vma *vma, *next; | |
141 | ||
61fb5881 | 142 | if (!ppgtt) |
e9f24d5f TU |
143 | return; |
144 | ||
e9f24d5f | 145 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
1c7f4bca | 146 | vm_link) { |
e9f24d5f TU |
147 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
148 | break; | |
149 | } | |
150 | } | |
151 | ||
dce3271b | 152 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 153 | { |
e2efd130 | 154 | struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
bca44d80 | 155 | int i; |
40521054 | 156 | |
499f2697 | 157 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); |
198c974d DCS |
158 | trace_i915_context_free(ctx); |
159 | ||
e9f24d5f TU |
160 | /* |
161 | * This context is going away and we need to remove all VMAs still | |
162 | * around. This is to handle imported shared objects for which | |
163 | * destructor did not run when their handles were closed. | |
164 | */ | |
165 | i915_gem_context_clean(ctx); | |
166 | ||
ae6c4806 DV |
167 | i915_ppgtt_put(ctx->ppgtt); |
168 | ||
bca44d80 CW |
169 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
170 | struct intel_context *ce = &ctx->engine[i]; | |
171 | ||
172 | if (!ce->state) | |
173 | continue; | |
174 | ||
175 | WARN_ON(ce->pin_count); | |
176 | if (ce->ringbuf) | |
177 | intel_ringbuffer_free(ce->ringbuf); | |
178 | ||
179 | drm_gem_object_unreference(&ce->state->base); | |
180 | } | |
181 | ||
c7c48dfd | 182 | list_del(&ctx->link); |
5d1808ec CW |
183 | |
184 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); | |
40521054 BW |
185 | kfree(ctx); |
186 | } | |
187 | ||
8c857917 | 188 | struct drm_i915_gem_object * |
aa0c13da OM |
189 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
190 | { | |
191 | struct drm_i915_gem_object *obj; | |
192 | int ret; | |
193 | ||
499f2697 CW |
194 | lockdep_assert_held(&dev->struct_mutex); |
195 | ||
d37cd8a8 | 196 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
197 | if (IS_ERR(obj)) |
198 | return obj; | |
aa0c13da OM |
199 | |
200 | /* | |
201 | * Try to make the context utilize L3 as well as LLC. | |
202 | * | |
203 | * On VLV we don't have L3 controls in the PTEs so we | |
204 | * shouldn't touch the cache level, especially as that | |
205 | * would make the object snooped which might have a | |
206 | * negative performance impact. | |
4d3e904c WB |
207 | * |
208 | * Snooping is required on non-llc platforms in execlist | |
209 | * mode, but since all GGTT accesses use PAT entry 0 we | |
210 | * get snooping anyway regardless of cache_level. | |
211 | * | |
212 | * This is only applicable for Ivy Bridge devices since | |
213 | * later platforms don't have L3 control bits in the PTE. | |
aa0c13da | 214 | */ |
4d3e904c | 215 | if (IS_IVYBRIDGE(dev)) { |
aa0c13da OM |
216 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
217 | /* Failure shouldn't ever happen this early */ | |
218 | if (WARN_ON(ret)) { | |
219 | drm_gem_object_unreference(&obj->base); | |
220 | return ERR_PTR(ret); | |
221 | } | |
222 | } | |
223 | ||
224 | return obj; | |
225 | } | |
226 | ||
5d1808ec CW |
227 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
228 | { | |
229 | int ret; | |
230 | ||
231 | ret = ida_simple_get(&dev_priv->context_hw_ida, | |
232 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
233 | if (ret < 0) { | |
234 | /* Contexts are only released when no longer active. | |
235 | * Flush any pending retires to hopefully release some | |
236 | * stale contexts and try again. | |
237 | */ | |
c033666a | 238 | i915_gem_retire_requests(dev_priv); |
5d1808ec CW |
239 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
240 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
241 | if (ret < 0) | |
242 | return ret; | |
243 | } | |
244 | ||
245 | *out = ret; | |
246 | return 0; | |
247 | } | |
248 | ||
e2efd130 | 249 | static struct i915_gem_context * |
0eea67eb | 250 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 251 | struct drm_i915_file_private *file_priv) |
40521054 BW |
252 | { |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2efd130 | 254 | struct i915_gem_context *ctx; |
c8c470af | 255 | int ret; |
40521054 | 256 | |
f94982b0 | 257 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
258 | if (ctx == NULL) |
259 | return ERR_PTR(-ENOMEM); | |
40521054 | 260 | |
5d1808ec CW |
261 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
262 | if (ret) { | |
263 | kfree(ctx); | |
264 | return ERR_PTR(ret); | |
265 | } | |
266 | ||
dce3271b | 267 | kref_init(&ctx->ref); |
691e6415 | 268 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 269 | ctx->i915 = dev_priv; |
40521054 | 270 | |
691e6415 | 271 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
272 | struct drm_i915_gem_object *obj = |
273 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
274 | if (IS_ERR(obj)) { | |
275 | ret = PTR_ERR(obj); | |
4615d4c9 | 276 | goto err_out; |
691e6415 | 277 | } |
bca44d80 | 278 | ctx->engine[RCS].state = obj; |
691e6415 | 279 | } |
40521054 BW |
280 | |
281 | /* Default context will never have a file_priv */ | |
691e6415 CW |
282 | if (file_priv != NULL) { |
283 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 284 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
285 | if (ret < 0) |
286 | goto err_out; | |
287 | } else | |
821d66dd | 288 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
289 | |
290 | ctx->file_priv = file_priv; | |
821d66dd | 291 | ctx->user_handle = ret; |
3ccfd19d BW |
292 | /* NB: Mark all slices as needing a remap so that when the context first |
293 | * loads it will restore whatever remap state already exists. If there | |
294 | * is no remap info, it will be a NOP. */ | |
b2e862d0 | 295 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
40521054 | 296 | |
676fa572 | 297 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
bcd794c2 | 298 | ctx->ring_size = 4 * PAGE_SIZE; |
676fa572 | 299 | |
146937e5 | 300 | return ctx; |
40521054 BW |
301 | |
302 | err_out: | |
dce3271b | 303 | i915_gem_context_unreference(ctx); |
146937e5 | 304 | return ERR_PTR(ret); |
40521054 BW |
305 | } |
306 | ||
254f965c BW |
307 | /** |
308 | * The default context needs to exist per ring that uses contexts. It stores the | |
309 | * context state of the GPU for applications that don't utilize HW contexts, as | |
310 | * well as an idle case. | |
311 | */ | |
e2efd130 | 312 | static struct i915_gem_context * |
0eea67eb | 313 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 314 | struct drm_i915_file_private *file_priv) |
254f965c | 315 | { |
e2efd130 | 316 | struct i915_gem_context *ctx; |
40521054 | 317 | |
499f2697 | 318 | lockdep_assert_held(&dev->struct_mutex); |
40521054 | 319 | |
0eea67eb | 320 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 321 | if (IS_ERR(ctx)) |
a45d0f6a | 322 | return ctx; |
40521054 | 323 | |
d624d86e | 324 | if (USES_FULL_PPGTT(dev)) { |
4d884705 | 325 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e | 326 | |
c6aab916 | 327 | if (IS_ERR(ppgtt)) { |
0eea67eb BW |
328 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
329 | PTR_ERR(ppgtt)); | |
c6aab916 CW |
330 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
331 | i915_gem_context_unreference(ctx); | |
332 | return ERR_CAST(ppgtt); | |
ae6c4806 DV |
333 | } |
334 | ||
335 | ctx->ppgtt = ppgtt; | |
336 | } | |
bdf4fd7e | 337 | |
198c974d DCS |
338 | trace_i915_context_create(ctx); |
339 | ||
a45d0f6a | 340 | return ctx; |
254f965c BW |
341 | } |
342 | ||
e2efd130 | 343 | static void i915_gem_context_unpin(struct i915_gem_context *ctx, |
a0b4a6a8 TU |
344 | struct intel_engine_cs *engine) |
345 | { | |
f4e2dece TU |
346 | if (i915.enable_execlists) { |
347 | intel_lr_context_unpin(ctx, engine); | |
348 | } else { | |
bca44d80 CW |
349 | struct intel_context *ce = &ctx->engine[engine->id]; |
350 | ||
351 | if (ce->state) | |
352 | i915_gem_object_ggtt_unpin(ce->state); | |
353 | ||
f4e2dece TU |
354 | i915_gem_context_unreference(ctx); |
355 | } | |
a0b4a6a8 TU |
356 | } |
357 | ||
acce9ffa BW |
358 | void i915_gem_context_reset(struct drm_device *dev) |
359 | { | |
360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa | 361 | |
499f2697 CW |
362 | lockdep_assert_held(&dev->struct_mutex); |
363 | ||
3e5b6f05 | 364 | if (i915.enable_execlists) { |
e2efd130 | 365 | struct i915_gem_context *ctx; |
3e5b6f05 | 366 | |
a0b4a6a8 | 367 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
7d774cac | 368 | intel_lr_context_reset(dev_priv, ctx); |
3e5b6f05 | 369 | } |
ecdb5fd8 | 370 | |
b2e862d0 | 371 | i915_gem_context_lost(dev_priv); |
acce9ffa BW |
372 | } |
373 | ||
8245be31 | 374 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
375 | { |
376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2efd130 | 377 | struct i915_gem_context *ctx; |
254f965c | 378 | |
2fa48d8d BW |
379 | /* Init should only be called once per module load. Eventually the |
380 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 381 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 382 | return 0; |
254f965c | 383 | |
c033666a CW |
384 | if (intel_vgpu_active(dev_priv) && |
385 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { | |
a0bd6c31 ZL |
386 | if (!i915.enable_execlists) { |
387 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
388 | return -EINVAL; | |
389 | } | |
390 | } | |
391 | ||
5d1808ec CW |
392 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
393 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); | |
394 | ida_init(&dev_priv->context_hw_ida); | |
395 | ||
ede7d42b OM |
396 | if (i915.enable_execlists) { |
397 | /* NB: intentionally left blank. We will allocate our own | |
398 | * backing objects as we need them, thank you very much */ | |
399 | dev_priv->hw_context_size = 0; | |
c033666a CW |
400 | } else if (HAS_HW_CONTEXTS(dev_priv)) { |
401 | dev_priv->hw_context_size = | |
402 | round_up(get_context_size(dev_priv), 4096); | |
691e6415 CW |
403 | if (dev_priv->hw_context_size > (1<<20)) { |
404 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
405 | dev_priv->hw_context_size); | |
406 | dev_priv->hw_context_size = 0; | |
407 | } | |
254f965c BW |
408 | } |
409 | ||
d624d86e | 410 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
411 | if (IS_ERR(ctx)) { |
412 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
413 | PTR_ERR(ctx)); | |
414 | return PTR_ERR(ctx); | |
254f965c BW |
415 | } |
416 | ||
bca44d80 | 417 | if (!i915.enable_execlists && ctx->engine[RCS].state) { |
c6aab916 CW |
418 | int ret; |
419 | ||
420 | /* We may need to do things with the shrinker which | |
421 | * require us to immediately switch back to the default | |
422 | * context. This can cause a problem as pinning the | |
423 | * default context also requires GTT space which may not | |
424 | * be available. To avoid this we always pin the default | |
425 | * context. | |
426 | */ | |
bca44d80 | 427 | ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state, |
c6aab916 CW |
428 | get_context_alignment(dev_priv), 0); |
429 | if (ret) { | |
430 | DRM_ERROR("Failed to pinned default global context (error %d)\n", | |
431 | ret); | |
432 | i915_gem_context_unreference(ctx); | |
433 | return ret; | |
434 | } | |
435 | } | |
436 | ||
ed54c1a1 | 437 | dev_priv->kernel_context = ctx; |
67e3d297 | 438 | |
ede7d42b OM |
439 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
440 | i915.enable_execlists ? "LR" : | |
441 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 442 | return 0; |
254f965c BW |
443 | } |
444 | ||
b2e862d0 CW |
445 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
446 | { | |
447 | struct intel_engine_cs *engine; | |
448 | ||
499f2697 CW |
449 | lockdep_assert_held(&dev_priv->dev->struct_mutex); |
450 | ||
b2e862d0 | 451 | for_each_engine(engine, dev_priv) { |
bca44d80 CW |
452 | if (engine->last_context) { |
453 | i915_gem_context_unpin(engine->last_context, engine); | |
454 | engine->last_context = NULL; | |
455 | } | |
b2e862d0 | 456 | |
bca44d80 CW |
457 | /* Force the GPU state to be reinitialised on enabling */ |
458 | dev_priv->kernel_context->engine[engine->id].initialised = | |
459 | engine->init_context == NULL; | |
b2e862d0 CW |
460 | } |
461 | ||
462 | /* Force the GPU state to be reinitialised on enabling */ | |
b2e862d0 CW |
463 | dev_priv->kernel_context->remap_slice = ALL_L3_SLICES(dev_priv); |
464 | } | |
465 | ||
254f965c BW |
466 | void i915_gem_context_fini(struct drm_device *dev) |
467 | { | |
468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2efd130 | 469 | struct i915_gem_context *dctx = dev_priv->kernel_context; |
b2e862d0 | 470 | |
499f2697 CW |
471 | lockdep_assert_held(&dev->struct_mutex); |
472 | ||
bca44d80 CW |
473 | if (!i915.enable_execlists && dctx->engine[RCS].state) |
474 | i915_gem_object_ggtt_unpin(dctx->engine[RCS].state); | |
67e3d297 | 475 | |
dce3271b | 476 | i915_gem_context_unreference(dctx); |
ed54c1a1 | 477 | dev_priv->kernel_context = NULL; |
5d1808ec CW |
478 | |
479 | ida_destroy(&dev_priv->context_hw_ida); | |
254f965c BW |
480 | } |
481 | ||
40521054 BW |
482 | static int context_idr_cleanup(int id, void *p, void *data) |
483 | { | |
e2efd130 | 484 | struct i915_gem_context *ctx = p; |
40521054 | 485 | |
d28b99ab | 486 | ctx->file_priv = ERR_PTR(-EBADF); |
dce3271b | 487 | i915_gem_context_unreference(ctx); |
40521054 | 488 | return 0; |
254f965c BW |
489 | } |
490 | ||
e422b888 BW |
491 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
492 | { | |
493 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 494 | struct i915_gem_context *ctx; |
e422b888 BW |
495 | |
496 | idr_init(&file_priv->context_idr); | |
497 | ||
0eea67eb | 498 | mutex_lock(&dev->struct_mutex); |
d624d86e | 499 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
500 | mutex_unlock(&dev->struct_mutex); |
501 | ||
f83d6518 | 502 | if (IS_ERR(ctx)) { |
0eea67eb | 503 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 504 | return PTR_ERR(ctx); |
0eea67eb BW |
505 | } |
506 | ||
e422b888 BW |
507 | return 0; |
508 | } | |
509 | ||
254f965c BW |
510 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
511 | { | |
40521054 | 512 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 513 | |
499f2697 CW |
514 | lockdep_assert_held(&dev->struct_mutex); |
515 | ||
73c273eb | 516 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 517 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
518 | } |
519 | ||
e0556841 | 520 | static inline int |
1d719cda | 521 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 522 | { |
c033666a | 523 | struct drm_i915_private *dev_priv = req->i915; |
4a570db5 | 524 | struct intel_engine_cs *engine = req->engine; |
e80f14b6 | 525 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
526 | const int num_rings = |
527 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
c033666a CW |
528 | i915_semaphore_is_enabled(dev_priv) ? |
529 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 : | |
2c550183 | 530 | 0; |
b4ac5afc | 531 | int len, ret; |
e0556841 | 532 | |
12b0286f BW |
533 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
534 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
535 | * explicitly, so we rely on the value at ring init, stored in | |
536 | * itlb_before_ctx_switch. | |
537 | */ | |
c033666a | 538 | if (IS_GEN6(dev_priv)) { |
e2f80391 | 539 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
540 | if (ret) |
541 | return ret; | |
542 | } | |
543 | ||
e80f14b6 | 544 | /* These flags are for resource streamer on HSW+ */ |
c033666a | 545 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
4c436d55 | 546 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
c033666a | 547 | else if (INTEL_GEN(dev_priv) < 8) |
e80f14b6 BW |
548 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
549 | ||
2c550183 CW |
550 | |
551 | len = 4; | |
c033666a | 552 | if (INTEL_GEN(dev_priv) >= 7) |
e9135c4f | 553 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
2c550183 | 554 | |
5fb9de1a | 555 | ret = intel_ring_begin(req, len); |
e0556841 BW |
556 | if (ret) |
557 | return ret; | |
558 | ||
b3f797ac | 559 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
c033666a | 560 | if (INTEL_GEN(dev_priv) >= 7) { |
e2f80391 | 561 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
562 | if (num_rings) { |
563 | struct intel_engine_cs *signaller; | |
564 | ||
e2f80391 TU |
565 | intel_ring_emit(engine, |
566 | MI_LOAD_REGISTER_IMM(num_rings)); | |
c033666a | 567 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 568 | if (signaller == engine) |
2c550183 CW |
569 | continue; |
570 | ||
e2f80391 TU |
571 | intel_ring_emit_reg(engine, |
572 | RING_PSMI_CTL(signaller->mmio_base)); | |
573 | intel_ring_emit(engine, | |
574 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 CW |
575 | } |
576 | } | |
577 | } | |
e37ec39b | 578 | |
e2f80391 TU |
579 | intel_ring_emit(engine, MI_NOOP); |
580 | intel_ring_emit(engine, MI_SET_CONTEXT); | |
581 | intel_ring_emit(engine, | |
bca44d80 | 582 | i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) | |
e80f14b6 | 583 | flags); |
2b7e8082 VS |
584 | /* |
585 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
586 | * WaMiSetContext_Hang:snb,ivb,vlv | |
587 | */ | |
e2f80391 | 588 | intel_ring_emit(engine, MI_NOOP); |
e0556841 | 589 | |
c033666a | 590 | if (INTEL_GEN(dev_priv) >= 7) { |
2c550183 CW |
591 | if (num_rings) { |
592 | struct intel_engine_cs *signaller; | |
e9135c4f | 593 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
2c550183 | 594 | |
e2f80391 TU |
595 | intel_ring_emit(engine, |
596 | MI_LOAD_REGISTER_IMM(num_rings)); | |
c033666a | 597 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 598 | if (signaller == engine) |
2c550183 CW |
599 | continue; |
600 | ||
e9135c4f CW |
601 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
602 | intel_ring_emit_reg(engine, last_reg); | |
e2f80391 TU |
603 | intel_ring_emit(engine, |
604 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 | 605 | } |
e9135c4f CW |
606 | |
607 | /* Insert a delay before the next switch! */ | |
608 | intel_ring_emit(engine, | |
609 | MI_STORE_REGISTER_MEM | | |
610 | MI_SRM_LRM_GLOBAL_GTT); | |
611 | intel_ring_emit_reg(engine, last_reg); | |
612 | intel_ring_emit(engine, engine->scratch.gtt_offset); | |
613 | intel_ring_emit(engine, MI_NOOP); | |
2c550183 | 614 | } |
e2f80391 | 615 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 616 | } |
e37ec39b | 617 | |
e2f80391 | 618 | intel_ring_advance(engine); |
e0556841 BW |
619 | |
620 | return ret; | |
621 | } | |
622 | ||
d200cda6 | 623 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
b0ebde39 | 624 | { |
ff55b5e8 | 625 | u32 *remap_info = req->i915->l3_parity.remap_info[slice]; |
b0ebde39 | 626 | struct intel_engine_cs *engine = req->engine; |
b0ebde39 CW |
627 | int i, ret; |
628 | ||
ff55b5e8 | 629 | if (!remap_info) |
b0ebde39 CW |
630 | return 0; |
631 | ||
ff55b5e8 | 632 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
b0ebde39 CW |
633 | if (ret) |
634 | return ret; | |
635 | ||
636 | /* | |
637 | * Note: We do not worry about the concurrent register cacheline hang | |
638 | * here because no other code should access these registers other than | |
639 | * at initialization time. | |
640 | */ | |
ff55b5e8 CW |
641 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); |
642 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
b0ebde39 CW |
643 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); |
644 | intel_ring_emit(engine, remap_info[i]); | |
645 | } | |
ff55b5e8 | 646 | intel_ring_emit(engine, MI_NOOP); |
b0ebde39 CW |
647 | intel_ring_advance(engine); |
648 | ||
ff55b5e8 | 649 | return 0; |
b0ebde39 CW |
650 | } |
651 | ||
f9326be5 CW |
652 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
653 | struct intel_engine_cs *engine, | |
e2efd130 | 654 | struct i915_gem_context *to) |
317b4e90 | 655 | { |
563222a7 BW |
656 | if (to->remap_slice) |
657 | return false; | |
658 | ||
bca44d80 | 659 | if (!to->engine[RCS].initialised) |
fcb5106d CW |
660 | return false; |
661 | ||
f9326be5 | 662 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
fcb5106d | 663 | return false; |
317b4e90 | 664 | |
fcb5106d | 665 | return to == engine->last_context; |
317b4e90 BW |
666 | } |
667 | ||
668 | static bool | |
f9326be5 CW |
669 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
670 | struct intel_engine_cs *engine, | |
e2efd130 | 671 | struct i915_gem_context *to) |
317b4e90 | 672 | { |
f9326be5 | 673 | if (!ppgtt) |
317b4e90 BW |
674 | return false; |
675 | ||
f9326be5 CW |
676 | /* Always load the ppgtt on first use */ |
677 | if (!engine->last_context) | |
678 | return true; | |
679 | ||
680 | /* Same context without new entries, skip */ | |
e1a8daa2 | 681 | if (engine->last_context == to && |
f9326be5 | 682 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
e1a8daa2 CW |
683 | return false; |
684 | ||
685 | if (engine->id != RCS) | |
317b4e90 BW |
686 | return true; |
687 | ||
c033666a | 688 | if (INTEL_GEN(engine->i915) < 8) |
317b4e90 BW |
689 | return true; |
690 | ||
691 | return false; | |
692 | } | |
693 | ||
694 | static bool | |
f9326be5 | 695 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
e2efd130 | 696 | struct i915_gem_context *to, |
f9326be5 | 697 | u32 hw_flags) |
317b4e90 | 698 | { |
f9326be5 | 699 | if (!ppgtt) |
317b4e90 BW |
700 | return false; |
701 | ||
fcb5106d | 702 | if (!IS_GEN8(to->i915)) |
317b4e90 BW |
703 | return false; |
704 | ||
6702cf16 | 705 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
706 | return true; |
707 | ||
708 | return false; | |
709 | } | |
710 | ||
e1a8daa2 | 711 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
e0556841 | 712 | { |
e2efd130 | 713 | struct i915_gem_context *to = req->ctx; |
4a570db5 | 714 | struct intel_engine_cs *engine = req->engine; |
f9326be5 | 715 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
e2efd130 | 716 | struct i915_gem_context *from; |
fcb5106d | 717 | u32 hw_flags; |
3ccfd19d | 718 | int ret, i; |
e0556841 | 719 | |
f9326be5 | 720 | if (skip_rcs_switch(ppgtt, engine, to)) |
9a3b5304 CW |
721 | return 0; |
722 | ||
7e0d96bc | 723 | /* Trying to pin first makes error handling easier. */ |
bca44d80 | 724 | ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state, |
c033666a | 725 | get_context_alignment(engine->i915), |
e1a8daa2 CW |
726 | 0); |
727 | if (ret) | |
728 | return ret; | |
67e3d297 | 729 | |
acc240d4 DV |
730 | /* |
731 | * Pin can switch back to the default context if we end up calling into | |
732 | * evict_everything - as a last ditch gtt defrag effort that also | |
733 | * switches to the default context. Hence we need to reload from here. | |
fcb5106d CW |
734 | * |
735 | * XXX: Doing so is painfully broken! | |
acc240d4 | 736 | */ |
e2f80391 | 737 | from = engine->last_context; |
acc240d4 DV |
738 | |
739 | /* | |
740 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
741 | * that thanks to write = false in this call and us not setting any gpu |
742 | * write domains when putting a context object onto the active list | |
743 | * (when switching away from it), this won't block. | |
acc240d4 DV |
744 | * |
745 | * XXX: We need a real interface to do this instead of trickery. | |
746 | */ | |
bca44d80 | 747 | ret = i915_gem_object_set_to_gtt_domain(to->engine[RCS].state, false); |
7e0d96bc BW |
748 | if (ret) |
749 | goto unpin_out; | |
d3373a24 | 750 | |
f9326be5 | 751 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
fcb5106d CW |
752 | /* Older GENs and non render rings still want the load first, |
753 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
754 | * Register Immediate commands in Ring Buffer before submitting | |
755 | * a context."*/ | |
756 | trace_switch_mm(engine, to); | |
f9326be5 | 757 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
758 | if (ret) |
759 | goto unpin_out; | |
760 | } | |
761 | ||
bca44d80 | 762 | if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) |
6702cf16 BW |
763 | /* NB: If we inhibit the restore, the context is not allowed to |
764 | * die because future work may end up depending on valid address | |
765 | * space. This means we must enforce that a page table load | |
766 | * occur when this occurs. */ | |
fcb5106d | 767 | hw_flags = MI_RESTORE_INHIBIT; |
f9326be5 | 768 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
fcb5106d CW |
769 | hw_flags = MI_FORCE_RESTORE; |
770 | else | |
771 | hw_flags = 0; | |
e0556841 | 772 | |
fcb5106d CW |
773 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
774 | ret = mi_set_context(req, hw_flags); | |
3ccfd19d | 775 | if (ret) |
fcb5106d | 776 | goto unpin_out; |
3ccfd19d BW |
777 | } |
778 | ||
e0556841 BW |
779 | /* The backing object for the context is done after switching to the |
780 | * *next* context. Therefore we cannot retire the previous context until | |
781 | * the next context has already started running. In fact, the below code | |
782 | * is a bit suboptimal because the retiring can occur simply after the | |
783 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
784 | */ | |
112522f6 | 785 | if (from != NULL) { |
bca44d80 CW |
786 | from->engine[RCS].state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
787 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req); | |
e0556841 BW |
788 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
789 | * whole damn pipeline, we don't need to explicitly mark the | |
790 | * object dirty. The only exception is that the context must be | |
791 | * correct in case the object gets swapped out. Ideally we'd be | |
792 | * able to defer doing this until we know the object would be | |
793 | * swapped, but there is no way to do that yet. | |
794 | */ | |
bca44d80 | 795 | from->engine[RCS].state->dirty = 1; |
112522f6 | 796 | |
c0321e2c | 797 | /* obj is kept alive until the next request by its active ref */ |
bca44d80 | 798 | i915_gem_object_ggtt_unpin(from->engine[RCS].state); |
112522f6 | 799 | i915_gem_context_unreference(from); |
e0556841 | 800 | } |
112522f6 | 801 | i915_gem_context_reference(to); |
e2f80391 | 802 | engine->last_context = to; |
e0556841 | 803 | |
fcb5106d CW |
804 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
805 | * setup, and we do not wish to move them. | |
806 | */ | |
f9326be5 | 807 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
fcb5106d | 808 | trace_switch_mm(engine, to); |
f9326be5 | 809 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
810 | /* The hardware context switch is emitted, but we haven't |
811 | * actually changed the state - so it's probably safe to bail | |
812 | * here. Still, let the user know something dangerous has | |
813 | * happened. | |
814 | */ | |
815 | if (ret) | |
816 | return ret; | |
817 | } | |
818 | ||
f9326be5 CW |
819 | if (ppgtt) |
820 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); | |
fcb5106d CW |
821 | |
822 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
823 | if (!(to->remap_slice & (1<<i))) | |
824 | continue; | |
825 | ||
d200cda6 | 826 | ret = remap_l3(req, i); |
fcb5106d CW |
827 | if (ret) |
828 | return ret; | |
829 | ||
830 | to->remap_slice &= ~(1<<i); | |
831 | } | |
832 | ||
bca44d80 | 833 | if (!to->engine[RCS].initialised) { |
e2f80391 TU |
834 | if (engine->init_context) { |
835 | ret = engine->init_context(req); | |
86d7f238 | 836 | if (ret) |
fcb5106d | 837 | return ret; |
86d7f238 | 838 | } |
bca44d80 | 839 | to->engine[RCS].initialised = true; |
46470fc9 MK |
840 | } |
841 | ||
e0556841 | 842 | return 0; |
7e0d96bc BW |
843 | |
844 | unpin_out: | |
bca44d80 | 845 | i915_gem_object_ggtt_unpin(to->engine[RCS].state); |
7e0d96bc | 846 | return ret; |
e0556841 BW |
847 | } |
848 | ||
849 | /** | |
850 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 851 | * @req: request for which we'll execute the context switch |
e0556841 BW |
852 | * |
853 | * The context life cycle is simple. The context refcount is incremented and | |
854 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 855 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 856 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
857 | * |
858 | * This function should not be used in execlists mode. Instead the context is | |
859 | * switched by writing to the ELSP and requests keep a reference to their | |
860 | * context. | |
e0556841 | 861 | */ |
ba01cc93 | 862 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 863 | { |
4a570db5 | 864 | struct intel_engine_cs *engine = req->engine; |
e0556841 | 865 | |
ecdb5fd8 | 866 | WARN_ON(i915.enable_execlists); |
499f2697 | 867 | lockdep_assert_held(&req->i915->dev->struct_mutex); |
0eea67eb | 868 | |
bca44d80 | 869 | if (!req->ctx->engine[engine->id].state) { |
e2efd130 | 870 | struct i915_gem_context *to = req->ctx; |
f9326be5 CW |
871 | struct i915_hw_ppgtt *ppgtt = |
872 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; | |
e1a8daa2 | 873 | |
f9326be5 | 874 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
e1a8daa2 CW |
875 | int ret; |
876 | ||
877 | trace_switch_mm(engine, to); | |
f9326be5 | 878 | ret = ppgtt->switch_mm(ppgtt, req); |
e1a8daa2 CW |
879 | if (ret) |
880 | return ret; | |
881 | ||
f9326be5 | 882 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
e1a8daa2 CW |
883 | } |
884 | ||
885 | if (to != engine->last_context) { | |
886 | i915_gem_context_reference(to); | |
e2f80391 TU |
887 | if (engine->last_context) |
888 | i915_gem_context_unreference(engine->last_context); | |
e1a8daa2 | 889 | engine->last_context = to; |
691e6415 | 890 | } |
e1a8daa2 | 891 | |
c482972a | 892 | return 0; |
a95f6a00 | 893 | } |
c482972a | 894 | |
e1a8daa2 | 895 | return do_rcs_switch(req); |
e0556841 | 896 | } |
84624813 | 897 | |
ec3e9963 | 898 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 899 | { |
ec3e9963 | 900 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
901 | } |
902 | ||
84624813 BW |
903 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
904 | struct drm_file *file) | |
905 | { | |
84624813 BW |
906 | struct drm_i915_gem_context_create *args = data; |
907 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 908 | struct i915_gem_context *ctx; |
84624813 BW |
909 | int ret; |
910 | ||
ec3e9963 | 911 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
912 | return -ENODEV; |
913 | ||
b31e5136 CW |
914 | if (args->pad != 0) |
915 | return -EINVAL; | |
916 | ||
84624813 BW |
917 | ret = i915_mutex_lock_interruptible(dev); |
918 | if (ret) | |
919 | return ret; | |
920 | ||
d624d86e | 921 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 922 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
923 | if (IS_ERR(ctx)) |
924 | return PTR_ERR(ctx); | |
84624813 | 925 | |
821d66dd | 926 | args->ctx_id = ctx->user_handle; |
84624813 BW |
927 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
928 | ||
be636387 | 929 | return 0; |
84624813 BW |
930 | } |
931 | ||
932 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
933 | struct drm_file *file) | |
934 | { | |
935 | struct drm_i915_gem_context_destroy *args = data; | |
936 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 937 | struct i915_gem_context *ctx; |
84624813 BW |
938 | int ret; |
939 | ||
b31e5136 CW |
940 | if (args->pad != 0) |
941 | return -EINVAL; | |
942 | ||
821d66dd | 943 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 944 | return -ENOENT; |
0eea67eb | 945 | |
84624813 BW |
946 | ret = i915_mutex_lock_interruptible(dev); |
947 | if (ret) | |
948 | return ret; | |
949 | ||
ca585b5d | 950 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
72ad5c45 | 951 | if (IS_ERR(ctx)) { |
84624813 | 952 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 953 | return PTR_ERR(ctx); |
84624813 BW |
954 | } |
955 | ||
d28b99ab | 956 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
dce3271b | 957 | i915_gem_context_unreference(ctx); |
84624813 BW |
958 | mutex_unlock(&dev->struct_mutex); |
959 | ||
960 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
961 | return 0; | |
962 | } | |
c9dc0f35 CW |
963 | |
964 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
965 | struct drm_file *file) | |
966 | { | |
967 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
968 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 969 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
970 | int ret; |
971 | ||
972 | ret = i915_mutex_lock_interruptible(dev); | |
973 | if (ret) | |
974 | return ret; | |
975 | ||
ca585b5d | 976 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
977 | if (IS_ERR(ctx)) { |
978 | mutex_unlock(&dev->struct_mutex); | |
979 | return PTR_ERR(ctx); | |
980 | } | |
981 | ||
982 | args->size = 0; | |
983 | switch (args->param) { | |
984 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
985 | args->value = ctx->hang_stats.ban_period_seconds; | |
986 | break; | |
b1b38278 DW |
987 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
988 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
989 | break; | |
fa8848f2 CW |
990 | case I915_CONTEXT_PARAM_GTT_SIZE: |
991 | if (ctx->ppgtt) | |
992 | args->value = ctx->ppgtt->base.total; | |
993 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
994 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
995 | else | |
62106b4f | 996 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 997 | break; |
c9dc0f35 CW |
998 | default: |
999 | ret = -EINVAL; | |
1000 | break; | |
1001 | } | |
1002 | mutex_unlock(&dev->struct_mutex); | |
1003 | ||
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
1008 | struct drm_file *file) | |
1009 | { | |
1010 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1011 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1012 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1013 | int ret; |
1014 | ||
1015 | ret = i915_mutex_lock_interruptible(dev); | |
1016 | if (ret) | |
1017 | return ret; | |
1018 | ||
ca585b5d | 1019 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1020 | if (IS_ERR(ctx)) { |
1021 | mutex_unlock(&dev->struct_mutex); | |
1022 | return PTR_ERR(ctx); | |
1023 | } | |
1024 | ||
1025 | switch (args->param) { | |
1026 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
1027 | if (args->size) | |
1028 | ret = -EINVAL; | |
1029 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
1030 | !capable(CAP_SYS_ADMIN)) | |
1031 | ret = -EPERM; | |
1032 | else | |
1033 | ctx->hang_stats.ban_period_seconds = args->value; | |
1034 | break; | |
b1b38278 DW |
1035 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1036 | if (args->size) { | |
1037 | ret = -EINVAL; | |
1038 | } else { | |
1039 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
1040 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
1041 | } | |
1042 | break; | |
c9dc0f35 CW |
1043 | default: |
1044 | ret = -EINVAL; | |
1045 | break; | |
1046 | } | |
1047 | mutex_unlock(&dev->struct_mutex); | |
1048 | ||
1049 | return ret; | |
1050 | } | |
d538704b CW |
1051 | |
1052 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, | |
1053 | void *data, struct drm_file *file) | |
1054 | { | |
1055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1056 | struct drm_i915_reset_stats *args = data; | |
1057 | struct i915_ctx_hang_stats *hs; | |
e2efd130 | 1058 | struct i915_gem_context *ctx; |
d538704b CW |
1059 | int ret; |
1060 | ||
1061 | if (args->flags || args->pad) | |
1062 | return -EINVAL; | |
1063 | ||
1064 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) | |
1065 | return -EPERM; | |
1066 | ||
bdb04614 | 1067 | ret = i915_mutex_lock_interruptible(dev); |
d538704b CW |
1068 | if (ret) |
1069 | return ret; | |
1070 | ||
ca585b5d | 1071 | ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id); |
d538704b CW |
1072 | if (IS_ERR(ctx)) { |
1073 | mutex_unlock(&dev->struct_mutex); | |
1074 | return PTR_ERR(ctx); | |
1075 | } | |
1076 | hs = &ctx->hang_stats; | |
1077 | ||
1078 | if (capable(CAP_SYS_ADMIN)) | |
1079 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1080 | else | |
1081 | args->reset_count = 0; | |
1082 | ||
1083 | args->batch_active = hs->batch_active; | |
1084 | args->batch_pending = hs->batch_pending; | |
1085 | ||
1086 | mutex_unlock(&dev->struct_mutex); | |
1087 | ||
1088 | return 0; | |
1089 | } |