]>
Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
40521054 BW |
93 | /* This is a HW constraint. The value below is the largest known requirement |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
95 | * part. It should be safe to decrease this, but it's more future proof as is. | |
96 | */ | |
b731d33d BW |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
98 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 99 | |
b731d33d BW |
100 | static size_t get_context_alignment(struct drm_device *dev) |
101 | { | |
102 | if (IS_GEN6(dev)) | |
103 | return GEN6_CONTEXT_ALIGN; | |
104 | ||
105 | return GEN7_CONTEXT_ALIGN; | |
106 | } | |
107 | ||
254f965c BW |
108 | static int get_context_size(struct drm_device *dev) |
109 | { | |
110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
111 | int ret; | |
112 | u32 reg; | |
113 | ||
114 | switch (INTEL_INFO(dev)->gen) { | |
115 | case 6: | |
116 | reg = I915_READ(CXT_SIZE); | |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
118 | break; | |
119 | case 7: | |
4f91dd6f | 120 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 121 | if (IS_HASWELL(dev)) |
a0de80a0 | 122 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
123 | else |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 125 | break; |
8897644a BW |
126 | case 8: |
127 | ret = GEN8_CXT_TOTAL_SIZE; | |
128 | break; | |
254f965c BW |
129 | default: |
130 | BUG(); | |
131 | } | |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
e9f24d5f TU |
136 | static void i915_gem_context_clean(struct intel_context *ctx) |
137 | { | |
138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; | |
139 | struct i915_vma *vma, *next; | |
140 | ||
61fb5881 | 141 | if (!ppgtt) |
e9f24d5f TU |
142 | return; |
143 | ||
e9f24d5f TU |
144 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
145 | mm_list) { | |
146 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) | |
147 | break; | |
148 | } | |
149 | } | |
150 | ||
dce3271b | 151 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 152 | { |
9ea4feec | 153 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
40521054 | 154 | |
198c974d DCS |
155 | trace_i915_context_free(ctx); |
156 | ||
ae6c4806 | 157 | if (i915.enable_execlists) |
ede7d42b | 158 | intel_lr_context_free(ctx); |
c7c48dfd | 159 | |
e9f24d5f TU |
160 | /* |
161 | * This context is going away and we need to remove all VMAs still | |
162 | * around. This is to handle imported shared objects for which | |
163 | * destructor did not run when their handles were closed. | |
164 | */ | |
165 | i915_gem_context_clean(ctx); | |
166 | ||
ae6c4806 DV |
167 | i915_ppgtt_put(ctx->ppgtt); |
168 | ||
2f295791 BW |
169 | if (ctx->legacy_hw_ctx.rcs_state) |
170 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); | |
c7c48dfd | 171 | list_del(&ctx->link); |
40521054 BW |
172 | kfree(ctx); |
173 | } | |
174 | ||
8c857917 | 175 | struct drm_i915_gem_object * |
aa0c13da OM |
176 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
177 | { | |
178 | struct drm_i915_gem_object *obj; | |
179 | int ret; | |
180 | ||
52613921 | 181 | obj = i915_gem_alloc_object(dev, size); |
aa0c13da OM |
182 | if (obj == NULL) |
183 | return ERR_PTR(-ENOMEM); | |
184 | ||
185 | /* | |
186 | * Try to make the context utilize L3 as well as LLC. | |
187 | * | |
188 | * On VLV we don't have L3 controls in the PTEs so we | |
189 | * shouldn't touch the cache level, especially as that | |
190 | * would make the object snooped which might have a | |
191 | * negative performance impact. | |
192 | */ | |
666a4537 | 193 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
aa0c13da OM |
194 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
195 | /* Failure shouldn't ever happen this early */ | |
196 | if (WARN_ON(ret)) { | |
197 | drm_gem_object_unreference(&obj->base); | |
198 | return ERR_PTR(ret); | |
199 | } | |
200 | } | |
201 | ||
202 | return obj; | |
203 | } | |
204 | ||
273497e5 | 205 | static struct intel_context * |
0eea67eb | 206 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 207 | struct drm_i915_file_private *file_priv) |
40521054 BW |
208 | { |
209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 210 | struct intel_context *ctx; |
c8c470af | 211 | int ret; |
40521054 | 212 | |
f94982b0 | 213 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
214 | if (ctx == NULL) |
215 | return ERR_PTR(-ENOMEM); | |
40521054 | 216 | |
dce3271b | 217 | kref_init(&ctx->ref); |
691e6415 | 218 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 219 | ctx->i915 = dev_priv; |
40521054 | 220 | |
691e6415 | 221 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
222 | struct drm_i915_gem_object *obj = |
223 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
224 | if (IS_ERR(obj)) { | |
225 | ret = PTR_ERR(obj); | |
4615d4c9 | 226 | goto err_out; |
691e6415 | 227 | } |
ea0c76f8 | 228 | ctx->legacy_hw_ctx.rcs_state = obj; |
691e6415 | 229 | } |
40521054 BW |
230 | |
231 | /* Default context will never have a file_priv */ | |
691e6415 CW |
232 | if (file_priv != NULL) { |
233 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 234 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
235 | if (ret < 0) |
236 | goto err_out; | |
237 | } else | |
821d66dd | 238 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
239 | |
240 | ctx->file_priv = file_priv; | |
821d66dd | 241 | ctx->user_handle = ret; |
3ccfd19d BW |
242 | /* NB: Mark all slices as needing a remap so that when the context first |
243 | * loads it will restore whatever remap state already exists. If there | |
244 | * is no remap info, it will be a NOP. */ | |
245 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 246 | |
676fa572 CW |
247 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
248 | ||
146937e5 | 249 | return ctx; |
40521054 BW |
250 | |
251 | err_out: | |
dce3271b | 252 | i915_gem_context_unreference(ctx); |
146937e5 | 253 | return ERR_PTR(ret); |
40521054 BW |
254 | } |
255 | ||
254f965c BW |
256 | /** |
257 | * The default context needs to exist per ring that uses contexts. It stores the | |
258 | * context state of the GPU for applications that don't utilize HW contexts, as | |
259 | * well as an idle case. | |
260 | */ | |
273497e5 | 261 | static struct intel_context * |
0eea67eb | 262 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 263 | struct drm_i915_file_private *file_priv) |
254f965c | 264 | { |
42c3b603 | 265 | const bool is_global_default_ctx = file_priv == NULL; |
273497e5 | 266 | struct intel_context *ctx; |
bdf4fd7e | 267 | int ret = 0; |
40521054 | 268 | |
b731d33d | 269 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 270 | |
0eea67eb | 271 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 272 | if (IS_ERR(ctx)) |
a45d0f6a | 273 | return ctx; |
40521054 | 274 | |
ea0c76f8 | 275 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
42c3b603 CW |
276 | /* We may need to do things with the shrinker which |
277 | * require us to immediately switch back to the default | |
278 | * context. This can cause a problem as pinning the | |
279 | * default context also requires GTT space which may not | |
280 | * be available. To avoid this we always pin the default | |
281 | * context. | |
282 | */ | |
ea0c76f8 | 283 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
1ec9e26d | 284 | get_context_alignment(dev), 0); |
42c3b603 CW |
285 | if (ret) { |
286 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
287 | goto err_destroy; | |
288 | } | |
289 | } | |
290 | ||
d624d86e | 291 | if (USES_FULL_PPGTT(dev)) { |
4d884705 | 292 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e BW |
293 | |
294 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
295 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
296 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 297 | ret = PTR_ERR(ppgtt); |
42c3b603 | 298 | goto err_unpin; |
ae6c4806 DV |
299 | } |
300 | ||
301 | ctx->ppgtt = ppgtt; | |
302 | } | |
bdf4fd7e | 303 | |
198c974d DCS |
304 | trace_i915_context_create(ctx); |
305 | ||
a45d0f6a | 306 | return ctx; |
9a3b5304 | 307 | |
42c3b603 | 308 | err_unpin: |
ea0c76f8 OM |
309 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
310 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
9a3b5304 | 311 | err_destroy: |
37876df6 | 312 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
dce3271b | 313 | i915_gem_context_unreference(ctx); |
a45d0f6a | 314 | return ERR_PTR(ret); |
254f965c BW |
315 | } |
316 | ||
acce9ffa BW |
317 | void i915_gem_context_reset(struct drm_device *dev) |
318 | { | |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa BW |
320 | int i; |
321 | ||
3e5b6f05 TD |
322 | if (i915.enable_execlists) { |
323 | struct intel_context *ctx; | |
324 | ||
325 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
326 | intel_lr_context_reset(dev, ctx); | |
327 | } | |
328 | ||
ecdb5fd8 | 329 | return; |
3e5b6f05 | 330 | } |
ecdb5fd8 | 331 | |
acce9ffa | 332 | for (i = 0; i < I915_NUM_RINGS; i++) { |
a4872ba6 | 333 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
ea0c76f8 | 334 | struct intel_context *lctx = ring->last_context; |
acce9ffa | 335 | |
6689c167 MA |
336 | if (lctx) { |
337 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) | |
338 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); | |
acce9ffa | 339 | |
6689c167 MA |
340 | i915_gem_context_unreference(lctx); |
341 | ring->last_context = NULL; | |
acce9ffa | 342 | } |
acce9ffa BW |
343 | } |
344 | } | |
345 | ||
8245be31 | 346 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
347 | { |
348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 349 | struct intel_context *ctx; |
a45d0f6a | 350 | int i; |
254f965c | 351 | |
2fa48d8d BW |
352 | /* Init should only be called once per module load. Eventually the |
353 | * restriction on the context_disabled check can be loosened. */ | |
354 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 355 | return 0; |
254f965c | 356 | |
a0bd6c31 ZL |
357 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
358 | if (!i915.enable_execlists) { | |
359 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
360 | return -EINVAL; | |
361 | } | |
362 | } | |
363 | ||
ede7d42b OM |
364 | if (i915.enable_execlists) { |
365 | /* NB: intentionally left blank. We will allocate our own | |
366 | * backing objects as we need them, thank you very much */ | |
367 | dev_priv->hw_context_size = 0; | |
368 | } else if (HAS_HW_CONTEXTS(dev)) { | |
691e6415 CW |
369 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
370 | if (dev_priv->hw_context_size > (1<<20)) { | |
371 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
372 | dev_priv->hw_context_size); | |
373 | dev_priv->hw_context_size = 0; | |
374 | } | |
254f965c BW |
375 | } |
376 | ||
d624d86e | 377 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
378 | if (IS_ERR(ctx)) { |
379 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
380 | PTR_ERR(ctx)); | |
381 | return PTR_ERR(ctx); | |
254f965c BW |
382 | } |
383 | ||
ede7d42b OM |
384 | for (i = 0; i < I915_NUM_RINGS; i++) { |
385 | struct intel_engine_cs *ring = &dev_priv->ring[i]; | |
386 | ||
387 | /* NB: RCS will hold a ref for all rings */ | |
388 | ring->default_context = ctx; | |
ede7d42b | 389 | } |
67e3d297 | 390 | |
ede7d42b OM |
391 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
392 | i915.enable_execlists ? "LR" : | |
393 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 394 | return 0; |
254f965c BW |
395 | } |
396 | ||
397 | void i915_gem_context_fini(struct drm_device *dev) | |
398 | { | |
399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 400 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 401 | int i; |
254f965c | 402 | |
ea0c76f8 | 403 | if (dctx->legacy_hw_ctx.rcs_state) { |
691e6415 CW |
404 | /* The only known way to stop the gpu from accessing the hw context is |
405 | * to reset it. Do this as the very last operation to avoid confusing | |
406 | * other code, leading to spurious errors. */ | |
407 | intel_gpu_reset(dev); | |
408 | ||
409 | /* When default context is created and switched to, base object refcount | |
410 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
411 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
412 | * to default context. So we need to unreference the base object once | |
413 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
414 | * can then free the base object correctly. */ | |
415 | WARN_ON(!dev_priv->ring[RCS].last_context); | |
416 | if (dev_priv->ring[RCS].last_context == dctx) { | |
417 | /* Fake switch to NULL context */ | |
ea0c76f8 OM |
418 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
419 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); | |
691e6415 CW |
420 | i915_gem_context_unreference(dctx); |
421 | dev_priv->ring[RCS].last_context = NULL; | |
422 | } | |
d3b448d9 | 423 | |
ea0c76f8 | 424 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
67e3d297 BW |
425 | } |
426 | ||
427 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 428 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
67e3d297 BW |
429 | |
430 | if (ring->last_context) | |
431 | i915_gem_context_unreference(ring->last_context); | |
432 | ||
433 | ring->default_context = NULL; | |
0009e46c | 434 | ring->last_context = NULL; |
71b76d00 BW |
435 | } |
436 | ||
dce3271b | 437 | i915_gem_context_unreference(dctx); |
254f965c BW |
438 | } |
439 | ||
b3dd6b96 | 440 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
2fa48d8d | 441 | { |
b3dd6b96 | 442 | struct intel_engine_cs *ring = req->ring; |
90638cc1 | 443 | int ret; |
bdf4fd7e | 444 | |
e7778be1 | 445 | if (i915.enable_execlists) { |
90638cc1 JH |
446 | if (ring->init_context == NULL) |
447 | return 0; | |
ecdb5fd8 | 448 | |
8753181e | 449 | ret = ring->init_context(req); |
e7778be1 | 450 | } else |
ba01cc93 | 451 | ret = i915_switch_context(req); |
90638cc1 JH |
452 | |
453 | if (ret) { | |
454 | DRM_ERROR("ring init context: %d\n", ret); | |
455 | return ret; | |
456 | } | |
2fa48d8d BW |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
40521054 BW |
461 | static int context_idr_cleanup(int id, void *p, void *data) |
462 | { | |
273497e5 | 463 | struct intel_context *ctx = p; |
40521054 | 464 | |
dce3271b | 465 | i915_gem_context_unreference(ctx); |
40521054 | 466 | return 0; |
254f965c BW |
467 | } |
468 | ||
e422b888 BW |
469 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
470 | { | |
471 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 472 | struct intel_context *ctx; |
e422b888 BW |
473 | |
474 | idr_init(&file_priv->context_idr); | |
475 | ||
0eea67eb | 476 | mutex_lock(&dev->struct_mutex); |
d624d86e | 477 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
478 | mutex_unlock(&dev->struct_mutex); |
479 | ||
f83d6518 | 480 | if (IS_ERR(ctx)) { |
0eea67eb | 481 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 482 | return PTR_ERR(ctx); |
0eea67eb BW |
483 | } |
484 | ||
e422b888 BW |
485 | return 0; |
486 | } | |
487 | ||
254f965c BW |
488 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
489 | { | |
40521054 | 490 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 491 | |
73c273eb | 492 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 493 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
494 | } |
495 | ||
273497e5 | 496 | struct intel_context * |
40521054 BW |
497 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
498 | { | |
273497e5 | 499 | struct intel_context *ctx; |
72ad5c45 | 500 | |
273497e5 | 501 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
502 | if (!ctx) |
503 | return ERR_PTR(-ENOENT); | |
504 | ||
505 | return ctx; | |
254f965c | 506 | } |
e0556841 BW |
507 | |
508 | static inline int | |
1d719cda | 509 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 510 | { |
1d719cda | 511 | struct intel_engine_cs *ring = req->ring; |
e80f14b6 | 512 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
513 | const int num_rings = |
514 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
515 | i915_semaphore_is_enabled(ring->dev) ? | |
516 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : | |
517 | 0; | |
518 | int len, i, ret; | |
e0556841 | 519 | |
12b0286f BW |
520 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
521 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
522 | * explicitly, so we rely on the value at ring init, stored in | |
523 | * itlb_before_ctx_switch. | |
524 | */ | |
057f6a8a | 525 | if (IS_GEN6(ring->dev)) { |
a84c3ae1 | 526 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
527 | if (ret) |
528 | return ret; | |
529 | } | |
530 | ||
e80f14b6 | 531 | /* These flags are for resource streamer on HSW+ */ |
4c436d55 AJ |
532 | if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) |
533 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); | |
534 | else if (INTEL_INFO(ring->dev)->gen < 8) | |
e80f14b6 BW |
535 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
536 | ||
2c550183 CW |
537 | |
538 | len = 4; | |
539 | if (INTEL_INFO(ring->dev)->gen >= 7) | |
540 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); | |
541 | ||
5fb9de1a | 542 | ret = intel_ring_begin(req, len); |
e0556841 BW |
543 | if (ret) |
544 | return ret; | |
545 | ||
b3f797ac | 546 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
2c550183 | 547 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
e37ec39b | 548 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
549 | if (num_rings) { |
550 | struct intel_engine_cs *signaller; | |
551 | ||
552 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); | |
553 | for_each_ring(signaller, to_i915(ring->dev), i) { | |
554 | if (signaller == ring) | |
555 | continue; | |
556 | ||
f92a9162 | 557 | intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base)); |
2c550183 CW |
558 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
559 | } | |
560 | } | |
561 | } | |
e37ec39b | 562 | |
e0556841 BW |
563 | intel_ring_emit(ring, MI_NOOP); |
564 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
1d719cda | 565 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
e80f14b6 | 566 | flags); |
2b7e8082 VS |
567 | /* |
568 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
569 | * WaMiSetContext_Hang:snb,ivb,vlv | |
570 | */ | |
e0556841 BW |
571 | intel_ring_emit(ring, MI_NOOP); |
572 | ||
2c550183 CW |
573 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
574 | if (num_rings) { | |
575 | struct intel_engine_cs *signaller; | |
576 | ||
577 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); | |
578 | for_each_ring(signaller, to_i915(ring->dev), i) { | |
579 | if (signaller == ring) | |
580 | continue; | |
581 | ||
f92a9162 | 582 | intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base)); |
2c550183 CW |
583 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
584 | } | |
585 | } | |
e37ec39b | 586 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 587 | } |
e37ec39b | 588 | |
e0556841 BW |
589 | intel_ring_advance(ring); |
590 | ||
591 | return ret; | |
592 | } | |
593 | ||
317b4e90 BW |
594 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
595 | struct intel_context *from, | |
596 | struct intel_context *to) | |
597 | { | |
563222a7 BW |
598 | if (to->remap_slice) |
599 | return false; | |
600 | ||
9258811c DV |
601 | if (to->ppgtt && from == to && |
602 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) | |
603 | return true; | |
317b4e90 BW |
604 | |
605 | return false; | |
606 | } | |
607 | ||
608 | static bool | |
609 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) | |
610 | { | |
611 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
612 | ||
613 | if (!to->ppgtt) | |
614 | return false; | |
615 | ||
616 | if (INTEL_INFO(ring->dev)->gen < 8) | |
617 | return true; | |
618 | ||
619 | if (ring != &dev_priv->ring[RCS]) | |
620 | return true; | |
621 | ||
622 | return false; | |
623 | } | |
624 | ||
625 | static bool | |
6702cf16 BW |
626 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
627 | u32 hw_flags) | |
317b4e90 BW |
628 | { |
629 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
630 | ||
631 | if (!to->ppgtt) | |
632 | return false; | |
633 | ||
634 | if (!IS_GEN8(ring->dev)) | |
635 | return false; | |
636 | ||
637 | if (ring != &dev_priv->ring[RCS]) | |
638 | return false; | |
639 | ||
6702cf16 | 640 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
641 | return true; |
642 | ||
643 | return false; | |
644 | } | |
645 | ||
abd68d9e | 646 | static int do_switch(struct drm_i915_gem_request *req) |
e0556841 | 647 | { |
abd68d9e JH |
648 | struct intel_context *to = req->ctx; |
649 | struct intel_engine_cs *ring = req->ring; | |
6f65e29a | 650 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
273497e5 | 651 | struct intel_context *from = ring->last_context; |
e0556841 | 652 | u32 hw_flags = 0; |
967ab6b1 | 653 | bool uninitialized = false; |
3ccfd19d | 654 | int ret, i; |
e0556841 | 655 | |
67e3d297 | 656 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
ea0c76f8 OM |
657 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
658 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); | |
67e3d297 | 659 | } |
e0556841 | 660 | |
317b4e90 | 661 | if (should_skip_switch(ring, from, to)) |
9a3b5304 CW |
662 | return 0; |
663 | ||
7e0d96bc BW |
664 | /* Trying to pin first makes error handling easier. */ |
665 | if (ring == &dev_priv->ring[RCS]) { | |
ea0c76f8 | 666 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
1ec9e26d | 667 | get_context_alignment(ring->dev), 0); |
7e0d96bc BW |
668 | if (ret) |
669 | return ret; | |
67e3d297 BW |
670 | } |
671 | ||
acc240d4 DV |
672 | /* |
673 | * Pin can switch back to the default context if we end up calling into | |
674 | * evict_everything - as a last ditch gtt defrag effort that also | |
675 | * switches to the default context. Hence we need to reload from here. | |
676 | */ | |
677 | from = ring->last_context; | |
678 | ||
317b4e90 BW |
679 | if (needs_pd_load_pre(ring, to)) { |
680 | /* Older GENs and non render rings still want the load first, | |
681 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
682 | * Register Immediate commands in Ring Buffer before submitting | |
683 | * a context."*/ | |
198c974d | 684 | trace_switch_mm(ring, to); |
e85b26dc | 685 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
7e0d96bc BW |
686 | if (ret) |
687 | goto unpin_out; | |
563222a7 BW |
688 | |
689 | /* Doing a PD load always reloads the page dirs */ | |
9258811c | 690 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
7e0d96bc BW |
691 | } |
692 | ||
693 | if (ring != &dev_priv->ring[RCS]) { | |
694 | if (from) | |
695 | i915_gem_context_unreference(from); | |
696 | goto done; | |
697 | } | |
698 | ||
acc240d4 DV |
699 | /* |
700 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
701 | * that thanks to write = false in this call and us not setting any gpu |
702 | * write domains when putting a context object onto the active list | |
703 | * (when switching away from it), this won't block. | |
acc240d4 DV |
704 | * |
705 | * XXX: We need a real interface to do this instead of trickery. | |
706 | */ | |
ea0c76f8 | 707 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
7e0d96bc BW |
708 | if (ret) |
709 | goto unpin_out; | |
d3373a24 | 710 | |
6702cf16 | 711 | if (!to->legacy_hw_ctx.initialized) { |
e0556841 | 712 | hw_flags |= MI_RESTORE_INHIBIT; |
6702cf16 BW |
713 | /* NB: If we inhibit the restore, the context is not allowed to |
714 | * die because future work may end up depending on valid address | |
715 | * space. This means we must enforce that a page table load | |
716 | * occur when this occurs. */ | |
717 | } else if (to->ppgtt && | |
9258811c | 718 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
563222a7 | 719 | hw_flags |= MI_FORCE_RESTORE; |
9258811c DV |
720 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
721 | } | |
e0556841 | 722 | |
6702cf16 BW |
723 | /* We should never emit switch_mm more than once */ |
724 | WARN_ON(needs_pd_load_pre(ring, to) && | |
9258811c | 725 | needs_pd_load_post(ring, to, hw_flags)); |
6702cf16 | 726 | |
1d719cda | 727 | ret = mi_set_context(req, hw_flags); |
7e0d96bc BW |
728 | if (ret) |
729 | goto unpin_out; | |
e0556841 | 730 | |
6702cf16 BW |
731 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
732 | * setup, and we do not wish to move them. | |
733 | */ | |
734 | if (needs_pd_load_post(ring, to, hw_flags)) { | |
317b4e90 | 735 | trace_switch_mm(ring, to); |
e85b26dc | 736 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
317b4e90 BW |
737 | /* The hardware context switch is emitted, but we haven't |
738 | * actually changed the state - so it's probably safe to bail | |
739 | * here. Still, let the user know something dangerous has | |
740 | * happened. | |
741 | */ | |
742 | if (ret) { | |
743 | DRM_ERROR("Failed to change address space on context switch\n"); | |
744 | goto unpin_out; | |
745 | } | |
746 | } | |
747 | ||
3ccfd19d BW |
748 | for (i = 0; i < MAX_L3_SLICES; i++) { |
749 | if (!(to->remap_slice & (1<<i))) | |
750 | continue; | |
751 | ||
6909a666 | 752 | ret = i915_gem_l3_remap(req, i); |
3ccfd19d BW |
753 | /* If it failed, try again next round */ |
754 | if (ret) | |
755 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
756 | else | |
757 | to->remap_slice &= ~(1<<i); | |
758 | } | |
759 | ||
e0556841 BW |
760 | /* The backing object for the context is done after switching to the |
761 | * *next* context. Therefore we cannot retire the previous context until | |
762 | * the next context has already started running. In fact, the below code | |
763 | * is a bit suboptimal because the retiring can occur simply after the | |
764 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
765 | */ | |
112522f6 | 766 | if (from != NULL) { |
ea0c76f8 | 767 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
b2af0376 | 768 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
e0556841 BW |
769 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
770 | * whole damn pipeline, we don't need to explicitly mark the | |
771 | * object dirty. The only exception is that the context must be | |
772 | * correct in case the object gets swapped out. Ideally we'd be | |
773 | * able to defer doing this until we know the object would be | |
774 | * swapped, but there is no way to do that yet. | |
775 | */ | |
ea0c76f8 | 776 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
112522f6 | 777 | |
c0321e2c | 778 | /* obj is kept alive until the next request by its active ref */ |
ea0c76f8 | 779 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
112522f6 | 780 | i915_gem_context_unreference(from); |
e0556841 BW |
781 | } |
782 | ||
6702cf16 | 783 | uninitialized = !to->legacy_hw_ctx.initialized; |
ea0c76f8 | 784 | to->legacy_hw_ctx.initialized = true; |
967ab6b1 | 785 | |
67e3d297 | 786 | done: |
112522f6 CW |
787 | i915_gem_context_reference(to); |
788 | ring->last_context = to; | |
e0556841 | 789 | |
967ab6b1 | 790 | if (uninitialized) { |
86d7f238 | 791 | if (ring->init_context) { |
8753181e | 792 | ret = ring->init_context(req); |
86d7f238 AS |
793 | if (ret) |
794 | DRM_ERROR("ring init context: %d\n", ret); | |
795 | } | |
46470fc9 MK |
796 | } |
797 | ||
e0556841 | 798 | return 0; |
7e0d96bc BW |
799 | |
800 | unpin_out: | |
801 | if (ring->id == RCS) | |
ea0c76f8 | 802 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
7e0d96bc | 803 | return ret; |
e0556841 BW |
804 | } |
805 | ||
806 | /** | |
807 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 808 | * @req: request for which we'll execute the context switch |
e0556841 BW |
809 | * |
810 | * The context life cycle is simple. The context refcount is incremented and | |
811 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 812 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 813 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
814 | * |
815 | * This function should not be used in execlists mode. Instead the context is | |
816 | * switched by writing to the ELSP and requests keep a reference to their | |
817 | * context. | |
e0556841 | 818 | */ |
ba01cc93 | 819 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 820 | { |
ba01cc93 | 821 | struct intel_engine_cs *ring = req->ring; |
e0556841 | 822 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e0556841 | 823 | |
ecdb5fd8 | 824 | WARN_ON(i915.enable_execlists); |
0eea67eb BW |
825 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
826 | ||
ba01cc93 JH |
827 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
828 | if (req->ctx != ring->last_context) { | |
829 | i915_gem_context_reference(req->ctx); | |
691e6415 CW |
830 | if (ring->last_context) |
831 | i915_gem_context_unreference(ring->last_context); | |
ba01cc93 | 832 | ring->last_context = req->ctx; |
691e6415 | 833 | } |
c482972a | 834 | return 0; |
a95f6a00 | 835 | } |
c482972a | 836 | |
abd68d9e | 837 | return do_switch(req); |
e0556841 | 838 | } |
84624813 | 839 | |
ec3e9963 | 840 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 841 | { |
ec3e9963 | 842 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
843 | } |
844 | ||
84624813 BW |
845 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
846 | struct drm_file *file) | |
847 | { | |
84624813 BW |
848 | struct drm_i915_gem_context_create *args = data; |
849 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 850 | struct intel_context *ctx; |
84624813 BW |
851 | int ret; |
852 | ||
ec3e9963 | 853 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
854 | return -ENODEV; |
855 | ||
84624813 BW |
856 | ret = i915_mutex_lock_interruptible(dev); |
857 | if (ret) | |
858 | return ret; | |
859 | ||
d624d86e | 860 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 861 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
862 | if (IS_ERR(ctx)) |
863 | return PTR_ERR(ctx); | |
84624813 | 864 | |
821d66dd | 865 | args->ctx_id = ctx->user_handle; |
84624813 BW |
866 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
867 | ||
be636387 | 868 | return 0; |
84624813 BW |
869 | } |
870 | ||
871 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
872 | struct drm_file *file) | |
873 | { | |
874 | struct drm_i915_gem_context_destroy *args = data; | |
875 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 876 | struct intel_context *ctx; |
84624813 BW |
877 | int ret; |
878 | ||
821d66dd | 879 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 880 | return -ENOENT; |
0eea67eb | 881 | |
84624813 BW |
882 | ret = i915_mutex_lock_interruptible(dev); |
883 | if (ret) | |
884 | return ret; | |
885 | ||
886 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 887 | if (IS_ERR(ctx)) { |
84624813 | 888 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 889 | return PTR_ERR(ctx); |
84624813 BW |
890 | } |
891 | ||
821d66dd | 892 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
dce3271b | 893 | i915_gem_context_unreference(ctx); |
84624813 BW |
894 | mutex_unlock(&dev->struct_mutex); |
895 | ||
896 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
897 | return 0; | |
898 | } | |
c9dc0f35 CW |
899 | |
900 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
901 | struct drm_file *file) | |
902 | { | |
903 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
904 | struct drm_i915_gem_context_param *args = data; | |
905 | struct intel_context *ctx; | |
906 | int ret; | |
907 | ||
908 | ret = i915_mutex_lock_interruptible(dev); | |
909 | if (ret) | |
910 | return ret; | |
911 | ||
912 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
913 | if (IS_ERR(ctx)) { | |
914 | mutex_unlock(&dev->struct_mutex); | |
915 | return PTR_ERR(ctx); | |
916 | } | |
917 | ||
918 | args->size = 0; | |
919 | switch (args->param) { | |
920 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
921 | args->value = ctx->hang_stats.ban_period_seconds; | |
922 | break; | |
b1b38278 DW |
923 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
924 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
925 | break; | |
fa8848f2 CW |
926 | case I915_CONTEXT_PARAM_GTT_SIZE: |
927 | if (ctx->ppgtt) | |
928 | args->value = ctx->ppgtt->base.total; | |
929 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
930 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
931 | else | |
932 | args->value = to_i915(dev)->gtt.base.total; | |
933 | break; | |
c9dc0f35 CW |
934 | default: |
935 | ret = -EINVAL; | |
936 | break; | |
937 | } | |
938 | mutex_unlock(&dev->struct_mutex); | |
939 | ||
940 | return ret; | |
941 | } | |
942 | ||
943 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
944 | struct drm_file *file) | |
945 | { | |
946 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
947 | struct drm_i915_gem_context_param *args = data; | |
948 | struct intel_context *ctx; | |
949 | int ret; | |
950 | ||
951 | ret = i915_mutex_lock_interruptible(dev); | |
952 | if (ret) | |
953 | return ret; | |
954 | ||
955 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
956 | if (IS_ERR(ctx)) { | |
957 | mutex_unlock(&dev->struct_mutex); | |
958 | return PTR_ERR(ctx); | |
959 | } | |
960 | ||
961 | switch (args->param) { | |
962 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
963 | if (args->size) | |
964 | ret = -EINVAL; | |
965 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
966 | !capable(CAP_SYS_ADMIN)) | |
967 | ret = -EPERM; | |
968 | else | |
969 | ctx->hang_stats.ban_period_seconds = args->value; | |
970 | break; | |
b1b38278 DW |
971 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
972 | if (args->size) { | |
973 | ret = -EINVAL; | |
974 | } else { | |
975 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
976 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
977 | } | |
978 | break; | |
c9dc0f35 CW |
979 | default: |
980 | ret = -EINVAL; | |
981 | break; | |
982 | } | |
983 | mutex_unlock(&dev->struct_mutex); | |
984 | ||
985 | return ret; | |
986 | } |