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drm/i915: Simplify ring handling in execbuf
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1/*
2 * Copyright © 2011-2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 *
26 */
27
28/*
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
35 *
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
46 *
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
51 *
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
63 *
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
73 *
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
508842a0 76 * GPU. The GPU has loaded its state already and has stored away the gtt
254f965c
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77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
80 *
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
85 *
86 */
87
760285e7
DH
88#include <drm/drmP.h>
89#include <drm/i915_drm.h>
254f965c
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90#include "i915_drv.h"
91
40521054
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92/* This is a HW constraint. The value below is the largest known requirement
93 * I've seen in a spec to date, and that was a workaround for a non-shipping
94 * part. It should be safe to decrease this, but it's more future proof as is.
95 */
b731d33d
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96#define GEN6_CONTEXT_ALIGN (64<<10)
97#define GEN7_CONTEXT_ALIGN 4096
40521054
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98
99static struct i915_hw_context *
100i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
9a3b5304 101static int do_switch(struct i915_hw_context *to);
40521054 102
b731d33d
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103static size_t get_context_alignment(struct drm_device *dev)
104{
105 if (IS_GEN6(dev))
106 return GEN6_CONTEXT_ALIGN;
107
108 return GEN7_CONTEXT_ALIGN;
109}
110
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111static int get_context_size(struct drm_device *dev)
112{
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 int ret;
115 u32 reg;
116
117 switch (INTEL_INFO(dev)->gen) {
118 case 6:
119 reg = I915_READ(CXT_SIZE);
120 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
121 break;
122 case 7:
4f91dd6f 123 reg = I915_READ(GEN7_CXT_SIZE);
2e4291e0 124 if (IS_HASWELL(dev))
a0de80a0 125 ret = HSW_CXT_TOTAL_SIZE;
2e4291e0
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126 else
127 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
254f965c 128 break;
8897644a
BW
129 case 8:
130 ret = GEN8_CXT_TOTAL_SIZE;
131 break;
254f965c
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132 default:
133 BUG();
134 }
135
136 return ret;
137}
138
dce3271b 139void i915_gem_context_free(struct kref *ctx_ref)
40521054 140{
dce3271b
MK
141 struct i915_hw_context *ctx = container_of(ctx_ref,
142 typeof(*ctx), ref);
40521054 143
a33afea5 144 list_del(&ctx->link);
40521054
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145 drm_gem_object_unreference(&ctx->obj->base);
146 kfree(ctx);
147}
148
146937e5 149static struct i915_hw_context *
40521054 150create_hw_context(struct drm_device *dev,
146937e5 151 struct drm_i915_file_private *file_priv)
40521054
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152{
153 struct drm_i915_private *dev_priv = dev->dev_private;
146937e5 154 struct i915_hw_context *ctx;
c8c470af 155 int ret;
40521054 156
f94982b0 157 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
146937e5
BW
158 if (ctx == NULL)
159 return ERR_PTR(-ENOMEM);
40521054 160
dce3271b 161 kref_init(&ctx->ref);
146937e5 162 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
a33afea5 163 INIT_LIST_HEAD(&ctx->link);
146937e5
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164 if (ctx->obj == NULL) {
165 kfree(ctx);
40521054 166 DRM_DEBUG_DRIVER("Context object allocated failed\n");
146937e5 167 return ERR_PTR(-ENOMEM);
40521054
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168 }
169
4615d4c9
CW
170 if (INTEL_INFO(dev)->gen >= 7) {
171 ret = i915_gem_object_set_cache_level(ctx->obj,
350ec881 172 I915_CACHE_L3_LLC);
bb036413
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173 /* Failure shouldn't ever happen this early */
174 if (WARN_ON(ret))
4615d4c9
CW
175 goto err_out;
176 }
177
40521054
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178 /* The ring associated with the context object is handled by the normal
179 * object tracking code. We give an initial ring value simple to pass an
180 * assertion in the context switch code.
181 */
146937e5 182 ctx->ring = &dev_priv->ring[RCS];
a33afea5 183 list_add_tail(&ctx->link, &dev_priv->context_list);
40521054
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184
185 /* Default context will never have a file_priv */
186 if (file_priv == NULL)
146937e5 187 return ctx;
40521054 188
c8c470af
TH
189 ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0,
190 GFP_KERNEL);
191 if (ret < 0)
40521054 192 goto err_out;
dce3271b
MK
193
194 ctx->file_priv = file_priv;
c8c470af 195 ctx->id = ret;
3ccfd19d
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196 /* NB: Mark all slices as needing a remap so that when the context first
197 * loads it will restore whatever remap state already exists. If there
198 * is no remap info, it will be a NOP. */
199 ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
40521054 200
146937e5 201 return ctx;
40521054
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202
203err_out:
dce3271b 204 i915_gem_context_unreference(ctx);
146937e5 205 return ERR_PTR(ret);
40521054
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206}
207
e0556841
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208static inline bool is_default_context(struct i915_hw_context *ctx)
209{
210 return (ctx == ctx->ring->default_context);
211}
212
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213/**
214 * The default context needs to exist per ring that uses contexts. It stores the
215 * context state of the GPU for applications that don't utilize HW contexts, as
216 * well as an idle case.
217 */
b731d33d 218static int create_default_context(struct drm_device *dev)
254f965c 219{
b731d33d 220 struct drm_i915_private *dev_priv = dev->dev_private;
40521054
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221 struct i915_hw_context *ctx;
222 int ret;
223
b731d33d 224 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
40521054 225
b731d33d 226 ctx = create_hw_context(dev, NULL);
146937e5
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227 if (IS_ERR(ctx))
228 return PTR_ERR(ctx);
40521054
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229
230 /* We may need to do things with the shrinker which require us to
231 * immediately switch back to the default context. This can cause a
232 * problem as pinning the default context also requires GTT space which
233 * may not be available. To avoid this we always pin the
234 * default context.
235 */
b731d33d
BW
236 ret = i915_gem_obj_ggtt_pin(ctx->obj, get_context_alignment(dev),
237 false, false);
bb036413
BW
238 if (ret) {
239 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
9a3b5304 240 goto err_destroy;
bb036413 241 }
40521054 242
9a3b5304 243 ret = do_switch(ctx);
bb036413
BW
244 if (ret) {
245 DRM_DEBUG_DRIVER("Switch failed %d\n", ret);
9a3b5304 246 goto err_unpin;
bb036413 247 }
dfabbcb4 248
71b76d00
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249 dev_priv->ring[RCS].default_context = ctx;
250
9a3b5304
CW
251 DRM_DEBUG_DRIVER("Default HW context loaded\n");
252 return 0;
253
254err_unpin:
d7f46fc4 255 i915_gem_object_ggtt_unpin(ctx->obj);
9a3b5304 256err_destroy:
dce3271b 257 i915_gem_context_unreference(ctx);
40521054 258 return ret;
254f965c
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259}
260
8245be31 261int i915_gem_context_init(struct drm_device *dev)
254f965c
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262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
8245be31 264 int ret;
254f965c 265
8245be31
BW
266 if (!HAS_HW_CONTEXTS(dev))
267 return 0;
254f965c
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268
269 /* If called from reset, or thaw... we've been here already */
8245be31
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270 if (dev_priv->ring[RCS].default_context)
271 return 0;
254f965c 272
07ea0d85 273 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
254f965c 274
07ea0d85 275 if (dev_priv->hw_context_size > (1<<20)) {
bb036413 276 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
8245be31 277 return -E2BIG;
254f965c
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278 }
279
b731d33d 280 ret = create_default_context(dev);
8245be31
BW
281 if (ret) {
282 DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %d\n",
283 ret);
284 return ret;
254f965c
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285 }
286
287 DRM_DEBUG_DRIVER("HW context support initialized\n");
8245be31 288 return 0;
254f965c
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289}
290
291void i915_gem_context_fini(struct drm_device *dev)
292{
293 struct drm_i915_private *dev_priv = dev->dev_private;
dce3271b 294 struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
254f965c 295
8245be31 296 if (!HAS_HW_CONTEXTS(dev))
254f965c 297 return;
40521054 298
55a66628
DV
299 /* The only known way to stop the gpu from accessing the hw context is
300 * to reset it. Do this as the very last operation to avoid confusing
301 * other code, leading to spurious errors. */
302 intel_gpu_reset(dev);
303
168f8366
MK
304 /* When default context is created and switched to, base object refcount
305 * will be 2 (+1 from object creation and +1 from do_switch()).
306 * i915_gem_context_fini() will be called after gpu_idle() has switched
307 * to default context. So we need to unreference the base object once
308 * to offset the do_switch part, so that i915_gem_context_unreference()
309 * can then free the base object correctly. */
71b76d00
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310 WARN_ON(!dev_priv->ring[RCS].last_context);
311 if (dev_priv->ring[RCS].last_context == dctx) {
312 /* Fake switch to NULL context */
313 WARN_ON(dctx->obj->active);
d7f46fc4 314 i915_gem_object_ggtt_unpin(dctx->obj);
71b76d00
BW
315 i915_gem_context_unreference(dctx);
316 }
317
d7f46fc4 318 i915_gem_object_ggtt_unpin(dctx->obj);
dce3271b 319 i915_gem_context_unreference(dctx);
71b76d00
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320 dev_priv->ring[RCS].default_context = NULL;
321 dev_priv->ring[RCS].last_context = NULL;
254f965c
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322}
323
40521054
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324static int context_idr_cleanup(int id, void *p, void *data)
325{
73c273eb 326 struct i915_hw_context *ctx = p;
40521054
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327
328 BUG_ON(id == DEFAULT_CONTEXT_ID);
40521054 329
dce3271b 330 i915_gem_context_unreference(ctx);
40521054 331 return 0;
254f965c
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332}
333
c0bb617a 334struct i915_ctx_hang_stats *
11fa3384 335i915_gem_context_get_hang_stats(struct drm_device *dev,
c0bb617a
MK
336 struct drm_file *file,
337 u32 id)
338{
c0bb617a 339 struct drm_i915_file_private *file_priv = file->driver_priv;
11fa3384 340 struct i915_hw_context *ctx;
c0bb617a
MK
341
342 if (id == DEFAULT_CONTEXT_ID)
343 return &file_priv->hang_stats;
344
8245be31
BW
345 if (!HAS_HW_CONTEXTS(dev))
346 return ERR_PTR(-ENOENT);
347
348 ctx = i915_gem_context_get(file->driver_priv, id);
11fa3384 349 if (ctx == NULL)
c0bb617a
MK
350 return ERR_PTR(-ENOENT);
351
11fa3384 352 return &ctx->hang_stats;
c0bb617a
MK
353}
354
e422b888
BW
355int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
356{
357 struct drm_i915_file_private *file_priv = file->driver_priv;
358
359 if (!HAS_HW_CONTEXTS(dev))
360 return 0;
361
362 idr_init(&file_priv->context_idr);
363
364 return 0;
365}
366
254f965c
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367void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
368{
40521054 369 struct drm_i915_file_private *file_priv = file->driver_priv;
254f965c 370
e422b888
BW
371 if (!HAS_HW_CONTEXTS(dev))
372 return;
373
40521054 374 mutex_lock(&dev->struct_mutex);
73c273eb 375 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
40521054
BW
376 idr_destroy(&file_priv->context_idr);
377 mutex_unlock(&dev->struct_mutex);
378}
379
e0556841 380static struct i915_hw_context *
40521054
BW
381i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
382{
383 return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
254f965c 384}
e0556841
BW
385
386static inline int
387mi_set_context(struct intel_ring_buffer *ring,
388 struct i915_hw_context *new_context,
389 u32 hw_flags)
390{
391 int ret;
392
12b0286f
BW
393 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
394 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
395 * explicitly, so we rely on the value at ring init, stored in
396 * itlb_before_ctx_switch.
397 */
398 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
ac82ea2e 399 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
12b0286f
BW
400 if (ret)
401 return ret;
402 }
403
e37ec39b 404 ret = intel_ring_begin(ring, 6);
e0556841
BW
405 if (ret)
406 return ret;
407
8693a824 408 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
e37ec39b
BW
409 if (IS_GEN7(ring->dev))
410 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
411 else
412 intel_ring_emit(ring, MI_NOOP);
413
e0556841
BW
414 intel_ring_emit(ring, MI_NOOP);
415 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 416 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
e0556841
BW
417 MI_MM_SPACE_GTT |
418 MI_SAVE_EXT_STATE_EN |
419 MI_RESTORE_EXT_STATE_EN |
420 hw_flags);
421 /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
422 intel_ring_emit(ring, MI_NOOP);
423
e37ec39b
BW
424 if (IS_GEN7(ring->dev))
425 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
426 else
427 intel_ring_emit(ring, MI_NOOP);
428
e0556841
BW
429 intel_ring_advance(ring);
430
431 return ret;
432}
433
9a3b5304 434static int do_switch(struct i915_hw_context *to)
e0556841 435{
9a3b5304 436 struct intel_ring_buffer *ring = to->ring;
6f65e29a 437 struct drm_i915_private *dev_priv = ring->dev->dev_private;
112522f6 438 struct i915_hw_context *from = ring->last_context;
e0556841 439 u32 hw_flags = 0;
3ccfd19d 440 int ret, i;
e0556841 441
d7f46fc4 442 BUG_ON(from != NULL && from->obj != NULL && !i915_gem_obj_is_pinned(from->obj));
e0556841 443
3ccfd19d 444 if (from == to && !to->remap_slice)
9a3b5304
CW
445 return 0;
446
b731d33d
BW
447 ret = i915_gem_obj_ggtt_pin(to->obj, get_context_alignment(ring->dev),
448 false, false);
e0556841
BW
449 if (ret)
450 return ret;
451
d3373a24
CW
452 /* Clear this page out of any CPU caches for coherent swap-in/out. Note
453 * that thanks to write = false in this call and us not setting any gpu
454 * write domains when putting a context object onto the active list
455 * (when switching away from it), this won't block.
456 * XXX: We need a real interface to do this instead of trickery. */
457 ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
458 if (ret) {
d7f46fc4 459 i915_gem_object_ggtt_unpin(to->obj);
d3373a24
CW
460 return ret;
461 }
462
6f65e29a
BW
463 if (!to->obj->has_global_gtt_mapping) {
464 struct i915_vma *vma = i915_gem_obj_to_vma(to->obj,
465 &dev_priv->gtt.base);
466 vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND);
467 }
3af7b857 468
e0556841
BW
469 if (!to->is_initialized || is_default_context(to))
470 hw_flags |= MI_RESTORE_INHIBIT;
e0556841 471
e0556841
BW
472 ret = mi_set_context(ring, to, hw_flags);
473 if (ret) {
d7f46fc4 474 i915_gem_object_ggtt_unpin(to->obj);
e0556841
BW
475 return ret;
476 }
477
3ccfd19d
BW
478 for (i = 0; i < MAX_L3_SLICES; i++) {
479 if (!(to->remap_slice & (1<<i)))
480 continue;
481
482 ret = i915_gem_l3_remap(ring, i);
483 /* If it failed, try again next round */
484 if (ret)
485 DRM_DEBUG_DRIVER("L3 remapping failed\n");
486 else
487 to->remap_slice &= ~(1<<i);
488 }
489
e0556841
BW
490 /* The backing object for the context is done after switching to the
491 * *next* context. Therefore we cannot retire the previous context until
492 * the next context has already started running. In fact, the below code
493 * is a bit suboptimal because the retiring can occur simply after the
494 * MI_SET_CONTEXT instead of when the next seqno has completed.
495 */
112522f6
CW
496 if (from != NULL) {
497 from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
e2d05a8b 498 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring);
e0556841
BW
499 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
500 * whole damn pipeline, we don't need to explicitly mark the
501 * object dirty. The only exception is that the context must be
502 * correct in case the object gets swapped out. Ideally we'd be
503 * able to defer doing this until we know the object would be
504 * swapped, but there is no way to do that yet.
505 */
112522f6
CW
506 from->obj->dirty = 1;
507 BUG_ON(from->obj->ring != ring);
508
c0321e2c 509 /* obj is kept alive until the next request by its active ref */
d7f46fc4 510 i915_gem_object_ggtt_unpin(from->obj);
112522f6 511 i915_gem_context_unreference(from);
e0556841
BW
512 }
513
112522f6
CW
514 i915_gem_context_reference(to);
515 ring->last_context = to;
e0556841
BW
516 to->is_initialized = true;
517
518 return 0;
519}
520
521/**
522 * i915_switch_context() - perform a GPU context switch.
523 * @ring: ring for which we'll execute the context switch
524 * @file_priv: file_priv associated with the context, may be NULL
525 * @id: context id number
e0556841
BW
526 *
527 * The context life cycle is simple. The context refcount is incremented and
528 * decremented by 1 and create and destroy. If the context is in use by the GPU,
529 * it will have a refoucnt > 1. This allows us to destroy the context abstract
530 * object while letting the normal object tracking destroy the backing BO.
531 */
532int i915_switch_context(struct intel_ring_buffer *ring,
533 struct drm_file *file,
534 int to_id)
535{
536 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e0556841 537 struct i915_hw_context *to;
e0556841 538
8245be31 539 if (!HAS_HW_CONTEXTS(ring->dev))
e0556841
BW
540 return 0;
541
186507e9
BW
542 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
543
e0556841
BW
544 if (ring != &dev_priv->ring[RCS])
545 return 0;
546
e0556841
BW
547 if (to_id == DEFAULT_CONTEXT_ID) {
548 to = ring->default_context;
549 } else {
9a3b5304
CW
550 if (file == NULL)
551 return -EINVAL;
552
553 to = i915_gem_context_get(file->driver_priv, to_id);
e0556841 554 if (to == NULL)
0d326013 555 return -ENOENT;
e0556841
BW
556 }
557
9a3b5304 558 return do_switch(to);
e0556841 559}
84624813
BW
560
561int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
562 struct drm_file *file)
563{
84624813
BW
564 struct drm_i915_gem_context_create *args = data;
565 struct drm_i915_file_private *file_priv = file->driver_priv;
566 struct i915_hw_context *ctx;
567 int ret;
568
569 if (!(dev->driver->driver_features & DRIVER_GEM))
570 return -ENODEV;
571
8245be31 572 if (!HAS_HW_CONTEXTS(dev))
5fa8be65
DV
573 return -ENODEV;
574
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BW
575 ret = i915_mutex_lock_interruptible(dev);
576 if (ret)
577 return ret;
578
146937e5 579 ctx = create_hw_context(dev, file_priv);
84624813 580 mutex_unlock(&dev->struct_mutex);
be636387
DC
581 if (IS_ERR(ctx))
582 return PTR_ERR(ctx);
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BW
583
584 args->ctx_id = ctx->id;
585 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
586
be636387 587 return 0;
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BW
588}
589
590int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
591 struct drm_file *file)
592{
593 struct drm_i915_gem_context_destroy *args = data;
594 struct drm_i915_file_private *file_priv = file->driver_priv;
84624813
BW
595 struct i915_hw_context *ctx;
596 int ret;
597
598 if (!(dev->driver->driver_features & DRIVER_GEM))
599 return -ENODEV;
600
601 ret = i915_mutex_lock_interruptible(dev);
602 if (ret)
603 return ret;
604
605 ctx = i915_gem_context_get(file_priv, args->ctx_id);
606 if (!ctx) {
607 mutex_unlock(&dev->struct_mutex);
0d326013 608 return -ENOENT;
84624813
BW
609 }
610
dce3271b
MK
611 idr_remove(&ctx->file_priv->context_idr, ctx->id);
612 i915_gem_context_unreference(ctx);
84624813
BW
613 mutex_unlock(&dev->struct_mutex);
614
615 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
616 return 0;
617}