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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
76 | * GPU. The GPU has loaded it's state already and has stored away the gtt | |
77 | * offset of the BO. The GPU is not actively referencing the data at this | |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
88 | #include "drmP.h" | |
89 | #include "i915_drm.h" | |
90 | #include "i915_drv.h" | |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
96 | #define CONTEXT_ALIGN (64<<10) | |
97 | ||
98 | static struct i915_hw_context * | |
99 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); | |
9a3b5304 | 100 | static int do_switch(struct i915_hw_context *to); |
40521054 | 101 | |
254f965c BW |
102 | static int get_context_size(struct drm_device *dev) |
103 | { | |
104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
105 | int ret; | |
106 | u32 reg; | |
107 | ||
108 | switch (INTEL_INFO(dev)->gen) { | |
109 | case 6: | |
110 | reg = I915_READ(CXT_SIZE); | |
111 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
112 | break; | |
113 | case 7: | |
4f91dd6f BW |
114 | reg = I915_READ(GEN7_CXT_SIZE); |
115 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c BW |
116 | break; |
117 | default: | |
118 | BUG(); | |
119 | } | |
120 | ||
121 | return ret; | |
122 | } | |
123 | ||
40521054 BW |
124 | static void do_destroy(struct i915_hw_context *ctx) |
125 | { | |
126 | struct drm_device *dev = ctx->obj->base.dev; | |
127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
128 | ||
129 | if (ctx->file_priv) | |
130 | idr_remove(&ctx->file_priv->context_idr, ctx->id); | |
131 | else | |
132 | BUG_ON(ctx != dev_priv->ring[RCS].default_context); | |
133 | ||
134 | drm_gem_object_unreference(&ctx->obj->base); | |
135 | kfree(ctx); | |
136 | } | |
137 | ||
146937e5 | 138 | static struct i915_hw_context * |
40521054 | 139 | create_hw_context(struct drm_device *dev, |
146937e5 | 140 | struct drm_i915_file_private *file_priv) |
40521054 BW |
141 | { |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146937e5 | 143 | struct i915_hw_context *ctx; |
40521054 BW |
144 | int ret, id; |
145 | ||
146937e5 BW |
146 | ctx = kzalloc(sizeof(struct drm_i915_file_private), GFP_KERNEL); |
147 | if (ctx == NULL) | |
148 | return ERR_PTR(-ENOMEM); | |
40521054 | 149 | |
146937e5 BW |
150 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
151 | if (ctx->obj == NULL) { | |
152 | kfree(ctx); | |
40521054 | 153 | DRM_DEBUG_DRIVER("Context object allocated failed\n"); |
146937e5 | 154 | return ERR_PTR(-ENOMEM); |
40521054 BW |
155 | } |
156 | ||
157 | /* The ring associated with the context object is handled by the normal | |
158 | * object tracking code. We give an initial ring value simple to pass an | |
159 | * assertion in the context switch code. | |
160 | */ | |
146937e5 | 161 | ctx->ring = &dev_priv->ring[RCS]; |
40521054 BW |
162 | |
163 | /* Default context will never have a file_priv */ | |
164 | if (file_priv == NULL) | |
146937e5 | 165 | return ctx; |
40521054 | 166 | |
146937e5 | 167 | ctx->file_priv = file_priv; |
40521054 BW |
168 | |
169 | again: | |
170 | if (idr_pre_get(&file_priv->context_idr, GFP_KERNEL) == 0) { | |
171 | ret = -ENOMEM; | |
172 | DRM_DEBUG_DRIVER("idr allocation failed\n"); | |
173 | goto err_out; | |
174 | } | |
175 | ||
146937e5 | 176 | ret = idr_get_new_above(&file_priv->context_idr, ctx, |
40521054 BW |
177 | DEFAULT_CONTEXT_ID + 1, &id); |
178 | if (ret == 0) | |
146937e5 | 179 | ctx->id = id; |
40521054 BW |
180 | |
181 | if (ret == -EAGAIN) | |
182 | goto again; | |
183 | else if (ret) | |
184 | goto err_out; | |
185 | ||
146937e5 | 186 | return ctx; |
40521054 BW |
187 | |
188 | err_out: | |
146937e5 BW |
189 | do_destroy(ctx); |
190 | return ERR_PTR(ret); | |
40521054 BW |
191 | } |
192 | ||
e0556841 BW |
193 | static inline bool is_default_context(struct i915_hw_context *ctx) |
194 | { | |
195 | return (ctx == ctx->ring->default_context); | |
196 | } | |
197 | ||
254f965c BW |
198 | /** |
199 | * The default context needs to exist per ring that uses contexts. It stores the | |
200 | * context state of the GPU for applications that don't utilize HW contexts, as | |
201 | * well as an idle case. | |
202 | */ | |
203 | static int create_default_context(struct drm_i915_private *dev_priv) | |
204 | { | |
40521054 BW |
205 | struct i915_hw_context *ctx; |
206 | int ret; | |
207 | ||
208 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); | |
209 | ||
146937e5 BW |
210 | ctx = create_hw_context(dev_priv->dev, NULL); |
211 | if (IS_ERR(ctx)) | |
212 | return PTR_ERR(ctx); | |
40521054 BW |
213 | |
214 | /* We may need to do things with the shrinker which require us to | |
215 | * immediately switch back to the default context. This can cause a | |
216 | * problem as pinning the default context also requires GTT space which | |
217 | * may not be available. To avoid this we always pin the | |
218 | * default context. | |
219 | */ | |
146937e5 | 220 | dev_priv->ring[RCS].default_context = ctx; |
40521054 | 221 | ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false); |
9a3b5304 CW |
222 | if (ret) |
223 | goto err_destroy; | |
40521054 | 224 | |
9a3b5304 CW |
225 | ret = do_switch(ctx); |
226 | if (ret) | |
227 | goto err_unpin; | |
dfabbcb4 | 228 | |
9a3b5304 CW |
229 | DRM_DEBUG_DRIVER("Default HW context loaded\n"); |
230 | return 0; | |
231 | ||
232 | err_unpin: | |
233 | i915_gem_object_unpin(ctx->obj); | |
234 | err_destroy: | |
235 | do_destroy(ctx); | |
40521054 | 236 | return ret; |
254f965c BW |
237 | } |
238 | ||
239 | void i915_gem_context_init(struct drm_device *dev) | |
240 | { | |
241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
242 | uint32_t ctx_size; | |
243 | ||
e158c5aa BW |
244 | if (!HAS_HW_CONTEXTS(dev)) { |
245 | dev_priv->hw_contexts_disabled = true; | |
254f965c | 246 | return; |
e158c5aa | 247 | } |
254f965c BW |
248 | |
249 | /* If called from reset, or thaw... we've been here already */ | |
40521054 BW |
250 | if (dev_priv->hw_contexts_disabled || |
251 | dev_priv->ring[RCS].default_context) | |
254f965c BW |
252 | return; |
253 | ||
254 | ctx_size = get_context_size(dev); | |
255 | dev_priv->hw_context_size = get_context_size(dev); | |
256 | dev_priv->hw_context_size = round_up(dev_priv->hw_context_size, 4096); | |
257 | ||
258 | if (ctx_size <= 0 || ctx_size > (1<<20)) { | |
259 | dev_priv->hw_contexts_disabled = true; | |
260 | return; | |
261 | } | |
262 | ||
263 | if (create_default_context(dev_priv)) { | |
264 | dev_priv->hw_contexts_disabled = true; | |
265 | return; | |
266 | } | |
267 | ||
268 | DRM_DEBUG_DRIVER("HW context support initialized\n"); | |
269 | } | |
270 | ||
271 | void i915_gem_context_fini(struct drm_device *dev) | |
272 | { | |
273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
274 | ||
275 | if (dev_priv->hw_contexts_disabled) | |
276 | return; | |
40521054 | 277 | |
55a66628 DV |
278 | /* The only known way to stop the gpu from accessing the hw context is |
279 | * to reset it. Do this as the very last operation to avoid confusing | |
280 | * other code, leading to spurious errors. */ | |
281 | intel_gpu_reset(dev); | |
282 | ||
40521054 BW |
283 | i915_gem_object_unpin(dev_priv->ring[RCS].default_context->obj); |
284 | ||
285 | do_destroy(dev_priv->ring[RCS].default_context); | |
254f965c BW |
286 | } |
287 | ||
40521054 BW |
288 | static int context_idr_cleanup(int id, void *p, void *data) |
289 | { | |
73c273eb | 290 | struct i915_hw_context *ctx = p; |
40521054 BW |
291 | |
292 | BUG_ON(id == DEFAULT_CONTEXT_ID); | |
40521054 BW |
293 | |
294 | do_destroy(ctx); | |
295 | ||
296 | return 0; | |
254f965c BW |
297 | } |
298 | ||
299 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) | |
300 | { | |
40521054 | 301 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 302 | |
40521054 | 303 | mutex_lock(&dev->struct_mutex); |
73c273eb | 304 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 BW |
305 | idr_destroy(&file_priv->context_idr); |
306 | mutex_unlock(&dev->struct_mutex); | |
307 | } | |
308 | ||
e0556841 | 309 | static struct i915_hw_context * |
40521054 BW |
310 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
311 | { | |
312 | return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); | |
254f965c | 313 | } |
e0556841 BW |
314 | |
315 | static inline int | |
316 | mi_set_context(struct intel_ring_buffer *ring, | |
317 | struct i915_hw_context *new_context, | |
318 | u32 hw_flags) | |
319 | { | |
320 | int ret; | |
321 | ||
12b0286f BW |
322 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
323 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
324 | * explicitly, so we rely on the value at ring init, stored in | |
325 | * itlb_before_ctx_switch. | |
326 | */ | |
327 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | |
328 | ret = ring->flush(ring, 0, 0); | |
329 | if (ret) | |
330 | return ret; | |
331 | } | |
332 | ||
e37ec39b | 333 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
334 | if (ret) |
335 | return ret; | |
336 | ||
e37ec39b BW |
337 | if (IS_GEN7(ring->dev)) |
338 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
339 | else | |
340 | intel_ring_emit(ring, MI_NOOP); | |
341 | ||
e0556841 BW |
342 | intel_ring_emit(ring, MI_NOOP); |
343 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
344 | intel_ring_emit(ring, new_context->obj->gtt_offset | | |
345 | MI_MM_SPACE_GTT | | |
346 | MI_SAVE_EXT_STATE_EN | | |
347 | MI_RESTORE_EXT_STATE_EN | | |
348 | hw_flags); | |
349 | /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ | |
350 | intel_ring_emit(ring, MI_NOOP); | |
351 | ||
e37ec39b BW |
352 | if (IS_GEN7(ring->dev)) |
353 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
354 | else | |
355 | intel_ring_emit(ring, MI_NOOP); | |
356 | ||
e0556841 BW |
357 | intel_ring_advance(ring); |
358 | ||
359 | return ret; | |
360 | } | |
361 | ||
9a3b5304 | 362 | static int do_switch(struct i915_hw_context *to) |
e0556841 | 363 | { |
9a3b5304 CW |
364 | struct intel_ring_buffer *ring = to->ring; |
365 | struct drm_i915_gem_object *from_obj = ring->last_context_obj; | |
e0556841 BW |
366 | u32 hw_flags = 0; |
367 | int ret; | |
368 | ||
e0556841 BW |
369 | BUG_ON(from_obj != NULL && from_obj->pin_count == 0); |
370 | ||
9a3b5304 CW |
371 | if (from_obj == to->obj) |
372 | return 0; | |
373 | ||
e0556841 BW |
374 | ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false); |
375 | if (ret) | |
376 | return ret; | |
377 | ||
d3373a24 CW |
378 | /* Clear this page out of any CPU caches for coherent swap-in/out. Note |
379 | * that thanks to write = false in this call and us not setting any gpu | |
380 | * write domains when putting a context object onto the active list | |
381 | * (when switching away from it), this won't block. | |
382 | * XXX: We need a real interface to do this instead of trickery. */ | |
383 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); | |
384 | if (ret) { | |
385 | i915_gem_object_unpin(to->obj); | |
386 | return ret; | |
387 | } | |
388 | ||
3af7b857 DV |
389 | if (!to->obj->has_global_gtt_mapping) |
390 | i915_gem_gtt_bind_object(to->obj, to->obj->cache_level); | |
391 | ||
e0556841 BW |
392 | if (!to->is_initialized || is_default_context(to)) |
393 | hw_flags |= MI_RESTORE_INHIBIT; | |
394 | else if (WARN_ON_ONCE(from_obj == to->obj)) /* not yet expected */ | |
395 | hw_flags |= MI_FORCE_RESTORE; | |
396 | ||
e0556841 BW |
397 | ret = mi_set_context(ring, to, hw_flags); |
398 | if (ret) { | |
399 | i915_gem_object_unpin(to->obj); | |
400 | return ret; | |
401 | } | |
402 | ||
403 | /* The backing object for the context is done after switching to the | |
404 | * *next* context. Therefore we cannot retire the previous context until | |
405 | * the next context has already started running. In fact, the below code | |
406 | * is a bit suboptimal because the retiring can occur simply after the | |
407 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
408 | */ | |
409 | if (from_obj != NULL) { | |
9a3b5304 | 410 | u32 seqno = i915_gem_next_request_seqno(ring); |
e0556841 BW |
411 | from_obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
412 | i915_gem_object_move_to_active(from_obj, ring, seqno); | |
413 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the | |
414 | * whole damn pipeline, we don't need to explicitly mark the | |
415 | * object dirty. The only exception is that the context must be | |
416 | * correct in case the object gets swapped out. Ideally we'd be | |
417 | * able to defer doing this until we know the object would be | |
418 | * swapped, but there is no way to do that yet. | |
419 | */ | |
420 | from_obj->dirty = 1; | |
9a3b5304 | 421 | BUG_ON(from_obj->ring != ring); |
e0556841 | 422 | i915_gem_object_unpin(from_obj); |
b259b312 CW |
423 | |
424 | drm_gem_object_unreference(&from_obj->base); | |
e0556841 BW |
425 | } |
426 | ||
b259b312 | 427 | drm_gem_object_reference(&to->obj->base); |
e0556841 BW |
428 | ring->last_context_obj = to->obj; |
429 | to->is_initialized = true; | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | /** | |
435 | * i915_switch_context() - perform a GPU context switch. | |
436 | * @ring: ring for which we'll execute the context switch | |
437 | * @file_priv: file_priv associated with the context, may be NULL | |
438 | * @id: context id number | |
439 | * @seqno: sequence number by which the new context will be switched to | |
440 | * @flags: | |
441 | * | |
442 | * The context life cycle is simple. The context refcount is incremented and | |
443 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
444 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
445 | * object while letting the normal object tracking destroy the backing BO. | |
446 | */ | |
447 | int i915_switch_context(struct intel_ring_buffer *ring, | |
448 | struct drm_file *file, | |
449 | int to_id) | |
450 | { | |
451 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 452 | struct i915_hw_context *to; |
e0556841 BW |
453 | |
454 | if (dev_priv->hw_contexts_disabled) | |
455 | return 0; | |
456 | ||
457 | if (ring != &dev_priv->ring[RCS]) | |
458 | return 0; | |
459 | ||
e0556841 BW |
460 | if (to_id == DEFAULT_CONTEXT_ID) { |
461 | to = ring->default_context; | |
462 | } else { | |
9a3b5304 CW |
463 | if (file == NULL) |
464 | return -EINVAL; | |
465 | ||
466 | to = i915_gem_context_get(file->driver_priv, to_id); | |
e0556841 | 467 | if (to == NULL) |
0d326013 | 468 | return -ENOENT; |
e0556841 BW |
469 | } |
470 | ||
9a3b5304 | 471 | return do_switch(to); |
e0556841 | 472 | } |
84624813 BW |
473 | |
474 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
475 | struct drm_file *file) | |
476 | { | |
5fa8be65 | 477 | struct drm_i915_private *dev_priv = dev->dev_private; |
84624813 BW |
478 | struct drm_i915_gem_context_create *args = data; |
479 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
480 | struct i915_hw_context *ctx; | |
481 | int ret; | |
482 | ||
483 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
484 | return -ENODEV; | |
485 | ||
5fa8be65 DV |
486 | if (dev_priv->hw_contexts_disabled) |
487 | return -ENODEV; | |
488 | ||
84624813 BW |
489 | ret = i915_mutex_lock_interruptible(dev); |
490 | if (ret) | |
491 | return ret; | |
492 | ||
146937e5 | 493 | ctx = create_hw_context(dev, file_priv); |
84624813 | 494 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
495 | if (IS_ERR(ctx)) |
496 | return PTR_ERR(ctx); | |
84624813 BW |
497 | |
498 | args->ctx_id = ctx->id; | |
499 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
500 | ||
be636387 | 501 | return 0; |
84624813 BW |
502 | } |
503 | ||
504 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
505 | struct drm_file *file) | |
506 | { | |
507 | struct drm_i915_gem_context_destroy *args = data; | |
508 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
84624813 BW |
509 | struct i915_hw_context *ctx; |
510 | int ret; | |
511 | ||
512 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
513 | return -ENODEV; | |
514 | ||
515 | ret = i915_mutex_lock_interruptible(dev); | |
516 | if (ret) | |
517 | return ret; | |
518 | ||
519 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
520 | if (!ctx) { | |
521 | mutex_unlock(&dev->struct_mutex); | |
0d326013 | 522 | return -ENOENT; |
84624813 BW |
523 | } |
524 | ||
525 | do_destroy(ctx); | |
526 | ||
527 | mutex_unlock(&dev->struct_mutex); | |
528 | ||
529 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
530 | return 0; | |
531 | } |