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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
a415d355 CW |
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 38 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c | 39 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
0079a7df | 40 | #define __EXEC_OBJECT_PURGEABLE (1<<27) |
d23db88c CW |
41 | |
42 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 43 | |
27173f1f BW |
44 | struct eb_vmas { |
45 | struct list_head vmas; | |
67731b87 | 46 | int and; |
eef90ccb | 47 | union { |
27173f1f | 48 | struct i915_vma *lut[0]; |
eef90ccb CW |
49 | struct hlist_head buckets[0]; |
50 | }; | |
67731b87 CW |
51 | }; |
52 | ||
27173f1f | 53 | static struct eb_vmas * |
17601cbc | 54 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 55 | { |
27173f1f | 56 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
57 | |
58 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 59 | unsigned size = args->buffer_count; |
27173f1f BW |
60 | size *= sizeof(struct i915_vma *); |
61 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
62 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
63 | } | |
64 | ||
65 | if (eb == NULL) { | |
b205ca57 DV |
66 | unsigned size = args->buffer_count; |
67 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 68 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
69 | while (count > 2*size) |
70 | count >>= 1; | |
71 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 72 | sizeof(struct eb_vmas), |
eef90ccb CW |
73 | GFP_TEMPORARY); |
74 | if (eb == NULL) | |
75 | return eb; | |
76 | ||
77 | eb->and = count - 1; | |
78 | } else | |
79 | eb->and = -args->buffer_count; | |
80 | ||
27173f1f | 81 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
82 | return eb; |
83 | } | |
84 | ||
85 | static void | |
27173f1f | 86 | eb_reset(struct eb_vmas *eb) |
67731b87 | 87 | { |
eef90ccb CW |
88 | if (eb->and >= 0) |
89 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
90 | } |
91 | ||
3b96eff4 | 92 | static int |
27173f1f BW |
93 | eb_lookup_vmas(struct eb_vmas *eb, |
94 | struct drm_i915_gem_exec_object2 *exec, | |
95 | const struct drm_i915_gem_execbuffer2 *args, | |
96 | struct i915_address_space *vm, | |
97 | struct drm_file *file) | |
3b96eff4 | 98 | { |
27173f1f BW |
99 | struct drm_i915_gem_object *obj; |
100 | struct list_head objects; | |
9ae9ab52 | 101 | int i, ret; |
3b96eff4 | 102 | |
27173f1f | 103 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 104 | spin_lock(&file->table_lock); |
27173f1f BW |
105 | /* Grab a reference to the object and release the lock so we can lookup |
106 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 107 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
108 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
109 | if (obj == NULL) { | |
110 | spin_unlock(&file->table_lock); | |
111 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
112 | exec[i].handle, i); | |
27173f1f | 113 | ret = -ENOENT; |
9ae9ab52 | 114 | goto err; |
3b96eff4 CW |
115 | } |
116 | ||
27173f1f | 117 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
118 | spin_unlock(&file->table_lock); |
119 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
120 | obj, exec[i].handle, i); | |
27173f1f | 121 | ret = -EINVAL; |
9ae9ab52 | 122 | goto err; |
3b96eff4 CW |
123 | } |
124 | ||
355a7018 TH |
125 | WARN_ONCE(obj->base.dumb, |
126 | "GPU use of dumb buffer is illegal.\n"); | |
127 | ||
3b96eff4 | 128 | drm_gem_object_reference(&obj->base); |
27173f1f BW |
129 | list_add_tail(&obj->obj_exec_link, &objects); |
130 | } | |
131 | spin_unlock(&file->table_lock); | |
3b96eff4 | 132 | |
27173f1f | 133 | i = 0; |
9ae9ab52 | 134 | while (!list_empty(&objects)) { |
27173f1f | 135 | struct i915_vma *vma; |
6f65e29a | 136 | |
9ae9ab52 CW |
137 | obj = list_first_entry(&objects, |
138 | struct drm_i915_gem_object, | |
139 | obj_exec_link); | |
140 | ||
e656a6cb DV |
141 | /* |
142 | * NOTE: We can leak any vmas created here when something fails | |
143 | * later on. But that's no issue since vma_unbind can deal with | |
144 | * vmas which are not actually bound. And since only | |
145 | * lookup_or_create exists as an interface to get at the vma | |
146 | * from the (obj, vm) we don't run the risk of creating | |
147 | * duplicated vmas for the same vm. | |
148 | */ | |
da51a1e7 | 149 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 150 | if (IS_ERR(vma)) { |
27173f1f BW |
151 | DRM_DEBUG("Failed to lookup VMA\n"); |
152 | ret = PTR_ERR(vma); | |
9ae9ab52 | 153 | goto err; |
27173f1f BW |
154 | } |
155 | ||
9ae9ab52 | 156 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 157 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 158 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
159 | |
160 | vma->exec_entry = &exec[i]; | |
eef90ccb | 161 | if (eb->and < 0) { |
27173f1f | 162 | eb->lut[i] = vma; |
eef90ccb CW |
163 | } else { |
164 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
165 | vma->exec_handle = handle; |
166 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
167 | &eb->buckets[handle & eb->and]); |
168 | } | |
27173f1f | 169 | ++i; |
3b96eff4 | 170 | } |
3b96eff4 | 171 | |
9ae9ab52 | 172 | return 0; |
27173f1f | 173 | |
27173f1f | 174 | |
9ae9ab52 | 175 | err: |
27173f1f BW |
176 | while (!list_empty(&objects)) { |
177 | obj = list_first_entry(&objects, | |
178 | struct drm_i915_gem_object, | |
179 | obj_exec_link); | |
180 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 181 | drm_gem_object_unreference(&obj->base); |
27173f1f | 182 | } |
9ae9ab52 CW |
183 | /* |
184 | * Objects already transfered to the vmas list will be unreferenced by | |
185 | * eb_destroy. | |
186 | */ | |
187 | ||
27173f1f | 188 | return ret; |
3b96eff4 CW |
189 | } |
190 | ||
27173f1f | 191 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 192 | { |
eef90ccb CW |
193 | if (eb->and < 0) { |
194 | if (handle >= -eb->and) | |
195 | return NULL; | |
196 | return eb->lut[handle]; | |
197 | } else { | |
198 | struct hlist_head *head; | |
199 | struct hlist_node *node; | |
67731b87 | 200 | |
eef90ccb CW |
201 | head = &eb->buckets[handle & eb->and]; |
202 | hlist_for_each(node, head) { | |
27173f1f | 203 | struct i915_vma *vma; |
67731b87 | 204 | |
27173f1f BW |
205 | vma = hlist_entry(node, struct i915_vma, exec_node); |
206 | if (vma->exec_handle == handle) | |
207 | return vma; | |
eef90ccb CW |
208 | } |
209 | return NULL; | |
210 | } | |
67731b87 CW |
211 | } |
212 | ||
a415d355 CW |
213 | static void |
214 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
215 | { | |
216 | struct drm_i915_gem_exec_object2 *entry; | |
217 | struct drm_i915_gem_object *obj = vma->obj; | |
218 | ||
219 | if (!drm_mm_node_allocated(&vma->node)) | |
220 | return; | |
221 | ||
222 | entry = vma->exec_entry; | |
223 | ||
224 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
225 | i915_gem_object_unpin_fence(obj); | |
226 | ||
227 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 228 | vma->pin_count--; |
a415d355 | 229 | |
0079a7df BV |
230 | if (entry->flags & __EXEC_OBJECT_PURGEABLE) |
231 | obj->madv = I915_MADV_DONTNEED; | |
232 | ||
233 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | | |
234 | __EXEC_OBJECT_HAS_PIN | | |
235 | __EXEC_OBJECT_PURGEABLE); | |
a415d355 CW |
236 | } |
237 | ||
238 | static void eb_destroy(struct eb_vmas *eb) | |
239 | { | |
27173f1f BW |
240 | while (!list_empty(&eb->vmas)) { |
241 | struct i915_vma *vma; | |
bcffc3fa | 242 | |
27173f1f BW |
243 | vma = list_first_entry(&eb->vmas, |
244 | struct i915_vma, | |
bcffc3fa | 245 | exec_list); |
27173f1f | 246 | list_del_init(&vma->exec_list); |
a415d355 | 247 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 248 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 249 | } |
67731b87 CW |
250 | kfree(eb); |
251 | } | |
252 | ||
dabdfe02 CW |
253 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
254 | { | |
2cc86b82 CW |
255 | return (HAS_LLC(obj->base.dev) || |
256 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 257 | !obj->map_and_fenceable || |
dabdfe02 CW |
258 | obj->cache_level != I915_CACHE_NONE); |
259 | } | |
260 | ||
5032d871 RB |
261 | static int |
262 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
263 | struct drm_i915_gem_relocation_entry *reloc, |
264 | uint64_t target_offset) | |
5032d871 | 265 | { |
3c94ceee | 266 | struct drm_device *dev = obj->base.dev; |
5032d871 | 267 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 268 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 269 | char *vaddr; |
8b78f0e5 | 270 | int ret; |
5032d871 | 271 | |
2cc86b82 | 272 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
273 | if (ret) |
274 | return ret; | |
275 | ||
276 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
277 | reloc->offset >> PAGE_SHIFT)); | |
d9ceb957 | 278 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
279 | |
280 | if (INTEL_INFO(dev)->gen >= 8) { | |
281 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
282 | ||
283 | if (page_offset == 0) { | |
284 | kunmap_atomic(vaddr); | |
285 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
286 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
287 | } | |
288 | ||
d9ceb957 | 289 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
290 | } |
291 | ||
5032d871 RB |
292 | kunmap_atomic(vaddr); |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int | |
298 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
299 | struct drm_i915_gem_relocation_entry *reloc, |
300 | uint64_t target_offset) | |
5032d871 RB |
301 | { |
302 | struct drm_device *dev = obj->base.dev; | |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 304 | uint64_t delta = reloc->delta + target_offset; |
906843c3 | 305 | uint64_t offset; |
5032d871 | 306 | void __iomem *reloc_page; |
8b78f0e5 | 307 | int ret; |
5032d871 RB |
308 | |
309 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
310 | if (ret) | |
311 | return ret; | |
312 | ||
313 | ret = i915_gem_object_put_fence(obj); | |
314 | if (ret) | |
315 | return ret; | |
316 | ||
317 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
318 | offset = i915_gem_obj_ggtt_offset(obj); |
319 | offset += reloc->offset; | |
5032d871 | 320 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
906843c3 CW |
321 | offset & PAGE_MASK); |
322 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
323 | |
324 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 325 | offset += sizeof(uint32_t); |
3c94ceee | 326 | |
906843c3 | 327 | if (offset_in_page(offset) == 0) { |
3c94ceee | 328 | io_mapping_unmap_atomic(reloc_page); |
906843c3 CW |
329 | reloc_page = |
330 | io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
331 | offset); | |
3c94ceee BW |
332 | } |
333 | ||
906843c3 CW |
334 | iowrite32(upper_32_bits(delta), |
335 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
336 | } |
337 | ||
5032d871 RB |
338 | io_mapping_unmap_atomic(reloc_page); |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
54cf91dc CW |
343 | static int |
344 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 345 | struct eb_vmas *eb, |
3e7a0322 | 346 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
347 | { |
348 | struct drm_device *dev = obj->base.dev; | |
349 | struct drm_gem_object *target_obj; | |
149c8407 | 350 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 351 | struct i915_vma *target_vma; |
d9ceb957 | 352 | uint64_t target_offset; |
8b78f0e5 | 353 | int ret; |
54cf91dc | 354 | |
67731b87 | 355 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
356 | target_vma = eb_get_vma(eb, reloc->target_handle); |
357 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 358 | return -ENOENT; |
27173f1f BW |
359 | target_i915_obj = target_vma->obj; |
360 | target_obj = &target_vma->obj->base; | |
54cf91dc | 361 | |
5ce09725 | 362 | target_offset = target_vma->node.start; |
54cf91dc | 363 | |
e844b990 EA |
364 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
365 | * pipe_control writes because the gpu doesn't properly redirect them | |
366 | * through the ppgtt for non_secure batchbuffers. */ | |
367 | if (unlikely(IS_GEN6(dev) && | |
368 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
fe14d5f4 TU |
369 | !(target_vma->bound & GLOBAL_BIND))) { |
370 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, | |
371 | GLOBAL_BIND); | |
372 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) | |
373 | return ret; | |
374 | } | |
e844b990 | 375 | |
54cf91dc | 376 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 377 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 378 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
379 | "obj %p target %d offset %d " |
380 | "read %08x write %08x", | |
381 | obj, reloc->target_handle, | |
382 | (int) reloc->offset, | |
383 | reloc->read_domains, | |
384 | reloc->write_domain); | |
8b78f0e5 | 385 | return -EINVAL; |
54cf91dc | 386 | } |
4ca4a250 DV |
387 | if (unlikely((reloc->write_domain | reloc->read_domains) |
388 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 389 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
390 | "obj %p target %d offset %d " |
391 | "read %08x write %08x", | |
392 | obj, reloc->target_handle, | |
393 | (int) reloc->offset, | |
394 | reloc->read_domains, | |
395 | reloc->write_domain); | |
8b78f0e5 | 396 | return -EINVAL; |
54cf91dc | 397 | } |
54cf91dc CW |
398 | |
399 | target_obj->pending_read_domains |= reloc->read_domains; | |
400 | target_obj->pending_write_domain |= reloc->write_domain; | |
401 | ||
402 | /* If the relocation already has the right value in it, no | |
403 | * more work needs to be done. | |
404 | */ | |
405 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 406 | return 0; |
54cf91dc CW |
407 | |
408 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
409 | if (unlikely(reloc->offset > |
410 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 411 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
412 | "obj %p target %d offset %d size %d.\n", |
413 | obj, reloc->target_handle, | |
414 | (int) reloc->offset, | |
415 | (int) obj->base.size); | |
8b78f0e5 | 416 | return -EINVAL; |
54cf91dc | 417 | } |
b8f7ab17 | 418 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 419 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
420 | "obj %p target %d offset %d.\n", |
421 | obj, reloc->target_handle, | |
422 | (int) reloc->offset); | |
8b78f0e5 | 423 | return -EINVAL; |
54cf91dc CW |
424 | } |
425 | ||
dabdfe02 CW |
426 | /* We can't wait for rendering with pagefaults disabled */ |
427 | if (obj->active && in_atomic()) | |
428 | return -EFAULT; | |
429 | ||
5032d871 | 430 | if (use_cpu_reloc(obj)) |
d9ceb957 | 431 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
5032d871 | 432 | else |
d9ceb957 | 433 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
54cf91dc | 434 | |
d4d36014 DV |
435 | if (ret) |
436 | return ret; | |
437 | ||
54cf91dc CW |
438 | /* and update the user's relocation entry */ |
439 | reloc->presumed_offset = target_offset; | |
440 | ||
67731b87 | 441 | return 0; |
54cf91dc CW |
442 | } |
443 | ||
444 | static int | |
27173f1f BW |
445 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
446 | struct eb_vmas *eb) | |
54cf91dc | 447 | { |
1d83f442 CW |
448 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
449 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 450 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 451 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 452 | int remain, ret; |
54cf91dc | 453 | |
2bb4629a | 454 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 455 | |
1d83f442 CW |
456 | remain = entry->relocation_count; |
457 | while (remain) { | |
458 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
459 | int count = remain; | |
460 | if (count > ARRAY_SIZE(stack_reloc)) | |
461 | count = ARRAY_SIZE(stack_reloc); | |
462 | remain -= count; | |
463 | ||
464 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
465 | return -EFAULT; |
466 | ||
1d83f442 CW |
467 | do { |
468 | u64 offset = r->presumed_offset; | |
54cf91dc | 469 | |
3e7a0322 | 470 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
471 | if (ret) |
472 | return ret; | |
473 | ||
474 | if (r->presumed_offset != offset && | |
475 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
476 | &r->presumed_offset, | |
477 | sizeof(r->presumed_offset))) { | |
478 | return -EFAULT; | |
479 | } | |
480 | ||
481 | user_relocs++; | |
482 | r++; | |
483 | } while (--count); | |
54cf91dc CW |
484 | } |
485 | ||
486 | return 0; | |
1d83f442 | 487 | #undef N_RELOC |
54cf91dc CW |
488 | } |
489 | ||
490 | static int | |
27173f1f BW |
491 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
492 | struct eb_vmas *eb, | |
493 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 494 | { |
27173f1f | 495 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
496 | int i, ret; |
497 | ||
498 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 499 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
500 | if (ret) |
501 | return ret; | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | static int | |
17601cbc | 508 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 509 | { |
27173f1f | 510 | struct i915_vma *vma; |
d4aeee77 CW |
511 | int ret = 0; |
512 | ||
513 | /* This is the fast path and we cannot handle a pagefault whilst | |
514 | * holding the struct mutex lest the user pass in the relocations | |
515 | * contained within a mmaped bo. For in such a case we, the page | |
516 | * fault handler would call i915_gem_fault() and we would try to | |
517 | * acquire the struct mutex again. Obviously this is bad and so | |
518 | * lockdep complains vehemently. | |
519 | */ | |
520 | pagefault_disable(); | |
27173f1f BW |
521 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
522 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 523 | if (ret) |
d4aeee77 | 524 | break; |
54cf91dc | 525 | } |
d4aeee77 | 526 | pagefault_enable(); |
54cf91dc | 527 | |
d4aeee77 | 528 | return ret; |
54cf91dc CW |
529 | } |
530 | ||
1690e1eb | 531 | static int |
27173f1f | 532 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 533 | struct intel_engine_cs *ring, |
27173f1f | 534 | bool *need_reloc) |
1690e1eb | 535 | { |
6f65e29a | 536 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 537 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 538 | uint64_t flags; |
1690e1eb CW |
539 | int ret; |
540 | ||
1ec9e26d | 541 | flags = 0; |
e6a84468 | 542 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
c826c449 | 543 | flags |= PIN_GLOBAL | PIN_MAPPABLE; |
1ec9e26d | 544 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
bf3d149b | 545 | flags |= PIN_GLOBAL; |
d23db88c CW |
546 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
547 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
1ec9e26d DV |
548 | |
549 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
1690e1eb CW |
550 | if (ret) |
551 | return ret; | |
552 | ||
7788a765 CW |
553 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
554 | ||
82b6b6d7 CW |
555 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
556 | ret = i915_gem_object_get_fence(obj); | |
557 | if (ret) | |
558 | return ret; | |
9a5a53b3 | 559 | |
82b6b6d7 CW |
560 | if (i915_gem_object_pin_fence(obj)) |
561 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
562 | } |
563 | ||
27173f1f BW |
564 | if (entry->offset != vma->node.start) { |
565 | entry->offset = vma->node.start; | |
ed5982e6 DV |
566 | *need_reloc = true; |
567 | } | |
568 | ||
569 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
570 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
571 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
572 | } | |
573 | ||
1690e1eb | 574 | return 0; |
7788a765 | 575 | } |
1690e1eb | 576 | |
d23db88c | 577 | static bool |
e6a84468 | 578 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
579 | { |
580 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 581 | |
e6a84468 CW |
582 | if (entry->relocation_count == 0) |
583 | return false; | |
584 | ||
585 | if (!i915_is_ggtt(vma->vm)) | |
586 | return false; | |
587 | ||
588 | /* See also use_cpu_reloc() */ | |
589 | if (HAS_LLC(vma->obj->base.dev)) | |
590 | return false; | |
591 | ||
592 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
593 | return false; | |
594 | ||
595 | return true; | |
596 | } | |
597 | ||
598 | static bool | |
599 | eb_vma_misplaced(struct i915_vma *vma) | |
600 | { | |
601 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
602 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 603 | |
e6a84468 | 604 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
d23db88c CW |
605 | !i915_is_ggtt(vma->vm)); |
606 | ||
607 | if (entry->alignment && | |
608 | vma->node.start & (entry->alignment - 1)) | |
609 | return true; | |
610 | ||
e6a84468 | 611 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) |
d23db88c CW |
612 | return true; |
613 | ||
614 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && | |
615 | vma->node.start < BATCH_OFFSET_BIAS) | |
616 | return true; | |
617 | ||
618 | return false; | |
619 | } | |
620 | ||
54cf91dc | 621 | static int |
a4872ba6 | 622 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 623 | struct list_head *vmas, |
ed5982e6 | 624 | bool *need_relocs) |
54cf91dc | 625 | { |
432e58ed | 626 | struct drm_i915_gem_object *obj; |
27173f1f | 627 | struct i915_vma *vma; |
68c8c17f | 628 | struct i915_address_space *vm; |
27173f1f | 629 | struct list_head ordered_vmas; |
7788a765 CW |
630 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
631 | int retry; | |
6fe4f140 | 632 | |
227f782e CW |
633 | i915_gem_retire_requests_ring(ring); |
634 | ||
68c8c17f BW |
635 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
636 | ||
27173f1f BW |
637 | INIT_LIST_HEAD(&ordered_vmas); |
638 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
639 | struct drm_i915_gem_exec_object2 *entry; |
640 | bool need_fence, need_mappable; | |
641 | ||
27173f1f BW |
642 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
643 | obj = vma->obj; | |
644 | entry = vma->exec_entry; | |
6fe4f140 | 645 | |
82b6b6d7 CW |
646 | if (!has_fenced_gpu_access) |
647 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 648 | need_fence = |
6fe4f140 CW |
649 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
650 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 651 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 652 | |
e6a84468 CW |
653 | if (need_mappable) { |
654 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; | |
27173f1f | 655 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 656 | } else |
27173f1f | 657 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 658 | |
ed5982e6 | 659 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 660 | obj->base.pending_write_domain = 0; |
6fe4f140 | 661 | } |
27173f1f | 662 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
663 | |
664 | /* Attempt to pin all of the buffers into the GTT. | |
665 | * This is done in 3 phases: | |
666 | * | |
667 | * 1a. Unbind all objects that do not match the GTT constraints for | |
668 | * the execbuffer (fenceable, mappable, alignment etc). | |
669 | * 1b. Increment pin count for already bound objects. | |
670 | * 2. Bind new objects. | |
671 | * 3. Decrement pin count. | |
672 | * | |
7788a765 | 673 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
674 | * room for the earlier objects *unless* we need to defragment. |
675 | */ | |
676 | retry = 0; | |
677 | do { | |
7788a765 | 678 | int ret = 0; |
54cf91dc CW |
679 | |
680 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 681 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 682 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
683 | continue; |
684 | ||
e6a84468 | 685 | if (eb_vma_misplaced(vma)) |
27173f1f | 686 | ret = i915_vma_unbind(vma); |
54cf91dc | 687 | else |
27173f1f | 688 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 689 | if (ret) |
54cf91dc | 690 | goto err; |
54cf91dc CW |
691 | } |
692 | ||
693 | /* Bind fresh objects */ | |
27173f1f BW |
694 | list_for_each_entry(vma, vmas, exec_list) { |
695 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 696 | continue; |
54cf91dc | 697 | |
27173f1f | 698 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
699 | if (ret) |
700 | goto err; | |
54cf91dc CW |
701 | } |
702 | ||
a415d355 | 703 | err: |
6c085a72 | 704 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
705 | return ret; |
706 | ||
a415d355 CW |
707 | /* Decrement pin count for bound objects */ |
708 | list_for_each_entry(vma, vmas, exec_list) | |
709 | i915_gem_execbuffer_unreserve_vma(vma); | |
710 | ||
68c8c17f | 711 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
712 | if (ret) |
713 | return ret; | |
54cf91dc CW |
714 | } while (1); |
715 | } | |
716 | ||
717 | static int | |
718 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 719 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 720 | struct drm_file *file, |
a4872ba6 | 721 | struct intel_engine_cs *ring, |
27173f1f BW |
722 | struct eb_vmas *eb, |
723 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
724 | { |
725 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
726 | struct i915_address_space *vm; |
727 | struct i915_vma *vma; | |
ed5982e6 | 728 | bool need_relocs; |
dd6864a4 | 729 | int *reloc_offset; |
54cf91dc | 730 | int i, total, ret; |
b205ca57 | 731 | unsigned count = args->buffer_count; |
54cf91dc | 732 | |
27173f1f BW |
733 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
734 | ||
67731b87 | 735 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
736 | while (!list_empty(&eb->vmas)) { |
737 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
738 | list_del_init(&vma->exec_list); | |
a415d355 | 739 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 740 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
741 | } |
742 | ||
54cf91dc CW |
743 | mutex_unlock(&dev->struct_mutex); |
744 | ||
745 | total = 0; | |
746 | for (i = 0; i < count; i++) | |
432e58ed | 747 | total += exec[i].relocation_count; |
54cf91dc | 748 | |
dd6864a4 | 749 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 750 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
751 | if (reloc == NULL || reloc_offset == NULL) { |
752 | drm_free_large(reloc); | |
753 | drm_free_large(reloc_offset); | |
54cf91dc CW |
754 | mutex_lock(&dev->struct_mutex); |
755 | return -ENOMEM; | |
756 | } | |
757 | ||
758 | total = 0; | |
759 | for (i = 0; i < count; i++) { | |
760 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
761 | u64 invalid_offset = (u64)-1; |
762 | int j; | |
54cf91dc | 763 | |
2bb4629a | 764 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
765 | |
766 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 767 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
768 | ret = -EFAULT; |
769 | mutex_lock(&dev->struct_mutex); | |
770 | goto err; | |
771 | } | |
772 | ||
262b6d36 CW |
773 | /* As we do not update the known relocation offsets after |
774 | * relocating (due to the complexities in lock handling), | |
775 | * we need to mark them as invalid now so that we force the | |
776 | * relocation processing next time. Just in case the target | |
777 | * object is evicted and then rebound into its old | |
778 | * presumed_offset before the next execbuffer - if that | |
779 | * happened we would make the mistake of assuming that the | |
780 | * relocations were valid. | |
781 | */ | |
782 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
783 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
784 | &invalid_offset, | |
785 | sizeof(invalid_offset))) { | |
262b6d36 CW |
786 | ret = -EFAULT; |
787 | mutex_lock(&dev->struct_mutex); | |
788 | goto err; | |
789 | } | |
790 | } | |
791 | ||
dd6864a4 | 792 | reloc_offset[i] = total; |
432e58ed | 793 | total += exec[i].relocation_count; |
54cf91dc CW |
794 | } |
795 | ||
796 | ret = i915_mutex_lock_interruptible(dev); | |
797 | if (ret) { | |
798 | mutex_lock(&dev->struct_mutex); | |
799 | goto err; | |
800 | } | |
801 | ||
67731b87 | 802 | /* reacquire the objects */ |
67731b87 | 803 | eb_reset(eb); |
27173f1f | 804 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
805 | if (ret) |
806 | goto err; | |
67731b87 | 807 | |
ed5982e6 | 808 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 809 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
810 | if (ret) |
811 | goto err; | |
812 | ||
27173f1f BW |
813 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
814 | int offset = vma->exec_entry - exec; | |
815 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
816 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
817 | if (ret) |
818 | goto err; | |
54cf91dc CW |
819 | } |
820 | ||
821 | /* Leave the user relocations as are, this is the painfully slow path, | |
822 | * and we want to avoid the complication of dropping the lock whilst | |
823 | * having buffers reserved in the aperture and so causing spurious | |
824 | * ENOSPC for random operations. | |
825 | */ | |
826 | ||
827 | err: | |
828 | drm_free_large(reloc); | |
dd6864a4 | 829 | drm_free_large(reloc_offset); |
54cf91dc CW |
830 | return ret; |
831 | } | |
832 | ||
54cf91dc | 833 | static int |
a4872ba6 | 834 | i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, |
27173f1f | 835 | struct list_head *vmas) |
54cf91dc | 836 | { |
27173f1f | 837 | struct i915_vma *vma; |
6ac42f41 | 838 | uint32_t flush_domains = 0; |
000433b6 | 839 | bool flush_chipset = false; |
432e58ed | 840 | int ret; |
54cf91dc | 841 | |
27173f1f BW |
842 | list_for_each_entry(vma, vmas, exec_list) { |
843 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 844 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
845 | if (ret) |
846 | return ret; | |
6ac42f41 DV |
847 | |
848 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 849 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 850 | |
6ac42f41 | 851 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
852 | } |
853 | ||
000433b6 | 854 | if (flush_chipset) |
e76e9aeb | 855 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
856 | |
857 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
858 | wmb(); | |
859 | ||
09cf7c9a CW |
860 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
861 | * any residual writes from the previous batch. | |
862 | */ | |
a7b9761d | 863 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
864 | } |
865 | ||
432e58ed CW |
866 | static bool |
867 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 868 | { |
ed5982e6 DV |
869 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
870 | return false; | |
871 | ||
432e58ed | 872 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
873 | } |
874 | ||
875 | static int | |
ad19f10b CW |
876 | validate_exec_list(struct drm_device *dev, |
877 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
878 | int count) |
879 | { | |
b205ca57 DV |
880 | unsigned relocs_total = 0; |
881 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
882 | unsigned invalid_flags; |
883 | int i; | |
884 | ||
885 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
886 | if (USES_FULL_PPGTT(dev)) | |
887 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
888 | |
889 | for (i = 0; i < count; i++) { | |
2bb4629a | 890 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
891 | int length; /* limited by fault_in_pages_readable() */ |
892 | ||
ad19f10b | 893 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
894 | return -EINVAL; |
895 | ||
3118a4f6 KC |
896 | /* First check for malicious input causing overflow in |
897 | * the worst case where we need to allocate the entire | |
898 | * relocation tree as a single array. | |
899 | */ | |
900 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 901 | return -EINVAL; |
3118a4f6 | 902 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
903 | |
904 | length = exec[i].relocation_count * | |
905 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
906 | /* |
907 | * We must check that the entire relocation array is safe | |
908 | * to read, but since we may need to update the presumed | |
909 | * offsets during execution, check for full write access. | |
910 | */ | |
54cf91dc CW |
911 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
912 | return -EFAULT; | |
913 | ||
d330a953 | 914 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
915 | if (fault_in_multipages_readable(ptr, length)) |
916 | return -EFAULT; | |
917 | } | |
54cf91dc CW |
918 | } |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
273497e5 | 923 | static struct intel_context * |
d299cce7 | 924 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 925 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 926 | { |
273497e5 | 927 | struct intel_context *ctx = NULL; |
d299cce7 MK |
928 | struct i915_ctx_hang_stats *hs; |
929 | ||
821d66dd | 930 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
931 | return ERR_PTR(-EINVAL); |
932 | ||
41bde553 | 933 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 934 | if (IS_ERR(ctx)) |
41bde553 | 935 | return ctx; |
d299cce7 | 936 | |
41bde553 | 937 | hs = &ctx->hang_stats; |
d299cce7 MK |
938 | if (hs->banned) { |
939 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 940 | return ERR_PTR(-EIO); |
d299cce7 MK |
941 | } |
942 | ||
ec3e9963 OM |
943 | if (i915.enable_execlists && !ctx->engine[ring->id].state) { |
944 | int ret = intel_lr_context_deferred_create(ctx, ring); | |
945 | if (ret) { | |
946 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
947 | return ERR_PTR(ret); | |
948 | } | |
949 | } | |
950 | ||
41bde553 | 951 | return ctx; |
d299cce7 MK |
952 | } |
953 | ||
ba8b7ccb | 954 | void |
27173f1f | 955 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
a4872ba6 | 956 | struct intel_engine_cs *ring) |
432e58ed | 957 | { |
97b2a6a1 | 958 | struct drm_i915_gem_request *req = intel_ring_get_request(ring); |
27173f1f | 959 | struct i915_vma *vma; |
432e58ed | 960 | |
27173f1f | 961 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 962 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 963 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
964 | u32 old_read = obj->base.read_domains; |
965 | u32 old_write = obj->base.write_domain; | |
db53a302 | 966 | |
432e58ed | 967 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
968 | if (obj->base.write_domain == 0) |
969 | obj->base.pending_read_domains |= obj->base.read_domains; | |
970 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 971 | |
e2d05a8b | 972 | i915_vma_move_to_active(vma, ring); |
432e58ed CW |
973 | if (obj->base.write_domain) { |
974 | obj->dirty = 1; | |
97b2a6a1 | 975 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 DV |
976 | |
977 | intel_fb_obj_invalidate(obj, ring); | |
c8725f3d CW |
978 | |
979 | /* update for the implicit flush after a batch */ | |
980 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 981 | } |
82b6b6d7 | 982 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 983 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 CW |
984 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
985 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
986 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
987 | &dev_priv->mm.fence_list); | |
988 | } | |
989 | } | |
432e58ed | 990 | |
db53a302 | 991 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
992 | } |
993 | } | |
994 | ||
ba8b7ccb | 995 | void |
54cf91dc | 996 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
432e58ed | 997 | struct drm_file *file, |
a4872ba6 | 998 | struct intel_engine_cs *ring, |
7d736f4f | 999 | struct drm_i915_gem_object *obj) |
54cf91dc | 1000 | { |
cc889e0f DV |
1001 | /* Unconditionally force add_request to emit a full flush. */ |
1002 | ring->gpu_caches_dirty = true; | |
54cf91dc | 1003 | |
432e58ed | 1004 | /* Add a breadcrumb for the completion of the batch buffer */ |
9400ae5c | 1005 | (void)__i915_add_request(ring, file, obj); |
432e58ed | 1006 | } |
54cf91dc | 1007 | |
ae662d31 EA |
1008 | static int |
1009 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
a4872ba6 | 1010 | struct intel_engine_cs *ring) |
ae662d31 | 1011 | { |
50227e1c | 1012 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1013 | int ret, i; |
1014 | ||
9d662da8 DV |
1015 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1016 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1017 | return -EINVAL; | |
1018 | } | |
ae662d31 EA |
1019 | |
1020 | ret = intel_ring_begin(ring, 4 * 3); | |
1021 | if (ret) | |
1022 | return ret; | |
1023 | ||
1024 | for (i = 0; i < 4; i++) { | |
1025 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1026 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1027 | intel_ring_emit(ring, 0); | |
1028 | } | |
1029 | ||
1030 | intel_ring_advance(ring); | |
1031 | ||
1032 | return 0; | |
1033 | } | |
1034 | ||
5c6c6003 CW |
1035 | static int |
1036 | i915_emit_box(struct intel_engine_cs *ring, | |
1037 | struct drm_clip_rect *box, | |
1038 | int DR1, int DR4) | |
1039 | { | |
1040 | int ret; | |
1041 | ||
1042 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || | |
1043 | box->y2 <= 0 || box->x2 <= 0) { | |
1044 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
1045 | box->x1, box->y1, box->x2, box->y2); | |
1046 | return -EINVAL; | |
1047 | } | |
1048 | ||
1049 | if (INTEL_INFO(ring->dev)->gen >= 4) { | |
1050 | ret = intel_ring_begin(ring, 4); | |
1051 | if (ret) | |
1052 | return ret; | |
1053 | ||
1054 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965); | |
1055 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1056 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1057 | intel_ring_emit(ring, DR4); | |
1058 | } else { | |
1059 | ret = intel_ring_begin(ring, 6); | |
1060 | if (ret) | |
1061 | return ret; | |
1062 | ||
1063 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO); | |
1064 | intel_ring_emit(ring, DR1); | |
1065 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1066 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1067 | intel_ring_emit(ring, DR4); | |
1068 | intel_ring_emit(ring, 0); | |
1069 | } | |
1070 | intel_ring_advance(ring); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | ||
a83014d3 OM |
1076 | int |
1077 | i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, | |
1078 | struct intel_engine_cs *ring, | |
1079 | struct intel_context *ctx, | |
1080 | struct drm_i915_gem_execbuffer2 *args, | |
1081 | struct list_head *vmas, | |
1082 | struct drm_i915_gem_object *batch_obj, | |
1083 | u64 exec_start, u32 flags) | |
78382593 OM |
1084 | { |
1085 | struct drm_clip_rect *cliprects = NULL; | |
1086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1087 | u64 exec_len; | |
1088 | int instp_mode; | |
1089 | u32 instp_mask; | |
1090 | int i, ret = 0; | |
1091 | ||
1092 | if (args->num_cliprects != 0) { | |
1093 | if (ring != &dev_priv->ring[RCS]) { | |
1094 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); | |
1095 | return -EINVAL; | |
1096 | } | |
1097 | ||
1098 | if (INTEL_INFO(dev)->gen >= 5) { | |
1099 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1100 | return -EINVAL; | |
1101 | } | |
1102 | ||
1103 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { | |
1104 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1105 | args->num_cliprects); | |
1106 | return -EINVAL; | |
1107 | } | |
1108 | ||
1109 | cliprects = kcalloc(args->num_cliprects, | |
1110 | sizeof(*cliprects), | |
1111 | GFP_KERNEL); | |
1112 | if (cliprects == NULL) { | |
1113 | ret = -ENOMEM; | |
1114 | goto error; | |
1115 | } | |
1116 | ||
1117 | if (copy_from_user(cliprects, | |
1118 | to_user_ptr(args->cliprects_ptr), | |
1119 | sizeof(*cliprects)*args->num_cliprects)) { | |
1120 | ret = -EFAULT; | |
1121 | goto error; | |
1122 | } | |
1123 | } else { | |
1124 | if (args->DR4 == 0xffffffff) { | |
1125 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1126 | args->DR4 = 0; | |
1127 | } | |
1128 | ||
1129 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
1130 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
1131 | return -EINVAL; | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | ret = i915_gem_execbuffer_move_to_gpu(ring, vmas); | |
1136 | if (ret) | |
1137 | goto error; | |
1138 | ||
1139 | ret = i915_switch_context(ring, ctx); | |
1140 | if (ret) | |
1141 | goto error; | |
1142 | ||
1143 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
1144 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1145 | switch (instp_mode) { | |
1146 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1147 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1148 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1149 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
1150 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
1151 | ret = -EINVAL; | |
1152 | goto error; | |
1153 | } | |
1154 | ||
1155 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1156 | if (INTEL_INFO(dev)->gen < 4) { | |
1157 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
1158 | ret = -EINVAL; | |
1159 | goto error; | |
1160 | } | |
1161 | ||
1162 | if (INTEL_INFO(dev)->gen > 5 && | |
1163 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1164 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
1165 | ret = -EINVAL; | |
1166 | goto error; | |
1167 | } | |
1168 | ||
1169 | /* The HW changed the meaning on this bit on gen6 */ | |
1170 | if (INTEL_INFO(dev)->gen >= 6) | |
1171 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1172 | } | |
1173 | break; | |
1174 | default: | |
1175 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
1176 | ret = -EINVAL; | |
1177 | goto error; | |
1178 | } | |
1179 | ||
1180 | if (ring == &dev_priv->ring[RCS] && | |
1181 | instp_mode != dev_priv->relative_constants_mode) { | |
1182 | ret = intel_ring_begin(ring, 4); | |
1183 | if (ret) | |
1184 | goto error; | |
1185 | ||
1186 | intel_ring_emit(ring, MI_NOOP); | |
1187 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1188 | intel_ring_emit(ring, INSTPM); | |
1189 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1190 | intel_ring_advance(ring); | |
1191 | ||
1192 | dev_priv->relative_constants_mode = instp_mode; | |
1193 | } | |
1194 | ||
1195 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
1196 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1197 | if (ret) | |
1198 | goto error; | |
1199 | } | |
1200 | ||
1201 | exec_len = args->batch_len; | |
1202 | if (cliprects) { | |
1203 | for (i = 0; i < args->num_cliprects; i++) { | |
5c6c6003 | 1204 | ret = i915_emit_box(ring, &cliprects[i], |
78382593 OM |
1205 | args->DR1, args->DR4); |
1206 | if (ret) | |
1207 | goto error; | |
1208 | ||
1209 | ret = ring->dispatch_execbuffer(ring, | |
1210 | exec_start, exec_len, | |
1211 | flags); | |
1212 | if (ret) | |
1213 | goto error; | |
1214 | } | |
1215 | } else { | |
1216 | ret = ring->dispatch_execbuffer(ring, | |
1217 | exec_start, exec_len, | |
1218 | flags); | |
1219 | if (ret) | |
1220 | return ret; | |
1221 | } | |
1222 | ||
74328ee5 | 1223 | trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), flags); |
78382593 OM |
1224 | |
1225 | i915_gem_execbuffer_move_to_active(vmas, ring); | |
1226 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); | |
1227 | ||
1228 | error: | |
1229 | kfree(cliprects); | |
1230 | return ret; | |
1231 | } | |
1232 | ||
a8ebba75 ZY |
1233 | /** |
1234 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1235 | * The Ring ID is returned. | |
1236 | */ | |
1237 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1238 | struct drm_file *file) | |
1239 | { | |
1240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1241 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1242 | ||
1243 | /* Check whether the file_priv is using one ring */ | |
1244 | if (file_priv->bsd_ring) | |
1245 | return file_priv->bsd_ring->id; | |
1246 | else { | |
1247 | /* If no, use the ping-pong mechanism to select one ring */ | |
1248 | int ring_id; | |
1249 | ||
1250 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1251 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1252 | ring_id = VCS; |
bdf1e7e3 | 1253 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1254 | } else { |
1255 | ring_id = VCS2; | |
bdf1e7e3 | 1256 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1257 | } |
1258 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1259 | mutex_unlock(&dev->struct_mutex); | |
1260 | return ring_id; | |
1261 | } | |
1262 | } | |
1263 | ||
d23db88c CW |
1264 | static struct drm_i915_gem_object * |
1265 | eb_get_batch(struct eb_vmas *eb) | |
1266 | { | |
1267 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1268 | ||
1269 | /* | |
1270 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1271 | * to negative relocation deltas. Usually that works out ok since the | |
1272 | * relocate address is still positive, except when the batch is placed | |
1273 | * very low in the GTT. Ensure this doesn't happen. | |
1274 | * | |
1275 | * Note that actual hangs have only been observed on gen7, but for | |
1276 | * paranoia do it everywhere. | |
1277 | */ | |
1278 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
1279 | ||
1280 | return vma->obj; | |
1281 | } | |
1282 | ||
54cf91dc CW |
1283 | static int |
1284 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1285 | struct drm_file *file, | |
1286 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1287 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1288 | { |
50227e1c | 1289 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1290 | struct eb_vmas *eb; |
54cf91dc | 1291 | struct drm_i915_gem_object *batch_obj; |
78a42377 BV |
1292 | struct drm_i915_gem_object *shadow_batch_obj = NULL; |
1293 | struct drm_i915_gem_exec_object2 shadow_exec_entry; | |
a4872ba6 | 1294 | struct intel_engine_cs *ring; |
273497e5 | 1295 | struct intel_context *ctx; |
41bde553 | 1296 | struct i915_address_space *vm; |
d299cce7 | 1297 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
78382593 OM |
1298 | u64 exec_start = args->batch_start_offset; |
1299 | u32 flags; | |
1300 | int ret; | |
ed5982e6 | 1301 | bool need_relocs; |
54cf91dc | 1302 | |
ed5982e6 | 1303 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1304 | return -EINVAL; |
432e58ed | 1305 | |
ad19f10b | 1306 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1307 | if (ret) |
1308 | return ret; | |
1309 | ||
d7d4eedd CW |
1310 | flags = 0; |
1311 | if (args->flags & I915_EXEC_SECURE) { | |
1312 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1313 | return -EPERM; | |
1314 | ||
1315 | flags |= I915_DISPATCH_SECURE; | |
1316 | } | |
b45305fc DV |
1317 | if (args->flags & I915_EXEC_IS_PINNED) |
1318 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 1319 | |
b1a93306 | 1320 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1321 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1322 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1323 | return -EINVAL; | |
1324 | } | |
ca01b12b BW |
1325 | |
1326 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) | |
1327 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1328 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1329 | if (HAS_BSD2(dev)) { | |
1330 | int ring_id; | |
1331 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1332 | ring = &dev_priv->ring[ring_id]; | |
1333 | } else | |
1334 | ring = &dev_priv->ring[VCS]; | |
1335 | } else | |
ca01b12b BW |
1336 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1337 | ||
a15817cf CW |
1338 | if (!intel_ring_initialized(ring)) { |
1339 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1340 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1341 | return -EINVAL; | |
1342 | } | |
54cf91dc CW |
1343 | |
1344 | if (args->buffer_count < 1) { | |
ff240199 | 1345 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1346 | return -EINVAL; |
1347 | } | |
54cf91dc | 1348 | |
f65c9168 PZ |
1349 | intel_runtime_pm_get(dev_priv); |
1350 | ||
54cf91dc CW |
1351 | ret = i915_mutex_lock_interruptible(dev); |
1352 | if (ret) | |
1353 | goto pre_mutex_err; | |
1354 | ||
7c9c4b8f | 1355 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1356 | if (IS_ERR(ctx)) { |
d299cce7 | 1357 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1358 | ret = PTR_ERR(ctx); |
d299cce7 | 1359 | goto pre_mutex_err; |
935f38d6 | 1360 | } |
41bde553 BW |
1361 | |
1362 | i915_gem_context_reference(ctx); | |
1363 | ||
ae6c4806 DV |
1364 | if (ctx->ppgtt) |
1365 | vm = &ctx->ppgtt->base; | |
1366 | else | |
7e0d96bc | 1367 | vm = &dev_priv->gtt.base; |
d299cce7 | 1368 | |
17601cbc | 1369 | eb = eb_create(args); |
67731b87 | 1370 | if (eb == NULL) { |
935f38d6 | 1371 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1372 | mutex_unlock(&dev->struct_mutex); |
1373 | ret = -ENOMEM; | |
1374 | goto pre_mutex_err; | |
1375 | } | |
1376 | ||
54cf91dc | 1377 | /* Look up object handles */ |
27173f1f | 1378 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1379 | if (ret) |
1380 | goto err; | |
54cf91dc | 1381 | |
6fe4f140 | 1382 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1383 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1384 | |
54cf91dc | 1385 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1386 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1387 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1388 | if (ret) |
1389 | goto err; | |
1390 | ||
1391 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1392 | if (need_relocs) |
17601cbc | 1393 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1394 | if (ret) { |
1395 | if (ret == -EFAULT) { | |
ed5982e6 | 1396 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1397 | eb, exec); |
54cf91dc CW |
1398 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1399 | } | |
1400 | if (ret) | |
1401 | goto err; | |
1402 | } | |
1403 | ||
1404 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1405 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1406 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1407 | ret = -EINVAL; |
1408 | goto err; | |
1409 | } | |
54cf91dc | 1410 | |
351e3db2 | 1411 | if (i915_needs_cmd_parser(ring)) { |
78a42377 BV |
1412 | shadow_batch_obj = |
1413 | i915_gem_batch_pool_get(&dev_priv->mm.batch_pool, | |
1414 | batch_obj->base.size); | |
1415 | if (IS_ERR(shadow_batch_obj)) { | |
1416 | ret = PTR_ERR(shadow_batch_obj); | |
1417 | /* Don't try to clean up the obj in the error path */ | |
1418 | shadow_batch_obj = NULL; | |
1419 | goto err; | |
1420 | } | |
1421 | ||
1422 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 4096, 0); | |
1423 | if (ret) | |
1424 | goto err; | |
1425 | ||
351e3db2 BV |
1426 | ret = i915_parse_cmds(ring, |
1427 | batch_obj, | |
78a42377 | 1428 | shadow_batch_obj, |
351e3db2 | 1429 | args->batch_start_offset, |
b9ffd80e | 1430 | args->batch_len, |
351e3db2 | 1431 | file->is_master); |
78a42377 BV |
1432 | i915_gem_object_ggtt_unpin(shadow_batch_obj); |
1433 | ||
42c7156a BV |
1434 | if (ret) { |
1435 | if (ret != -EACCES) | |
1436 | goto err; | |
1437 | } else { | |
78a42377 BV |
1438 | struct i915_vma *vma; |
1439 | ||
1440 | memset(&shadow_exec_entry, 0, | |
1441 | sizeof(shadow_exec_entry)); | |
1442 | ||
1443 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); | |
1444 | vma->exec_entry = &shadow_exec_entry; | |
0079a7df | 1445 | vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE; |
78a42377 BV |
1446 | drm_gem_object_reference(&shadow_batch_obj->base); |
1447 | list_add_tail(&vma->exec_list, &eb->vmas); | |
1448 | ||
1449 | shadow_batch_obj->base.pending_read_domains = | |
1450 | batch_obj->base.pending_read_domains; | |
1451 | ||
1452 | batch_obj = shadow_batch_obj; | |
1453 | ||
42c7156a | 1454 | /* |
78a42377 BV |
1455 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE |
1456 | * bit from MI_BATCH_BUFFER_START commands issued in the | |
1457 | * dispatch_execbuffer implementations. We specifically | |
1458 | * don't want that set when the command parser is | |
1459 | * enabled. | |
42c7156a | 1460 | * |
78a42377 BV |
1461 | * FIXME: with aliasing ppgtt, buffers that should only |
1462 | * be in ggtt still end up in the aliasing ppgtt. remove | |
1463 | * this check when that is fixed. | |
42c7156a | 1464 | */ |
78a42377 BV |
1465 | if (USES_FULL_PPGTT(dev)) |
1466 | flags |= I915_DISPATCH_SECURE; | |
42c7156a | 1467 | } |
351e3db2 BV |
1468 | } |
1469 | ||
78a42377 BV |
1470 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1471 | ||
d7d4eedd CW |
1472 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1473 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1474 | * hsw should have this fixed, but bdw mucks it up again. */ |
da51a1e7 DV |
1475 | if (flags & I915_DISPATCH_SECURE) { |
1476 | /* | |
1477 | * So on first glance it looks freaky that we pin the batch here | |
1478 | * outside of the reservation loop. But: | |
1479 | * - The batch is already pinned into the relevant ppgtt, so we | |
1480 | * already have the backing storage fully allocated. | |
1481 | * - No other BO uses the global gtt (well contexts, but meh), | |
1482 | * so we don't really have issues with mutliple objects not | |
1483 | * fitting due to fragmentation. | |
1484 | * So this is actually safe. | |
1485 | */ | |
1486 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1487 | if (ret) | |
1488 | goto err; | |
d7d4eedd | 1489 | |
7e0d96bc | 1490 | exec_start += i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1491 | } else |
7e0d96bc | 1492 | exec_start += i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1493 | |
a83014d3 OM |
1494 | ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args, |
1495 | &eb->vmas, batch_obj, exec_start, flags); | |
54cf91dc | 1496 | |
da51a1e7 DV |
1497 | /* |
1498 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1499 | * batch vma for correctness. For less ugly and less fragility this | |
1500 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1501 | * active. | |
1502 | */ | |
1503 | if (flags & I915_DISPATCH_SECURE) | |
1504 | i915_gem_object_ggtt_unpin(batch_obj); | |
54cf91dc | 1505 | err: |
41bde553 BW |
1506 | /* the request owns the ref now */ |
1507 | i915_gem_context_unreference(ctx); | |
67731b87 | 1508 | eb_destroy(eb); |
54cf91dc CW |
1509 | |
1510 | mutex_unlock(&dev->struct_mutex); | |
1511 | ||
1512 | pre_mutex_err: | |
f65c9168 PZ |
1513 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1514 | * is really idle. */ | |
1515 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1516 | return ret; |
1517 | } | |
1518 | ||
1519 | /* | |
1520 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1521 | * list array and passes it to the real function. | |
1522 | */ | |
1523 | int | |
1524 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1525 | struct drm_file *file) | |
1526 | { | |
1527 | struct drm_i915_gem_execbuffer *args = data; | |
1528 | struct drm_i915_gem_execbuffer2 exec2; | |
1529 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1530 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1531 | int ret, i; | |
1532 | ||
54cf91dc | 1533 | if (args->buffer_count < 1) { |
ff240199 | 1534 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1535 | return -EINVAL; |
1536 | } | |
1537 | ||
1538 | /* Copy in the exec list from userland */ | |
1539 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1540 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1541 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1542 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1543 | args->buffer_count); |
1544 | drm_free_large(exec_list); | |
1545 | drm_free_large(exec2_list); | |
1546 | return -ENOMEM; | |
1547 | } | |
1548 | ret = copy_from_user(exec_list, | |
2bb4629a | 1549 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1550 | sizeof(*exec_list) * args->buffer_count); |
1551 | if (ret != 0) { | |
ff240199 | 1552 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1553 | args->buffer_count, ret); |
1554 | drm_free_large(exec_list); | |
1555 | drm_free_large(exec2_list); | |
1556 | return -EFAULT; | |
1557 | } | |
1558 | ||
1559 | for (i = 0; i < args->buffer_count; i++) { | |
1560 | exec2_list[i].handle = exec_list[i].handle; | |
1561 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1562 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1563 | exec2_list[i].alignment = exec_list[i].alignment; | |
1564 | exec2_list[i].offset = exec_list[i].offset; | |
1565 | if (INTEL_INFO(dev)->gen < 4) | |
1566 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1567 | else | |
1568 | exec2_list[i].flags = 0; | |
1569 | } | |
1570 | ||
1571 | exec2.buffers_ptr = args->buffers_ptr; | |
1572 | exec2.buffer_count = args->buffer_count; | |
1573 | exec2.batch_start_offset = args->batch_start_offset; | |
1574 | exec2.batch_len = args->batch_len; | |
1575 | exec2.DR1 = args->DR1; | |
1576 | exec2.DR4 = args->DR4; | |
1577 | exec2.num_cliprects = args->num_cliprects; | |
1578 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1579 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1580 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1581 | |
41bde553 | 1582 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1583 | if (!ret) { |
9aab8bff CW |
1584 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1585 | to_user_ptr(args->buffers_ptr); | |
1586 | ||
54cf91dc | 1587 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff CW |
1588 | for (i = 0; i < args->buffer_count; i++) { |
1589 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1590 | &exec2_list[i].offset, | |
1591 | sizeof(user_exec_list[i].offset)); | |
1592 | if (ret) { | |
1593 | ret = -EFAULT; | |
1594 | DRM_DEBUG("failed to copy %d exec entries " | |
1595 | "back to user (%d)\n", | |
1596 | args->buffer_count, ret); | |
1597 | break; | |
1598 | } | |
54cf91dc CW |
1599 | } |
1600 | } | |
1601 | ||
1602 | drm_free_large(exec_list); | |
1603 | drm_free_large(exec2_list); | |
1604 | return ret; | |
1605 | } | |
1606 | ||
1607 | int | |
1608 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1609 | struct drm_file *file) | |
1610 | { | |
1611 | struct drm_i915_gem_execbuffer2 *args = data; | |
1612 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1613 | int ret; | |
1614 | ||
ed8cd3b2 XW |
1615 | if (args->buffer_count < 1 || |
1616 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1617 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1618 | return -EINVAL; |
1619 | } | |
1620 | ||
9cb34664 DV |
1621 | if (args->rsvd2 != 0) { |
1622 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1623 | return -EINVAL; | |
1624 | } | |
1625 | ||
8408c282 | 1626 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1627 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1628 | if (exec2_list == NULL) |
1629 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1630 | args->buffer_count); | |
54cf91dc | 1631 | if (exec2_list == NULL) { |
ff240199 | 1632 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1633 | args->buffer_count); |
1634 | return -ENOMEM; | |
1635 | } | |
1636 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1637 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1638 | sizeof(*exec2_list) * args->buffer_count); |
1639 | if (ret != 0) { | |
ff240199 | 1640 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1641 | args->buffer_count, ret); |
1642 | drm_free_large(exec2_list); | |
1643 | return -EFAULT; | |
1644 | } | |
1645 | ||
41bde553 | 1646 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1647 | if (!ret) { |
1648 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1649 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1650 | to_user_ptr(args->buffers_ptr); |
1651 | int i; | |
1652 | ||
1653 | for (i = 0; i < args->buffer_count; i++) { | |
1654 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1655 | &exec2_list[i].offset, | |
1656 | sizeof(user_exec_list[i].offset)); | |
1657 | if (ret) { | |
1658 | ret = -EFAULT; | |
1659 | DRM_DEBUG("failed to copy %d exec entries " | |
1660 | "back to user\n", | |
1661 | args->buffer_count); | |
1662 | break; | |
1663 | } | |
54cf91dc CW |
1664 | } |
1665 | } | |
1666 | ||
1667 | drm_free_large(exec2_list); | |
1668 | return ret; | |
1669 | } |