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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | #include "i915_trace.h" | |
34 | #include "intel_drv.h" | |
f45b5557 | 35 | #include <linux/dma_remapping.h> |
54cf91dc | 36 | |
67731b87 CW |
37 | struct eb_objects { |
38 | int and; | |
39 | struct hlist_head buckets[0]; | |
40 | }; | |
41 | ||
42 | static struct eb_objects * | |
43 | eb_create(int size) | |
44 | { | |
45 | struct eb_objects *eb; | |
46 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
47 | while (count > size) | |
48 | count >>= 1; | |
49 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
50 | sizeof(struct eb_objects), | |
51 | GFP_KERNEL); | |
52 | if (eb == NULL) | |
53 | return eb; | |
54 | ||
55 | eb->and = count - 1; | |
56 | return eb; | |
57 | } | |
58 | ||
59 | static void | |
60 | eb_reset(struct eb_objects *eb) | |
61 | { | |
62 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
63 | } | |
64 | ||
65 | static void | |
66 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
67 | { | |
68 | hlist_add_head(&obj->exec_node, | |
69 | &eb->buckets[obj->exec_handle & eb->and]); | |
70 | } | |
71 | ||
72 | static struct drm_i915_gem_object * | |
73 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
74 | { | |
75 | struct hlist_head *head; | |
76 | struct hlist_node *node; | |
77 | struct drm_i915_gem_object *obj; | |
78 | ||
79 | head = &eb->buckets[handle & eb->and]; | |
80 | hlist_for_each(node, head) { | |
81 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
82 | if (obj->exec_handle == handle) | |
83 | return obj; | |
84 | } | |
85 | ||
86 | return NULL; | |
87 | } | |
88 | ||
89 | static void | |
90 | eb_destroy(struct eb_objects *eb) | |
91 | { | |
92 | kfree(eb); | |
93 | } | |
94 | ||
dabdfe02 CW |
95 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
96 | { | |
97 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 98 | !obj->map_and_fenceable || |
dabdfe02 CW |
99 | obj->cache_level != I915_CACHE_NONE); |
100 | } | |
101 | ||
54cf91dc CW |
102 | static int |
103 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 104 | struct eb_objects *eb, |
54cf91dc CW |
105 | struct drm_i915_gem_relocation_entry *reloc) |
106 | { | |
107 | struct drm_device *dev = obj->base.dev; | |
108 | struct drm_gem_object *target_obj; | |
149c8407 | 109 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
110 | uint32_t target_offset; |
111 | int ret = -EINVAL; | |
112 | ||
67731b87 CW |
113 | /* we've already hold a reference to all valid objects */ |
114 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
115 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
116 | return -ENOENT; |
117 | ||
149c8407 DV |
118 | target_i915_obj = to_intel_bo(target_obj); |
119 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 120 | |
e844b990 EA |
121 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
122 | * pipe_control writes because the gpu doesn't properly redirect them | |
123 | * through the ppgtt for non_secure batchbuffers. */ | |
124 | if (unlikely(IS_GEN6(dev) && | |
125 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
126 | !target_i915_obj->has_global_gtt_mapping)) { | |
127 | i915_gem_gtt_bind_object(target_i915_obj, | |
128 | target_i915_obj->cache_level); | |
129 | } | |
130 | ||
54cf91dc CW |
131 | /* The target buffer should have appeared before us in the |
132 | * exec_object list, so it should have a GTT space bound by now. | |
133 | */ | |
b8f7ab17 | 134 | if (unlikely(target_offset == 0)) { |
ff240199 | 135 | DRM_DEBUG("No GTT space found for object %d\n", |
54cf91dc | 136 | reloc->target_handle); |
67731b87 | 137 | return ret; |
54cf91dc CW |
138 | } |
139 | ||
140 | /* Validate that the target is in a valid r/w GPU domain */ | |
b8f7ab17 | 141 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 142 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
143 | "obj %p target %d offset %d " |
144 | "read %08x write %08x", | |
145 | obj, reloc->target_handle, | |
146 | (int) reloc->offset, | |
147 | reloc->read_domains, | |
148 | reloc->write_domain); | |
67731b87 | 149 | return ret; |
54cf91dc | 150 | } |
4ca4a250 DV |
151 | if (unlikely((reloc->write_domain | reloc->read_domains) |
152 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 153 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
154 | "obj %p target %d offset %d " |
155 | "read %08x write %08x", | |
156 | obj, reloc->target_handle, | |
157 | (int) reloc->offset, | |
158 | reloc->read_domains, | |
159 | reloc->write_domain); | |
67731b87 | 160 | return ret; |
54cf91dc | 161 | } |
b8f7ab17 CW |
162 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
163 | reloc->write_domain != target_obj->pending_write_domain)) { | |
ff240199 | 164 | DRM_DEBUG("Write domain conflict: " |
54cf91dc CW |
165 | "obj %p target %d offset %d " |
166 | "new %08x old %08x\n", | |
167 | obj, reloc->target_handle, | |
168 | (int) reloc->offset, | |
169 | reloc->write_domain, | |
170 | target_obj->pending_write_domain); | |
67731b87 | 171 | return ret; |
54cf91dc CW |
172 | } |
173 | ||
174 | target_obj->pending_read_domains |= reloc->read_domains; | |
175 | target_obj->pending_write_domain |= reloc->write_domain; | |
176 | ||
177 | /* If the relocation already has the right value in it, no | |
178 | * more work needs to be done. | |
179 | */ | |
180 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 181 | return 0; |
54cf91dc CW |
182 | |
183 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 184 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 185 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
186 | "obj %p target %d offset %d size %d.\n", |
187 | obj, reloc->target_handle, | |
188 | (int) reloc->offset, | |
189 | (int) obj->base.size); | |
67731b87 | 190 | return ret; |
54cf91dc | 191 | } |
b8f7ab17 | 192 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 193 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
194 | "obj %p target %d offset %d.\n", |
195 | obj, reloc->target_handle, | |
196 | (int) reloc->offset); | |
67731b87 | 197 | return ret; |
54cf91dc CW |
198 | } |
199 | ||
dabdfe02 CW |
200 | /* We can't wait for rendering with pagefaults disabled */ |
201 | if (obj->active && in_atomic()) | |
202 | return -EFAULT; | |
203 | ||
54cf91dc | 204 | reloc->delta += target_offset; |
dabdfe02 | 205 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
206 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
207 | char *vaddr; | |
208 | ||
dabdfe02 CW |
209 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
210 | if (ret) | |
211 | return ret; | |
212 | ||
54cf91dc CW |
213 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
214 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
215 | kunmap_atomic(vaddr); | |
216 | } else { | |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | uint32_t __iomem *reloc_entry; | |
219 | void __iomem *reloc_page; | |
220 | ||
7b09638f CW |
221 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 226 | if (ret) |
67731b87 | 227 | return ret; |
54cf91dc CW |
228 | |
229 | /* Map the page containing the relocation we're going to perform. */ | |
230 | reloc->offset += obj->gtt_offset; | |
231 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
232 | reloc->offset & PAGE_MASK); | |
233 | reloc_entry = (uint32_t __iomem *) | |
234 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
235 | iowrite32(reloc->delta, reloc_entry); | |
236 | io_mapping_unmap_atomic(reloc_page); | |
237 | } | |
238 | ||
239 | /* and update the user's relocation entry */ | |
240 | reloc->presumed_offset = target_offset; | |
241 | ||
67731b87 | 242 | return 0; |
54cf91dc CW |
243 | } |
244 | ||
245 | static int | |
246 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 247 | struct eb_objects *eb) |
54cf91dc | 248 | { |
1d83f442 CW |
249 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
250 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 251 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 252 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 253 | int remain, ret; |
54cf91dc CW |
254 | |
255 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 256 | |
1d83f442 CW |
257 | remain = entry->relocation_count; |
258 | while (remain) { | |
259 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
260 | int count = remain; | |
261 | if (count > ARRAY_SIZE(stack_reloc)) | |
262 | count = ARRAY_SIZE(stack_reloc); | |
263 | remain -= count; | |
264 | ||
265 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
266 | return -EFAULT; |
267 | ||
1d83f442 CW |
268 | do { |
269 | u64 offset = r->presumed_offset; | |
54cf91dc | 270 | |
1d83f442 CW |
271 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
272 | if (ret) | |
273 | return ret; | |
274 | ||
275 | if (r->presumed_offset != offset && | |
276 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
277 | &r->presumed_offset, | |
278 | sizeof(r->presumed_offset))) { | |
279 | return -EFAULT; | |
280 | } | |
281 | ||
282 | user_relocs++; | |
283 | r++; | |
284 | } while (--count); | |
54cf91dc CW |
285 | } |
286 | ||
287 | return 0; | |
1d83f442 | 288 | #undef N_RELOC |
54cf91dc CW |
289 | } |
290 | ||
291 | static int | |
292 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 293 | struct eb_objects *eb, |
54cf91dc CW |
294 | struct drm_i915_gem_relocation_entry *relocs) |
295 | { | |
6fe4f140 | 296 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
297 | int i, ret; |
298 | ||
299 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 300 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
301 | if (ret) |
302 | return ret; | |
303 | } | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | static int | |
309 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 310 | struct eb_objects *eb, |
6fe4f140 | 311 | struct list_head *objects) |
54cf91dc | 312 | { |
432e58ed | 313 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
314 | int ret = 0; |
315 | ||
316 | /* This is the fast path and we cannot handle a pagefault whilst | |
317 | * holding the struct mutex lest the user pass in the relocations | |
318 | * contained within a mmaped bo. For in such a case we, the page | |
319 | * fault handler would call i915_gem_fault() and we would try to | |
320 | * acquire the struct mutex again. Obviously this is bad and so | |
321 | * lockdep complains vehemently. | |
322 | */ | |
323 | pagefault_disable(); | |
432e58ed | 324 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 325 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 326 | if (ret) |
d4aeee77 | 327 | break; |
54cf91dc | 328 | } |
d4aeee77 | 329 | pagefault_enable(); |
54cf91dc | 330 | |
d4aeee77 | 331 | return ret; |
54cf91dc CW |
332 | } |
333 | ||
1690e1eb CW |
334 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
335 | ||
dabdfe02 CW |
336 | static int |
337 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
338 | { | |
339 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
340 | return entry->relocation_count && !use_cpu_reloc(obj); | |
341 | } | |
342 | ||
1690e1eb CW |
343 | static int |
344 | pin_and_fence_object(struct drm_i915_gem_object *obj, | |
345 | struct intel_ring_buffer *ring) | |
346 | { | |
347 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
348 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
349 | bool need_fence, need_mappable; | |
350 | int ret; | |
351 | ||
352 | need_fence = | |
353 | has_fenced_gpu_access && | |
354 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
355 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 356 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb | 357 | |
86a1ee26 | 358 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); |
1690e1eb CW |
359 | if (ret) |
360 | return ret; | |
361 | ||
362 | if (has_fenced_gpu_access) { | |
363 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 364 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
365 | if (ret) |
366 | goto err_unpin; | |
1690e1eb | 367 | |
9a5a53b3 | 368 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 369 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 370 | |
7dd49065 | 371 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 372 | } |
1690e1eb CW |
373 | } |
374 | ||
375 | entry->offset = obj->gtt_offset; | |
376 | return 0; | |
377 | ||
378 | err_unpin: | |
379 | i915_gem_object_unpin(obj); | |
380 | return ret; | |
381 | } | |
382 | ||
54cf91dc | 383 | static int |
d9e86c0e | 384 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 385 | struct drm_file *file, |
6fe4f140 | 386 | struct list_head *objects) |
54cf91dc | 387 | { |
7bddb01f | 388 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
432e58ed | 389 | struct drm_i915_gem_object *obj; |
432e58ed | 390 | int ret, retry; |
9b3826bf | 391 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
6fe4f140 CW |
392 | struct list_head ordered_objects; |
393 | ||
394 | INIT_LIST_HEAD(&ordered_objects); | |
395 | while (!list_empty(objects)) { | |
396 | struct drm_i915_gem_exec_object2 *entry; | |
397 | bool need_fence, need_mappable; | |
398 | ||
399 | obj = list_first_entry(objects, | |
400 | struct drm_i915_gem_object, | |
401 | exec_list); | |
402 | entry = obj->exec_entry; | |
403 | ||
404 | need_fence = | |
405 | has_fenced_gpu_access && | |
406 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
407 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 408 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
409 | |
410 | if (need_mappable) | |
411 | list_move(&obj->exec_list, &ordered_objects); | |
412 | else | |
413 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
414 | |
415 | obj->base.pending_read_domains = 0; | |
416 | obj->base.pending_write_domain = 0; | |
016fd0c1 | 417 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
418 | } |
419 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
420 | |
421 | /* Attempt to pin all of the buffers into the GTT. | |
422 | * This is done in 3 phases: | |
423 | * | |
424 | * 1a. Unbind all objects that do not match the GTT constraints for | |
425 | * the execbuffer (fenceable, mappable, alignment etc). | |
426 | * 1b. Increment pin count for already bound objects. | |
427 | * 2. Bind new objects. | |
428 | * 3. Decrement pin count. | |
429 | * | |
430 | * This avoid unnecessary unbinding of later objects in order to makr | |
431 | * room for the earlier objects *unless* we need to defragment. | |
432 | */ | |
433 | retry = 0; | |
434 | do { | |
435 | ret = 0; | |
436 | ||
437 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 438 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 439 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 440 | bool need_fence, need_mappable; |
1690e1eb | 441 | |
6fe4f140 | 442 | if (!obj->gtt_space) |
54cf91dc CW |
443 | continue; |
444 | ||
445 | need_fence = | |
9b3826bf | 446 | has_fenced_gpu_access && |
54cf91dc CW |
447 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
448 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 449 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
450 | |
451 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
452 | (need_mappable && !obj->map_and_fenceable)) | |
453 | ret = i915_gem_object_unbind(obj); | |
454 | else | |
1690e1eb | 455 | ret = pin_and_fence_object(obj, ring); |
432e58ed | 456 | if (ret) |
54cf91dc | 457 | goto err; |
54cf91dc CW |
458 | } |
459 | ||
460 | /* Bind fresh objects */ | |
432e58ed | 461 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
462 | if (obj->gtt_space) |
463 | continue; | |
54cf91dc | 464 | |
1690e1eb CW |
465 | ret = pin_and_fence_object(obj, ring); |
466 | if (ret) { | |
467 | int ret_ignore; | |
468 | ||
469 | /* This can potentially raise a harmless | |
470 | * -EINVAL if we failed to bind in the above | |
471 | * call. It cannot raise -EINTR since we know | |
472 | * that the bo is freshly bound and so will | |
473 | * not need to be flushed or waited upon. | |
474 | */ | |
475 | ret_ignore = i915_gem_object_unbind(obj); | |
476 | (void)ret_ignore; | |
477 | WARN_ON(obj->gtt_space); | |
478 | break; | |
54cf91dc | 479 | } |
54cf91dc CW |
480 | } |
481 | ||
432e58ed CW |
482 | /* Decrement pin count for bound objects */ |
483 | list_for_each_entry(obj, objects, exec_list) { | |
1690e1eb CW |
484 | struct drm_i915_gem_exec_object2 *entry; |
485 | ||
486 | if (!obj->gtt_space) | |
487 | continue; | |
488 | ||
489 | entry = obj->exec_entry; | |
490 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
491 | i915_gem_object_unpin_fence(obj); | |
492 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
493 | } | |
494 | ||
495 | i915_gem_object_unpin(obj); | |
7bddb01f DV |
496 | |
497 | /* ... and ensure ppgtt mapping exist if needed. */ | |
498 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
499 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
500 | obj, obj->cache_level); | |
501 | ||
502 | obj->has_aliasing_ppgtt_mapping = 1; | |
503 | } | |
54cf91dc CW |
504 | } |
505 | ||
6c085a72 | 506 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
507 | return ret; |
508 | ||
6c085a72 | 509 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
510 | if (ret) |
511 | return ret; | |
54cf91dc | 512 | } while (1); |
432e58ed CW |
513 | |
514 | err: | |
1690e1eb CW |
515 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
516 | struct drm_i915_gem_exec_object2 *entry; | |
517 | ||
518 | if (!obj->gtt_space) | |
519 | continue; | |
520 | ||
521 | entry = obj->exec_entry; | |
522 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
523 | i915_gem_object_unpin_fence(obj); | |
524 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
525 | } | |
432e58ed | 526 | |
1690e1eb | 527 | i915_gem_object_unpin(obj); |
432e58ed CW |
528 | } |
529 | ||
530 | return ret; | |
54cf91dc CW |
531 | } |
532 | ||
533 | static int | |
534 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
535 | struct drm_file *file, | |
d9e86c0e | 536 | struct intel_ring_buffer *ring, |
432e58ed | 537 | struct list_head *objects, |
67731b87 | 538 | struct eb_objects *eb, |
432e58ed | 539 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
540 | int count) |
541 | { | |
542 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 543 | struct drm_i915_gem_object *obj; |
dd6864a4 | 544 | int *reloc_offset; |
54cf91dc CW |
545 | int i, total, ret; |
546 | ||
67731b87 | 547 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 548 | while (!list_empty(objects)) { |
67731b87 CW |
549 | obj = list_first_entry(objects, |
550 | struct drm_i915_gem_object, | |
551 | exec_list); | |
552 | list_del_init(&obj->exec_list); | |
553 | drm_gem_object_unreference(&obj->base); | |
554 | } | |
555 | ||
54cf91dc CW |
556 | mutex_unlock(&dev->struct_mutex); |
557 | ||
558 | total = 0; | |
559 | for (i = 0; i < count; i++) | |
432e58ed | 560 | total += exec[i].relocation_count; |
54cf91dc | 561 | |
dd6864a4 | 562 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 563 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
564 | if (reloc == NULL || reloc_offset == NULL) { |
565 | drm_free_large(reloc); | |
566 | drm_free_large(reloc_offset); | |
54cf91dc CW |
567 | mutex_lock(&dev->struct_mutex); |
568 | return -ENOMEM; | |
569 | } | |
570 | ||
571 | total = 0; | |
572 | for (i = 0; i < count; i++) { | |
573 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
574 | ||
432e58ed | 575 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
576 | |
577 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 578 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
579 | ret = -EFAULT; |
580 | mutex_lock(&dev->struct_mutex); | |
581 | goto err; | |
582 | } | |
583 | ||
dd6864a4 | 584 | reloc_offset[i] = total; |
432e58ed | 585 | total += exec[i].relocation_count; |
54cf91dc CW |
586 | } |
587 | ||
588 | ret = i915_mutex_lock_interruptible(dev); | |
589 | if (ret) { | |
590 | mutex_lock(&dev->struct_mutex); | |
591 | goto err; | |
592 | } | |
593 | ||
67731b87 | 594 | /* reacquire the objects */ |
67731b87 CW |
595 | eb_reset(eb); |
596 | for (i = 0; i < count; i++) { | |
67731b87 CW |
597 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
598 | exec[i].handle)); | |
c8725226 | 599 | if (&obj->base == NULL) { |
ff240199 | 600 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
67731b87 CW |
601 | exec[i].handle, i); |
602 | ret = -ENOENT; | |
603 | goto err; | |
604 | } | |
605 | ||
606 | list_add_tail(&obj->exec_list, objects); | |
607 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 608 | obj->exec_entry = &exec[i]; |
67731b87 CW |
609 | eb_add_object(eb, obj); |
610 | } | |
611 | ||
6fe4f140 | 612 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
613 | if (ret) |
614 | goto err; | |
615 | ||
432e58ed | 616 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 617 | int offset = obj->exec_entry - exec; |
67731b87 | 618 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 619 | reloc + reloc_offset[offset]); |
54cf91dc CW |
620 | if (ret) |
621 | goto err; | |
54cf91dc CW |
622 | } |
623 | ||
624 | /* Leave the user relocations as are, this is the painfully slow path, | |
625 | * and we want to avoid the complication of dropping the lock whilst | |
626 | * having buffers reserved in the aperture and so causing spurious | |
627 | * ENOSPC for random operations. | |
628 | */ | |
629 | ||
630 | err: | |
631 | drm_free_large(reloc); | |
dd6864a4 | 632 | drm_free_large(reloc_offset); |
54cf91dc CW |
633 | return ret; |
634 | } | |
635 | ||
c59a333f CW |
636 | static int |
637 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
638 | { | |
639 | u32 plane, flip_mask; | |
640 | int ret; | |
641 | ||
642 | /* Check for any pending flips. As we only maintain a flip queue depth | |
643 | * of 1, we can simply insert a WAIT for the next display flip prior | |
644 | * to executing the batch and avoid stalling the CPU. | |
645 | */ | |
646 | ||
647 | for (plane = 0; flips >> plane; plane++) { | |
648 | if (((flips >> plane) & 1) == 0) | |
649 | continue; | |
650 | ||
651 | if (plane) | |
652 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
653 | else | |
654 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
655 | ||
656 | ret = intel_ring_begin(ring, 2); | |
657 | if (ret) | |
658 | return ret; | |
659 | ||
660 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
661 | intel_ring_emit(ring, MI_NOOP); | |
662 | intel_ring_advance(ring); | |
663 | } | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
54cf91dc | 668 | static int |
432e58ed CW |
669 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
670 | struct list_head *objects) | |
54cf91dc | 671 | { |
432e58ed | 672 | struct drm_i915_gem_object *obj; |
6ac42f41 DV |
673 | uint32_t flush_domains = 0; |
674 | uint32_t flips = 0; | |
432e58ed | 675 | int ret; |
54cf91dc | 676 | |
6ac42f41 DV |
677 | list_for_each_entry(obj, objects, exec_list) { |
678 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
679 | if (ret) |
680 | return ret; | |
6ac42f41 DV |
681 | |
682 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
683 | i915_gem_clflush_object(obj); | |
684 | ||
685 | if (obj->base.pending_write_domain) | |
686 | flips |= atomic_read(&obj->pending_flip); | |
687 | ||
688 | flush_domains |= obj->base.write_domain; | |
c59a333f CW |
689 | } |
690 | ||
6ac42f41 DV |
691 | if (flips) { |
692 | ret = i915_gem_execbuffer_wait_for_flips(ring, flips); | |
1ec14ad3 CW |
693 | if (ret) |
694 | return ret; | |
54cf91dc CW |
695 | } |
696 | ||
6ac42f41 DV |
697 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
698 | intel_gtt_chipset_flush(); | |
699 | ||
700 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
701 | wmb(); | |
702 | ||
09cf7c9a CW |
703 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
704 | * any residual writes from the previous batch. | |
705 | */ | |
a7b9761d | 706 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
707 | } |
708 | ||
432e58ed CW |
709 | static bool |
710 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 711 | { |
432e58ed | 712 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
713 | } |
714 | ||
715 | static int | |
716 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
717 | int count) | |
718 | { | |
719 | int i; | |
720 | ||
721 | for (i = 0; i < count; i++) { | |
722 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
723 | int length; /* limited by fault_in_pages_readable() */ | |
724 | ||
725 | /* First check for malicious input causing overflow */ | |
726 | if (exec[i].relocation_count > | |
727 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
728 | return -EINVAL; | |
729 | ||
730 | length = exec[i].relocation_count * | |
731 | sizeof(struct drm_i915_gem_relocation_entry); | |
732 | if (!access_ok(VERIFY_READ, ptr, length)) | |
733 | return -EFAULT; | |
734 | ||
735 | /* we may also need to update the presumed offsets */ | |
736 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
737 | return -EFAULT; | |
738 | ||
f56f821f | 739 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
740 | return -EFAULT; |
741 | } | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
432e58ed CW |
746 | static void |
747 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
748 | struct intel_ring_buffer *ring, |
749 | u32 seqno) | |
432e58ed CW |
750 | { |
751 | struct drm_i915_gem_object *obj; | |
752 | ||
753 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
754 | u32 old_read = obj->base.read_domains; |
755 | u32 old_write = obj->base.write_domain; | |
db53a302 | 756 | |
432e58ed CW |
757 | obj->base.read_domains = obj->base.pending_read_domains; |
758 | obj->base.write_domain = obj->base.pending_write_domain; | |
759 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
760 | ||
1ec14ad3 | 761 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
762 | if (obj->base.write_domain) { |
763 | obj->dirty = 1; | |
0201f1ec | 764 | obj->last_write_seqno = seqno; |
acb87dfb | 765 | if (obj->pin_count) /* check for potential scanout */ |
f047e395 | 766 | intel_mark_fb_busy(obj); |
432e58ed CW |
767 | } |
768 | ||
db53a302 | 769 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
770 | } |
771 | } | |
772 | ||
54cf91dc CW |
773 | static void |
774 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 775 | struct drm_file *file, |
54cf91dc CW |
776 | struct intel_ring_buffer *ring) |
777 | { | |
cc889e0f DV |
778 | /* Unconditionally force add_request to emit a full flush. */ |
779 | ring->gpu_caches_dirty = true; | |
54cf91dc | 780 | |
432e58ed | 781 | /* Add a breadcrumb for the completion of the batch buffer */ |
3bb73aba | 782 | (void)i915_add_request(ring, file, NULL); |
432e58ed | 783 | } |
54cf91dc | 784 | |
ae662d31 EA |
785 | static int |
786 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
787 | struct intel_ring_buffer *ring) | |
788 | { | |
789 | drm_i915_private_t *dev_priv = dev->dev_private; | |
790 | int ret, i; | |
791 | ||
792 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
793 | return 0; | |
794 | ||
795 | ret = intel_ring_begin(ring, 4 * 3); | |
796 | if (ret) | |
797 | return ret; | |
798 | ||
799 | for (i = 0; i < 4; i++) { | |
800 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
801 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
802 | intel_ring_emit(ring, 0); | |
803 | } | |
804 | ||
805 | intel_ring_advance(ring); | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
54cf91dc CW |
810 | static int |
811 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
812 | struct drm_file *file, | |
813 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 814 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
815 | { |
816 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 817 | struct list_head objects; |
67731b87 | 818 | struct eb_objects *eb; |
54cf91dc CW |
819 | struct drm_i915_gem_object *batch_obj; |
820 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 821 | struct intel_ring_buffer *ring; |
6e0a69db | 822 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 823 | u32 exec_start, exec_len; |
1ec14ad3 | 824 | u32 seqno; |
84f9f938 | 825 | u32 mask; |
72bfa19c | 826 | int ret, mode, i; |
54cf91dc | 827 | |
432e58ed | 828 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 829 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
830 | return -EINVAL; |
831 | } | |
832 | ||
833 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
834 | if (ret) |
835 | return ret; | |
836 | ||
54cf91dc CW |
837 | switch (args->flags & I915_EXEC_RING_MASK) { |
838 | case I915_EXEC_DEFAULT: | |
839 | case I915_EXEC_RENDER: | |
1ec14ad3 | 840 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
841 | break; |
842 | case I915_EXEC_BSD: | |
1ec14ad3 | 843 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
844 | if (ctx_id != 0) { |
845 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
846 | ring->name); | |
847 | return -EPERM; | |
848 | } | |
54cf91dc CW |
849 | break; |
850 | case I915_EXEC_BLT: | |
1ec14ad3 | 851 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
852 | if (ctx_id != 0) { |
853 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
854 | ring->name); | |
855 | return -EPERM; | |
856 | } | |
54cf91dc CW |
857 | break; |
858 | default: | |
ff240199 | 859 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
860 | (int)(args->flags & I915_EXEC_RING_MASK)); |
861 | return -EINVAL; | |
862 | } | |
a15817cf CW |
863 | if (!intel_ring_initialized(ring)) { |
864 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
865 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
866 | return -EINVAL; | |
867 | } | |
54cf91dc | 868 | |
72bfa19c | 869 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 870 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
871 | switch (mode) { |
872 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
873 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
874 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
875 | if (ring == &dev_priv->ring[RCS] && | |
876 | mode != dev_priv->relative_constants_mode) { | |
877 | if (INTEL_INFO(dev)->gen < 4) | |
878 | return -EINVAL; | |
879 | ||
880 | if (INTEL_INFO(dev)->gen > 5 && | |
881 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
882 | return -EINVAL; | |
84f9f938 BW |
883 | |
884 | /* The HW changed the meaning on this bit on gen6 */ | |
885 | if (INTEL_INFO(dev)->gen >= 6) | |
886 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
887 | } |
888 | break; | |
889 | default: | |
ff240199 | 890 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
891 | return -EINVAL; |
892 | } | |
893 | ||
54cf91dc | 894 | if (args->buffer_count < 1) { |
ff240199 | 895 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
896 | return -EINVAL; |
897 | } | |
54cf91dc CW |
898 | |
899 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 900 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 901 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
902 | return -EINVAL; |
903 | } | |
904 | ||
6ebebc92 DV |
905 | if (INTEL_INFO(dev)->gen >= 5) { |
906 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
907 | return -EINVAL; | |
908 | } | |
909 | ||
44afb3a0 XW |
910 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
911 | DRM_DEBUG("execbuf with %u cliprects\n", | |
912 | args->num_cliprects); | |
913 | return -EINVAL; | |
914 | } | |
5e13a0c5 | 915 | |
432e58ed | 916 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
917 | GFP_KERNEL); |
918 | if (cliprects == NULL) { | |
919 | ret = -ENOMEM; | |
920 | goto pre_mutex_err; | |
921 | } | |
922 | ||
432e58ed CW |
923 | if (copy_from_user(cliprects, |
924 | (struct drm_clip_rect __user *)(uintptr_t) | |
925 | args->cliprects_ptr, | |
926 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
927 | ret = -EFAULT; |
928 | goto pre_mutex_err; | |
929 | } | |
930 | } | |
931 | ||
54cf91dc CW |
932 | ret = i915_mutex_lock_interruptible(dev); |
933 | if (ret) | |
934 | goto pre_mutex_err; | |
935 | ||
936 | if (dev_priv->mm.suspended) { | |
937 | mutex_unlock(&dev->struct_mutex); | |
938 | ret = -EBUSY; | |
939 | goto pre_mutex_err; | |
940 | } | |
941 | ||
67731b87 CW |
942 | eb = eb_create(args->buffer_count); |
943 | if (eb == NULL) { | |
944 | mutex_unlock(&dev->struct_mutex); | |
945 | ret = -ENOMEM; | |
946 | goto pre_mutex_err; | |
947 | } | |
948 | ||
54cf91dc | 949 | /* Look up object handles */ |
432e58ed | 950 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
951 | for (i = 0; i < args->buffer_count; i++) { |
952 | struct drm_i915_gem_object *obj; | |
953 | ||
432e58ed CW |
954 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
955 | exec[i].handle)); | |
c8725226 | 956 | if (&obj->base == NULL) { |
ff240199 | 957 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
432e58ed | 958 | exec[i].handle, i); |
54cf91dc | 959 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
960 | ret = -ENOENT; |
961 | goto err; | |
962 | } | |
54cf91dc | 963 | |
432e58ed | 964 | if (!list_empty(&obj->exec_list)) { |
ff240199 | 965 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
432e58ed | 966 | obj, exec[i].handle, i); |
54cf91dc CW |
967 | ret = -EINVAL; |
968 | goto err; | |
969 | } | |
432e58ed CW |
970 | |
971 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 972 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 973 | obj->exec_entry = &exec[i]; |
67731b87 | 974 | eb_add_object(eb, obj); |
54cf91dc CW |
975 | } |
976 | ||
6fe4f140 CW |
977 | /* take note of the batch buffer before we might reorder the lists */ |
978 | batch_obj = list_entry(objects.prev, | |
979 | struct drm_i915_gem_object, | |
980 | exec_list); | |
981 | ||
54cf91dc | 982 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 983 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
984 | if (ret) |
985 | goto err; | |
986 | ||
987 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 988 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
989 | if (ret) { |
990 | if (ret == -EFAULT) { | |
d9e86c0e | 991 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
992 | &objects, eb, |
993 | exec, | |
54cf91dc CW |
994 | args->buffer_count); |
995 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
996 | } | |
997 | if (ret) | |
998 | goto err; | |
999 | } | |
1000 | ||
1001 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1002 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1003 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1004 | ret = -EINVAL; |
1005 | goto err; | |
1006 | } | |
1007 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1008 | ||
432e58ed CW |
1009 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1010 | if (ret) | |
54cf91dc | 1011 | goto err; |
54cf91dc | 1012 | |
db53a302 | 1013 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 1014 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
1015 | if (seqno < ring->sync_seqno[i]) { |
1016 | /* The GPU can not handle its semaphore value wrapping, | |
1017 | * so every billion or so execbuffers, we need to stall | |
1018 | * the GPU in order to reset the counters. | |
1019 | */ | |
b2da9fe5 | 1020 | ret = i915_gpu_idle(dev); |
1ec14ad3 CW |
1021 | if (ret) |
1022 | goto err; | |
b2da9fe5 | 1023 | i915_gem_retire_requests(dev); |
1ec14ad3 CW |
1024 | |
1025 | BUG_ON(ring->sync_seqno[i]); | |
1026 | } | |
1027 | } | |
1028 | ||
0da5cec1 EA |
1029 | ret = i915_switch_context(ring, file, ctx_id); |
1030 | if (ret) | |
1031 | goto err; | |
1032 | ||
e2971bda BW |
1033 | if (ring == &dev_priv->ring[RCS] && |
1034 | mode != dev_priv->relative_constants_mode) { | |
1035 | ret = intel_ring_begin(ring, 4); | |
1036 | if (ret) | |
1037 | goto err; | |
1038 | ||
1039 | intel_ring_emit(ring, MI_NOOP); | |
1040 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1041 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1042 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1043 | intel_ring_advance(ring); |
1044 | ||
1045 | dev_priv->relative_constants_mode = mode; | |
1046 | } | |
1047 | ||
ae662d31 EA |
1048 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1049 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1050 | if (ret) | |
1051 | goto err; | |
1052 | } | |
1053 | ||
db53a302 CW |
1054 | trace_i915_gem_ring_dispatch(ring, seqno); |
1055 | ||
c4e7a414 CW |
1056 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1057 | exec_len = args->batch_len; | |
1058 | if (cliprects) { | |
1059 | for (i = 0; i < args->num_cliprects; i++) { | |
1060 | ret = i915_emit_box(dev, &cliprects[i], | |
1061 | args->DR1, args->DR4); | |
1062 | if (ret) | |
1063 | goto err; | |
1064 | ||
1065 | ret = ring->dispatch_execbuffer(ring, | |
1066 | exec_start, exec_len); | |
1067 | if (ret) | |
1068 | goto err; | |
1069 | } | |
1070 | } else { | |
1071 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); | |
1072 | if (ret) | |
1073 | goto err; | |
1074 | } | |
54cf91dc | 1075 | |
1ec14ad3 | 1076 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1077 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1078 | |
1079 | err: | |
67731b87 | 1080 | eb_destroy(eb); |
432e58ed CW |
1081 | while (!list_empty(&objects)) { |
1082 | struct drm_i915_gem_object *obj; | |
1083 | ||
1084 | obj = list_first_entry(&objects, | |
1085 | struct drm_i915_gem_object, | |
1086 | exec_list); | |
1087 | list_del_init(&obj->exec_list); | |
1088 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1089 | } |
1090 | ||
1091 | mutex_unlock(&dev->struct_mutex); | |
1092 | ||
1093 | pre_mutex_err: | |
54cf91dc | 1094 | kfree(cliprects); |
54cf91dc CW |
1095 | return ret; |
1096 | } | |
1097 | ||
1098 | /* | |
1099 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1100 | * list array and passes it to the real function. | |
1101 | */ | |
1102 | int | |
1103 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1104 | struct drm_file *file) | |
1105 | { | |
1106 | struct drm_i915_gem_execbuffer *args = data; | |
1107 | struct drm_i915_gem_execbuffer2 exec2; | |
1108 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1109 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1110 | int ret, i; | |
1111 | ||
54cf91dc | 1112 | if (args->buffer_count < 1) { |
ff240199 | 1113 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1114 | return -EINVAL; |
1115 | } | |
1116 | ||
1117 | /* Copy in the exec list from userland */ | |
1118 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1119 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1120 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1121 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1122 | args->buffer_count); |
1123 | drm_free_large(exec_list); | |
1124 | drm_free_large(exec2_list); | |
1125 | return -ENOMEM; | |
1126 | } | |
1127 | ret = copy_from_user(exec_list, | |
1128 | (struct drm_i915_relocation_entry __user *) | |
1129 | (uintptr_t) args->buffers_ptr, | |
1130 | sizeof(*exec_list) * args->buffer_count); | |
1131 | if (ret != 0) { | |
ff240199 | 1132 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1133 | args->buffer_count, ret); |
1134 | drm_free_large(exec_list); | |
1135 | drm_free_large(exec2_list); | |
1136 | return -EFAULT; | |
1137 | } | |
1138 | ||
1139 | for (i = 0; i < args->buffer_count; i++) { | |
1140 | exec2_list[i].handle = exec_list[i].handle; | |
1141 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1142 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1143 | exec2_list[i].alignment = exec_list[i].alignment; | |
1144 | exec2_list[i].offset = exec_list[i].offset; | |
1145 | if (INTEL_INFO(dev)->gen < 4) | |
1146 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1147 | else | |
1148 | exec2_list[i].flags = 0; | |
1149 | } | |
1150 | ||
1151 | exec2.buffers_ptr = args->buffers_ptr; | |
1152 | exec2.buffer_count = args->buffer_count; | |
1153 | exec2.batch_start_offset = args->batch_start_offset; | |
1154 | exec2.batch_len = args->batch_len; | |
1155 | exec2.DR1 = args->DR1; | |
1156 | exec2.DR4 = args->DR4; | |
1157 | exec2.num_cliprects = args->num_cliprects; | |
1158 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1159 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1160 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1161 | |
1162 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1163 | if (!ret) { | |
1164 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1165 | for (i = 0; i < args->buffer_count; i++) | |
1166 | exec_list[i].offset = exec2_list[i].offset; | |
1167 | /* ... and back out to userspace */ | |
1168 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1169 | (uintptr_t) args->buffers_ptr, | |
1170 | exec_list, | |
1171 | sizeof(*exec_list) * args->buffer_count); | |
1172 | if (ret) { | |
1173 | ret = -EFAULT; | |
ff240199 | 1174 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1175 | "back to user (%d)\n", |
1176 | args->buffer_count, ret); | |
1177 | } | |
1178 | } | |
1179 | ||
1180 | drm_free_large(exec_list); | |
1181 | drm_free_large(exec2_list); | |
1182 | return ret; | |
1183 | } | |
1184 | ||
1185 | int | |
1186 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1187 | struct drm_file *file) | |
1188 | { | |
1189 | struct drm_i915_gem_execbuffer2 *args = data; | |
1190 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1191 | int ret; | |
1192 | ||
ed8cd3b2 XW |
1193 | if (args->buffer_count < 1 || |
1194 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1195 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1196 | return -EINVAL; |
1197 | } | |
1198 | ||
8408c282 CW |
1199 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1200 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1201 | if (exec2_list == NULL) | |
1202 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1203 | args->buffer_count); | |
54cf91dc | 1204 | if (exec2_list == NULL) { |
ff240199 | 1205 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1206 | args->buffer_count); |
1207 | return -ENOMEM; | |
1208 | } | |
1209 | ret = copy_from_user(exec2_list, | |
1210 | (struct drm_i915_relocation_entry __user *) | |
1211 | (uintptr_t) args->buffers_ptr, | |
1212 | sizeof(*exec2_list) * args->buffer_count); | |
1213 | if (ret != 0) { | |
ff240199 | 1214 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1215 | args->buffer_count, ret); |
1216 | drm_free_large(exec2_list); | |
1217 | return -EFAULT; | |
1218 | } | |
1219 | ||
1220 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1221 | if (!ret) { | |
1222 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1223 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1224 | (uintptr_t) args->buffers_ptr, | |
1225 | exec2_list, | |
1226 | sizeof(*exec2_list) * args->buffer_count); | |
1227 | if (ret) { | |
1228 | ret = -EFAULT; | |
ff240199 | 1229 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1230 | "back to user (%d)\n", |
1231 | args->buffer_count, ret); | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | drm_free_large(exec2_list); | |
1236 | return ret; | |
1237 | } |