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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
67731b87 CW |
36 | struct eb_objects { |
37 | int and; | |
38 | struct hlist_head buckets[0]; | |
39 | }; | |
40 | ||
41 | static struct eb_objects * | |
42 | eb_create(int size) | |
43 | { | |
44 | struct eb_objects *eb; | |
45 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
41783eea | 46 | BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head))); |
67731b87 CW |
47 | while (count > size) |
48 | count >>= 1; | |
49 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
50 | sizeof(struct eb_objects), | |
51 | GFP_KERNEL); | |
52 | if (eb == NULL) | |
53 | return eb; | |
54 | ||
55 | eb->and = count - 1; | |
56 | return eb; | |
57 | } | |
58 | ||
59 | static void | |
60 | eb_reset(struct eb_objects *eb) | |
61 | { | |
62 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
63 | } | |
64 | ||
65 | static void | |
66 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
67 | { | |
68 | hlist_add_head(&obj->exec_node, | |
69 | &eb->buckets[obj->exec_handle & eb->and]); | |
70 | } | |
71 | ||
3b96eff4 CW |
72 | static int |
73 | eb_lookup_objects(struct eb_objects *eb, | |
74 | struct drm_i915_gem_exec_object2 *exec, | |
75 | int count, | |
76 | struct drm_file *file, | |
77 | struct list_head *objects) | |
78 | { | |
79 | int i; | |
80 | ||
81 | spin_lock(&file->table_lock); | |
82 | for (i = 0; i < count; i++) { | |
83 | struct drm_i915_gem_object *obj; | |
84 | ||
85 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); | |
86 | if (obj == NULL) { | |
87 | spin_unlock(&file->table_lock); | |
88 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
89 | exec[i].handle, i); | |
90 | return -ENOENT; | |
91 | } | |
92 | ||
93 | if (!list_empty(&obj->exec_list)) { | |
94 | spin_unlock(&file->table_lock); | |
95 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
96 | obj, exec[i].handle, i); | |
97 | return -EINVAL; | |
98 | } | |
99 | ||
100 | drm_gem_object_reference(&obj->base); | |
101 | list_add_tail(&obj->exec_list, objects); | |
102 | ||
103 | obj->exec_handle = exec[i].handle; | |
104 | obj->exec_entry = &exec[i]; | |
105 | eb_add_object(eb, obj); | |
106 | } | |
107 | spin_unlock(&file->table_lock); | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
67731b87 CW |
112 | static struct drm_i915_gem_object * |
113 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
114 | { | |
115 | struct hlist_head *head; | |
116 | struct hlist_node *node; | |
117 | struct drm_i915_gem_object *obj; | |
118 | ||
119 | head = &eb->buckets[handle & eb->and]; | |
120 | hlist_for_each(node, head) { | |
121 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
122 | if (obj->exec_handle == handle) | |
123 | return obj; | |
124 | } | |
125 | ||
126 | return NULL; | |
127 | } | |
128 | ||
129 | static void | |
130 | eb_destroy(struct eb_objects *eb) | |
131 | { | |
132 | kfree(eb); | |
133 | } | |
134 | ||
dabdfe02 CW |
135 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
136 | { | |
137 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 138 | !obj->map_and_fenceable || |
dabdfe02 CW |
139 | obj->cache_level != I915_CACHE_NONE); |
140 | } | |
141 | ||
54cf91dc CW |
142 | static int |
143 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 144 | struct eb_objects *eb, |
54cf91dc CW |
145 | struct drm_i915_gem_relocation_entry *reloc) |
146 | { | |
147 | struct drm_device *dev = obj->base.dev; | |
148 | struct drm_gem_object *target_obj; | |
149c8407 | 149 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
150 | uint32_t target_offset; |
151 | int ret = -EINVAL; | |
152 | ||
67731b87 CW |
153 | /* we've already hold a reference to all valid objects */ |
154 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
155 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
156 | return -ENOENT; |
157 | ||
149c8407 DV |
158 | target_i915_obj = to_intel_bo(target_obj); |
159 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 160 | |
e844b990 EA |
161 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
162 | * pipe_control writes because the gpu doesn't properly redirect them | |
163 | * through the ppgtt for non_secure batchbuffers. */ | |
164 | if (unlikely(IS_GEN6(dev) && | |
165 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
166 | !target_i915_obj->has_global_gtt_mapping)) { | |
167 | i915_gem_gtt_bind_object(target_i915_obj, | |
168 | target_i915_obj->cache_level); | |
169 | } | |
170 | ||
54cf91dc | 171 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 172 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 173 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
174 | "obj %p target %d offset %d " |
175 | "read %08x write %08x", | |
176 | obj, reloc->target_handle, | |
177 | (int) reloc->offset, | |
178 | reloc->read_domains, | |
179 | reloc->write_domain); | |
67731b87 | 180 | return ret; |
54cf91dc | 181 | } |
4ca4a250 DV |
182 | if (unlikely((reloc->write_domain | reloc->read_domains) |
183 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 184 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
185 | "obj %p target %d offset %d " |
186 | "read %08x write %08x", | |
187 | obj, reloc->target_handle, | |
188 | (int) reloc->offset, | |
189 | reloc->read_domains, | |
190 | reloc->write_domain); | |
67731b87 | 191 | return ret; |
54cf91dc | 192 | } |
54cf91dc CW |
193 | |
194 | target_obj->pending_read_domains |= reloc->read_domains; | |
195 | target_obj->pending_write_domain |= reloc->write_domain; | |
196 | ||
197 | /* If the relocation already has the right value in it, no | |
198 | * more work needs to be done. | |
199 | */ | |
200 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 201 | return 0; |
54cf91dc CW |
202 | |
203 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 204 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 205 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
206 | "obj %p target %d offset %d size %d.\n", |
207 | obj, reloc->target_handle, | |
208 | (int) reloc->offset, | |
209 | (int) obj->base.size); | |
67731b87 | 210 | return ret; |
54cf91dc | 211 | } |
b8f7ab17 | 212 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 213 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
214 | "obj %p target %d offset %d.\n", |
215 | obj, reloc->target_handle, | |
216 | (int) reloc->offset); | |
67731b87 | 217 | return ret; |
54cf91dc CW |
218 | } |
219 | ||
dabdfe02 CW |
220 | /* We can't wait for rendering with pagefaults disabled */ |
221 | if (obj->active && in_atomic()) | |
222 | return -EFAULT; | |
223 | ||
54cf91dc | 224 | reloc->delta += target_offset; |
dabdfe02 | 225 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
226 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
227 | char *vaddr; | |
228 | ||
dabdfe02 CW |
229 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
230 | if (ret) | |
231 | return ret; | |
232 | ||
9da3da66 CW |
233 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, |
234 | reloc->offset >> PAGE_SHIFT)); | |
54cf91dc CW |
235 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
236 | kunmap_atomic(vaddr); | |
237 | } else { | |
238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
239 | uint32_t __iomem *reloc_entry; | |
240 | void __iomem *reloc_page; | |
241 | ||
7b09638f CW |
242 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
243 | if (ret) | |
244 | return ret; | |
245 | ||
246 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 247 | if (ret) |
67731b87 | 248 | return ret; |
54cf91dc CW |
249 | |
250 | /* Map the page containing the relocation we're going to perform. */ | |
251 | reloc->offset += obj->gtt_offset; | |
252 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
253 | reloc->offset & PAGE_MASK); | |
254 | reloc_entry = (uint32_t __iomem *) | |
255 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
256 | iowrite32(reloc->delta, reloc_entry); | |
257 | io_mapping_unmap_atomic(reloc_page); | |
258 | } | |
259 | ||
260 | /* and update the user's relocation entry */ | |
261 | reloc->presumed_offset = target_offset; | |
262 | ||
67731b87 | 263 | return 0; |
54cf91dc CW |
264 | } |
265 | ||
266 | static int | |
267 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 268 | struct eb_objects *eb) |
54cf91dc | 269 | { |
1d83f442 CW |
270 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
271 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 272 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 273 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 274 | int remain, ret; |
54cf91dc CW |
275 | |
276 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 277 | |
1d83f442 CW |
278 | remain = entry->relocation_count; |
279 | while (remain) { | |
280 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
281 | int count = remain; | |
282 | if (count > ARRAY_SIZE(stack_reloc)) | |
283 | count = ARRAY_SIZE(stack_reloc); | |
284 | remain -= count; | |
285 | ||
286 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
287 | return -EFAULT; |
288 | ||
1d83f442 CW |
289 | do { |
290 | u64 offset = r->presumed_offset; | |
54cf91dc | 291 | |
1d83f442 CW |
292 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
293 | if (ret) | |
294 | return ret; | |
295 | ||
296 | if (r->presumed_offset != offset && | |
297 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
298 | &r->presumed_offset, | |
299 | sizeof(r->presumed_offset))) { | |
300 | return -EFAULT; | |
301 | } | |
302 | ||
303 | user_relocs++; | |
304 | r++; | |
305 | } while (--count); | |
54cf91dc CW |
306 | } |
307 | ||
308 | return 0; | |
1d83f442 | 309 | #undef N_RELOC |
54cf91dc CW |
310 | } |
311 | ||
312 | static int | |
313 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 314 | struct eb_objects *eb, |
54cf91dc CW |
315 | struct drm_i915_gem_relocation_entry *relocs) |
316 | { | |
6fe4f140 | 317 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
318 | int i, ret; |
319 | ||
320 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 321 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
322 | if (ret) |
323 | return ret; | |
324 | } | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | static int | |
330 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 331 | struct eb_objects *eb, |
6fe4f140 | 332 | struct list_head *objects) |
54cf91dc | 333 | { |
432e58ed | 334 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
335 | int ret = 0; |
336 | ||
337 | /* This is the fast path and we cannot handle a pagefault whilst | |
338 | * holding the struct mutex lest the user pass in the relocations | |
339 | * contained within a mmaped bo. For in such a case we, the page | |
340 | * fault handler would call i915_gem_fault() and we would try to | |
341 | * acquire the struct mutex again. Obviously this is bad and so | |
342 | * lockdep complains vehemently. | |
343 | */ | |
344 | pagefault_disable(); | |
432e58ed | 345 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 346 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 347 | if (ret) |
d4aeee77 | 348 | break; |
54cf91dc | 349 | } |
d4aeee77 | 350 | pagefault_enable(); |
54cf91dc | 351 | |
d4aeee77 | 352 | return ret; |
54cf91dc CW |
353 | } |
354 | ||
7788a765 CW |
355 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
356 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 357 | |
dabdfe02 CW |
358 | static int |
359 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
360 | { | |
361 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
362 | return entry->relocation_count && !use_cpu_reloc(obj); | |
363 | } | |
364 | ||
1690e1eb | 365 | static int |
7788a765 CW |
366 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
367 | struct intel_ring_buffer *ring) | |
1690e1eb | 368 | { |
7788a765 | 369 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1690e1eb CW |
370 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
371 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
372 | bool need_fence, need_mappable; | |
373 | int ret; | |
374 | ||
375 | need_fence = | |
376 | has_fenced_gpu_access && | |
377 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
378 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 379 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb | 380 | |
86a1ee26 | 381 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); |
1690e1eb CW |
382 | if (ret) |
383 | return ret; | |
384 | ||
7788a765 CW |
385 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
386 | ||
1690e1eb CW |
387 | if (has_fenced_gpu_access) { |
388 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 389 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 390 | if (ret) |
7788a765 | 391 | return ret; |
1690e1eb | 392 | |
9a5a53b3 | 393 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 394 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 395 | |
7dd49065 | 396 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 397 | } |
1690e1eb CW |
398 | } |
399 | ||
7788a765 CW |
400 | /* Ensure ppgtt mapping exists if needed */ |
401 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
402 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
403 | obj, obj->cache_level); | |
404 | ||
405 | obj->has_aliasing_ppgtt_mapping = 1; | |
406 | } | |
407 | ||
1690e1eb CW |
408 | entry->offset = obj->gtt_offset; |
409 | return 0; | |
7788a765 | 410 | } |
1690e1eb | 411 | |
7788a765 CW |
412 | static void |
413 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) | |
414 | { | |
415 | struct drm_i915_gem_exec_object2 *entry; | |
416 | ||
417 | if (!obj->gtt_space) | |
418 | return; | |
419 | ||
420 | entry = obj->exec_entry; | |
421 | ||
422 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
423 | i915_gem_object_unpin_fence(obj); | |
424 | ||
425 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
426 | i915_gem_object_unpin(obj); | |
427 | ||
428 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
429 | } |
430 | ||
54cf91dc | 431 | static int |
d9e86c0e | 432 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 433 | struct drm_file *file, |
6fe4f140 | 434 | struct list_head *objects) |
54cf91dc | 435 | { |
432e58ed | 436 | struct drm_i915_gem_object *obj; |
6fe4f140 | 437 | struct list_head ordered_objects; |
7788a765 CW |
438 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
439 | int retry; | |
6fe4f140 CW |
440 | |
441 | INIT_LIST_HEAD(&ordered_objects); | |
442 | while (!list_empty(objects)) { | |
443 | struct drm_i915_gem_exec_object2 *entry; | |
444 | bool need_fence, need_mappable; | |
445 | ||
446 | obj = list_first_entry(objects, | |
447 | struct drm_i915_gem_object, | |
448 | exec_list); | |
449 | entry = obj->exec_entry; | |
450 | ||
451 | need_fence = | |
452 | has_fenced_gpu_access && | |
453 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
454 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 455 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
456 | |
457 | if (need_mappable) | |
458 | list_move(&obj->exec_list, &ordered_objects); | |
459 | else | |
460 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
461 | |
462 | obj->base.pending_read_domains = 0; | |
463 | obj->base.pending_write_domain = 0; | |
016fd0c1 | 464 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
465 | } |
466 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
467 | |
468 | /* Attempt to pin all of the buffers into the GTT. | |
469 | * This is done in 3 phases: | |
470 | * | |
471 | * 1a. Unbind all objects that do not match the GTT constraints for | |
472 | * the execbuffer (fenceable, mappable, alignment etc). | |
473 | * 1b. Increment pin count for already bound objects. | |
474 | * 2. Bind new objects. | |
475 | * 3. Decrement pin count. | |
476 | * | |
7788a765 | 477 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
478 | * room for the earlier objects *unless* we need to defragment. |
479 | */ | |
480 | retry = 0; | |
481 | do { | |
7788a765 | 482 | int ret = 0; |
54cf91dc CW |
483 | |
484 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 485 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 486 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 487 | bool need_fence, need_mappable; |
1690e1eb | 488 | |
6fe4f140 | 489 | if (!obj->gtt_space) |
54cf91dc CW |
490 | continue; |
491 | ||
492 | need_fence = | |
9b3826bf | 493 | has_fenced_gpu_access && |
54cf91dc CW |
494 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
495 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 496 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
497 | |
498 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
499 | (need_mappable && !obj->map_and_fenceable)) | |
500 | ret = i915_gem_object_unbind(obj); | |
501 | else | |
7788a765 | 502 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
432e58ed | 503 | if (ret) |
54cf91dc | 504 | goto err; |
54cf91dc CW |
505 | } |
506 | ||
507 | /* Bind fresh objects */ | |
432e58ed | 508 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
509 | if (obj->gtt_space) |
510 | continue; | |
54cf91dc | 511 | |
7788a765 CW |
512 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
513 | if (ret) | |
514 | goto err; | |
54cf91dc CW |
515 | } |
516 | ||
7788a765 CW |
517 | err: /* Decrement pin count for bound objects */ |
518 | list_for_each_entry(obj, objects, exec_list) | |
519 | i915_gem_execbuffer_unreserve_object(obj); | |
54cf91dc | 520 | |
6c085a72 | 521 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
522 | return ret; |
523 | ||
6c085a72 | 524 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
525 | if (ret) |
526 | return ret; | |
54cf91dc CW |
527 | } while (1); |
528 | } | |
529 | ||
530 | static int | |
531 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
532 | struct drm_file *file, | |
d9e86c0e | 533 | struct intel_ring_buffer *ring, |
432e58ed | 534 | struct list_head *objects, |
67731b87 | 535 | struct eb_objects *eb, |
432e58ed | 536 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
537 | int count) |
538 | { | |
539 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 540 | struct drm_i915_gem_object *obj; |
dd6864a4 | 541 | int *reloc_offset; |
54cf91dc CW |
542 | int i, total, ret; |
543 | ||
67731b87 | 544 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 545 | while (!list_empty(objects)) { |
67731b87 CW |
546 | obj = list_first_entry(objects, |
547 | struct drm_i915_gem_object, | |
548 | exec_list); | |
549 | list_del_init(&obj->exec_list); | |
550 | drm_gem_object_unreference(&obj->base); | |
551 | } | |
552 | ||
54cf91dc CW |
553 | mutex_unlock(&dev->struct_mutex); |
554 | ||
555 | total = 0; | |
556 | for (i = 0; i < count; i++) | |
432e58ed | 557 | total += exec[i].relocation_count; |
54cf91dc | 558 | |
dd6864a4 | 559 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 560 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
561 | if (reloc == NULL || reloc_offset == NULL) { |
562 | drm_free_large(reloc); | |
563 | drm_free_large(reloc_offset); | |
54cf91dc CW |
564 | mutex_lock(&dev->struct_mutex); |
565 | return -ENOMEM; | |
566 | } | |
567 | ||
568 | total = 0; | |
569 | for (i = 0; i < count; i++) { | |
570 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
571 | ||
432e58ed | 572 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
573 | |
574 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 575 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
576 | ret = -EFAULT; |
577 | mutex_lock(&dev->struct_mutex); | |
578 | goto err; | |
579 | } | |
580 | ||
dd6864a4 | 581 | reloc_offset[i] = total; |
432e58ed | 582 | total += exec[i].relocation_count; |
54cf91dc CW |
583 | } |
584 | ||
585 | ret = i915_mutex_lock_interruptible(dev); | |
586 | if (ret) { | |
587 | mutex_lock(&dev->struct_mutex); | |
588 | goto err; | |
589 | } | |
590 | ||
67731b87 | 591 | /* reacquire the objects */ |
67731b87 | 592 | eb_reset(eb); |
3b96eff4 CW |
593 | ret = eb_lookup_objects(eb, exec, count, file, objects); |
594 | if (ret) | |
595 | goto err; | |
67731b87 | 596 | |
6fe4f140 | 597 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
598 | if (ret) |
599 | goto err; | |
600 | ||
432e58ed | 601 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 602 | int offset = obj->exec_entry - exec; |
67731b87 | 603 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 604 | reloc + reloc_offset[offset]); |
54cf91dc CW |
605 | if (ret) |
606 | goto err; | |
54cf91dc CW |
607 | } |
608 | ||
609 | /* Leave the user relocations as are, this is the painfully slow path, | |
610 | * and we want to avoid the complication of dropping the lock whilst | |
611 | * having buffers reserved in the aperture and so causing spurious | |
612 | * ENOSPC for random operations. | |
613 | */ | |
614 | ||
615 | err: | |
616 | drm_free_large(reloc); | |
dd6864a4 | 617 | drm_free_large(reloc_offset); |
54cf91dc CW |
618 | return ret; |
619 | } | |
620 | ||
54cf91dc | 621 | static int |
432e58ed CW |
622 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
623 | struct list_head *objects) | |
54cf91dc | 624 | { |
432e58ed | 625 | struct drm_i915_gem_object *obj; |
6ac42f41 | 626 | uint32_t flush_domains = 0; |
432e58ed | 627 | int ret; |
54cf91dc | 628 | |
6ac42f41 DV |
629 | list_for_each_entry(obj, objects, exec_list) { |
630 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
631 | if (ret) |
632 | return ret; | |
6ac42f41 DV |
633 | |
634 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
635 | i915_gem_clflush_object(obj); | |
636 | ||
6ac42f41 | 637 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
638 | } |
639 | ||
6ac42f41 | 640 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
e76e9aeb | 641 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
642 | |
643 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
644 | wmb(); | |
645 | ||
09cf7c9a CW |
646 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
647 | * any residual writes from the previous batch. | |
648 | */ | |
a7b9761d | 649 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
650 | } |
651 | ||
432e58ed CW |
652 | static bool |
653 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 654 | { |
432e58ed | 655 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
656 | } |
657 | ||
658 | static int | |
659 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
660 | int count) | |
661 | { | |
662 | int i; | |
663 | ||
664 | for (i = 0; i < count; i++) { | |
665 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
666 | int length; /* limited by fault_in_pages_readable() */ | |
667 | ||
668 | /* First check for malicious input causing overflow */ | |
669 | if (exec[i].relocation_count > | |
670 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
671 | return -EINVAL; | |
672 | ||
673 | length = exec[i].relocation_count * | |
674 | sizeof(struct drm_i915_gem_relocation_entry); | |
675 | if (!access_ok(VERIFY_READ, ptr, length)) | |
676 | return -EFAULT; | |
677 | ||
678 | /* we may also need to update the presumed offsets */ | |
679 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
680 | return -EFAULT; | |
681 | ||
f56f821f | 682 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
683 | return -EFAULT; |
684 | } | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
432e58ed CW |
689 | static void |
690 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
9d773091 | 691 | struct intel_ring_buffer *ring) |
432e58ed CW |
692 | { |
693 | struct drm_i915_gem_object *obj; | |
694 | ||
695 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
696 | u32 old_read = obj->base.read_domains; |
697 | u32 old_write = obj->base.write_domain; | |
db53a302 | 698 | |
432e58ed CW |
699 | obj->base.read_domains = obj->base.pending_read_domains; |
700 | obj->base.write_domain = obj->base.pending_write_domain; | |
701 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
702 | ||
9d773091 | 703 | i915_gem_object_move_to_active(obj, ring); |
432e58ed CW |
704 | if (obj->base.write_domain) { |
705 | obj->dirty = 1; | |
9d773091 | 706 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
acb87dfb | 707 | if (obj->pin_count) /* check for potential scanout */ |
f047e395 | 708 | intel_mark_fb_busy(obj); |
432e58ed CW |
709 | } |
710 | ||
db53a302 | 711 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
712 | } |
713 | } | |
714 | ||
54cf91dc CW |
715 | static void |
716 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 717 | struct drm_file *file, |
54cf91dc CW |
718 | struct intel_ring_buffer *ring) |
719 | { | |
cc889e0f DV |
720 | /* Unconditionally force add_request to emit a full flush. */ |
721 | ring->gpu_caches_dirty = true; | |
54cf91dc | 722 | |
432e58ed | 723 | /* Add a breadcrumb for the completion of the batch buffer */ |
3bb73aba | 724 | (void)i915_add_request(ring, file, NULL); |
432e58ed | 725 | } |
54cf91dc | 726 | |
ae662d31 EA |
727 | static int |
728 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
729 | struct intel_ring_buffer *ring) | |
730 | { | |
731 | drm_i915_private_t *dev_priv = dev->dev_private; | |
732 | int ret, i; | |
733 | ||
734 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
735 | return 0; | |
736 | ||
737 | ret = intel_ring_begin(ring, 4 * 3); | |
738 | if (ret) | |
739 | return ret; | |
740 | ||
741 | for (i = 0; i < 4; i++) { | |
742 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
743 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
744 | intel_ring_emit(ring, 0); | |
745 | } | |
746 | ||
747 | intel_ring_advance(ring); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
54cf91dc CW |
752 | static int |
753 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
754 | struct drm_file *file, | |
755 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 756 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
757 | { |
758 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 759 | struct list_head objects; |
67731b87 | 760 | struct eb_objects *eb; |
54cf91dc CW |
761 | struct drm_i915_gem_object *batch_obj; |
762 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 763 | struct intel_ring_buffer *ring; |
6e0a69db | 764 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 765 | u32 exec_start, exec_len; |
84f9f938 | 766 | u32 mask; |
d7d4eedd | 767 | u32 flags; |
72bfa19c | 768 | int ret, mode, i; |
54cf91dc | 769 | |
432e58ed | 770 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 771 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
772 | return -EINVAL; |
773 | } | |
774 | ||
775 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
776 | if (ret) |
777 | return ret; | |
778 | ||
d7d4eedd CW |
779 | flags = 0; |
780 | if (args->flags & I915_EXEC_SECURE) { | |
781 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
782 | return -EPERM; | |
783 | ||
784 | flags |= I915_DISPATCH_SECURE; | |
785 | } | |
b45305fc DV |
786 | if (args->flags & I915_EXEC_IS_PINNED) |
787 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 788 | |
54cf91dc CW |
789 | switch (args->flags & I915_EXEC_RING_MASK) { |
790 | case I915_EXEC_DEFAULT: | |
791 | case I915_EXEC_RENDER: | |
1ec14ad3 | 792 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
793 | break; |
794 | case I915_EXEC_BSD: | |
1ec14ad3 | 795 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
796 | if (ctx_id != 0) { |
797 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
798 | ring->name); | |
799 | return -EPERM; | |
800 | } | |
54cf91dc CW |
801 | break; |
802 | case I915_EXEC_BLT: | |
1ec14ad3 | 803 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
804 | if (ctx_id != 0) { |
805 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
806 | ring->name); | |
807 | return -EPERM; | |
808 | } | |
54cf91dc CW |
809 | break; |
810 | default: | |
ff240199 | 811 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
812 | (int)(args->flags & I915_EXEC_RING_MASK)); |
813 | return -EINVAL; | |
814 | } | |
a15817cf CW |
815 | if (!intel_ring_initialized(ring)) { |
816 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
817 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
818 | return -EINVAL; | |
819 | } | |
54cf91dc | 820 | |
72bfa19c | 821 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 822 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
823 | switch (mode) { |
824 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
825 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
826 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
827 | if (ring == &dev_priv->ring[RCS] && | |
828 | mode != dev_priv->relative_constants_mode) { | |
829 | if (INTEL_INFO(dev)->gen < 4) | |
830 | return -EINVAL; | |
831 | ||
832 | if (INTEL_INFO(dev)->gen > 5 && | |
833 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
834 | return -EINVAL; | |
84f9f938 BW |
835 | |
836 | /* The HW changed the meaning on this bit on gen6 */ | |
837 | if (INTEL_INFO(dev)->gen >= 6) | |
838 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
839 | } |
840 | break; | |
841 | default: | |
ff240199 | 842 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
843 | return -EINVAL; |
844 | } | |
845 | ||
54cf91dc | 846 | if (args->buffer_count < 1) { |
ff240199 | 847 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
848 | return -EINVAL; |
849 | } | |
54cf91dc CW |
850 | |
851 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 852 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 853 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
854 | return -EINVAL; |
855 | } | |
856 | ||
6ebebc92 DV |
857 | if (INTEL_INFO(dev)->gen >= 5) { |
858 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
44afb3a0 XW |
862 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
863 | DRM_DEBUG("execbuf with %u cliprects\n", | |
864 | args->num_cliprects); | |
865 | return -EINVAL; | |
866 | } | |
5e13a0c5 | 867 | |
432e58ed | 868 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
869 | GFP_KERNEL); |
870 | if (cliprects == NULL) { | |
871 | ret = -ENOMEM; | |
872 | goto pre_mutex_err; | |
873 | } | |
874 | ||
432e58ed CW |
875 | if (copy_from_user(cliprects, |
876 | (struct drm_clip_rect __user *)(uintptr_t) | |
877 | args->cliprects_ptr, | |
878 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
879 | ret = -EFAULT; |
880 | goto pre_mutex_err; | |
881 | } | |
882 | } | |
883 | ||
54cf91dc CW |
884 | ret = i915_mutex_lock_interruptible(dev); |
885 | if (ret) | |
886 | goto pre_mutex_err; | |
887 | ||
888 | if (dev_priv->mm.suspended) { | |
889 | mutex_unlock(&dev->struct_mutex); | |
890 | ret = -EBUSY; | |
891 | goto pre_mutex_err; | |
892 | } | |
893 | ||
67731b87 CW |
894 | eb = eb_create(args->buffer_count); |
895 | if (eb == NULL) { | |
896 | mutex_unlock(&dev->struct_mutex); | |
897 | ret = -ENOMEM; | |
898 | goto pre_mutex_err; | |
899 | } | |
900 | ||
54cf91dc | 901 | /* Look up object handles */ |
432e58ed | 902 | INIT_LIST_HEAD(&objects); |
3b96eff4 CW |
903 | ret = eb_lookup_objects(eb, exec, args->buffer_count, file, &objects); |
904 | if (ret) | |
905 | goto err; | |
54cf91dc | 906 | |
6fe4f140 CW |
907 | /* take note of the batch buffer before we might reorder the lists */ |
908 | batch_obj = list_entry(objects.prev, | |
909 | struct drm_i915_gem_object, | |
910 | exec_list); | |
911 | ||
54cf91dc | 912 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 913 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
914 | if (ret) |
915 | goto err; | |
916 | ||
917 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 918 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
919 | if (ret) { |
920 | if (ret == -EFAULT) { | |
d9e86c0e | 921 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
922 | &objects, eb, |
923 | exec, | |
54cf91dc CW |
924 | args->buffer_count); |
925 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
926 | } | |
927 | if (ret) | |
928 | goto err; | |
929 | } | |
930 | ||
931 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 932 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 933 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
934 | ret = -EINVAL; |
935 | goto err; | |
936 | } | |
937 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
938 | ||
d7d4eedd CW |
939 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
940 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
941 | * hsw should have this fixed, but let's be paranoid and do it | |
942 | * unconditionally for now. */ | |
943 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
944 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
945 | ||
432e58ed CW |
946 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
947 | if (ret) | |
54cf91dc | 948 | goto err; |
54cf91dc | 949 | |
0da5cec1 EA |
950 | ret = i915_switch_context(ring, file, ctx_id); |
951 | if (ret) | |
952 | goto err; | |
953 | ||
e2971bda BW |
954 | if (ring == &dev_priv->ring[RCS] && |
955 | mode != dev_priv->relative_constants_mode) { | |
956 | ret = intel_ring_begin(ring, 4); | |
957 | if (ret) | |
958 | goto err; | |
959 | ||
960 | intel_ring_emit(ring, MI_NOOP); | |
961 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
962 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 963 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
964 | intel_ring_advance(ring); |
965 | ||
966 | dev_priv->relative_constants_mode = mode; | |
967 | } | |
968 | ||
ae662d31 EA |
969 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
970 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
971 | if (ret) | |
972 | goto err; | |
973 | } | |
974 | ||
c4e7a414 CW |
975 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
976 | exec_len = args->batch_len; | |
977 | if (cliprects) { | |
978 | for (i = 0; i < args->num_cliprects; i++) { | |
979 | ret = i915_emit_box(dev, &cliprects[i], | |
980 | args->DR1, args->DR4); | |
981 | if (ret) | |
982 | goto err; | |
983 | ||
984 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
985 | exec_start, exec_len, |
986 | flags); | |
c4e7a414 CW |
987 | if (ret) |
988 | goto err; | |
989 | } | |
990 | } else { | |
d7d4eedd CW |
991 | ret = ring->dispatch_execbuffer(ring, |
992 | exec_start, exec_len, | |
993 | flags); | |
c4e7a414 CW |
994 | if (ret) |
995 | goto err; | |
996 | } | |
54cf91dc | 997 | |
9d773091 CW |
998 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
999 | ||
1000 | i915_gem_execbuffer_move_to_active(&objects, ring); | |
432e58ed | 1001 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1002 | |
1003 | err: | |
67731b87 | 1004 | eb_destroy(eb); |
432e58ed CW |
1005 | while (!list_empty(&objects)) { |
1006 | struct drm_i915_gem_object *obj; | |
1007 | ||
1008 | obj = list_first_entry(&objects, | |
1009 | struct drm_i915_gem_object, | |
1010 | exec_list); | |
1011 | list_del_init(&obj->exec_list); | |
1012 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1013 | } |
1014 | ||
1015 | mutex_unlock(&dev->struct_mutex); | |
1016 | ||
1017 | pre_mutex_err: | |
54cf91dc | 1018 | kfree(cliprects); |
54cf91dc CW |
1019 | return ret; |
1020 | } | |
1021 | ||
1022 | /* | |
1023 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1024 | * list array and passes it to the real function. | |
1025 | */ | |
1026 | int | |
1027 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1028 | struct drm_file *file) | |
1029 | { | |
1030 | struct drm_i915_gem_execbuffer *args = data; | |
1031 | struct drm_i915_gem_execbuffer2 exec2; | |
1032 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1033 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1034 | int ret, i; | |
1035 | ||
54cf91dc | 1036 | if (args->buffer_count < 1) { |
ff240199 | 1037 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1038 | return -EINVAL; |
1039 | } | |
1040 | ||
1041 | /* Copy in the exec list from userland */ | |
1042 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1043 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1044 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1045 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1046 | args->buffer_count); |
1047 | drm_free_large(exec_list); | |
1048 | drm_free_large(exec2_list); | |
1049 | return -ENOMEM; | |
1050 | } | |
1051 | ret = copy_from_user(exec_list, | |
ba7a6458 | 1052 | (void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1053 | sizeof(*exec_list) * args->buffer_count); |
1054 | if (ret != 0) { | |
ff240199 | 1055 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1056 | args->buffer_count, ret); |
1057 | drm_free_large(exec_list); | |
1058 | drm_free_large(exec2_list); | |
1059 | return -EFAULT; | |
1060 | } | |
1061 | ||
1062 | for (i = 0; i < args->buffer_count; i++) { | |
1063 | exec2_list[i].handle = exec_list[i].handle; | |
1064 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1065 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1066 | exec2_list[i].alignment = exec_list[i].alignment; | |
1067 | exec2_list[i].offset = exec_list[i].offset; | |
1068 | if (INTEL_INFO(dev)->gen < 4) | |
1069 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1070 | else | |
1071 | exec2_list[i].flags = 0; | |
1072 | } | |
1073 | ||
1074 | exec2.buffers_ptr = args->buffers_ptr; | |
1075 | exec2.buffer_count = args->buffer_count; | |
1076 | exec2.batch_start_offset = args->batch_start_offset; | |
1077 | exec2.batch_len = args->batch_len; | |
1078 | exec2.DR1 = args->DR1; | |
1079 | exec2.DR4 = args->DR4; | |
1080 | exec2.num_cliprects = args->num_cliprects; | |
1081 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1082 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1083 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1084 | |
1085 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1086 | if (!ret) { | |
1087 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1088 | for (i = 0; i < args->buffer_count; i++) | |
1089 | exec_list[i].offset = exec2_list[i].offset; | |
1090 | /* ... and back out to userspace */ | |
ba7a6458 | 1091 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1092 | exec_list, |
1093 | sizeof(*exec_list) * args->buffer_count); | |
1094 | if (ret) { | |
1095 | ret = -EFAULT; | |
ff240199 | 1096 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1097 | "back to user (%d)\n", |
1098 | args->buffer_count, ret); | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | drm_free_large(exec_list); | |
1103 | drm_free_large(exec2_list); | |
1104 | return ret; | |
1105 | } | |
1106 | ||
1107 | int | |
1108 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1109 | struct drm_file *file) | |
1110 | { | |
1111 | struct drm_i915_gem_execbuffer2 *args = data; | |
1112 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1113 | int ret; | |
1114 | ||
ed8cd3b2 XW |
1115 | if (args->buffer_count < 1 || |
1116 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1117 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1118 | return -EINVAL; |
1119 | } | |
1120 | ||
8408c282 | 1121 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1122 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1123 | if (exec2_list == NULL) |
1124 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1125 | args->buffer_count); | |
54cf91dc | 1126 | if (exec2_list == NULL) { |
ff240199 | 1127 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1128 | args->buffer_count); |
1129 | return -ENOMEM; | |
1130 | } | |
1131 | ret = copy_from_user(exec2_list, | |
1132 | (struct drm_i915_relocation_entry __user *) | |
1133 | (uintptr_t) args->buffers_ptr, | |
1134 | sizeof(*exec2_list) * args->buffer_count); | |
1135 | if (ret != 0) { | |
ff240199 | 1136 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1137 | args->buffer_count, ret); |
1138 | drm_free_large(exec2_list); | |
1139 | return -EFAULT; | |
1140 | } | |
1141 | ||
1142 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1143 | if (!ret) { | |
1144 | /* Copy the new buffer offsets back to the user's exec list. */ | |
ba7a6458 | 1145 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1146 | exec2_list, |
1147 | sizeof(*exec2_list) * args->buffer_count); | |
1148 | if (ret) { | |
1149 | ret = -EFAULT; | |
ff240199 | 1150 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1151 | "back to user (%d)\n", |
1152 | args->buffer_count, ret); | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | drm_free_large(exec2_list); | |
1157 | return ret; | |
1158 | } |