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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
ad778f89 CW |
29 | #include <linux/dma_remapping.h> |
30 | #include <linux/reservation.h> | |
fec0445c | 31 | #include <linux/sync_file.h> |
ad778f89 CW |
32 | #include <linux/uaccess.h> |
33 | ||
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
ad778f89 | 36 | |
54cf91dc | 37 | #include "i915_drv.h" |
57822dc6 | 38 | #include "i915_gem_clflush.h" |
54cf91dc CW |
39 | #include "i915_trace.h" |
40 | #include "intel_drv.h" | |
5d723d7a | 41 | #include "intel_frontbuffer.h" |
54cf91dc | 42 | |
d50415cc CW |
43 | #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */ |
44 | ||
9e2793f6 DG |
45 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
46 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
47 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) | |
48 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) | |
49 | #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */ | |
d23db88c CW |
50 | |
51 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 52 | |
650bc635 CW |
53 | #define __I915_EXEC_ILLEGAL_FLAGS \ |
54 | (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK) | |
5b043f4e | 55 | |
650bc635 | 56 | struct i915_execbuffer { |
d50415cc | 57 | struct drm_i915_private *i915; |
650bc635 CW |
58 | struct drm_file *file; |
59 | struct drm_i915_gem_execbuffer2 *args; | |
60 | struct drm_i915_gem_exec_object2 *exec; | |
61 | struct intel_engine_cs *engine; | |
62 | struct i915_gem_context *ctx; | |
63 | struct i915_address_space *vm; | |
64 | struct i915_vma *batch; | |
65 | struct drm_i915_gem_request *request; | |
66 | u32 batch_start_offset; | |
67 | u32 batch_len; | |
68 | unsigned int dispatch_flags; | |
69 | struct drm_i915_gem_exec_object2 shadow_exec_entry; | |
70 | bool need_relocs; | |
27173f1f | 71 | struct list_head vmas; |
650bc635 CW |
72 | struct reloc_cache { |
73 | struct drm_mm_node node; | |
74 | unsigned long vaddr; | |
75 | unsigned int page; | |
76 | bool use_64bit_reloc : 1; | |
77 | } reloc_cache; | |
4ff4b44c CW |
78 | int lut_mask; |
79 | struct hlist_head *buckets; | |
67731b87 CW |
80 | }; |
81 | ||
4ff4b44c CW |
82 | /* |
83 | * As an alternative to creating a hashtable of handle-to-vma for a batch, | |
84 | * we used the last available reserved field in the execobject[] and stash | |
85 | * a link from the execobj to its vma. | |
86 | */ | |
87 | #define __exec_to_vma(ee) (ee)->rsvd2 | |
88 | #define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee)) | |
89 | ||
650bc635 | 90 | static int eb_create(struct i915_execbuffer *eb) |
67731b87 | 91 | { |
4ff4b44c CW |
92 | if ((eb->args->flags & I915_EXEC_HANDLE_LUT) == 0) { |
93 | unsigned int size = 1 + ilog2(eb->args->buffer_count); | |
94 | ||
95 | do { | |
96 | eb->buckets = kzalloc(sizeof(struct hlist_head) << size, | |
97 | GFP_TEMPORARY | | |
98 | __GFP_NORETRY | | |
99 | __GFP_NOWARN); | |
100 | if (eb->buckets) | |
101 | break; | |
102 | } while (--size); | |
103 | ||
104 | if (unlikely(!eb->buckets)) { | |
105 | eb->buckets = kzalloc(sizeof(struct hlist_head), | |
106 | GFP_TEMPORARY); | |
107 | if (unlikely(!eb->buckets)) | |
108 | return -ENOMEM; | |
109 | } | |
eef90ccb | 110 | |
4ff4b44c | 111 | eb->lut_mask = size; |
650bc635 | 112 | } else { |
4ff4b44c | 113 | eb->lut_mask = -eb->args->buffer_count; |
650bc635 | 114 | } |
eef90ccb | 115 | |
650bc635 | 116 | return 0; |
67731b87 CW |
117 | } |
118 | ||
d55495b4 CW |
119 | static inline void |
120 | __eb_unreserve_vma(struct i915_vma *vma, | |
121 | const struct drm_i915_gem_exec_object2 *entry) | |
122 | { | |
123 | if (unlikely(entry->flags & __EXEC_OBJECT_HAS_FENCE)) | |
124 | i915_vma_unpin_fence(vma); | |
125 | ||
126 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
127 | __i915_vma_unpin(vma); | |
128 | } | |
129 | ||
130 | static void | |
131 | eb_unreserve_vma(struct i915_vma *vma) | |
132 | { | |
133 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
134 | ||
135 | __eb_unreserve_vma(vma, entry); | |
136 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
137 | } | |
138 | ||
67731b87 | 139 | static void |
650bc635 | 140 | eb_reset(struct i915_execbuffer *eb) |
67731b87 | 141 | { |
d55495b4 CW |
142 | struct i915_vma *vma; |
143 | ||
8c45cec4 | 144 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
d55495b4 CW |
145 | eb_unreserve_vma(vma); |
146 | i915_vma_put(vma); | |
147 | vma->exec_entry = NULL; | |
148 | } | |
149 | ||
4ff4b44c CW |
150 | if (eb->lut_mask >= 0) |
151 | memset(eb->buckets, 0, | |
152 | sizeof(struct hlist_head) << eb->lut_mask); | |
67731b87 CW |
153 | } |
154 | ||
4ff4b44c CW |
155 | static bool |
156 | eb_add_vma(struct i915_execbuffer *eb, struct i915_vma *vma, int i) | |
59bfa124 | 157 | { |
4ff4b44c CW |
158 | if (unlikely(vma->exec_entry)) { |
159 | DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n", | |
160 | eb->exec[i].handle, i); | |
161 | return false; | |
162 | } | |
163 | list_add_tail(&vma->exec_link, &eb->vmas); | |
164 | ||
165 | vma->exec_entry = &eb->exec[i]; | |
166 | if (eb->lut_mask >= 0) { | |
167 | vma->exec_handle = eb->exec[i].handle; | |
168 | hlist_add_head(&vma->exec_node, | |
169 | &eb->buckets[hash_32(vma->exec_handle, | |
170 | eb->lut_mask)]); | |
171 | } | |
59bfa124 | 172 | |
4ff4b44c CW |
173 | i915_vma_get(vma); |
174 | __exec_to_vma(&eb->exec[i]) = (uintptr_t)vma; | |
175 | return true; | |
176 | } | |
59bfa124 | 177 | |
4ff4b44c CW |
178 | static inline struct hlist_head * |
179 | ht_head(const struct i915_gem_context *ctx, u32 handle) | |
180 | { | |
181 | return &ctx->vma_lut.ht[hash_32(handle, ctx->vma_lut.ht_bits)]; | |
182 | } | |
183 | ||
184 | static inline bool | |
185 | ht_needs_resize(const struct i915_gem_context *ctx) | |
186 | { | |
187 | return (4*ctx->vma_lut.ht_count > 3*ctx->vma_lut.ht_size || | |
188 | 4*ctx->vma_lut.ht_count + 1 < ctx->vma_lut.ht_size); | |
59bfa124 CW |
189 | } |
190 | ||
3b96eff4 | 191 | static int |
650bc635 | 192 | eb_lookup_vmas(struct i915_execbuffer *eb) |
3b96eff4 | 193 | { |
4ff4b44c CW |
194 | #define INTERMEDIATE BIT(0) |
195 | const int count = eb->args->buffer_count; | |
196 | struct i915_vma *vma; | |
197 | int slow_pass = -1; | |
198 | int i; | |
3b96eff4 | 199 | |
d55495b4 CW |
200 | INIT_LIST_HEAD(&eb->vmas); |
201 | ||
4ff4b44c CW |
202 | if (unlikely(eb->ctx->vma_lut.ht_size & I915_CTX_RESIZE_IN_PROGRESS)) |
203 | flush_work(&eb->ctx->vma_lut.resize); | |
204 | GEM_BUG_ON(eb->ctx->vma_lut.ht_size & I915_CTX_RESIZE_IN_PROGRESS); | |
205 | ||
206 | for (i = 0; i < count; i++) { | |
207 | __exec_to_vma(&eb->exec[i]) = 0; | |
208 | ||
209 | hlist_for_each_entry(vma, | |
210 | ht_head(eb->ctx, eb->exec[i].handle), | |
211 | ctx_node) { | |
212 | if (vma->ctx_handle != eb->exec[i].handle) | |
213 | continue; | |
214 | ||
215 | if (!eb_add_vma(eb, vma, i)) | |
216 | return -EINVAL; | |
217 | ||
218 | goto next_vma; | |
219 | } | |
220 | ||
221 | if (slow_pass < 0) | |
222 | slow_pass = i; | |
223 | next_vma: ; | |
224 | } | |
225 | ||
226 | if (slow_pass < 0) | |
227 | return 0; | |
228 | ||
650bc635 | 229 | spin_lock(&eb->file->table_lock); |
27173f1f BW |
230 | /* Grab a reference to the object and release the lock so we can lookup |
231 | * or create the VMA without using GFP_ATOMIC */ | |
4ff4b44c CW |
232 | for (i = slow_pass; i < count; i++) { |
233 | struct drm_i915_gem_object *obj; | |
3b96eff4 | 234 | |
4ff4b44c CW |
235 | if (__exec_to_vma(&eb->exec[i])) |
236 | continue; | |
237 | ||
238 | obj = to_intel_bo(idr_find(&eb->file->object_idr, | |
239 | eb->exec[i].handle)); | |
240 | if (unlikely(!obj)) { | |
650bc635 | 241 | spin_unlock(&eb->file->table_lock); |
4ff4b44c CW |
242 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
243 | eb->exec[i].handle, i); | |
244 | return -ENOENT; | |
3b96eff4 CW |
245 | } |
246 | ||
4ff4b44c | 247 | __exec_to_vma(&eb->exec[i]) = INTERMEDIATE | (uintptr_t)obj; |
27173f1f | 248 | } |
650bc635 | 249 | spin_unlock(&eb->file->table_lock); |
3b96eff4 | 250 | |
4ff4b44c CW |
251 | for (i = slow_pass; i < count; i++) { |
252 | struct drm_i915_gem_object *obj; | |
6f65e29a | 253 | |
4ff4b44c CW |
254 | if ((__exec_to_vma(&eb->exec[i]) & INTERMEDIATE) == 0) |
255 | continue; | |
9ae9ab52 | 256 | |
e656a6cb DV |
257 | /* |
258 | * NOTE: We can leak any vmas created here when something fails | |
259 | * later on. But that's no issue since vma_unbind can deal with | |
260 | * vmas which are not actually bound. And since only | |
261 | * lookup_or_create exists as an interface to get at the vma | |
262 | * from the (obj, vm) we don't run the risk of creating | |
263 | * duplicated vmas for the same vm. | |
264 | */ | |
4ff4b44c CW |
265 | obj = u64_to_ptr(struct drm_i915_gem_object, |
266 | __exec_to_vma(&eb->exec[i]) & ~INTERMEDIATE); | |
650bc635 | 267 | vma = i915_vma_instance(obj, eb->vm, NULL); |
058d88c4 | 268 | if (unlikely(IS_ERR(vma))) { |
27173f1f | 269 | DRM_DEBUG("Failed to lookup VMA\n"); |
4ff4b44c | 270 | return PTR_ERR(vma); |
27173f1f BW |
271 | } |
272 | ||
4ff4b44c CW |
273 | /* First come, first served */ |
274 | if (!vma->ctx) { | |
275 | vma->ctx = eb->ctx; | |
276 | vma->ctx_handle = eb->exec[i].handle; | |
277 | hlist_add_head(&vma->ctx_node, | |
278 | ht_head(eb->ctx, eb->exec[i].handle)); | |
279 | eb->ctx->vma_lut.ht_count++; | |
280 | if (i915_vma_is_ggtt(vma)) { | |
281 | GEM_BUG_ON(obj->vma_hashed); | |
282 | obj->vma_hashed = vma; | |
283 | } | |
eef90ccb | 284 | } |
4ff4b44c CW |
285 | |
286 | if (!eb_add_vma(eb, vma, i)) | |
287 | return -EINVAL; | |
288 | } | |
289 | ||
290 | if (ht_needs_resize(eb->ctx)) { | |
291 | eb->ctx->vma_lut.ht_size |= I915_CTX_RESIZE_IN_PROGRESS; | |
292 | queue_work(system_highpri_wq, &eb->ctx->vma_lut.resize); | |
3b96eff4 | 293 | } |
3b96eff4 | 294 | |
9ae9ab52 | 295 | return 0; |
4ff4b44c CW |
296 | #undef INTERMEDIATE |
297 | } | |
27173f1f | 298 | |
4ff4b44c CW |
299 | static struct i915_vma * |
300 | eb_get_batch(struct i915_execbuffer *eb) | |
301 | { | |
302 | struct i915_vma *vma = | |
303 | exec_to_vma(&eb->exec[eb->args->buffer_count - 1]); | |
27173f1f | 304 | |
9ae9ab52 | 305 | /* |
4ff4b44c CW |
306 | * SNA is doing fancy tricks with compressing batch buffers, which leads |
307 | * to negative relocation deltas. Usually that works out ok since the | |
308 | * relocate address is still positive, except when the batch is placed | |
309 | * very low in the GTT. Ensure this doesn't happen. | |
310 | * | |
311 | * Note that actual hangs have only been observed on gen7, but for | |
312 | * paranoia do it everywhere. | |
9ae9ab52 | 313 | */ |
4ff4b44c CW |
314 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) |
315 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
9ae9ab52 | 316 | |
4ff4b44c | 317 | return vma; |
3b96eff4 CW |
318 | } |
319 | ||
4ff4b44c CW |
320 | static struct i915_vma * |
321 | eb_get_vma(struct i915_execbuffer *eb, unsigned long handle) | |
67731b87 | 322 | { |
4ff4b44c CW |
323 | if (eb->lut_mask < 0) { |
324 | if (handle >= -eb->lut_mask) | |
eef90ccb | 325 | return NULL; |
4ff4b44c | 326 | return exec_to_vma(&eb->exec[handle]); |
eef90ccb CW |
327 | } else { |
328 | struct hlist_head *head; | |
aa45950b | 329 | struct i915_vma *vma; |
67731b87 | 330 | |
4ff4b44c | 331 | head = &eb->buckets[hash_32(handle, eb->lut_mask)]; |
aa45950b | 332 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
333 | if (vma->exec_handle == handle) |
334 | return vma; | |
eef90ccb CW |
335 | } |
336 | return NULL; | |
337 | } | |
67731b87 CW |
338 | } |
339 | ||
650bc635 | 340 | static void eb_destroy(struct i915_execbuffer *eb) |
a415d355 | 341 | { |
d55495b4 | 342 | struct i915_vma *vma; |
650bc635 | 343 | |
8c45cec4 | 344 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
d55495b4 CW |
345 | if (!vma->exec_entry) |
346 | continue; | |
bcffc3fa | 347 | |
d55495b4 | 348 | __eb_unreserve_vma(vma, vma->exec_entry); |
172ae5b4 | 349 | vma->exec_entry = NULL; |
624192cf | 350 | i915_vma_put(vma); |
bcffc3fa | 351 | } |
d55495b4 CW |
352 | |
353 | i915_gem_context_put(eb->ctx); | |
354 | ||
4ff4b44c | 355 | if (eb->lut_mask >= 0) |
d55495b4 | 356 | kfree(eb->buckets); |
67731b87 CW |
357 | } |
358 | ||
dabdfe02 CW |
359 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
360 | { | |
9e53d9be CW |
361 | if (!i915_gem_object_has_struct_page(obj)) |
362 | return false; | |
363 | ||
d50415cc CW |
364 | if (DBG_USE_CPU_RELOC) |
365 | return DBG_USE_CPU_RELOC > 0; | |
366 | ||
0031fb96 | 367 | return (HAS_LLC(to_i915(obj->base.dev)) || |
e27ab73d | 368 | obj->cache_dirty || |
dabdfe02 CW |
369 | obj->cache_level != I915_CACHE_NONE); |
370 | } | |
371 | ||
934acce3 MW |
372 | /* Used to convert any address to canonical form. |
373 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
374 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
375 | * addresses to be in a canonical form: | |
376 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
377 | * canonical form [63:48] == [47]." | |
378 | */ | |
379 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
380 | static inline uint64_t gen8_canonical_addr(uint64_t address) | |
381 | { | |
382 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
383 | } | |
384 | ||
385 | static inline uint64_t gen8_noncanonical_addr(uint64_t address) | |
386 | { | |
387 | return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1); | |
388 | } | |
389 | ||
390 | static inline uint64_t | |
d50415cc | 391 | relocation_target(const struct drm_i915_gem_relocation_entry *reloc, |
934acce3 MW |
392 | uint64_t target_offset) |
393 | { | |
394 | return gen8_canonical_addr((int)reloc->delta + target_offset); | |
395 | } | |
396 | ||
d50415cc CW |
397 | static void reloc_cache_init(struct reloc_cache *cache, |
398 | struct drm_i915_private *i915) | |
5032d871 | 399 | { |
31a39207 | 400 | cache->page = -1; |
d50415cc | 401 | cache->vaddr = 0; |
dfc5148f JL |
402 | /* Must be a variable in the struct to allow GCC to unroll. */ |
403 | cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); | |
e8cb909a | 404 | cache->node.allocated = false; |
d50415cc | 405 | } |
5032d871 | 406 | |
d50415cc CW |
407 | static inline void *unmask_page(unsigned long p) |
408 | { | |
409 | return (void *)(uintptr_t)(p & PAGE_MASK); | |
410 | } | |
411 | ||
412 | static inline unsigned int unmask_flags(unsigned long p) | |
413 | { | |
414 | return p & ~PAGE_MASK; | |
31a39207 CW |
415 | } |
416 | ||
d50415cc CW |
417 | #define KMAP 0x4 /* after CLFLUSH_FLAGS */ |
418 | ||
650bc635 CW |
419 | static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) |
420 | { | |
421 | struct drm_i915_private *i915 = | |
422 | container_of(cache, struct i915_execbuffer, reloc_cache)->i915; | |
423 | return &i915->ggtt; | |
424 | } | |
425 | ||
426 | static void reloc_cache_reset(struct reloc_cache *cache) | |
31a39207 | 427 | { |
d50415cc | 428 | void *vaddr; |
5032d871 | 429 | |
31a39207 CW |
430 | if (!cache->vaddr) |
431 | return; | |
3c94ceee | 432 | |
d50415cc CW |
433 | vaddr = unmask_page(cache->vaddr); |
434 | if (cache->vaddr & KMAP) { | |
435 | if (cache->vaddr & CLFLUSH_AFTER) | |
436 | mb(); | |
3c94ceee | 437 | |
d50415cc CW |
438 | kunmap_atomic(vaddr); |
439 | i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm); | |
440 | } else { | |
e8cb909a | 441 | wmb(); |
d50415cc | 442 | io_mapping_unmap_atomic((void __iomem *)vaddr); |
e8cb909a | 443 | if (cache->node.allocated) { |
650bc635 | 444 | struct i915_ggtt *ggtt = cache_to_ggtt(cache); |
e8cb909a CW |
445 | |
446 | ggtt->base.clear_range(&ggtt->base, | |
447 | cache->node.start, | |
4fb84d99 | 448 | cache->node.size); |
e8cb909a CW |
449 | drm_mm_remove_node(&cache->node); |
450 | } else { | |
451 | i915_vma_unpin((struct i915_vma *)cache->node.mm); | |
3c94ceee | 452 | } |
31a39207 | 453 | } |
650bc635 CW |
454 | |
455 | cache->vaddr = 0; | |
456 | cache->page = -1; | |
31a39207 CW |
457 | } |
458 | ||
459 | static void *reloc_kmap(struct drm_i915_gem_object *obj, | |
460 | struct reloc_cache *cache, | |
461 | int page) | |
462 | { | |
d50415cc CW |
463 | void *vaddr; |
464 | ||
465 | if (cache->vaddr) { | |
466 | kunmap_atomic(unmask_page(cache->vaddr)); | |
467 | } else { | |
468 | unsigned int flushes; | |
469 | int ret; | |
31a39207 | 470 | |
d50415cc CW |
471 | ret = i915_gem_obj_prepare_shmem_write(obj, &flushes); |
472 | if (ret) | |
473 | return ERR_PTR(ret); | |
474 | ||
475 | BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); | |
476 | BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); | |
3c94ceee | 477 | |
d50415cc CW |
478 | cache->vaddr = flushes | KMAP; |
479 | cache->node.mm = (void *)obj; | |
480 | if (flushes) | |
481 | mb(); | |
3c94ceee BW |
482 | } |
483 | ||
d50415cc CW |
484 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); |
485 | cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; | |
31a39207 | 486 | cache->page = page; |
5032d871 | 487 | |
d50415cc | 488 | return vaddr; |
5032d871 RB |
489 | } |
490 | ||
d50415cc CW |
491 | static void *reloc_iomap(struct drm_i915_gem_object *obj, |
492 | struct reloc_cache *cache, | |
493 | int page) | |
5032d871 | 494 | { |
650bc635 | 495 | struct i915_ggtt *ggtt = cache_to_ggtt(cache); |
e8cb909a | 496 | unsigned long offset; |
d50415cc | 497 | void *vaddr; |
5032d871 | 498 | |
d50415cc | 499 | if (cache->vaddr) { |
615e5000 | 500 | io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); |
d50415cc CW |
501 | } else { |
502 | struct i915_vma *vma; | |
503 | int ret; | |
5032d871 | 504 | |
d50415cc CW |
505 | if (use_cpu_reloc(obj)) |
506 | return NULL; | |
3c94ceee | 507 | |
d50415cc CW |
508 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
509 | if (ret) | |
510 | return ERR_PTR(ret); | |
3c94ceee | 511 | |
d50415cc CW |
512 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
513 | PIN_MAPPABLE | PIN_NONBLOCK); | |
e8cb909a CW |
514 | if (IS_ERR(vma)) { |
515 | memset(&cache->node, 0, sizeof(cache->node)); | |
4e64e553 | 516 | ret = drm_mm_insert_node_in_range |
e8cb909a | 517 | (&ggtt->base.mm, &cache->node, |
f51455d4 | 518 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, |
e8cb909a | 519 | 0, ggtt->mappable_end, |
4e64e553 | 520 | DRM_MM_INSERT_LOW); |
c92fa4fe CW |
521 | if (ret) /* no inactive aperture space, use cpu reloc */ |
522 | return NULL; | |
e8cb909a | 523 | } else { |
49ef5294 | 524 | ret = i915_vma_put_fence(vma); |
e8cb909a CW |
525 | if (ret) { |
526 | i915_vma_unpin(vma); | |
527 | return ERR_PTR(ret); | |
528 | } | |
5032d871 | 529 | |
e8cb909a CW |
530 | cache->node.start = vma->node.start; |
531 | cache->node.mm = (void *)vma; | |
3c94ceee | 532 | } |
e8cb909a | 533 | } |
3c94ceee | 534 | |
e8cb909a CW |
535 | offset = cache->node.start; |
536 | if (cache->node.allocated) { | |
fc099090 | 537 | wmb(); |
e8cb909a CW |
538 | ggtt->base.insert_page(&ggtt->base, |
539 | i915_gem_object_get_dma_address(obj, page), | |
540 | offset, I915_CACHE_NONE, 0); | |
541 | } else { | |
542 | offset += page << PAGE_SHIFT; | |
3c94ceee BW |
543 | } |
544 | ||
650bc635 CW |
545 | vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable, |
546 | offset); | |
d50415cc CW |
547 | cache->page = page; |
548 | cache->vaddr = (unsigned long)vaddr; | |
5032d871 | 549 | |
d50415cc | 550 | return vaddr; |
5032d871 RB |
551 | } |
552 | ||
d50415cc CW |
553 | static void *reloc_vaddr(struct drm_i915_gem_object *obj, |
554 | struct reloc_cache *cache, | |
555 | int page) | |
edf4427b | 556 | { |
d50415cc | 557 | void *vaddr; |
5032d871 | 558 | |
d50415cc CW |
559 | if (cache->page == page) { |
560 | vaddr = unmask_page(cache->vaddr); | |
561 | } else { | |
562 | vaddr = NULL; | |
563 | if ((cache->vaddr & KMAP) == 0) | |
564 | vaddr = reloc_iomap(obj, cache, page); | |
565 | if (!vaddr) | |
566 | vaddr = reloc_kmap(obj, cache, page); | |
3c94ceee BW |
567 | } |
568 | ||
d50415cc | 569 | return vaddr; |
edf4427b CW |
570 | } |
571 | ||
d50415cc | 572 | static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) |
edf4427b | 573 | { |
d50415cc CW |
574 | if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { |
575 | if (flushes & CLFLUSH_BEFORE) { | |
576 | clflushopt(addr); | |
577 | mb(); | |
578 | } | |
edf4427b | 579 | |
d50415cc | 580 | *addr = value; |
edf4427b | 581 | |
d50415cc CW |
582 | /* Writes to the same cacheline are serialised by the CPU |
583 | * (including clflush). On the write path, we only require | |
584 | * that it hits memory in an orderly fashion and place | |
585 | * mb barriers at the start and end of the relocation phase | |
586 | * to ensure ordering of clflush wrt to the system. | |
587 | */ | |
588 | if (flushes & CLFLUSH_AFTER) | |
589 | clflushopt(addr); | |
590 | } else | |
591 | *addr = value; | |
edf4427b | 592 | } |
edf4427b | 593 | |
edf4427b | 594 | static int |
d50415cc CW |
595 | relocate_entry(struct drm_i915_gem_object *obj, |
596 | const struct drm_i915_gem_relocation_entry *reloc, | |
597 | struct reloc_cache *cache, | |
598 | u64 target_offset) | |
edf4427b | 599 | { |
d50415cc CW |
600 | u64 offset = reloc->offset; |
601 | bool wide = cache->use_64bit_reloc; | |
602 | void *vaddr; | |
edf4427b | 603 | |
d50415cc CW |
604 | target_offset = relocation_target(reloc, target_offset); |
605 | repeat: | |
606 | vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT); | |
607 | if (IS_ERR(vaddr)) | |
608 | return PTR_ERR(vaddr); | |
609 | ||
610 | clflush_write32(vaddr + offset_in_page(offset), | |
611 | lower_32_bits(target_offset), | |
612 | cache->vaddr); | |
613 | ||
614 | if (wide) { | |
615 | offset += sizeof(u32); | |
616 | target_offset >>= 32; | |
617 | wide = false; | |
618 | goto repeat; | |
edf4427b | 619 | } |
edf4427b | 620 | |
edf4427b CW |
621 | return 0; |
622 | } | |
edf4427b | 623 | |
54cf91dc | 624 | static int |
507d977f | 625 | eb_relocate_entry(struct i915_vma *vma, |
650bc635 CW |
626 | struct i915_execbuffer *eb, |
627 | struct drm_i915_gem_relocation_entry *reloc) | |
54cf91dc | 628 | { |
507d977f CW |
629 | struct i915_vma *target; |
630 | u64 target_offset; | |
8b78f0e5 | 631 | int ret; |
54cf91dc | 632 | |
67731b87 | 633 | /* we've already hold a reference to all valid objects */ |
507d977f CW |
634 | target = eb_get_vma(eb, reloc->target_handle); |
635 | if (unlikely(!target)) | |
54cf91dc | 636 | return -ENOENT; |
e844b990 | 637 | |
54cf91dc | 638 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 639 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 640 | DRM_DEBUG("reloc with multiple write domains: " |
507d977f | 641 | "target %d offset %d " |
54cf91dc | 642 | "read %08x write %08x", |
507d977f | 643 | reloc->target_handle, |
54cf91dc CW |
644 | (int) reloc->offset, |
645 | reloc->read_domains, | |
646 | reloc->write_domain); | |
8b78f0e5 | 647 | return -EINVAL; |
54cf91dc | 648 | } |
4ca4a250 DV |
649 | if (unlikely((reloc->write_domain | reloc->read_domains) |
650 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 651 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
507d977f | 652 | "target %d offset %d " |
54cf91dc | 653 | "read %08x write %08x", |
507d977f | 654 | reloc->target_handle, |
54cf91dc CW |
655 | (int) reloc->offset, |
656 | reloc->read_domains, | |
657 | reloc->write_domain); | |
8b78f0e5 | 658 | return -EINVAL; |
54cf91dc | 659 | } |
54cf91dc | 660 | |
507d977f CW |
661 | if (reloc->write_domain) |
662 | target->exec_entry->flags |= EXEC_OBJECT_WRITE; | |
663 | ||
664 | /* | |
665 | * Sandybridge PPGTT errata: We need a global gtt mapping for MI and | |
666 | * pipe_control writes because the gpu doesn't properly redirect them | |
667 | * through the ppgtt for non_secure batchbuffers. | |
668 | */ | |
669 | if (unlikely(IS_GEN6(eb->i915) && | |
670 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { | |
671 | ret = i915_vma_bind(target, target->obj->cache_level, | |
672 | PIN_GLOBAL); | |
673 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) | |
674 | return ret; | |
675 | } | |
54cf91dc CW |
676 | |
677 | /* If the relocation already has the right value in it, no | |
678 | * more work needs to be done. | |
679 | */ | |
507d977f | 680 | target_offset = gen8_canonical_addr(target->node.start); |
54cf91dc | 681 | if (target_offset == reloc->presumed_offset) |
67731b87 | 682 | return 0; |
54cf91dc CW |
683 | |
684 | /* Check that the relocation address is valid... */ | |
3c94ceee | 685 | if (unlikely(reloc->offset > |
507d977f | 686 | vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) { |
ff240199 | 687 | DRM_DEBUG("Relocation beyond object bounds: " |
507d977f CW |
688 | "target %d offset %d size %d.\n", |
689 | reloc->target_handle, | |
690 | (int)reloc->offset, | |
691 | (int)vma->size); | |
8b78f0e5 | 692 | return -EINVAL; |
54cf91dc | 693 | } |
b8f7ab17 | 694 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 695 | DRM_DEBUG("Relocation not 4-byte aligned: " |
507d977f CW |
696 | "target %d offset %d.\n", |
697 | reloc->target_handle, | |
698 | (int)reloc->offset); | |
8b78f0e5 | 699 | return -EINVAL; |
54cf91dc CW |
700 | } |
701 | ||
507d977f | 702 | ret = relocate_entry(vma->obj, reloc, &eb->reloc_cache, target_offset); |
d4d36014 DV |
703 | if (ret) |
704 | return ret; | |
705 | ||
54cf91dc CW |
706 | /* and update the user's relocation entry */ |
707 | reloc->presumed_offset = target_offset; | |
67731b87 | 708 | return 0; |
54cf91dc CW |
709 | } |
710 | ||
650bc635 | 711 | static int eb_relocate_vma(struct i915_vma *vma, struct i915_execbuffer *eb) |
54cf91dc | 712 | { |
1d83f442 CW |
713 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
714 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 715 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 716 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
31a39207 | 717 | int remain, ret = 0; |
54cf91dc | 718 | |
3ed605bc | 719 | user_relocs = u64_to_user_ptr(entry->relocs_ptr); |
54cf91dc | 720 | |
1d83f442 CW |
721 | remain = entry->relocation_count; |
722 | while (remain) { | |
723 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
ebc0808f CW |
724 | unsigned long unwritten; |
725 | unsigned int count; | |
726 | ||
727 | count = min_t(unsigned int, remain, ARRAY_SIZE(stack_reloc)); | |
1d83f442 CW |
728 | remain -= count; |
729 | ||
ebc0808f CW |
730 | /* This is the fast path and we cannot handle a pagefault |
731 | * whilst holding the struct mutex lest the user pass in the | |
732 | * relocations contained within a mmaped bo. For in such a case | |
733 | * we, the page fault handler would call i915_gem_fault() and | |
734 | * we would try to acquire the struct mutex again. Obviously | |
735 | * this is bad and so lockdep complains vehemently. | |
736 | */ | |
737 | pagefault_disable(); | |
738 | unwritten = __copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])); | |
739 | pagefault_enable(); | |
740 | if (unlikely(unwritten)) { | |
31a39207 CW |
741 | ret = -EFAULT; |
742 | goto out; | |
743 | } | |
54cf91dc | 744 | |
1d83f442 CW |
745 | do { |
746 | u64 offset = r->presumed_offset; | |
54cf91dc | 747 | |
507d977f | 748 | ret = eb_relocate_entry(vma, eb, r); |
1d83f442 | 749 | if (ret) |
31a39207 | 750 | goto out; |
1d83f442 | 751 | |
ebc0808f CW |
752 | if (r->presumed_offset != offset) { |
753 | pagefault_disable(); | |
754 | unwritten = __put_user(r->presumed_offset, | |
755 | &user_relocs->presumed_offset); | |
756 | pagefault_enable(); | |
757 | if (unlikely(unwritten)) { | |
758 | /* Note that reporting an error now | |
759 | * leaves everything in an inconsistent | |
760 | * state as we have *already* changed | |
761 | * the relocation value inside the | |
762 | * object. As we have not changed the | |
763 | * reloc.presumed_offset or will not | |
764 | * change the execobject.offset, on the | |
765 | * call we may not rewrite the value | |
766 | * inside the object, leaving it | |
767 | * dangling and causing a GPU hang. | |
768 | */ | |
769 | ret = -EFAULT; | |
770 | goto out; | |
771 | } | |
1d83f442 CW |
772 | } |
773 | ||
774 | user_relocs++; | |
775 | r++; | |
776 | } while (--count); | |
54cf91dc CW |
777 | } |
778 | ||
31a39207 | 779 | out: |
650bc635 | 780 | reloc_cache_reset(&eb->reloc_cache); |
31a39207 | 781 | return ret; |
1d83f442 | 782 | #undef N_RELOC |
54cf91dc CW |
783 | } |
784 | ||
785 | static int | |
650bc635 CW |
786 | eb_relocate_vma_slow(struct i915_vma *vma, |
787 | struct i915_execbuffer *eb, | |
788 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 789 | { |
27173f1f | 790 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
31a39207 | 791 | int i, ret = 0; |
54cf91dc CW |
792 | |
793 | for (i = 0; i < entry->relocation_count; i++) { | |
507d977f | 794 | ret = eb_relocate_entry(vma, eb, &relocs[i]); |
54cf91dc | 795 | if (ret) |
31a39207 | 796 | break; |
54cf91dc | 797 | } |
650bc635 | 798 | reloc_cache_reset(&eb->reloc_cache); |
31a39207 | 799 | return ret; |
54cf91dc CW |
800 | } |
801 | ||
650bc635 | 802 | static int eb_relocate(struct i915_execbuffer *eb) |
54cf91dc | 803 | { |
27173f1f | 804 | struct i915_vma *vma; |
d4aeee77 CW |
805 | int ret = 0; |
806 | ||
8c45cec4 | 807 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
650bc635 | 808 | ret = eb_relocate_vma(vma, eb); |
54cf91dc | 809 | if (ret) |
d4aeee77 | 810 | break; |
54cf91dc CW |
811 | } |
812 | ||
d4aeee77 | 813 | return ret; |
54cf91dc CW |
814 | } |
815 | ||
edf4427b CW |
816 | static bool only_mappable_for_reloc(unsigned int flags) |
817 | { | |
818 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
819 | __EXEC_OBJECT_NEEDS_MAP; | |
820 | } | |
821 | ||
1690e1eb | 822 | static int |
650bc635 CW |
823 | eb_reserve_vma(struct i915_vma *vma, |
824 | struct intel_engine_cs *engine, | |
825 | bool *need_reloc) | |
1690e1eb | 826 | { |
27173f1f | 827 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 828 | uint64_t flags; |
1690e1eb CW |
829 | int ret; |
830 | ||
0875546c | 831 | flags = PIN_USER; |
0229da32 DV |
832 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
833 | flags |= PIN_GLOBAL; | |
834 | ||
edf4427b | 835 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
836 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
837 | * limit address to the first 4GBs for unflagged objects. | |
838 | */ | |
839 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
840 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
841 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
842 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
843 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
844 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
845 | if (entry->flags & EXEC_OBJECT_PINNED) |
846 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
847 | if ((flags & PIN_MAPPABLE) == 0) |
848 | flags |= PIN_HIGH; | |
edf4427b | 849 | } |
1ec9e26d | 850 | |
59bfa124 CW |
851 | ret = i915_vma_pin(vma, |
852 | entry->pad_to_size, | |
853 | entry->alignment, | |
854 | flags); | |
855 | if ((ret == -ENOSPC || ret == -E2BIG) && | |
edf4427b | 856 | only_mappable_for_reloc(entry->flags)) |
59bfa124 CW |
857 | ret = i915_vma_pin(vma, |
858 | entry->pad_to_size, | |
859 | entry->alignment, | |
860 | flags & ~PIN_MAPPABLE); | |
1690e1eb CW |
861 | if (ret) |
862 | return ret; | |
863 | ||
7788a765 CW |
864 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
865 | ||
82b6b6d7 | 866 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
49ef5294 | 867 | ret = i915_vma_get_fence(vma); |
82b6b6d7 CW |
868 | if (ret) |
869 | return ret; | |
9a5a53b3 | 870 | |
49ef5294 | 871 | if (i915_vma_pin_fence(vma)) |
82b6b6d7 | 872 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
1690e1eb CW |
873 | } |
874 | ||
27173f1f BW |
875 | if (entry->offset != vma->node.start) { |
876 | entry->offset = vma->node.start; | |
ed5982e6 DV |
877 | *need_reloc = true; |
878 | } | |
879 | ||
1690e1eb | 880 | return 0; |
7788a765 | 881 | } |
1690e1eb | 882 | |
d23db88c | 883 | static bool |
e6a84468 | 884 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
885 | { |
886 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 887 | |
e6a84468 CW |
888 | if (entry->relocation_count == 0) |
889 | return false; | |
890 | ||
3272db53 | 891 | if (!i915_vma_is_ggtt(vma)) |
e6a84468 CW |
892 | return false; |
893 | ||
894 | /* See also use_cpu_reloc() */ | |
0031fb96 | 895 | if (HAS_LLC(to_i915(vma->obj->base.dev))) |
e6a84468 CW |
896 | return false; |
897 | ||
898 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
899 | return false; | |
900 | ||
901 | return true; | |
902 | } | |
903 | ||
904 | static bool | |
905 | eb_vma_misplaced(struct i915_vma *vma) | |
906 | { | |
907 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 908 | |
3272db53 CW |
909 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
910 | !i915_vma_is_ggtt(vma)); | |
d23db88c | 911 | |
f51455d4 | 912 | if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) |
d23db88c CW |
913 | return true; |
914 | ||
91b2db6f CW |
915 | if (vma->node.size < entry->pad_to_size) |
916 | return true; | |
917 | ||
506a8e87 CW |
918 | if (entry->flags & EXEC_OBJECT_PINNED && |
919 | vma->node.start != entry->offset) | |
920 | return true; | |
921 | ||
d23db88c CW |
922 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
923 | vma->node.start < BATCH_OFFSET_BIAS) | |
924 | return true; | |
925 | ||
edf4427b | 926 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
05a20d09 CW |
927 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
928 | !i915_vma_is_map_and_fenceable(vma)) | |
edf4427b CW |
929 | return !only_mappable_for_reloc(entry->flags); |
930 | ||
101b506a MT |
931 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
932 | (vma->node.start + vma->node.size - 1) >> 32) | |
933 | return true; | |
934 | ||
d23db88c CW |
935 | return false; |
936 | } | |
937 | ||
650bc635 | 938 | static int eb_reserve(struct i915_execbuffer *eb) |
54cf91dc | 939 | { |
650bc635 CW |
940 | const bool has_fenced_gpu_access = INTEL_GEN(eb->i915) < 4; |
941 | const bool needs_unfenced_map = INTEL_INFO(eb->i915)->unfenced_needs_alignment; | |
27173f1f BW |
942 | struct i915_vma *vma; |
943 | struct list_head ordered_vmas; | |
506a8e87 | 944 | struct list_head pinned_vmas; |
7788a765 | 945 | int retry; |
6fe4f140 | 946 | |
27173f1f | 947 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 948 | INIT_LIST_HEAD(&pinned_vmas); |
650bc635 | 949 | while (!list_empty(&eb->vmas)) { |
6fe4f140 CW |
950 | struct drm_i915_gem_exec_object2 *entry; |
951 | bool need_fence, need_mappable; | |
952 | ||
8c45cec4 | 953 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_link); |
27173f1f | 954 | entry = vma->exec_entry; |
6fe4f140 | 955 | |
650bc635 | 956 | if (eb->ctx->flags & CONTEXT_NO_ZEROMAP) |
b1b38278 DW |
957 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; |
958 | ||
82b6b6d7 CW |
959 | if (!has_fenced_gpu_access) |
960 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 961 | need_fence = |
f4ce766f CW |
962 | (entry->flags & EXEC_OBJECT_NEEDS_FENCE || |
963 | needs_unfenced_map) && | |
4ff4b44c | 964 | i915_gem_object_is_tiled(vma->obj); |
27173f1f | 965 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 966 | |
506a8e87 | 967 | if (entry->flags & EXEC_OBJECT_PINNED) |
8c45cec4 | 968 | list_move_tail(&vma->exec_link, &pinned_vmas); |
506a8e87 | 969 | else if (need_mappable) { |
e6a84468 | 970 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
8c45cec4 | 971 | list_move(&vma->exec_link, &ordered_vmas); |
e6a84468 | 972 | } else |
8c45cec4 | 973 | list_move_tail(&vma->exec_link, &ordered_vmas); |
6fe4f140 | 974 | } |
650bc635 CW |
975 | list_splice(&ordered_vmas, &eb->vmas); |
976 | list_splice(&pinned_vmas, &eb->vmas); | |
54cf91dc CW |
977 | |
978 | /* Attempt to pin all of the buffers into the GTT. | |
979 | * This is done in 3 phases: | |
980 | * | |
981 | * 1a. Unbind all objects that do not match the GTT constraints for | |
982 | * the execbuffer (fenceable, mappable, alignment etc). | |
983 | * 1b. Increment pin count for already bound objects. | |
984 | * 2. Bind new objects. | |
985 | * 3. Decrement pin count. | |
986 | * | |
7788a765 | 987 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
988 | * room for the earlier objects *unless* we need to defragment. |
989 | */ | |
990 | retry = 0; | |
991 | do { | |
7788a765 | 992 | int ret = 0; |
54cf91dc CW |
993 | |
994 | /* Unbind any ill-fitting objects or pin. */ | |
8c45cec4 | 995 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
27173f1f | 996 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
997 | continue; |
998 | ||
e6a84468 | 999 | if (eb_vma_misplaced(vma)) |
27173f1f | 1000 | ret = i915_vma_unbind(vma); |
54cf91dc | 1001 | else |
650bc635 | 1002 | ret = eb_reserve_vma(vma, eb->engine, &eb->need_relocs); |
432e58ed | 1003 | if (ret) |
54cf91dc | 1004 | goto err; |
54cf91dc CW |
1005 | } |
1006 | ||
1007 | /* Bind fresh objects */ | |
8c45cec4 | 1008 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
27173f1f | 1009 | if (drm_mm_node_allocated(&vma->node)) |
1690e1eb | 1010 | continue; |
54cf91dc | 1011 | |
650bc635 | 1012 | ret = eb_reserve_vma(vma, eb->engine, &eb->need_relocs); |
7788a765 CW |
1013 | if (ret) |
1014 | goto err; | |
54cf91dc CW |
1015 | } |
1016 | ||
a415d355 | 1017 | err: |
6c085a72 | 1018 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
1019 | return ret; |
1020 | ||
a415d355 | 1021 | /* Decrement pin count for bound objects */ |
8c45cec4 | 1022 | list_for_each_entry(vma, &eb->vmas, exec_link) |
650bc635 | 1023 | eb_unreserve_vma(vma); |
a415d355 | 1024 | |
650bc635 | 1025 | ret = i915_gem_evict_vm(eb->vm, true); |
54cf91dc CW |
1026 | if (ret) |
1027 | return ret; | |
54cf91dc CW |
1028 | } while (1); |
1029 | } | |
1030 | ||
1031 | static int | |
650bc635 | 1032 | eb_relocate_slow(struct i915_execbuffer *eb) |
54cf91dc | 1033 | { |
650bc635 CW |
1034 | const unsigned int count = eb->args->buffer_count; |
1035 | struct drm_device *dev = &eb->i915->drm; | |
54cf91dc | 1036 | struct drm_i915_gem_relocation_entry *reloc; |
27173f1f | 1037 | struct i915_vma *vma; |
dd6864a4 | 1038 | int *reloc_offset; |
54cf91dc | 1039 | int i, total, ret; |
27173f1f | 1040 | |
67731b87 | 1041 | /* We may process another execbuffer during the unlock... */ |
d55495b4 | 1042 | eb_reset(eb); |
54cf91dc CW |
1043 | mutex_unlock(&dev->struct_mutex); |
1044 | ||
1045 | total = 0; | |
1046 | for (i = 0; i < count; i++) | |
650bc635 | 1047 | total += eb->exec[i].relocation_count; |
54cf91dc | 1048 | |
2098105e MH |
1049 | reloc_offset = kvmalloc_array(count, sizeof(*reloc_offset), GFP_KERNEL); |
1050 | reloc = kvmalloc_array(total, sizeof(*reloc), GFP_KERNEL); | |
dd6864a4 | 1051 | if (reloc == NULL || reloc_offset == NULL) { |
2098105e MH |
1052 | kvfree(reloc); |
1053 | kvfree(reloc_offset); | |
54cf91dc CW |
1054 | mutex_lock(&dev->struct_mutex); |
1055 | return -ENOMEM; | |
1056 | } | |
1057 | ||
1058 | total = 0; | |
1059 | for (i = 0; i < count; i++) { | |
1060 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
1061 | u64 invalid_offset = (u64)-1; |
1062 | int j; | |
54cf91dc | 1063 | |
650bc635 | 1064 | user_relocs = u64_to_user_ptr(eb->exec[i].relocs_ptr); |
54cf91dc CW |
1065 | |
1066 | if (copy_from_user(reloc+total, user_relocs, | |
650bc635 | 1067 | eb->exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
1068 | ret = -EFAULT; |
1069 | mutex_lock(&dev->struct_mutex); | |
1070 | goto err; | |
1071 | } | |
1072 | ||
262b6d36 CW |
1073 | /* As we do not update the known relocation offsets after |
1074 | * relocating (due to the complexities in lock handling), | |
1075 | * we need to mark them as invalid now so that we force the | |
1076 | * relocation processing next time. Just in case the target | |
1077 | * object is evicted and then rebound into its old | |
1078 | * presumed_offset before the next execbuffer - if that | |
1079 | * happened we would make the mistake of assuming that the | |
1080 | * relocations were valid. | |
1081 | */ | |
650bc635 | 1082 | for (j = 0; j < eb->exec[i].relocation_count; j++) { |
9aab8bff CW |
1083 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
1084 | &invalid_offset, | |
1085 | sizeof(invalid_offset))) { | |
262b6d36 CW |
1086 | ret = -EFAULT; |
1087 | mutex_lock(&dev->struct_mutex); | |
1088 | goto err; | |
1089 | } | |
1090 | } | |
1091 | ||
dd6864a4 | 1092 | reloc_offset[i] = total; |
650bc635 | 1093 | total += eb->exec[i].relocation_count; |
54cf91dc CW |
1094 | } |
1095 | ||
1096 | ret = i915_mutex_lock_interruptible(dev); | |
1097 | if (ret) { | |
1098 | mutex_lock(&dev->struct_mutex); | |
1099 | goto err; | |
1100 | } | |
1101 | ||
67731b87 | 1102 | /* reacquire the objects */ |
650bc635 | 1103 | ret = eb_lookup_vmas(eb); |
3b96eff4 CW |
1104 | if (ret) |
1105 | goto err; | |
67731b87 | 1106 | |
650bc635 | 1107 | ret = eb_reserve(eb); |
54cf91dc CW |
1108 | if (ret) |
1109 | goto err; | |
1110 | ||
8c45cec4 | 1111 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
650bc635 CW |
1112 | int idx = vma->exec_entry - eb->exec; |
1113 | ||
1114 | ret = eb_relocate_vma_slow(vma, eb, reloc + reloc_offset[idx]); | |
54cf91dc CW |
1115 | if (ret) |
1116 | goto err; | |
54cf91dc CW |
1117 | } |
1118 | ||
1119 | /* Leave the user relocations as are, this is the painfully slow path, | |
1120 | * and we want to avoid the complication of dropping the lock whilst | |
1121 | * having buffers reserved in the aperture and so causing spurious | |
1122 | * ENOSPC for random operations. | |
1123 | */ | |
1124 | ||
1125 | err: | |
2098105e MH |
1126 | kvfree(reloc); |
1127 | kvfree(reloc_offset); | |
54cf91dc CW |
1128 | return ret; |
1129 | } | |
1130 | ||
54cf91dc | 1131 | static int |
650bc635 | 1132 | eb_move_to_gpu(struct i915_execbuffer *eb) |
54cf91dc | 1133 | { |
27173f1f | 1134 | struct i915_vma *vma; |
432e58ed | 1135 | int ret; |
54cf91dc | 1136 | |
8c45cec4 | 1137 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
27173f1f | 1138 | struct drm_i915_gem_object *obj = vma->obj; |
03ade511 | 1139 | |
b0fd47ad CW |
1140 | if (vma->exec_entry->flags & EXEC_OBJECT_CAPTURE) { |
1141 | struct i915_gem_capture_list *capture; | |
1142 | ||
1143 | capture = kmalloc(sizeof(*capture), GFP_KERNEL); | |
1144 | if (unlikely(!capture)) | |
1145 | return -ENOMEM; | |
1146 | ||
650bc635 | 1147 | capture->next = eb->request->capture_list; |
b0fd47ad | 1148 | capture->vma = vma; |
650bc635 | 1149 | eb->request->capture_list = capture; |
b0fd47ad CW |
1150 | } |
1151 | ||
77ae9957 CW |
1152 | if (vma->exec_entry->flags & EXEC_OBJECT_ASYNC) |
1153 | continue; | |
1154 | ||
7fc92e96 | 1155 | if (unlikely(obj->cache_dirty && !obj->cache_coherent)) |
57822dc6 | 1156 | i915_gem_clflush_object(obj, 0); |
57822dc6 | 1157 | |
d07f0e59 | 1158 | ret = i915_gem_request_await_object |
507d977f | 1159 | (eb->request, obj, vma->exec_entry->flags & EXEC_OBJECT_WRITE); |
d07f0e59 CW |
1160 | if (ret) |
1161 | return ret; | |
c59a333f CW |
1162 | } |
1163 | ||
dcd79934 | 1164 | /* Unconditionally flush any chipset caches (for streaming writes). */ |
650bc635 | 1165 | i915_gem_chipset_flush(eb->i915); |
6ac42f41 | 1166 | |
c7fe7d25 | 1167 | /* Unconditionally invalidate GPU caches and TLBs. */ |
650bc635 | 1168 | return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE); |
54cf91dc CW |
1169 | } |
1170 | ||
432e58ed CW |
1171 | static bool |
1172 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 1173 | { |
650bc635 | 1174 | if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS) |
ed5982e6 DV |
1175 | return false; |
1176 | ||
2f5945bc CW |
1177 | /* Kernel clipping was a DRI1 misfeature */ |
1178 | if (exec->num_cliprects || exec->cliprects_ptr) | |
1179 | return false; | |
1180 | ||
1181 | if (exec->DR4 == 0xffffffff) { | |
1182 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1183 | exec->DR4 = 0; | |
1184 | } | |
1185 | if (exec->DR1 || exec->DR4) | |
1186 | return false; | |
1187 | ||
1188 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
1189 | return false; | |
1190 | ||
1191 | return true; | |
54cf91dc CW |
1192 | } |
1193 | ||
1194 | static int | |
ad19f10b CW |
1195 | validate_exec_list(struct drm_device *dev, |
1196 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
1197 | int count) |
1198 | { | |
b205ca57 DV |
1199 | unsigned relocs_total = 0; |
1200 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
1201 | unsigned invalid_flags; |
1202 | int i; | |
1203 | ||
9e2793f6 DG |
1204 | /* INTERNAL flags must not overlap with external ones */ |
1205 | BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS); | |
1206 | ||
ad19f10b CW |
1207 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; |
1208 | if (USES_FULL_PPGTT(dev)) | |
1209 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
1210 | |
1211 | for (i = 0; i < count; i++) { | |
3ed605bc | 1212 | char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1213 | int length; /* limited by fault_in_pages_readable() */ |
1214 | ||
ad19f10b | 1215 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
1216 | return -EINVAL; |
1217 | ||
934acce3 MW |
1218 | /* Offset can be used as input (EXEC_OBJECT_PINNED), reject |
1219 | * any non-page-aligned or non-canonical addresses. | |
1220 | */ | |
1221 | if (exec[i].flags & EXEC_OBJECT_PINNED) { | |
1222 | if (exec[i].offset != | |
1223 | gen8_canonical_addr(exec[i].offset & PAGE_MASK)) | |
1224 | return -EINVAL; | |
934acce3 MW |
1225 | } |
1226 | ||
038c95a3 MW |
1227 | /* From drm_mm perspective address space is continuous, |
1228 | * so from this point we're always using non-canonical | |
1229 | * form internally. | |
1230 | */ | |
1231 | exec[i].offset = gen8_noncanonical_addr(exec[i].offset); | |
1232 | ||
55a9785d CW |
1233 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
1234 | return -EINVAL; | |
1235 | ||
91b2db6f CW |
1236 | /* pad_to_size was once a reserved field, so sanitize it */ |
1237 | if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) { | |
1238 | if (offset_in_page(exec[i].pad_to_size)) | |
1239 | return -EINVAL; | |
1240 | } else { | |
1241 | exec[i].pad_to_size = 0; | |
1242 | } | |
1243 | ||
3118a4f6 KC |
1244 | /* First check for malicious input causing overflow in |
1245 | * the worst case where we need to allocate the entire | |
1246 | * relocation tree as a single array. | |
1247 | */ | |
1248 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1249 | return -EINVAL; |
3118a4f6 | 1250 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1251 | |
1252 | length = exec[i].relocation_count * | |
1253 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1254 | /* |
1255 | * We must check that the entire relocation array is safe | |
1256 | * to read, but since we may need to update the presumed | |
1257 | * offsets during execution, check for full write access. | |
1258 | */ | |
54cf91dc CW |
1259 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1260 | return -EFAULT; | |
1261 | ||
d330a953 | 1262 | if (likely(!i915.prefault_disable)) { |
4bce9f6e | 1263 | if (fault_in_pages_readable(ptr, length)) |
0b74b508 XZ |
1264 | return -EFAULT; |
1265 | } | |
54cf91dc CW |
1266 | } |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
650bc635 | 1271 | static int eb_select_context(struct i915_execbuffer *eb) |
d299cce7 | 1272 | { |
650bc635 | 1273 | unsigned int ctx_id = i915_execbuffer2_get_context_id(*eb->args); |
f7978a0c | 1274 | struct i915_gem_context *ctx; |
d299cce7 | 1275 | |
650bc635 CW |
1276 | ctx = i915_gem_context_lookup(eb->file->driver_priv, ctx_id); |
1277 | if (unlikely(IS_ERR(ctx))) | |
1278 | return PTR_ERR(ctx); | |
d299cce7 | 1279 | |
650bc635 | 1280 | if (unlikely(i915_gem_context_is_banned(ctx))) { |
d299cce7 | 1281 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); |
650bc635 | 1282 | return -EIO; |
d299cce7 MK |
1283 | } |
1284 | ||
650bc635 CW |
1285 | eb->ctx = i915_gem_context_get(ctx); |
1286 | eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base; | |
1287 | ||
1288 | return 0; | |
d299cce7 MK |
1289 | } |
1290 | ||
5cf3d280 CW |
1291 | void i915_vma_move_to_active(struct i915_vma *vma, |
1292 | struct drm_i915_gem_request *req, | |
1293 | unsigned int flags) | |
1294 | { | |
1295 | struct drm_i915_gem_object *obj = vma->obj; | |
1296 | const unsigned int idx = req->engine->id; | |
1297 | ||
81147b07 | 1298 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5cf3d280 CW |
1299 | GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); |
1300 | ||
b0decaf7 CW |
1301 | /* Add a reference if we're newly entering the active list. |
1302 | * The order in which we add operations to the retirement queue is | |
1303 | * vital here: mark_active adds to the start of the callback list, | |
1304 | * such that subsequent callbacks are called first. Therefore we | |
1305 | * add the active reference first and queue for it to be dropped | |
1306 | * *last*. | |
1307 | */ | |
d07f0e59 CW |
1308 | if (!i915_vma_is_active(vma)) |
1309 | obj->active_count++; | |
1310 | i915_vma_set_active(vma, idx); | |
1311 | i915_gem_active_set(&vma->last_read[idx], req); | |
1312 | list_move_tail(&vma->vm_link, &vma->vm->active_list); | |
5cf3d280 | 1313 | |
e27ab73d | 1314 | obj->base.write_domain = 0; |
5cf3d280 | 1315 | if (flags & EXEC_OBJECT_WRITE) { |
e27ab73d CW |
1316 | obj->base.write_domain = I915_GEM_DOMAIN_RENDER; |
1317 | ||
5b8c8aec CW |
1318 | if (intel_fb_obj_invalidate(obj, ORIGIN_CS)) |
1319 | i915_gem_active_set(&obj->frontbuffer_write, req); | |
5cf3d280 | 1320 | |
e27ab73d | 1321 | obj->base.read_domains = 0; |
5cf3d280 | 1322 | } |
e27ab73d | 1323 | obj->base.read_domains |= I915_GEM_GPU_DOMAINS; |
5cf3d280 | 1324 | |
49ef5294 CW |
1325 | if (flags & EXEC_OBJECT_NEEDS_FENCE) |
1326 | i915_gem_active_set(&vma->last_fence, req); | |
5cf3d280 CW |
1327 | } |
1328 | ||
ad778f89 CW |
1329 | static void eb_export_fence(struct drm_i915_gem_object *obj, |
1330 | struct drm_i915_gem_request *req, | |
1331 | unsigned int flags) | |
1332 | { | |
d07f0e59 | 1333 | struct reservation_object *resv = obj->resv; |
ad778f89 CW |
1334 | |
1335 | /* Ignore errors from failing to allocate the new fence, we can't | |
1336 | * handle an error right now. Worst case should be missed | |
1337 | * synchronisation leading to rendering corruption. | |
1338 | */ | |
e2989f14 | 1339 | reservation_object_lock(resv, NULL); |
ad778f89 CW |
1340 | if (flags & EXEC_OBJECT_WRITE) |
1341 | reservation_object_add_excl_fence(resv, &req->fence); | |
1342 | else if (reservation_object_reserve_shared(resv) == 0) | |
1343 | reservation_object_add_shared_fence(resv, &req->fence); | |
e2989f14 | 1344 | reservation_object_unlock(resv); |
ad778f89 CW |
1345 | } |
1346 | ||
5b043f4e | 1347 | static void |
650bc635 | 1348 | eb_move_to_active(struct i915_execbuffer *eb) |
432e58ed | 1349 | { |
27173f1f | 1350 | struct i915_vma *vma; |
432e58ed | 1351 | |
8c45cec4 | 1352 | list_for_each_entry(vma, &eb->vmas, exec_link) { |
27173f1f | 1353 | struct drm_i915_gem_object *obj = vma->obj; |
db53a302 | 1354 | |
507d977f CW |
1355 | obj->base.write_domain = 0; |
1356 | if (vma->exec_entry->flags & EXEC_OBJECT_WRITE) | |
1357 | obj->base.read_domains = 0; | |
1358 | obj->base.read_domains |= I915_GEM_GPU_DOMAINS; | |
432e58ed | 1359 | |
650bc635 CW |
1360 | i915_vma_move_to_active(vma, eb->request, vma->exec_entry->flags); |
1361 | eb_export_fence(obj, eb->request, vma->exec_entry->flags); | |
432e58ed CW |
1362 | } |
1363 | } | |
1364 | ||
ae662d31 | 1365 | static int |
b5321f30 | 1366 | i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req) |
ae662d31 | 1367 | { |
73dec95e TU |
1368 | u32 *cs; |
1369 | int i; | |
ae662d31 | 1370 | |
b5321f30 | 1371 | if (!IS_GEN7(req->i915) || req->engine->id != RCS) { |
9d662da8 DV |
1372 | DRM_DEBUG("sol reset is gen7/rcs only\n"); |
1373 | return -EINVAL; | |
1374 | } | |
ae662d31 | 1375 | |
73dec95e TU |
1376 | cs = intel_ring_begin(req, 4 * 3); |
1377 | if (IS_ERR(cs)) | |
1378 | return PTR_ERR(cs); | |
ae662d31 EA |
1379 | |
1380 | for (i = 0; i < 4; i++) { | |
73dec95e TU |
1381 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
1382 | *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); | |
1383 | *cs++ = 0; | |
ae662d31 EA |
1384 | } |
1385 | ||
73dec95e | 1386 | intel_ring_advance(req, cs); |
ae662d31 EA |
1387 | |
1388 | return 0; | |
1389 | } | |
1390 | ||
650bc635 | 1391 | static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master) |
71745376 | 1392 | { |
71745376 | 1393 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1394 | struct i915_vma *vma; |
71745376 BV |
1395 | int ret; |
1396 | ||
650bc635 CW |
1397 | shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, |
1398 | PAGE_ALIGN(eb->batch_len)); | |
71745376 | 1399 | if (IS_ERR(shadow_batch_obj)) |
59bfa124 | 1400 | return ERR_CAST(shadow_batch_obj); |
71745376 | 1401 | |
650bc635 CW |
1402 | ret = intel_engine_cmd_parser(eb->engine, |
1403 | eb->batch->obj, | |
33a051a5 | 1404 | shadow_batch_obj, |
650bc635 CW |
1405 | eb->batch_start_offset, |
1406 | eb->batch_len, | |
33a051a5 | 1407 | is_master); |
058d88c4 CW |
1408 | if (ret) { |
1409 | if (ret == -EACCES) /* unhandled chained batch */ | |
1410 | vma = NULL; | |
1411 | else | |
1412 | vma = ERR_PTR(ret); | |
1413 | goto out; | |
1414 | } | |
71745376 | 1415 | |
058d88c4 CW |
1416 | vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0); |
1417 | if (IS_ERR(vma)) | |
1418 | goto out; | |
de4e783a | 1419 | |
650bc635 CW |
1420 | vma->exec_entry = |
1421 | memset(&eb->shadow_exec_entry, 0, sizeof(*vma->exec_entry)); | |
de4e783a | 1422 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
25dc556a | 1423 | i915_gem_object_get(shadow_batch_obj); |
8c45cec4 | 1424 | list_add_tail(&vma->exec_link, &eb->vmas); |
71745376 | 1425 | |
058d88c4 | 1426 | out: |
de4e783a | 1427 | i915_gem_object_unpin_pages(shadow_batch_obj); |
058d88c4 | 1428 | return vma; |
71745376 | 1429 | } |
5c6c6003 | 1430 | |
c8659efa CW |
1431 | static void |
1432 | add_to_client(struct drm_i915_gem_request *req, | |
1433 | struct drm_file *file) | |
1434 | { | |
1435 | req->file_priv = file->driver_priv; | |
1436 | list_add_tail(&req->client_link, &req->file_priv->mm.request_list); | |
1437 | } | |
1438 | ||
5b043f4e | 1439 | static int |
650bc635 | 1440 | execbuf_submit(struct i915_execbuffer *eb) |
78382593 | 1441 | { |
2f5945bc | 1442 | int ret; |
78382593 | 1443 | |
650bc635 | 1444 | ret = eb_move_to_gpu(eb); |
78382593 | 1445 | if (ret) |
2f5945bc | 1446 | return ret; |
78382593 | 1447 | |
650bc635 | 1448 | ret = i915_switch_context(eb->request); |
78382593 | 1449 | if (ret) |
2f5945bc | 1450 | return ret; |
78382593 | 1451 | |
650bc635 CW |
1452 | if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1453 | ret = i915_reset_gen7_sol_offsets(eb->request); | |
78382593 | 1454 | if (ret) |
2f5945bc | 1455 | return ret; |
78382593 OM |
1456 | } |
1457 | ||
650bc635 CW |
1458 | ret = eb->engine->emit_bb_start(eb->request, |
1459 | eb->batch->node.start + | |
1460 | eb->batch_start_offset, | |
1461 | eb->batch_len, | |
1462 | eb->dispatch_flags); | |
2f5945bc CW |
1463 | if (ret) |
1464 | return ret; | |
78382593 | 1465 | |
650bc635 | 1466 | eb_move_to_active(eb); |
78382593 | 1467 | |
2f5945bc | 1468 | return 0; |
78382593 OM |
1469 | } |
1470 | ||
a8ebba75 ZY |
1471 | /** |
1472 | * Find one BSD ring to dispatch the corresponding BSD command. | |
c80ff16e | 1473 | * The engine index is returned. |
a8ebba75 | 1474 | */ |
de1add36 | 1475 | static unsigned int |
c80ff16e CW |
1476 | gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, |
1477 | struct drm_file *file) | |
a8ebba75 | 1478 | { |
a8ebba75 ZY |
1479 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1480 | ||
de1add36 | 1481 | /* Check whether the file_priv has already selected one ring. */ |
6f633402 JL |
1482 | if ((int)file_priv->bsd_engine < 0) |
1483 | file_priv->bsd_engine = atomic_fetch_xor(1, | |
1484 | &dev_priv->mm.bsd_engine_dispatch_index); | |
d23db88c | 1485 | |
c80ff16e | 1486 | return file_priv->bsd_engine; |
d23db88c CW |
1487 | } |
1488 | ||
de1add36 TU |
1489 | #define I915_USER_RINGS (4) |
1490 | ||
117897f4 | 1491 | static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { |
de1add36 TU |
1492 | [I915_EXEC_DEFAULT] = RCS, |
1493 | [I915_EXEC_RENDER] = RCS, | |
1494 | [I915_EXEC_BLT] = BCS, | |
1495 | [I915_EXEC_BSD] = VCS, | |
1496 | [I915_EXEC_VEBOX] = VECS | |
1497 | }; | |
1498 | ||
f8ca0c07 DG |
1499 | static struct intel_engine_cs * |
1500 | eb_select_engine(struct drm_i915_private *dev_priv, | |
1501 | struct drm_file *file, | |
1502 | struct drm_i915_gem_execbuffer2 *args) | |
de1add36 TU |
1503 | { |
1504 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
f8ca0c07 | 1505 | struct intel_engine_cs *engine; |
de1add36 TU |
1506 | |
1507 | if (user_ring_id > I915_USER_RINGS) { | |
1508 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
f8ca0c07 | 1509 | return NULL; |
de1add36 TU |
1510 | } |
1511 | ||
1512 | if ((user_ring_id != I915_EXEC_BSD) && | |
1513 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1514 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1515 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
f8ca0c07 | 1516 | return NULL; |
de1add36 TU |
1517 | } |
1518 | ||
1519 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
1520 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
1521 | ||
1522 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
c80ff16e | 1523 | bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file); |
de1add36 TU |
1524 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && |
1525 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 1526 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
1527 | bsd_idx--; |
1528 | } else { | |
1529 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
1530 | bsd_idx); | |
f8ca0c07 | 1531 | return NULL; |
de1add36 TU |
1532 | } |
1533 | ||
3b3f1650 | 1534 | engine = dev_priv->engine[_VCS(bsd_idx)]; |
de1add36 | 1535 | } else { |
3b3f1650 | 1536 | engine = dev_priv->engine[user_ring_map[user_ring_id]]; |
de1add36 TU |
1537 | } |
1538 | ||
3b3f1650 | 1539 | if (!engine) { |
de1add36 | 1540 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); |
f8ca0c07 | 1541 | return NULL; |
de1add36 TU |
1542 | } |
1543 | ||
f8ca0c07 | 1544 | return engine; |
de1add36 TU |
1545 | } |
1546 | ||
54cf91dc | 1547 | static int |
650bc635 | 1548 | i915_gem_do_execbuffer(struct drm_device *dev, |
54cf91dc CW |
1549 | struct drm_file *file, |
1550 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1551 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1552 | { |
650bc635 | 1553 | struct i915_execbuffer eb; |
fec0445c CW |
1554 | struct dma_fence *in_fence = NULL; |
1555 | struct sync_file *out_fence = NULL; | |
1556 | int out_fence_fd = -1; | |
78382593 | 1557 | int ret; |
54cf91dc | 1558 | |
ed5982e6 | 1559 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1560 | return -EINVAL; |
432e58ed | 1561 | |
ad19f10b | 1562 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1563 | if (ret) |
1564 | return ret; | |
1565 | ||
650bc635 CW |
1566 | eb.i915 = to_i915(dev); |
1567 | eb.file = file; | |
1568 | eb.args = args; | |
1569 | eb.exec = exec; | |
1570 | eb.need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; | |
1571 | reloc_cache_init(&eb.reloc_cache, eb.i915); | |
1572 | ||
1573 | eb.batch_start_offset = args->batch_start_offset; | |
1574 | eb.batch_len = args->batch_len; | |
1575 | ||
1576 | eb.dispatch_flags = 0; | |
d7d4eedd | 1577 | if (args->flags & I915_EXEC_SECURE) { |
b3ac9f25 | 1578 | if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) |
d7d4eedd CW |
1579 | return -EPERM; |
1580 | ||
650bc635 | 1581 | eb.dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1582 | } |
b45305fc | 1583 | if (args->flags & I915_EXEC_IS_PINNED) |
650bc635 | 1584 | eb.dispatch_flags |= I915_DISPATCH_PINNED; |
54cf91dc | 1585 | |
650bc635 CW |
1586 | eb.engine = eb_select_engine(eb.i915, file, args); |
1587 | if (!eb.engine) | |
54cf91dc | 1588 | return -EINVAL; |
54cf91dc | 1589 | |
a9ed33ca | 1590 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
650bc635 | 1591 | if (!HAS_RESOURCE_STREAMER(eb.i915)) { |
a9ed33ca AJ |
1592 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); |
1593 | return -EINVAL; | |
1594 | } | |
650bc635 | 1595 | if (eb.engine->id != RCS) { |
a9ed33ca | 1596 | DRM_DEBUG("RS is not available on %s\n", |
650bc635 | 1597 | eb.engine->name); |
a9ed33ca AJ |
1598 | return -EINVAL; |
1599 | } | |
1600 | ||
650bc635 | 1601 | eb.dispatch_flags |= I915_DISPATCH_RS; |
a9ed33ca AJ |
1602 | } |
1603 | ||
fec0445c CW |
1604 | if (args->flags & I915_EXEC_FENCE_IN) { |
1605 | in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); | |
4a04e371 DCS |
1606 | if (!in_fence) |
1607 | return -EINVAL; | |
fec0445c CW |
1608 | } |
1609 | ||
1610 | if (args->flags & I915_EXEC_FENCE_OUT) { | |
1611 | out_fence_fd = get_unused_fd_flags(O_CLOEXEC); | |
1612 | if (out_fence_fd < 0) { | |
1613 | ret = out_fence_fd; | |
4a04e371 | 1614 | goto err_in_fence; |
fec0445c CW |
1615 | } |
1616 | } | |
1617 | ||
67d97da3 CW |
1618 | /* Take a local wakeref for preparing to dispatch the execbuf as |
1619 | * we expect to access the hardware fairly frequently in the | |
1620 | * process. Upon first dispatch, we acquire another prolonged | |
1621 | * wakeref that we hold until the GPU has been idle for at least | |
1622 | * 100ms. | |
1623 | */ | |
650bc635 | 1624 | intel_runtime_pm_get(eb.i915); |
f65c9168 | 1625 | |
54cf91dc CW |
1626 | ret = i915_mutex_lock_interruptible(dev); |
1627 | if (ret) | |
1628 | goto pre_mutex_err; | |
1629 | ||
650bc635 CW |
1630 | ret = eb_select_context(&eb); |
1631 | if (ret) { | |
d299cce7 MK |
1632 | mutex_unlock(&dev->struct_mutex); |
1633 | goto pre_mutex_err; | |
935f38d6 | 1634 | } |
41bde553 | 1635 | |
650bc635 CW |
1636 | if (eb_create(&eb)) { |
1637 | i915_gem_context_put(eb.ctx); | |
67731b87 CW |
1638 | mutex_unlock(&dev->struct_mutex); |
1639 | ret = -ENOMEM; | |
1640 | goto pre_mutex_err; | |
1641 | } | |
1642 | ||
54cf91dc | 1643 | /* Look up object handles */ |
650bc635 | 1644 | ret = eb_lookup_vmas(&eb); |
3b96eff4 CW |
1645 | if (ret) |
1646 | goto err; | |
54cf91dc | 1647 | |
6fe4f140 | 1648 | /* take note of the batch buffer before we might reorder the lists */ |
650bc635 | 1649 | eb.batch = eb_get_batch(&eb); |
6fe4f140 | 1650 | |
54cf91dc | 1651 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
650bc635 | 1652 | ret = eb_reserve(&eb); |
54cf91dc CW |
1653 | if (ret) |
1654 | goto err; | |
1655 | ||
1656 | /* The objects are in their final locations, apply the relocations. */ | |
650bc635 CW |
1657 | if (eb.need_relocs) |
1658 | ret = eb_relocate(&eb); | |
54cf91dc CW |
1659 | if (ret) { |
1660 | if (ret == -EFAULT) { | |
650bc635 | 1661 | ret = eb_relocate_slow(&eb); |
54cf91dc CW |
1662 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1663 | } | |
1664 | if (ret) | |
1665 | goto err; | |
1666 | } | |
1667 | ||
507d977f | 1668 | if (eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE) { |
ff240199 | 1669 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1670 | ret = -EINVAL; |
1671 | goto err; | |
1672 | } | |
650bc635 CW |
1673 | if (eb.batch_start_offset > eb.batch->size || |
1674 | eb.batch_len > eb.batch->size - eb.batch_start_offset) { | |
0b537272 CW |
1675 | DRM_DEBUG("Attempting to use out-of-bounds batch\n"); |
1676 | ret = -EINVAL; | |
1677 | goto err; | |
1678 | } | |
54cf91dc | 1679 | |
650bc635 | 1680 | if (eb.engine->needs_cmd_parser && eb.batch_len) { |
59bfa124 CW |
1681 | struct i915_vma *vma; |
1682 | ||
650bc635 | 1683 | vma = eb_parse(&eb, drm_is_current_master(file)); |
59bfa124 CW |
1684 | if (IS_ERR(vma)) { |
1685 | ret = PTR_ERR(vma); | |
78a42377 BV |
1686 | goto err; |
1687 | } | |
17cabf57 | 1688 | |
59bfa124 | 1689 | if (vma) { |
c7c7372e RP |
1690 | /* |
1691 | * Batch parsed and accepted: | |
1692 | * | |
1693 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1694 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1695 | * the dispatch_execbuffer implementations. We | |
1696 | * specifically don't want that set on batches the | |
1697 | * command parser has accepted. | |
1698 | */ | |
650bc635 CW |
1699 | eb.dispatch_flags |= I915_DISPATCH_SECURE; |
1700 | eb.batch_start_offset = 0; | |
1701 | eb.batch = vma; | |
c7c7372e | 1702 | } |
351e3db2 BV |
1703 | } |
1704 | ||
650bc635 CW |
1705 | if (eb.batch_len == 0) |
1706 | eb.batch_len = eb.batch->size - eb.batch_start_offset; | |
78a42377 | 1707 | |
d7d4eedd CW |
1708 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1709 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1710 | * hsw should have this fixed, but bdw mucks it up again. */ |
650bc635 CW |
1711 | if (eb.dispatch_flags & I915_DISPATCH_SECURE) { |
1712 | struct drm_i915_gem_object *obj = eb.batch->obj; | |
058d88c4 | 1713 | struct i915_vma *vma; |
59bfa124 | 1714 | |
da51a1e7 DV |
1715 | /* |
1716 | * So on first glance it looks freaky that we pin the batch here | |
1717 | * outside of the reservation loop. But: | |
1718 | * - The batch is already pinned into the relevant ppgtt, so we | |
1719 | * already have the backing storage fully allocated. | |
1720 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1721 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1722 | * fitting due to fragmentation. |
1723 | * So this is actually safe. | |
1724 | */ | |
058d88c4 CW |
1725 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); |
1726 | if (IS_ERR(vma)) { | |
1727 | ret = PTR_ERR(vma); | |
da51a1e7 | 1728 | goto err; |
058d88c4 | 1729 | } |
d7d4eedd | 1730 | |
650bc635 | 1731 | eb.batch = vma; |
59bfa124 | 1732 | } |
d7d4eedd | 1733 | |
0c8dac88 | 1734 | /* Allocate a request for this batch buffer nice and early. */ |
650bc635 CW |
1735 | eb.request = i915_gem_request_alloc(eb.engine, eb.ctx); |
1736 | if (IS_ERR(eb.request)) { | |
1737 | ret = PTR_ERR(eb.request); | |
0c8dac88 | 1738 | goto err_batch_unpin; |
26827088 | 1739 | } |
0c8dac88 | 1740 | |
fec0445c | 1741 | if (in_fence) { |
650bc635 | 1742 | ret = i915_gem_request_await_dma_fence(eb.request, in_fence); |
fec0445c CW |
1743 | if (ret < 0) |
1744 | goto err_request; | |
1745 | } | |
1746 | ||
1747 | if (out_fence_fd != -1) { | |
650bc635 | 1748 | out_fence = sync_file_create(&eb.request->fence); |
fec0445c CW |
1749 | if (!out_fence) { |
1750 | ret = -ENOMEM; | |
1751 | goto err_request; | |
1752 | } | |
1753 | } | |
1754 | ||
17f298cf CW |
1755 | /* Whilst this request exists, batch_obj will be on the |
1756 | * active_list, and so will hold the active reference. Only when this | |
1757 | * request is retired will the the batch_obj be moved onto the | |
1758 | * inactive_list and lose its active reference. Hence we do not need | |
1759 | * to explicitly hold another reference here. | |
1760 | */ | |
650bc635 | 1761 | eb.request->batch = eb.batch; |
5f19e2bf | 1762 | |
650bc635 CW |
1763 | trace_i915_gem_request_queue(eb.request, eb.dispatch_flags); |
1764 | ret = execbuf_submit(&eb); | |
aa9b7810 | 1765 | err_request: |
650bc635 CW |
1766 | __i915_add_request(eb.request, ret == 0); |
1767 | add_to_client(eb.request, file); | |
c8659efa | 1768 | |
fec0445c CW |
1769 | if (out_fence) { |
1770 | if (ret == 0) { | |
1771 | fd_install(out_fence_fd, out_fence->file); | |
1772 | args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */ | |
1773 | args->rsvd2 |= (u64)out_fence_fd << 32; | |
1774 | out_fence_fd = -1; | |
1775 | } else { | |
1776 | fput(out_fence->file); | |
1777 | } | |
1778 | } | |
54cf91dc | 1779 | |
0c8dac88 | 1780 | err_batch_unpin: |
da51a1e7 DV |
1781 | /* |
1782 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1783 | * batch vma for correctness. For less ugly and less fragility this | |
1784 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1785 | * active. | |
1786 | */ | |
650bc635 CW |
1787 | if (eb.dispatch_flags & I915_DISPATCH_SECURE) |
1788 | i915_vma_unpin(eb.batch); | |
54cf91dc | 1789 | err: |
41bde553 | 1790 | /* the request owns the ref now */ |
650bc635 | 1791 | eb_destroy(&eb); |
54cf91dc CW |
1792 | mutex_unlock(&dev->struct_mutex); |
1793 | ||
1794 | pre_mutex_err: | |
f65c9168 PZ |
1795 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1796 | * is really idle. */ | |
650bc635 | 1797 | intel_runtime_pm_put(eb.i915); |
fec0445c CW |
1798 | if (out_fence_fd != -1) |
1799 | put_unused_fd(out_fence_fd); | |
4a04e371 | 1800 | err_in_fence: |
fec0445c | 1801 | dma_fence_put(in_fence); |
54cf91dc CW |
1802 | return ret; |
1803 | } | |
1804 | ||
1805 | /* | |
1806 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1807 | * list array and passes it to the real function. | |
1808 | */ | |
1809 | int | |
1810 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1811 | struct drm_file *file) | |
1812 | { | |
1813 | struct drm_i915_gem_execbuffer *args = data; | |
1814 | struct drm_i915_gem_execbuffer2 exec2; | |
1815 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1816 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1817 | int ret, i; | |
1818 | ||
54cf91dc | 1819 | if (args->buffer_count < 1) { |
ff240199 | 1820 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1821 | return -EINVAL; |
1822 | } | |
1823 | ||
1824 | /* Copy in the exec list from userland */ | |
2098105e MH |
1825 | exec_list = kvmalloc_array(sizeof(*exec_list), args->buffer_count, GFP_KERNEL); |
1826 | exec2_list = kvmalloc_array(sizeof(*exec2_list), args->buffer_count, GFP_KERNEL); | |
54cf91dc | 1827 | if (exec_list == NULL || exec2_list == NULL) { |
ff240199 | 1828 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc | 1829 | args->buffer_count); |
2098105e MH |
1830 | kvfree(exec_list); |
1831 | kvfree(exec2_list); | |
54cf91dc CW |
1832 | return -ENOMEM; |
1833 | } | |
1834 | ret = copy_from_user(exec_list, | |
3ed605bc | 1835 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1836 | sizeof(*exec_list) * args->buffer_count); |
1837 | if (ret != 0) { | |
ff240199 | 1838 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc | 1839 | args->buffer_count, ret); |
2098105e MH |
1840 | kvfree(exec_list); |
1841 | kvfree(exec2_list); | |
54cf91dc CW |
1842 | return -EFAULT; |
1843 | } | |
1844 | ||
1845 | for (i = 0; i < args->buffer_count; i++) { | |
1846 | exec2_list[i].handle = exec_list[i].handle; | |
1847 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1848 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1849 | exec2_list[i].alignment = exec_list[i].alignment; | |
1850 | exec2_list[i].offset = exec_list[i].offset; | |
f0836b72 | 1851 | if (INTEL_GEN(to_i915(dev)) < 4) |
54cf91dc CW |
1852 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
1853 | else | |
1854 | exec2_list[i].flags = 0; | |
1855 | } | |
1856 | ||
1857 | exec2.buffers_ptr = args->buffers_ptr; | |
1858 | exec2.buffer_count = args->buffer_count; | |
1859 | exec2.batch_start_offset = args->batch_start_offset; | |
1860 | exec2.batch_len = args->batch_len; | |
1861 | exec2.DR1 = args->DR1; | |
1862 | exec2.DR4 = args->DR4; | |
1863 | exec2.num_cliprects = args->num_cliprects; | |
1864 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1865 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1866 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1867 | |
650bc635 | 1868 | ret = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list); |
54cf91dc | 1869 | if (!ret) { |
9aab8bff | 1870 | struct drm_i915_gem_exec_object __user *user_exec_list = |
3ed605bc | 1871 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff | 1872 | |
54cf91dc | 1873 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 1874 | for (i = 0; i < args->buffer_count; i++) { |
934acce3 MW |
1875 | exec2_list[i].offset = |
1876 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1877 | ret = __copy_to_user(&user_exec_list[i].offset, |
1878 | &exec2_list[i].offset, | |
1879 | sizeof(user_exec_list[i].offset)); | |
1880 | if (ret) { | |
1881 | ret = -EFAULT; | |
1882 | DRM_DEBUG("failed to copy %d exec entries " | |
1883 | "back to user (%d)\n", | |
1884 | args->buffer_count, ret); | |
1885 | break; | |
1886 | } | |
54cf91dc CW |
1887 | } |
1888 | } | |
1889 | ||
2098105e MH |
1890 | kvfree(exec_list); |
1891 | kvfree(exec2_list); | |
54cf91dc CW |
1892 | return ret; |
1893 | } | |
1894 | ||
1895 | int | |
1896 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1897 | struct drm_file *file) | |
1898 | { | |
1899 | struct drm_i915_gem_execbuffer2 *args = data; | |
1900 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1901 | int ret; | |
1902 | ||
ed8cd3b2 XW |
1903 | if (args->buffer_count < 1 || |
1904 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1905 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1906 | return -EINVAL; |
1907 | } | |
1908 | ||
2098105e | 1909 | exec2_list = kvmalloc_array(args->buffer_count, |
f2a85e19 CW |
1910 | sizeof(*exec2_list), |
1911 | GFP_TEMPORARY); | |
54cf91dc | 1912 | if (exec2_list == NULL) { |
ff240199 | 1913 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1914 | args->buffer_count); |
1915 | return -ENOMEM; | |
1916 | } | |
1917 | ret = copy_from_user(exec2_list, | |
3ed605bc | 1918 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1919 | sizeof(*exec2_list) * args->buffer_count); |
1920 | if (ret != 0) { | |
ff240199 | 1921 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc | 1922 | args->buffer_count, ret); |
2098105e | 1923 | kvfree(exec2_list); |
54cf91dc CW |
1924 | return -EFAULT; |
1925 | } | |
1926 | ||
650bc635 | 1927 | ret = i915_gem_do_execbuffer(dev, file, args, exec2_list); |
54cf91dc CW |
1928 | if (!ret) { |
1929 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1930 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
3ed605bc | 1931 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff CW |
1932 | int i; |
1933 | ||
1934 | for (i = 0; i < args->buffer_count; i++) { | |
934acce3 MW |
1935 | exec2_list[i].offset = |
1936 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1937 | ret = __copy_to_user(&user_exec_list[i].offset, |
1938 | &exec2_list[i].offset, | |
1939 | sizeof(user_exec_list[i].offset)); | |
1940 | if (ret) { | |
1941 | ret = -EFAULT; | |
1942 | DRM_DEBUG("failed to copy %d exec entries " | |
1943 | "back to user\n", | |
1944 | args->buffer_count); | |
1945 | break; | |
1946 | } | |
54cf91dc CW |
1947 | } |
1948 | } | |
1949 | ||
2098105e | 1950 | kvfree(exec2_list); |
54cf91dc CW |
1951 | return ret; |
1952 | } |