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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
32d82067 | 35 | #include <linux/uaccess.h> |
54cf91dc | 36 | |
9e2793f6 DG |
37 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
38 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
39 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) | |
40 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) | |
41 | #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */ | |
d23db88c CW |
42 | |
43 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 44 | |
27173f1f BW |
45 | struct eb_vmas { |
46 | struct list_head vmas; | |
67731b87 | 47 | int and; |
eef90ccb | 48 | union { |
27173f1f | 49 | struct i915_vma *lut[0]; |
eef90ccb CW |
50 | struct hlist_head buckets[0]; |
51 | }; | |
67731b87 CW |
52 | }; |
53 | ||
27173f1f | 54 | static struct eb_vmas * |
17601cbc | 55 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 56 | { |
27173f1f | 57 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
58 | |
59 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 60 | unsigned size = args->buffer_count; |
27173f1f BW |
61 | size *= sizeof(struct i915_vma *); |
62 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
63 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
64 | } | |
65 | ||
66 | if (eb == NULL) { | |
b205ca57 DV |
67 | unsigned size = args->buffer_count; |
68 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 69 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
70 | while (count > 2*size) |
71 | count >>= 1; | |
72 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 73 | sizeof(struct eb_vmas), |
eef90ccb CW |
74 | GFP_TEMPORARY); |
75 | if (eb == NULL) | |
76 | return eb; | |
77 | ||
78 | eb->and = count - 1; | |
79 | } else | |
80 | eb->and = -args->buffer_count; | |
81 | ||
27173f1f | 82 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
83 | return eb; |
84 | } | |
85 | ||
86 | static void | |
27173f1f | 87 | eb_reset(struct eb_vmas *eb) |
67731b87 | 88 | { |
eef90ccb CW |
89 | if (eb->and >= 0) |
90 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
91 | } |
92 | ||
3b96eff4 | 93 | static int |
27173f1f BW |
94 | eb_lookup_vmas(struct eb_vmas *eb, |
95 | struct drm_i915_gem_exec_object2 *exec, | |
96 | const struct drm_i915_gem_execbuffer2 *args, | |
97 | struct i915_address_space *vm, | |
98 | struct drm_file *file) | |
3b96eff4 | 99 | { |
27173f1f BW |
100 | struct drm_i915_gem_object *obj; |
101 | struct list_head objects; | |
9ae9ab52 | 102 | int i, ret; |
3b96eff4 | 103 | |
27173f1f | 104 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 105 | spin_lock(&file->table_lock); |
27173f1f BW |
106 | /* Grab a reference to the object and release the lock so we can lookup |
107 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 108 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
109 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
110 | if (obj == NULL) { | |
111 | spin_unlock(&file->table_lock); | |
112 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
113 | exec[i].handle, i); | |
27173f1f | 114 | ret = -ENOENT; |
9ae9ab52 | 115 | goto err; |
3b96eff4 CW |
116 | } |
117 | ||
27173f1f | 118 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
119 | spin_unlock(&file->table_lock); |
120 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
121 | obj, exec[i].handle, i); | |
27173f1f | 122 | ret = -EINVAL; |
9ae9ab52 | 123 | goto err; |
3b96eff4 CW |
124 | } |
125 | ||
25dc556a | 126 | i915_gem_object_get(obj); |
27173f1f BW |
127 | list_add_tail(&obj->obj_exec_link, &objects); |
128 | } | |
129 | spin_unlock(&file->table_lock); | |
3b96eff4 | 130 | |
27173f1f | 131 | i = 0; |
9ae9ab52 | 132 | while (!list_empty(&objects)) { |
27173f1f | 133 | struct i915_vma *vma; |
6f65e29a | 134 | |
9ae9ab52 CW |
135 | obj = list_first_entry(&objects, |
136 | struct drm_i915_gem_object, | |
137 | obj_exec_link); | |
138 | ||
e656a6cb DV |
139 | /* |
140 | * NOTE: We can leak any vmas created here when something fails | |
141 | * later on. But that's no issue since vma_unbind can deal with | |
142 | * vmas which are not actually bound. And since only | |
143 | * lookup_or_create exists as an interface to get at the vma | |
144 | * from the (obj, vm) we don't run the risk of creating | |
145 | * duplicated vmas for the same vm. | |
146 | */ | |
da51a1e7 | 147 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 148 | if (IS_ERR(vma)) { |
27173f1f BW |
149 | DRM_DEBUG("Failed to lookup VMA\n"); |
150 | ret = PTR_ERR(vma); | |
9ae9ab52 | 151 | goto err; |
27173f1f BW |
152 | } |
153 | ||
9ae9ab52 | 154 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 155 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 156 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
157 | |
158 | vma->exec_entry = &exec[i]; | |
eef90ccb | 159 | if (eb->and < 0) { |
27173f1f | 160 | eb->lut[i] = vma; |
eef90ccb CW |
161 | } else { |
162 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
163 | vma->exec_handle = handle; |
164 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
165 | &eb->buckets[handle & eb->and]); |
166 | } | |
27173f1f | 167 | ++i; |
3b96eff4 | 168 | } |
3b96eff4 | 169 | |
9ae9ab52 | 170 | return 0; |
27173f1f | 171 | |
27173f1f | 172 | |
9ae9ab52 | 173 | err: |
27173f1f BW |
174 | while (!list_empty(&objects)) { |
175 | obj = list_first_entry(&objects, | |
176 | struct drm_i915_gem_object, | |
177 | obj_exec_link); | |
178 | list_del_init(&obj->obj_exec_link); | |
f8c417cd | 179 | i915_gem_object_put(obj); |
27173f1f | 180 | } |
9ae9ab52 CW |
181 | /* |
182 | * Objects already transfered to the vmas list will be unreferenced by | |
183 | * eb_destroy. | |
184 | */ | |
185 | ||
27173f1f | 186 | return ret; |
3b96eff4 CW |
187 | } |
188 | ||
4bfa339a DG |
189 | static inline struct i915_vma * |
190 | eb_get_batch_vma(struct eb_vmas *eb) | |
191 | { | |
192 | /* The batch is always the LAST item in the VMA list */ | |
193 | struct i915_vma *vma = list_last_entry(&eb->vmas, typeof(*vma), exec_list); | |
194 | ||
195 | return vma; | |
196 | } | |
197 | ||
198 | static struct drm_i915_gem_object * | |
199 | eb_get_batch(struct eb_vmas *eb) | |
200 | { | |
201 | struct i915_vma *vma = eb_get_batch_vma(eb); | |
202 | ||
203 | /* | |
204 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
205 | * to negative relocation deltas. Usually that works out ok since the | |
206 | * relocate address is still positive, except when the batch is placed | |
207 | * very low in the GTT. Ensure this doesn't happen. | |
208 | * | |
209 | * Note that actual hangs have only been observed on gen7, but for | |
210 | * paranoia do it everywhere. | |
211 | */ | |
212 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) | |
213 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
214 | ||
215 | return vma->obj; | |
216 | } | |
217 | ||
27173f1f | 218 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 219 | { |
eef90ccb CW |
220 | if (eb->and < 0) { |
221 | if (handle >= -eb->and) | |
222 | return NULL; | |
223 | return eb->lut[handle]; | |
224 | } else { | |
225 | struct hlist_head *head; | |
aa45950b | 226 | struct i915_vma *vma; |
67731b87 | 227 | |
eef90ccb | 228 | head = &eb->buckets[handle & eb->and]; |
aa45950b | 229 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
230 | if (vma->exec_handle == handle) |
231 | return vma; | |
eef90ccb CW |
232 | } |
233 | return NULL; | |
234 | } | |
67731b87 CW |
235 | } |
236 | ||
a415d355 CW |
237 | static void |
238 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
239 | { | |
240 | struct drm_i915_gem_exec_object2 *entry; | |
241 | struct drm_i915_gem_object *obj = vma->obj; | |
242 | ||
243 | if (!drm_mm_node_allocated(&vma->node)) | |
244 | return; | |
245 | ||
246 | entry = vma->exec_entry; | |
247 | ||
248 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
249 | i915_gem_object_unpin_fence(obj); | |
250 | ||
251 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 252 | vma->pin_count--; |
a415d355 | 253 | |
de4e783a | 254 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
255 | } |
256 | ||
257 | static void eb_destroy(struct eb_vmas *eb) | |
258 | { | |
27173f1f BW |
259 | while (!list_empty(&eb->vmas)) { |
260 | struct i915_vma *vma; | |
bcffc3fa | 261 | |
27173f1f BW |
262 | vma = list_first_entry(&eb->vmas, |
263 | struct i915_vma, | |
bcffc3fa | 264 | exec_list); |
27173f1f | 265 | list_del_init(&vma->exec_list); |
a415d355 | 266 | i915_gem_execbuffer_unreserve_vma(vma); |
f8c417cd | 267 | i915_gem_object_put(vma->obj); |
bcffc3fa | 268 | } |
67731b87 CW |
269 | kfree(eb); |
270 | } | |
271 | ||
dabdfe02 CW |
272 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
273 | { | |
2cc86b82 CW |
274 | return (HAS_LLC(obj->base.dev) || |
275 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
dabdfe02 CW |
276 | obj->cache_level != I915_CACHE_NONE); |
277 | } | |
278 | ||
934acce3 MW |
279 | /* Used to convert any address to canonical form. |
280 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
281 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
282 | * addresses to be in a canonical form: | |
283 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
284 | * canonical form [63:48] == [47]." | |
285 | */ | |
286 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
287 | static inline uint64_t gen8_canonical_addr(uint64_t address) | |
288 | { | |
289 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
290 | } | |
291 | ||
292 | static inline uint64_t gen8_noncanonical_addr(uint64_t address) | |
293 | { | |
294 | return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1); | |
295 | } | |
296 | ||
297 | static inline uint64_t | |
298 | relocation_target(struct drm_i915_gem_relocation_entry *reloc, | |
299 | uint64_t target_offset) | |
300 | { | |
301 | return gen8_canonical_addr((int)reloc->delta + target_offset); | |
302 | } | |
303 | ||
5032d871 RB |
304 | static int |
305 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
306 | struct drm_i915_gem_relocation_entry *reloc, |
307 | uint64_t target_offset) | |
5032d871 | 308 | { |
3c94ceee | 309 | struct drm_device *dev = obj->base.dev; |
5032d871 | 310 | uint32_t page_offset = offset_in_page(reloc->offset); |
934acce3 | 311 | uint64_t delta = relocation_target(reloc, target_offset); |
5032d871 | 312 | char *vaddr; |
8b78f0e5 | 313 | int ret; |
5032d871 | 314 | |
2cc86b82 | 315 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
316 | if (ret) |
317 | return ret; | |
318 | ||
033908ae | 319 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
5032d871 | 320 | reloc->offset >> PAGE_SHIFT)); |
d9ceb957 | 321 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
322 | |
323 | if (INTEL_INFO(dev)->gen >= 8) { | |
324 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
325 | ||
326 | if (page_offset == 0) { | |
327 | kunmap_atomic(vaddr); | |
033908ae | 328 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
3c94ceee BW |
329 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
330 | } | |
331 | ||
d9ceb957 | 332 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
333 | } |
334 | ||
5032d871 RB |
335 | kunmap_atomic(vaddr); |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | static int | |
341 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
342 | struct drm_i915_gem_relocation_entry *reloc, |
343 | uint64_t target_offset) | |
5032d871 RB |
344 | { |
345 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
346 | struct drm_i915_private *dev_priv = to_i915(dev); |
347 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
934acce3 | 348 | uint64_t delta = relocation_target(reloc, target_offset); |
906843c3 | 349 | uint64_t offset; |
5032d871 | 350 | void __iomem *reloc_page; |
8b78f0e5 | 351 | int ret; |
5032d871 RB |
352 | |
353 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
354 | if (ret) | |
355 | return ret; | |
356 | ||
357 | ret = i915_gem_object_put_fence(obj); | |
358 | if (ret) | |
359 | return ret; | |
360 | ||
361 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
362 | offset = i915_gem_obj_ggtt_offset(obj); |
363 | offset += reloc->offset; | |
72e96d64 | 364 | reloc_page = io_mapping_map_atomic_wc(ggtt->mappable, |
906843c3 CW |
365 | offset & PAGE_MASK); |
366 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
367 | |
368 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 369 | offset += sizeof(uint32_t); |
3c94ceee | 370 | |
906843c3 | 371 | if (offset_in_page(offset) == 0) { |
3c94ceee | 372 | io_mapping_unmap_atomic(reloc_page); |
906843c3 | 373 | reloc_page = |
72e96d64 | 374 | io_mapping_map_atomic_wc(ggtt->mappable, |
906843c3 | 375 | offset); |
3c94ceee BW |
376 | } |
377 | ||
906843c3 CW |
378 | iowrite32(upper_32_bits(delta), |
379 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
380 | } |
381 | ||
5032d871 RB |
382 | io_mapping_unmap_atomic(reloc_page); |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
edf4427b CW |
387 | static void |
388 | clflush_write32(void *addr, uint32_t value) | |
389 | { | |
390 | /* This is not a fast path, so KISS. */ | |
391 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
392 | *(uint32_t *)addr = value; | |
393 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
394 | } | |
395 | ||
396 | static int | |
397 | relocate_entry_clflush(struct drm_i915_gem_object *obj, | |
398 | struct drm_i915_gem_relocation_entry *reloc, | |
399 | uint64_t target_offset) | |
400 | { | |
401 | struct drm_device *dev = obj->base.dev; | |
402 | uint32_t page_offset = offset_in_page(reloc->offset); | |
934acce3 | 403 | uint64_t delta = relocation_target(reloc, target_offset); |
edf4427b CW |
404 | char *vaddr; |
405 | int ret; | |
406 | ||
407 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
408 | if (ret) | |
409 | return ret; | |
410 | ||
033908ae | 411 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
412 | reloc->offset >> PAGE_SHIFT)); |
413 | clflush_write32(vaddr + page_offset, lower_32_bits(delta)); | |
414 | ||
415 | if (INTEL_INFO(dev)->gen >= 8) { | |
416 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
417 | ||
418 | if (page_offset == 0) { | |
419 | kunmap_atomic(vaddr); | |
033908ae | 420 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
421 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
422 | } | |
423 | ||
424 | clflush_write32(vaddr + page_offset, upper_32_bits(delta)); | |
425 | } | |
426 | ||
427 | kunmap_atomic(vaddr); | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
54cf91dc CW |
432 | static int |
433 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 434 | struct eb_vmas *eb, |
3e7a0322 | 435 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
436 | { |
437 | struct drm_device *dev = obj->base.dev; | |
438 | struct drm_gem_object *target_obj; | |
149c8407 | 439 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 440 | struct i915_vma *target_vma; |
d9ceb957 | 441 | uint64_t target_offset; |
8b78f0e5 | 442 | int ret; |
54cf91dc | 443 | |
67731b87 | 444 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
445 | target_vma = eb_get_vma(eb, reloc->target_handle); |
446 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 447 | return -ENOENT; |
27173f1f BW |
448 | target_i915_obj = target_vma->obj; |
449 | target_obj = &target_vma->obj->base; | |
54cf91dc | 450 | |
934acce3 | 451 | target_offset = gen8_canonical_addr(target_vma->node.start); |
54cf91dc | 452 | |
e844b990 EA |
453 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
454 | * pipe_control writes because the gpu doesn't properly redirect them | |
455 | * through the ppgtt for non_secure batchbuffers. */ | |
456 | if (unlikely(IS_GEN6(dev) && | |
0875546c | 457 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 458 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 459 | PIN_GLOBAL); |
fe14d5f4 TU |
460 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
461 | return ret; | |
462 | } | |
e844b990 | 463 | |
54cf91dc | 464 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 465 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 466 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
467 | "obj %p target %d offset %d " |
468 | "read %08x write %08x", | |
469 | obj, reloc->target_handle, | |
470 | (int) reloc->offset, | |
471 | reloc->read_domains, | |
472 | reloc->write_domain); | |
8b78f0e5 | 473 | return -EINVAL; |
54cf91dc | 474 | } |
4ca4a250 DV |
475 | if (unlikely((reloc->write_domain | reloc->read_domains) |
476 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 477 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
478 | "obj %p target %d offset %d " |
479 | "read %08x write %08x", | |
480 | obj, reloc->target_handle, | |
481 | (int) reloc->offset, | |
482 | reloc->read_domains, | |
483 | reloc->write_domain); | |
8b78f0e5 | 484 | return -EINVAL; |
54cf91dc | 485 | } |
54cf91dc CW |
486 | |
487 | target_obj->pending_read_domains |= reloc->read_domains; | |
488 | target_obj->pending_write_domain |= reloc->write_domain; | |
489 | ||
490 | /* If the relocation already has the right value in it, no | |
491 | * more work needs to be done. | |
492 | */ | |
493 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 494 | return 0; |
54cf91dc CW |
495 | |
496 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
497 | if (unlikely(reloc->offset > |
498 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 499 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
500 | "obj %p target %d offset %d size %d.\n", |
501 | obj, reloc->target_handle, | |
502 | (int) reloc->offset, | |
503 | (int) obj->base.size); | |
8b78f0e5 | 504 | return -EINVAL; |
54cf91dc | 505 | } |
b8f7ab17 | 506 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 507 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
508 | "obj %p target %d offset %d.\n", |
509 | obj, reloc->target_handle, | |
510 | (int) reloc->offset); | |
8b78f0e5 | 511 | return -EINVAL; |
54cf91dc CW |
512 | } |
513 | ||
dabdfe02 | 514 | /* We can't wait for rendering with pagefaults disabled */ |
32d82067 | 515 | if (obj->active && pagefault_disabled()) |
dabdfe02 CW |
516 | return -EFAULT; |
517 | ||
5032d871 | 518 | if (use_cpu_reloc(obj)) |
d9ceb957 | 519 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
edf4427b | 520 | else if (obj->map_and_fenceable) |
d9ceb957 | 521 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
906bf7fd | 522 | else if (static_cpu_has(X86_FEATURE_CLFLUSH)) |
edf4427b CW |
523 | ret = relocate_entry_clflush(obj, reloc, target_offset); |
524 | else { | |
525 | WARN_ONCE(1, "Impossible case in relocation handling\n"); | |
526 | ret = -ENODEV; | |
527 | } | |
54cf91dc | 528 | |
d4d36014 DV |
529 | if (ret) |
530 | return ret; | |
531 | ||
54cf91dc CW |
532 | /* and update the user's relocation entry */ |
533 | reloc->presumed_offset = target_offset; | |
534 | ||
67731b87 | 535 | return 0; |
54cf91dc CW |
536 | } |
537 | ||
538 | static int | |
27173f1f BW |
539 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
540 | struct eb_vmas *eb) | |
54cf91dc | 541 | { |
1d83f442 CW |
542 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
543 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 544 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 545 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 546 | int remain, ret; |
54cf91dc | 547 | |
3ed605bc | 548 | user_relocs = u64_to_user_ptr(entry->relocs_ptr); |
54cf91dc | 549 | |
1d83f442 CW |
550 | remain = entry->relocation_count; |
551 | while (remain) { | |
552 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
553 | int count = remain; | |
554 | if (count > ARRAY_SIZE(stack_reloc)) | |
555 | count = ARRAY_SIZE(stack_reloc); | |
556 | remain -= count; | |
557 | ||
558 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
559 | return -EFAULT; |
560 | ||
1d83f442 CW |
561 | do { |
562 | u64 offset = r->presumed_offset; | |
54cf91dc | 563 | |
3e7a0322 | 564 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
565 | if (ret) |
566 | return ret; | |
567 | ||
568 | if (r->presumed_offset != offset && | |
5b09c3ed | 569 | __put_user(r->presumed_offset, &user_relocs->presumed_offset)) { |
1d83f442 CW |
570 | return -EFAULT; |
571 | } | |
572 | ||
573 | user_relocs++; | |
574 | r++; | |
575 | } while (--count); | |
54cf91dc CW |
576 | } |
577 | ||
578 | return 0; | |
1d83f442 | 579 | #undef N_RELOC |
54cf91dc CW |
580 | } |
581 | ||
582 | static int | |
27173f1f BW |
583 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
584 | struct eb_vmas *eb, | |
585 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 586 | { |
27173f1f | 587 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
588 | int i, ret; |
589 | ||
590 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 591 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
592 | if (ret) |
593 | return ret; | |
594 | } | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static int | |
17601cbc | 600 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 601 | { |
27173f1f | 602 | struct i915_vma *vma; |
d4aeee77 CW |
603 | int ret = 0; |
604 | ||
605 | /* This is the fast path and we cannot handle a pagefault whilst | |
606 | * holding the struct mutex lest the user pass in the relocations | |
607 | * contained within a mmaped bo. For in such a case we, the page | |
608 | * fault handler would call i915_gem_fault() and we would try to | |
609 | * acquire the struct mutex again. Obviously this is bad and so | |
610 | * lockdep complains vehemently. | |
611 | */ | |
612 | pagefault_disable(); | |
27173f1f BW |
613 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
614 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 615 | if (ret) |
d4aeee77 | 616 | break; |
54cf91dc | 617 | } |
d4aeee77 | 618 | pagefault_enable(); |
54cf91dc | 619 | |
d4aeee77 | 620 | return ret; |
54cf91dc CW |
621 | } |
622 | ||
edf4427b CW |
623 | static bool only_mappable_for_reloc(unsigned int flags) |
624 | { | |
625 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
626 | __EXEC_OBJECT_NEEDS_MAP; | |
627 | } | |
628 | ||
1690e1eb | 629 | static int |
27173f1f | 630 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
0bc40be8 | 631 | struct intel_engine_cs *engine, |
27173f1f | 632 | bool *need_reloc) |
1690e1eb | 633 | { |
6f65e29a | 634 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 635 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 636 | uint64_t flags; |
1690e1eb CW |
637 | int ret; |
638 | ||
0875546c | 639 | flags = PIN_USER; |
0229da32 DV |
640 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
641 | flags |= PIN_GLOBAL; | |
642 | ||
edf4427b | 643 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
644 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
645 | * limit address to the first 4GBs for unflagged objects. | |
646 | */ | |
647 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
648 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
649 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
650 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
651 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
652 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
653 | if (entry->flags & EXEC_OBJECT_PINNED) |
654 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
655 | if ((flags & PIN_MAPPABLE) == 0) |
656 | flags |= PIN_HIGH; | |
edf4427b | 657 | } |
1ec9e26d DV |
658 | |
659 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
edf4427b CW |
660 | if ((ret == -ENOSPC || ret == -E2BIG) && |
661 | only_mappable_for_reloc(entry->flags)) | |
662 | ret = i915_gem_object_pin(obj, vma->vm, | |
663 | entry->alignment, | |
0229da32 | 664 | flags & ~PIN_MAPPABLE); |
1690e1eb CW |
665 | if (ret) |
666 | return ret; | |
667 | ||
7788a765 CW |
668 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
669 | ||
82b6b6d7 CW |
670 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
671 | ret = i915_gem_object_get_fence(obj); | |
672 | if (ret) | |
673 | return ret; | |
9a5a53b3 | 674 | |
82b6b6d7 CW |
675 | if (i915_gem_object_pin_fence(obj)) |
676 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
677 | } |
678 | ||
27173f1f BW |
679 | if (entry->offset != vma->node.start) { |
680 | entry->offset = vma->node.start; | |
ed5982e6 DV |
681 | *need_reloc = true; |
682 | } | |
683 | ||
684 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
685 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
686 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
687 | } | |
688 | ||
1690e1eb | 689 | return 0; |
7788a765 | 690 | } |
1690e1eb | 691 | |
d23db88c | 692 | static bool |
e6a84468 | 693 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
694 | { |
695 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 696 | |
e6a84468 CW |
697 | if (entry->relocation_count == 0) |
698 | return false; | |
699 | ||
596c5923 | 700 | if (!vma->is_ggtt) |
e6a84468 CW |
701 | return false; |
702 | ||
703 | /* See also use_cpu_reloc() */ | |
704 | if (HAS_LLC(vma->obj->base.dev)) | |
705 | return false; | |
706 | ||
707 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
708 | return false; | |
709 | ||
710 | return true; | |
711 | } | |
712 | ||
713 | static bool | |
714 | eb_vma_misplaced(struct i915_vma *vma) | |
715 | { | |
716 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
717 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 718 | |
596c5923 | 719 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt); |
d23db88c CW |
720 | |
721 | if (entry->alignment && | |
722 | vma->node.start & (entry->alignment - 1)) | |
723 | return true; | |
724 | ||
506a8e87 CW |
725 | if (entry->flags & EXEC_OBJECT_PINNED && |
726 | vma->node.start != entry->offset) | |
727 | return true; | |
728 | ||
d23db88c CW |
729 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
730 | vma->node.start < BATCH_OFFSET_BIAS) | |
731 | return true; | |
732 | ||
edf4427b CW |
733 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
734 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) | |
735 | return !only_mappable_for_reloc(entry->flags); | |
736 | ||
101b506a MT |
737 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
738 | (vma->node.start + vma->node.size - 1) >> 32) | |
739 | return true; | |
740 | ||
d23db88c CW |
741 | return false; |
742 | } | |
743 | ||
54cf91dc | 744 | static int |
0bc40be8 | 745 | i915_gem_execbuffer_reserve(struct intel_engine_cs *engine, |
27173f1f | 746 | struct list_head *vmas, |
e2efd130 | 747 | struct i915_gem_context *ctx, |
ed5982e6 | 748 | bool *need_relocs) |
54cf91dc | 749 | { |
432e58ed | 750 | struct drm_i915_gem_object *obj; |
27173f1f | 751 | struct i915_vma *vma; |
68c8c17f | 752 | struct i915_address_space *vm; |
27173f1f | 753 | struct list_head ordered_vmas; |
506a8e87 | 754 | struct list_head pinned_vmas; |
c033666a | 755 | bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4; |
7788a765 | 756 | int retry; |
6fe4f140 | 757 | |
0bc40be8 | 758 | i915_gem_retire_requests_ring(engine); |
227f782e | 759 | |
68c8c17f BW |
760 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
761 | ||
27173f1f | 762 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 763 | INIT_LIST_HEAD(&pinned_vmas); |
27173f1f | 764 | while (!list_empty(vmas)) { |
6fe4f140 CW |
765 | struct drm_i915_gem_exec_object2 *entry; |
766 | bool need_fence, need_mappable; | |
767 | ||
27173f1f BW |
768 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
769 | obj = vma->obj; | |
770 | entry = vma->exec_entry; | |
6fe4f140 | 771 | |
b1b38278 DW |
772 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
773 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
774 | ||
82b6b6d7 CW |
775 | if (!has_fenced_gpu_access) |
776 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 777 | need_fence = |
6fe4f140 CW |
778 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
779 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 780 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 781 | |
506a8e87 CW |
782 | if (entry->flags & EXEC_OBJECT_PINNED) |
783 | list_move_tail(&vma->exec_list, &pinned_vmas); | |
784 | else if (need_mappable) { | |
e6a84468 | 785 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
27173f1f | 786 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 787 | } else |
27173f1f | 788 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 789 | |
ed5982e6 | 790 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 791 | obj->base.pending_write_domain = 0; |
6fe4f140 | 792 | } |
27173f1f | 793 | list_splice(&ordered_vmas, vmas); |
506a8e87 | 794 | list_splice(&pinned_vmas, vmas); |
54cf91dc CW |
795 | |
796 | /* Attempt to pin all of the buffers into the GTT. | |
797 | * This is done in 3 phases: | |
798 | * | |
799 | * 1a. Unbind all objects that do not match the GTT constraints for | |
800 | * the execbuffer (fenceable, mappable, alignment etc). | |
801 | * 1b. Increment pin count for already bound objects. | |
802 | * 2. Bind new objects. | |
803 | * 3. Decrement pin count. | |
804 | * | |
7788a765 | 805 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
806 | * room for the earlier objects *unless* we need to defragment. |
807 | */ | |
808 | retry = 0; | |
809 | do { | |
7788a765 | 810 | int ret = 0; |
54cf91dc CW |
811 | |
812 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 813 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 814 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
815 | continue; |
816 | ||
e6a84468 | 817 | if (eb_vma_misplaced(vma)) |
27173f1f | 818 | ret = i915_vma_unbind(vma); |
54cf91dc | 819 | else |
0bc40be8 TU |
820 | ret = i915_gem_execbuffer_reserve_vma(vma, |
821 | engine, | |
822 | need_relocs); | |
432e58ed | 823 | if (ret) |
54cf91dc | 824 | goto err; |
54cf91dc CW |
825 | } |
826 | ||
827 | /* Bind fresh objects */ | |
27173f1f BW |
828 | list_for_each_entry(vma, vmas, exec_list) { |
829 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 830 | continue; |
54cf91dc | 831 | |
0bc40be8 TU |
832 | ret = i915_gem_execbuffer_reserve_vma(vma, engine, |
833 | need_relocs); | |
7788a765 CW |
834 | if (ret) |
835 | goto err; | |
54cf91dc CW |
836 | } |
837 | ||
a415d355 | 838 | err: |
6c085a72 | 839 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
840 | return ret; |
841 | ||
a415d355 CW |
842 | /* Decrement pin count for bound objects */ |
843 | list_for_each_entry(vma, vmas, exec_list) | |
844 | i915_gem_execbuffer_unreserve_vma(vma); | |
845 | ||
68c8c17f | 846 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
847 | if (ret) |
848 | return ret; | |
54cf91dc CW |
849 | } while (1); |
850 | } | |
851 | ||
852 | static int | |
853 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 854 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 855 | struct drm_file *file, |
0bc40be8 | 856 | struct intel_engine_cs *engine, |
27173f1f | 857 | struct eb_vmas *eb, |
b1b38278 | 858 | struct drm_i915_gem_exec_object2 *exec, |
e2efd130 | 859 | struct i915_gem_context *ctx) |
54cf91dc CW |
860 | { |
861 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
862 | struct i915_address_space *vm; |
863 | struct i915_vma *vma; | |
ed5982e6 | 864 | bool need_relocs; |
dd6864a4 | 865 | int *reloc_offset; |
54cf91dc | 866 | int i, total, ret; |
b205ca57 | 867 | unsigned count = args->buffer_count; |
54cf91dc | 868 | |
27173f1f BW |
869 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
870 | ||
67731b87 | 871 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
872 | while (!list_empty(&eb->vmas)) { |
873 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
874 | list_del_init(&vma->exec_list); | |
a415d355 | 875 | i915_gem_execbuffer_unreserve_vma(vma); |
f8c417cd | 876 | i915_gem_object_put(vma->obj); |
67731b87 CW |
877 | } |
878 | ||
54cf91dc CW |
879 | mutex_unlock(&dev->struct_mutex); |
880 | ||
881 | total = 0; | |
882 | for (i = 0; i < count; i++) | |
432e58ed | 883 | total += exec[i].relocation_count; |
54cf91dc | 884 | |
dd6864a4 | 885 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 886 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
887 | if (reloc == NULL || reloc_offset == NULL) { |
888 | drm_free_large(reloc); | |
889 | drm_free_large(reloc_offset); | |
54cf91dc CW |
890 | mutex_lock(&dev->struct_mutex); |
891 | return -ENOMEM; | |
892 | } | |
893 | ||
894 | total = 0; | |
895 | for (i = 0; i < count; i++) { | |
896 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
897 | u64 invalid_offset = (u64)-1; |
898 | int j; | |
54cf91dc | 899 | |
3ed605bc | 900 | user_relocs = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
901 | |
902 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 903 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
904 | ret = -EFAULT; |
905 | mutex_lock(&dev->struct_mutex); | |
906 | goto err; | |
907 | } | |
908 | ||
262b6d36 CW |
909 | /* As we do not update the known relocation offsets after |
910 | * relocating (due to the complexities in lock handling), | |
911 | * we need to mark them as invalid now so that we force the | |
912 | * relocation processing next time. Just in case the target | |
913 | * object is evicted and then rebound into its old | |
914 | * presumed_offset before the next execbuffer - if that | |
915 | * happened we would make the mistake of assuming that the | |
916 | * relocations were valid. | |
917 | */ | |
918 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
919 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
920 | &invalid_offset, | |
921 | sizeof(invalid_offset))) { | |
262b6d36 CW |
922 | ret = -EFAULT; |
923 | mutex_lock(&dev->struct_mutex); | |
924 | goto err; | |
925 | } | |
926 | } | |
927 | ||
dd6864a4 | 928 | reloc_offset[i] = total; |
432e58ed | 929 | total += exec[i].relocation_count; |
54cf91dc CW |
930 | } |
931 | ||
932 | ret = i915_mutex_lock_interruptible(dev); | |
933 | if (ret) { | |
934 | mutex_lock(&dev->struct_mutex); | |
935 | goto err; | |
936 | } | |
937 | ||
67731b87 | 938 | /* reacquire the objects */ |
67731b87 | 939 | eb_reset(eb); |
27173f1f | 940 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
941 | if (ret) |
942 | goto err; | |
67731b87 | 943 | |
ed5982e6 | 944 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
0bc40be8 TU |
945 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
946 | &need_relocs); | |
54cf91dc CW |
947 | if (ret) |
948 | goto err; | |
949 | ||
27173f1f BW |
950 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
951 | int offset = vma->exec_entry - exec; | |
952 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
953 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
954 | if (ret) |
955 | goto err; | |
54cf91dc CW |
956 | } |
957 | ||
958 | /* Leave the user relocations as are, this is the painfully slow path, | |
959 | * and we want to avoid the complication of dropping the lock whilst | |
960 | * having buffers reserved in the aperture and so causing spurious | |
961 | * ENOSPC for random operations. | |
962 | */ | |
963 | ||
964 | err: | |
965 | drm_free_large(reloc); | |
dd6864a4 | 966 | drm_free_large(reloc_offset); |
54cf91dc CW |
967 | return ret; |
968 | } | |
969 | ||
54cf91dc | 970 | static int |
535fbe82 | 971 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 972 | struct list_head *vmas) |
54cf91dc | 973 | { |
666796da | 974 | const unsigned other_rings = ~intel_engine_flag(req->engine); |
27173f1f | 975 | struct i915_vma *vma; |
6ac42f41 | 976 | uint32_t flush_domains = 0; |
000433b6 | 977 | bool flush_chipset = false; |
432e58ed | 978 | int ret; |
54cf91dc | 979 | |
27173f1f BW |
980 | list_for_each_entry(vma, vmas, exec_list) { |
981 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 CW |
982 | |
983 | if (obj->active & other_rings) { | |
4a570db5 | 984 | ret = i915_gem_object_sync(obj, req->engine, &req); |
03ade511 CW |
985 | if (ret) |
986 | return ret; | |
987 | } | |
6ac42f41 DV |
988 | |
989 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 990 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 991 | |
6ac42f41 | 992 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
993 | } |
994 | ||
000433b6 | 995 | if (flush_chipset) |
c033666a | 996 | i915_gem_chipset_flush(req->engine->i915); |
6ac42f41 DV |
997 | |
998 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
999 | wmb(); | |
1000 | ||
09cf7c9a CW |
1001 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
1002 | * any residual writes from the previous batch. | |
1003 | */ | |
7e37f889 | 1004 | return intel_engine_invalidate_all_caches(req); |
54cf91dc CW |
1005 | } |
1006 | ||
432e58ed CW |
1007 | static bool |
1008 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 1009 | { |
ed5982e6 DV |
1010 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
1011 | return false; | |
1012 | ||
2f5945bc CW |
1013 | /* Kernel clipping was a DRI1 misfeature */ |
1014 | if (exec->num_cliprects || exec->cliprects_ptr) | |
1015 | return false; | |
1016 | ||
1017 | if (exec->DR4 == 0xffffffff) { | |
1018 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1019 | exec->DR4 = 0; | |
1020 | } | |
1021 | if (exec->DR1 || exec->DR4) | |
1022 | return false; | |
1023 | ||
1024 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
1025 | return false; | |
1026 | ||
1027 | return true; | |
54cf91dc CW |
1028 | } |
1029 | ||
1030 | static int | |
ad19f10b CW |
1031 | validate_exec_list(struct drm_device *dev, |
1032 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
1033 | int count) |
1034 | { | |
b205ca57 DV |
1035 | unsigned relocs_total = 0; |
1036 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
1037 | unsigned invalid_flags; |
1038 | int i; | |
1039 | ||
9e2793f6 DG |
1040 | /* INTERNAL flags must not overlap with external ones */ |
1041 | BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS); | |
1042 | ||
ad19f10b CW |
1043 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; |
1044 | if (USES_FULL_PPGTT(dev)) | |
1045 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
1046 | |
1047 | for (i = 0; i < count; i++) { | |
3ed605bc | 1048 | char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1049 | int length; /* limited by fault_in_pages_readable() */ |
1050 | ||
ad19f10b | 1051 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
1052 | return -EINVAL; |
1053 | ||
934acce3 MW |
1054 | /* Offset can be used as input (EXEC_OBJECT_PINNED), reject |
1055 | * any non-page-aligned or non-canonical addresses. | |
1056 | */ | |
1057 | if (exec[i].flags & EXEC_OBJECT_PINNED) { | |
1058 | if (exec[i].offset != | |
1059 | gen8_canonical_addr(exec[i].offset & PAGE_MASK)) | |
1060 | return -EINVAL; | |
1061 | ||
1062 | /* From drm_mm perspective address space is continuous, | |
1063 | * so from this point we're always using non-canonical | |
1064 | * form internally. | |
1065 | */ | |
1066 | exec[i].offset = gen8_noncanonical_addr(exec[i].offset); | |
1067 | } | |
1068 | ||
55a9785d CW |
1069 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
1070 | return -EINVAL; | |
1071 | ||
3118a4f6 KC |
1072 | /* First check for malicious input causing overflow in |
1073 | * the worst case where we need to allocate the entire | |
1074 | * relocation tree as a single array. | |
1075 | */ | |
1076 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1077 | return -EINVAL; |
3118a4f6 | 1078 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1079 | |
1080 | length = exec[i].relocation_count * | |
1081 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1082 | /* |
1083 | * We must check that the entire relocation array is safe | |
1084 | * to read, but since we may need to update the presumed | |
1085 | * offsets during execution, check for full write access. | |
1086 | */ | |
54cf91dc CW |
1087 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1088 | return -EFAULT; | |
1089 | ||
d330a953 | 1090 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1091 | if (fault_in_multipages_readable(ptr, length)) |
1092 | return -EFAULT; | |
1093 | } | |
54cf91dc CW |
1094 | } |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
e2efd130 | 1099 | static struct i915_gem_context * |
d299cce7 | 1100 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
0bc40be8 | 1101 | struct intel_engine_cs *engine, const u32 ctx_id) |
d299cce7 | 1102 | { |
e2efd130 | 1103 | struct i915_gem_context *ctx = NULL; |
d299cce7 MK |
1104 | struct i915_ctx_hang_stats *hs; |
1105 | ||
0bc40be8 | 1106 | if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
1107 | return ERR_PTR(-EINVAL); |
1108 | ||
ca585b5d | 1109 | ctx = i915_gem_context_lookup(file->driver_priv, ctx_id); |
72ad5c45 | 1110 | if (IS_ERR(ctx)) |
41bde553 | 1111 | return ctx; |
d299cce7 | 1112 | |
41bde553 | 1113 | hs = &ctx->hang_stats; |
d299cce7 MK |
1114 | if (hs->banned) { |
1115 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 1116 | return ERR_PTR(-EIO); |
d299cce7 MK |
1117 | } |
1118 | ||
41bde553 | 1119 | return ctx; |
d299cce7 MK |
1120 | } |
1121 | ||
ba8b7ccb | 1122 | void |
27173f1f | 1123 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1124 | struct drm_i915_gem_request *req) |
432e58ed | 1125 | { |
666796da | 1126 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
27173f1f | 1127 | struct i915_vma *vma; |
432e58ed | 1128 | |
27173f1f | 1129 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 1130 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 1131 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
1132 | u32 old_read = obj->base.read_domains; |
1133 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1134 | |
51bc1404 | 1135 | obj->dirty = 1; /* be paranoid */ |
432e58ed | 1136 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
1137 | if (obj->base.write_domain == 0) |
1138 | obj->base.pending_read_domains |= obj->base.read_domains; | |
1139 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1140 | |
b2af0376 | 1141 | i915_vma_move_to_active(vma, req); |
432e58ed | 1142 | if (obj->base.write_domain) { |
97b2a6a1 | 1143 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 | 1144 | |
77a0d1ca | 1145 | intel_fb_obj_invalidate(obj, ORIGIN_CS); |
c8725f3d CW |
1146 | |
1147 | /* update for the implicit flush after a batch */ | |
1148 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 1149 | } |
82b6b6d7 | 1150 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 1151 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 | 1152 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
c033666a | 1153 | struct drm_i915_private *dev_priv = engine->i915; |
82b6b6d7 CW |
1154 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, |
1155 | &dev_priv->mm.fence_list); | |
1156 | } | |
1157 | } | |
432e58ed | 1158 | |
db53a302 | 1159 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1160 | } |
1161 | } | |
1162 | ||
aa9b7810 | 1163 | static void |
adeca76d | 1164 | i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params) |
54cf91dc | 1165 | { |
cc889e0f | 1166 | /* Unconditionally force add_request to emit a full flush. */ |
4a570db5 | 1167 | params->engine->gpu_caches_dirty = true; |
54cf91dc | 1168 | |
432e58ed | 1169 | /* Add a breadcrumb for the completion of the batch buffer */ |
fcfa423c | 1170 | __i915_add_request(params->request, params->batch_obj, true); |
432e58ed | 1171 | } |
54cf91dc | 1172 | |
ae662d31 | 1173 | static int |
b5321f30 | 1174 | i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req) |
ae662d31 | 1175 | { |
7e37f889 | 1176 | struct intel_ring *ring = req->ring; |
ae662d31 EA |
1177 | int ret, i; |
1178 | ||
b5321f30 | 1179 | if (!IS_GEN7(req->i915) || req->engine->id != RCS) { |
9d662da8 DV |
1180 | DRM_DEBUG("sol reset is gen7/rcs only\n"); |
1181 | return -EINVAL; | |
1182 | } | |
ae662d31 | 1183 | |
5fb9de1a | 1184 | ret = intel_ring_begin(req, 4 * 3); |
ae662d31 EA |
1185 | if (ret) |
1186 | return ret; | |
1187 | ||
1188 | for (i = 0; i < 4; i++) { | |
b5321f30 CW |
1189 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
1190 | intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1191 | intel_ring_emit(ring, 0); | |
ae662d31 EA |
1192 | } |
1193 | ||
b5321f30 | 1194 | intel_ring_advance(ring); |
ae662d31 EA |
1195 | |
1196 | return 0; | |
1197 | } | |
1198 | ||
71745376 | 1199 | static struct drm_i915_gem_object* |
0bc40be8 | 1200 | i915_gem_execbuffer_parse(struct intel_engine_cs *engine, |
71745376 BV |
1201 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, |
1202 | struct eb_vmas *eb, | |
1203 | struct drm_i915_gem_object *batch_obj, | |
1204 | u32 batch_start_offset, | |
1205 | u32 batch_len, | |
17cabf57 | 1206 | bool is_master) |
71745376 | 1207 | { |
71745376 | 1208 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1209 | struct i915_vma *vma; |
71745376 BV |
1210 | int ret; |
1211 | ||
0bc40be8 | 1212 | shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool, |
17cabf57 | 1213 | PAGE_ALIGN(batch_len)); |
71745376 BV |
1214 | if (IS_ERR(shadow_batch_obj)) |
1215 | return shadow_batch_obj; | |
1216 | ||
33a051a5 CW |
1217 | ret = intel_engine_cmd_parser(engine, |
1218 | batch_obj, | |
1219 | shadow_batch_obj, | |
1220 | batch_start_offset, | |
1221 | batch_len, | |
1222 | is_master); | |
17cabf57 CW |
1223 | if (ret) |
1224 | goto err; | |
71745376 | 1225 | |
17cabf57 CW |
1226 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); |
1227 | if (ret) | |
1228 | goto err; | |
71745376 | 1229 | |
de4e783a CW |
1230 | i915_gem_object_unpin_pages(shadow_batch_obj); |
1231 | ||
17cabf57 | 1232 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1233 | |
17cabf57 CW |
1234 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1235 | vma->exec_entry = shadow_exec_entry; | |
de4e783a | 1236 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
25dc556a | 1237 | i915_gem_object_get(shadow_batch_obj); |
17cabf57 | 1238 | list_add_tail(&vma->exec_list, &eb->vmas); |
71745376 | 1239 | |
17cabf57 CW |
1240 | shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
1241 | ||
1242 | return shadow_batch_obj; | |
71745376 | 1243 | |
17cabf57 | 1244 | err: |
de4e783a | 1245 | i915_gem_object_unpin_pages(shadow_batch_obj); |
17cabf57 CW |
1246 | if (ret == -EACCES) /* unhandled chained batch */ |
1247 | return batch_obj; | |
1248 | else | |
1249 | return ERR_PTR(ret); | |
71745376 | 1250 | } |
5c6c6003 | 1251 | |
a83014d3 | 1252 | int |
5f19e2bf | 1253 | i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 1254 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1255 | struct list_head *vmas) |
78382593 | 1256 | { |
b5321f30 | 1257 | struct drm_i915_private *dev_priv = params->request->i915; |
5f19e2bf | 1258 | u64 exec_start, exec_len; |
78382593 OM |
1259 | int instp_mode; |
1260 | u32 instp_mask; | |
2f5945bc | 1261 | int ret; |
78382593 | 1262 | |
535fbe82 | 1263 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 | 1264 | if (ret) |
2f5945bc | 1265 | return ret; |
78382593 | 1266 | |
ba01cc93 | 1267 | ret = i915_switch_context(params->request); |
78382593 | 1268 | if (ret) |
2f5945bc | 1269 | return ret; |
78382593 OM |
1270 | |
1271 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
1272 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1273 | switch (instp_mode) { | |
1274 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1275 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1276 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
b5321f30 | 1277 | if (instp_mode != 0 && params->engine->id != RCS) { |
78382593 | 1278 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
2f5945bc | 1279 | return -EINVAL; |
78382593 OM |
1280 | } |
1281 | ||
1282 | if (instp_mode != dev_priv->relative_constants_mode) { | |
b5321f30 | 1283 | if (INTEL_INFO(dev_priv)->gen < 4) { |
78382593 | 1284 | DRM_DEBUG("no rel constants on pre-gen4\n"); |
2f5945bc | 1285 | return -EINVAL; |
78382593 OM |
1286 | } |
1287 | ||
b5321f30 | 1288 | if (INTEL_INFO(dev_priv)->gen > 5 && |
78382593 OM |
1289 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { |
1290 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
2f5945bc | 1291 | return -EINVAL; |
78382593 OM |
1292 | } |
1293 | ||
1294 | /* The HW changed the meaning on this bit on gen6 */ | |
b5321f30 | 1295 | if (INTEL_INFO(dev_priv)->gen >= 6) |
78382593 OM |
1296 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
1297 | } | |
1298 | break; | |
1299 | default: | |
1300 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
2f5945bc | 1301 | return -EINVAL; |
78382593 OM |
1302 | } |
1303 | ||
b5321f30 | 1304 | if (params->engine->id == RCS && |
2f5945bc | 1305 | instp_mode != dev_priv->relative_constants_mode) { |
7e37f889 | 1306 | struct intel_ring *ring = params->request->ring; |
b5321f30 | 1307 | |
5fb9de1a | 1308 | ret = intel_ring_begin(params->request, 4); |
78382593 | 1309 | if (ret) |
2f5945bc | 1310 | return ret; |
78382593 | 1311 | |
b5321f30 CW |
1312 | intel_ring_emit(ring, MI_NOOP); |
1313 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1314 | intel_ring_emit_reg(ring, INSTPM); | |
1315 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1316 | intel_ring_advance(ring); | |
78382593 OM |
1317 | |
1318 | dev_priv->relative_constants_mode = instp_mode; | |
1319 | } | |
1320 | ||
1321 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
b5321f30 | 1322 | ret = i915_reset_gen7_sol_offsets(params->request); |
78382593 | 1323 | if (ret) |
2f5945bc | 1324 | return ret; |
78382593 OM |
1325 | } |
1326 | ||
5f19e2bf JH |
1327 | exec_len = args->batch_len; |
1328 | exec_start = params->batch_obj_vm_offset + | |
1329 | params->args_batch_start_offset; | |
1330 | ||
9d611c03 VS |
1331 | if (exec_len == 0) |
1332 | exec_len = params->batch_obj->base.size; | |
1333 | ||
b5321f30 CW |
1334 | ret = params->engine->dispatch_execbuffer(params->request, |
1335 | exec_start, exec_len, | |
1336 | params->dispatch_flags); | |
2f5945bc CW |
1337 | if (ret) |
1338 | return ret; | |
78382593 | 1339 | |
95c24161 | 1340 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
78382593 | 1341 | |
8a8edb59 | 1342 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
78382593 | 1343 | |
2f5945bc | 1344 | return 0; |
78382593 OM |
1345 | } |
1346 | ||
a8ebba75 ZY |
1347 | /** |
1348 | * Find one BSD ring to dispatch the corresponding BSD command. | |
c80ff16e | 1349 | * The engine index is returned. |
a8ebba75 | 1350 | */ |
de1add36 | 1351 | static unsigned int |
c80ff16e CW |
1352 | gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, |
1353 | struct drm_file *file) | |
a8ebba75 | 1354 | { |
a8ebba75 ZY |
1355 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1356 | ||
de1add36 | 1357 | /* Check whether the file_priv has already selected one ring. */ |
c80ff16e | 1358 | if ((int)file_priv->bsd_engine < 0) { |
de1add36 | 1359 | /* If not, use the ping-pong mechanism to select one. */ |
91c8a326 | 1360 | mutex_lock(&dev_priv->drm.struct_mutex); |
c80ff16e CW |
1361 | file_priv->bsd_engine = dev_priv->mm.bsd_engine_dispatch_index; |
1362 | dev_priv->mm.bsd_engine_dispatch_index ^= 1; | |
91c8a326 | 1363 | mutex_unlock(&dev_priv->drm.struct_mutex); |
a8ebba75 | 1364 | } |
de1add36 | 1365 | |
c80ff16e | 1366 | return file_priv->bsd_engine; |
a8ebba75 ZY |
1367 | } |
1368 | ||
de1add36 TU |
1369 | #define I915_USER_RINGS (4) |
1370 | ||
117897f4 | 1371 | static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { |
de1add36 TU |
1372 | [I915_EXEC_DEFAULT] = RCS, |
1373 | [I915_EXEC_RENDER] = RCS, | |
1374 | [I915_EXEC_BLT] = BCS, | |
1375 | [I915_EXEC_BSD] = VCS, | |
1376 | [I915_EXEC_VEBOX] = VECS | |
1377 | }; | |
1378 | ||
f8ca0c07 DG |
1379 | static struct intel_engine_cs * |
1380 | eb_select_engine(struct drm_i915_private *dev_priv, | |
1381 | struct drm_file *file, | |
1382 | struct drm_i915_gem_execbuffer2 *args) | |
de1add36 TU |
1383 | { |
1384 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
f8ca0c07 | 1385 | struct intel_engine_cs *engine; |
de1add36 TU |
1386 | |
1387 | if (user_ring_id > I915_USER_RINGS) { | |
1388 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
f8ca0c07 | 1389 | return NULL; |
de1add36 TU |
1390 | } |
1391 | ||
1392 | if ((user_ring_id != I915_EXEC_BSD) && | |
1393 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1394 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1395 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
f8ca0c07 | 1396 | return NULL; |
de1add36 TU |
1397 | } |
1398 | ||
1399 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
1400 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
1401 | ||
1402 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
c80ff16e | 1403 | bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file); |
de1add36 TU |
1404 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && |
1405 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 1406 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
1407 | bsd_idx--; |
1408 | } else { | |
1409 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
1410 | bsd_idx); | |
f8ca0c07 | 1411 | return NULL; |
de1add36 TU |
1412 | } |
1413 | ||
f8ca0c07 | 1414 | engine = &dev_priv->engine[_VCS(bsd_idx)]; |
de1add36 | 1415 | } else { |
f8ca0c07 | 1416 | engine = &dev_priv->engine[user_ring_map[user_ring_id]]; |
de1add36 TU |
1417 | } |
1418 | ||
f8ca0c07 | 1419 | if (!intel_engine_initialized(engine)) { |
de1add36 | 1420 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); |
f8ca0c07 | 1421 | return NULL; |
de1add36 TU |
1422 | } |
1423 | ||
f8ca0c07 | 1424 | return engine; |
de1add36 TU |
1425 | } |
1426 | ||
54cf91dc CW |
1427 | static int |
1428 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1429 | struct drm_file *file, | |
1430 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1431 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1432 | { |
72e96d64 JL |
1433 | struct drm_i915_private *dev_priv = to_i915(dev); |
1434 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
26827088 | 1435 | struct drm_i915_gem_request *req = NULL; |
27173f1f | 1436 | struct eb_vmas *eb; |
54cf91dc | 1437 | struct drm_i915_gem_object *batch_obj; |
78a42377 | 1438 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
e2f80391 | 1439 | struct intel_engine_cs *engine; |
e2efd130 | 1440 | struct i915_gem_context *ctx; |
41bde553 | 1441 | struct i915_address_space *vm; |
5f19e2bf JH |
1442 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1443 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1444 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1445 | u32 dispatch_flags; |
78382593 | 1446 | int ret; |
ed5982e6 | 1447 | bool need_relocs; |
54cf91dc | 1448 | |
ed5982e6 | 1449 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1450 | return -EINVAL; |
432e58ed | 1451 | |
ad19f10b | 1452 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1453 | if (ret) |
1454 | return ret; | |
1455 | ||
8e004efc | 1456 | dispatch_flags = 0; |
d7d4eedd | 1457 | if (args->flags & I915_EXEC_SECURE) { |
b3ac9f25 | 1458 | if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) |
d7d4eedd CW |
1459 | return -EPERM; |
1460 | ||
8e004efc | 1461 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1462 | } |
b45305fc | 1463 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1464 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1465 | |
f8ca0c07 DG |
1466 | engine = eb_select_engine(dev_priv, file, args); |
1467 | if (!engine) | |
1468 | return -EINVAL; | |
54cf91dc CW |
1469 | |
1470 | if (args->buffer_count < 1) { | |
ff240199 | 1471 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1472 | return -EINVAL; |
1473 | } | |
54cf91dc | 1474 | |
a9ed33ca AJ |
1475 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
1476 | if (!HAS_RESOURCE_STREAMER(dev)) { | |
1477 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); | |
1478 | return -EINVAL; | |
1479 | } | |
e2f80391 | 1480 | if (engine->id != RCS) { |
a9ed33ca | 1481 | DRM_DEBUG("RS is not available on %s\n", |
e2f80391 | 1482 | engine->name); |
a9ed33ca AJ |
1483 | return -EINVAL; |
1484 | } | |
1485 | ||
1486 | dispatch_flags |= I915_DISPATCH_RS; | |
1487 | } | |
1488 | ||
67d97da3 CW |
1489 | /* Take a local wakeref for preparing to dispatch the execbuf as |
1490 | * we expect to access the hardware fairly frequently in the | |
1491 | * process. Upon first dispatch, we acquire another prolonged | |
1492 | * wakeref that we hold until the GPU has been idle for at least | |
1493 | * 100ms. | |
1494 | */ | |
f65c9168 PZ |
1495 | intel_runtime_pm_get(dev_priv); |
1496 | ||
54cf91dc CW |
1497 | ret = i915_mutex_lock_interruptible(dev); |
1498 | if (ret) | |
1499 | goto pre_mutex_err; | |
1500 | ||
e2f80391 | 1501 | ctx = i915_gem_validate_context(dev, file, engine, ctx_id); |
72ad5c45 | 1502 | if (IS_ERR(ctx)) { |
d299cce7 | 1503 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1504 | ret = PTR_ERR(ctx); |
d299cce7 | 1505 | goto pre_mutex_err; |
935f38d6 | 1506 | } |
41bde553 | 1507 | |
9a6feaf0 | 1508 | i915_gem_context_get(ctx); |
41bde553 | 1509 | |
ae6c4806 DV |
1510 | if (ctx->ppgtt) |
1511 | vm = &ctx->ppgtt->base; | |
1512 | else | |
72e96d64 | 1513 | vm = &ggtt->base; |
d299cce7 | 1514 | |
5f19e2bf JH |
1515 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1516 | ||
17601cbc | 1517 | eb = eb_create(args); |
67731b87 | 1518 | if (eb == NULL) { |
9a6feaf0 | 1519 | i915_gem_context_put(ctx); |
67731b87 CW |
1520 | mutex_unlock(&dev->struct_mutex); |
1521 | ret = -ENOMEM; | |
1522 | goto pre_mutex_err; | |
1523 | } | |
1524 | ||
54cf91dc | 1525 | /* Look up object handles */ |
27173f1f | 1526 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1527 | if (ret) |
1528 | goto err; | |
54cf91dc | 1529 | |
6fe4f140 | 1530 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1531 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1532 | |
54cf91dc | 1533 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1534 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
e2f80391 TU |
1535 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
1536 | &need_relocs); | |
54cf91dc CW |
1537 | if (ret) |
1538 | goto err; | |
1539 | ||
1540 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1541 | if (need_relocs) |
17601cbc | 1542 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1543 | if (ret) { |
1544 | if (ret == -EFAULT) { | |
e2f80391 TU |
1545 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, |
1546 | engine, | |
b1b38278 | 1547 | eb, exec, ctx); |
54cf91dc CW |
1548 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1549 | } | |
1550 | if (ret) | |
1551 | goto err; | |
1552 | } | |
1553 | ||
1554 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1555 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1556 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1557 | ret = -EINVAL; |
1558 | goto err; | |
1559 | } | |
54cf91dc | 1560 | |
5f19e2bf | 1561 | params->args_batch_start_offset = args->batch_start_offset; |
33a051a5 | 1562 | if (intel_engine_needs_cmd_parser(engine) && args->batch_len) { |
c7c7372e RP |
1563 | struct drm_i915_gem_object *parsed_batch_obj; |
1564 | ||
e2f80391 TU |
1565 | parsed_batch_obj = i915_gem_execbuffer_parse(engine, |
1566 | &shadow_exec_entry, | |
1567 | eb, | |
1568 | batch_obj, | |
1569 | args->batch_start_offset, | |
1570 | args->batch_len, | |
b3ac9f25 | 1571 | drm_is_current_master(file)); |
c7c7372e RP |
1572 | if (IS_ERR(parsed_batch_obj)) { |
1573 | ret = PTR_ERR(parsed_batch_obj); | |
78a42377 BV |
1574 | goto err; |
1575 | } | |
17cabf57 CW |
1576 | |
1577 | /* | |
c7c7372e RP |
1578 | * parsed_batch_obj == batch_obj means batch not fully parsed: |
1579 | * Accept, but don't promote to secure. | |
17cabf57 | 1580 | */ |
17cabf57 | 1581 | |
c7c7372e RP |
1582 | if (parsed_batch_obj != batch_obj) { |
1583 | /* | |
1584 | * Batch parsed and accepted: | |
1585 | * | |
1586 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1587 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1588 | * the dispatch_execbuffer implementations. We | |
1589 | * specifically don't want that set on batches the | |
1590 | * command parser has accepted. | |
1591 | */ | |
1592 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1593 | params->args_batch_start_offset = 0; |
c7c7372e RP |
1594 | batch_obj = parsed_batch_obj; |
1595 | } | |
351e3db2 BV |
1596 | } |
1597 | ||
78a42377 BV |
1598 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1599 | ||
d7d4eedd CW |
1600 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1601 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1602 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1603 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
da51a1e7 DV |
1604 | /* |
1605 | * So on first glance it looks freaky that we pin the batch here | |
1606 | * outside of the reservation loop. But: | |
1607 | * - The batch is already pinned into the relevant ppgtt, so we | |
1608 | * already have the backing storage fully allocated. | |
1609 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1610 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1611 | * fitting due to fragmentation. |
1612 | * So this is actually safe. | |
1613 | */ | |
1614 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1615 | if (ret) | |
1616 | goto err; | |
d7d4eedd | 1617 | |
5f19e2bf | 1618 | params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1619 | } else |
5f19e2bf | 1620 | params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1621 | |
0c8dac88 | 1622 | /* Allocate a request for this batch buffer nice and early. */ |
e2f80391 | 1623 | req = i915_gem_request_alloc(engine, ctx); |
26827088 DG |
1624 | if (IS_ERR(req)) { |
1625 | ret = PTR_ERR(req); | |
0c8dac88 | 1626 | goto err_batch_unpin; |
26827088 | 1627 | } |
0c8dac88 | 1628 | |
26827088 | 1629 | ret = i915_gem_request_add_to_client(req, file); |
fcfa423c | 1630 | if (ret) |
aa9b7810 | 1631 | goto err_request; |
fcfa423c | 1632 | |
5f19e2bf JH |
1633 | /* |
1634 | * Save assorted stuff away to pass through to *_submission(). | |
1635 | * NB: This data should be 'persistent' and not local as it will | |
1636 | * kept around beyond the duration of the IOCTL once the GPU | |
1637 | * scheduler arrives. | |
1638 | */ | |
1639 | params->dev = dev; | |
1640 | params->file = file; | |
4a570db5 | 1641 | params->engine = engine; |
5f19e2bf JH |
1642 | params->dispatch_flags = dispatch_flags; |
1643 | params->batch_obj = batch_obj; | |
1644 | params->ctx = ctx; | |
26827088 | 1645 | params->request = req; |
5f19e2bf JH |
1646 | |
1647 | ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas); | |
aa9b7810 CW |
1648 | err_request: |
1649 | i915_gem_execbuffer_retire_commands(params); | |
54cf91dc | 1650 | |
0c8dac88 | 1651 | err_batch_unpin: |
da51a1e7 DV |
1652 | /* |
1653 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1654 | * batch vma for correctness. For less ugly and less fragility this | |
1655 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1656 | * active. | |
1657 | */ | |
8e004efc | 1658 | if (dispatch_flags & I915_DISPATCH_SECURE) |
da51a1e7 | 1659 | i915_gem_object_ggtt_unpin(batch_obj); |
0c8dac88 | 1660 | |
54cf91dc | 1661 | err: |
41bde553 | 1662 | /* the request owns the ref now */ |
9a6feaf0 | 1663 | i915_gem_context_put(ctx); |
67731b87 | 1664 | eb_destroy(eb); |
54cf91dc CW |
1665 | |
1666 | mutex_unlock(&dev->struct_mutex); | |
1667 | ||
1668 | pre_mutex_err: | |
f65c9168 PZ |
1669 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1670 | * is really idle. */ | |
1671 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1672 | return ret; |
1673 | } | |
1674 | ||
1675 | /* | |
1676 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1677 | * list array and passes it to the real function. | |
1678 | */ | |
1679 | int | |
1680 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1681 | struct drm_file *file) | |
1682 | { | |
1683 | struct drm_i915_gem_execbuffer *args = data; | |
1684 | struct drm_i915_gem_execbuffer2 exec2; | |
1685 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1686 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1687 | int ret, i; | |
1688 | ||
54cf91dc | 1689 | if (args->buffer_count < 1) { |
ff240199 | 1690 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1691 | return -EINVAL; |
1692 | } | |
1693 | ||
1694 | /* Copy in the exec list from userland */ | |
1695 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1696 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1697 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1698 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1699 | args->buffer_count); |
1700 | drm_free_large(exec_list); | |
1701 | drm_free_large(exec2_list); | |
1702 | return -ENOMEM; | |
1703 | } | |
1704 | ret = copy_from_user(exec_list, | |
3ed605bc | 1705 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1706 | sizeof(*exec_list) * args->buffer_count); |
1707 | if (ret != 0) { | |
ff240199 | 1708 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1709 | args->buffer_count, ret); |
1710 | drm_free_large(exec_list); | |
1711 | drm_free_large(exec2_list); | |
1712 | return -EFAULT; | |
1713 | } | |
1714 | ||
1715 | for (i = 0; i < args->buffer_count; i++) { | |
1716 | exec2_list[i].handle = exec_list[i].handle; | |
1717 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1718 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1719 | exec2_list[i].alignment = exec_list[i].alignment; | |
1720 | exec2_list[i].offset = exec_list[i].offset; | |
1721 | if (INTEL_INFO(dev)->gen < 4) | |
1722 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1723 | else | |
1724 | exec2_list[i].flags = 0; | |
1725 | } | |
1726 | ||
1727 | exec2.buffers_ptr = args->buffers_ptr; | |
1728 | exec2.buffer_count = args->buffer_count; | |
1729 | exec2.batch_start_offset = args->batch_start_offset; | |
1730 | exec2.batch_len = args->batch_len; | |
1731 | exec2.DR1 = args->DR1; | |
1732 | exec2.DR4 = args->DR4; | |
1733 | exec2.num_cliprects = args->num_cliprects; | |
1734 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1735 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1736 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1737 | |
41bde553 | 1738 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1739 | if (!ret) { |
9aab8bff | 1740 | struct drm_i915_gem_exec_object __user *user_exec_list = |
3ed605bc | 1741 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff | 1742 | |
54cf91dc | 1743 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 1744 | for (i = 0; i < args->buffer_count; i++) { |
934acce3 MW |
1745 | exec2_list[i].offset = |
1746 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1747 | ret = __copy_to_user(&user_exec_list[i].offset, |
1748 | &exec2_list[i].offset, | |
1749 | sizeof(user_exec_list[i].offset)); | |
1750 | if (ret) { | |
1751 | ret = -EFAULT; | |
1752 | DRM_DEBUG("failed to copy %d exec entries " | |
1753 | "back to user (%d)\n", | |
1754 | args->buffer_count, ret); | |
1755 | break; | |
1756 | } | |
54cf91dc CW |
1757 | } |
1758 | } | |
1759 | ||
1760 | drm_free_large(exec_list); | |
1761 | drm_free_large(exec2_list); | |
1762 | return ret; | |
1763 | } | |
1764 | ||
1765 | int | |
1766 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1767 | struct drm_file *file) | |
1768 | { | |
1769 | struct drm_i915_gem_execbuffer2 *args = data; | |
1770 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1771 | int ret; | |
1772 | ||
ed8cd3b2 XW |
1773 | if (args->buffer_count < 1 || |
1774 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1775 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1776 | return -EINVAL; |
1777 | } | |
1778 | ||
9cb34664 DV |
1779 | if (args->rsvd2 != 0) { |
1780 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1781 | return -EINVAL; | |
1782 | } | |
1783 | ||
f2a85e19 CW |
1784 | exec2_list = drm_malloc_gfp(args->buffer_count, |
1785 | sizeof(*exec2_list), | |
1786 | GFP_TEMPORARY); | |
54cf91dc | 1787 | if (exec2_list == NULL) { |
ff240199 | 1788 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1789 | args->buffer_count); |
1790 | return -ENOMEM; | |
1791 | } | |
1792 | ret = copy_from_user(exec2_list, | |
3ed605bc | 1793 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1794 | sizeof(*exec2_list) * args->buffer_count); |
1795 | if (ret != 0) { | |
ff240199 | 1796 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1797 | args->buffer_count, ret); |
1798 | drm_free_large(exec2_list); | |
1799 | return -EFAULT; | |
1800 | } | |
1801 | ||
41bde553 | 1802 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1803 | if (!ret) { |
1804 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1805 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
3ed605bc | 1806 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff CW |
1807 | int i; |
1808 | ||
1809 | for (i = 0; i < args->buffer_count; i++) { | |
934acce3 MW |
1810 | exec2_list[i].offset = |
1811 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1812 | ret = __copy_to_user(&user_exec_list[i].offset, |
1813 | &exec2_list[i].offset, | |
1814 | sizeof(user_exec_list[i].offset)); | |
1815 | if (ret) { | |
1816 | ret = -EFAULT; | |
1817 | DRM_DEBUG("failed to copy %d exec entries " | |
1818 | "back to user\n", | |
1819 | args->buffer_count); | |
1820 | break; | |
1821 | } | |
54cf91dc CW |
1822 | } |
1823 | } | |
1824 | ||
1825 | drm_free_large(exec2_list); | |
1826 | return ret; | |
1827 | } |