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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
32d82067 | 35 | #include <linux/uaccess.h> |
54cf91dc | 36 | |
a415d355 CW |
37 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
38 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 39 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c CW |
40 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
41 | ||
42 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 43 | |
27173f1f BW |
44 | struct eb_vmas { |
45 | struct list_head vmas; | |
67731b87 | 46 | int and; |
eef90ccb | 47 | union { |
27173f1f | 48 | struct i915_vma *lut[0]; |
eef90ccb CW |
49 | struct hlist_head buckets[0]; |
50 | }; | |
67731b87 CW |
51 | }; |
52 | ||
27173f1f | 53 | static struct eb_vmas * |
17601cbc | 54 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 55 | { |
27173f1f | 56 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
57 | |
58 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 59 | unsigned size = args->buffer_count; |
27173f1f BW |
60 | size *= sizeof(struct i915_vma *); |
61 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
62 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
63 | } | |
64 | ||
65 | if (eb == NULL) { | |
b205ca57 DV |
66 | unsigned size = args->buffer_count; |
67 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 68 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
69 | while (count > 2*size) |
70 | count >>= 1; | |
71 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 72 | sizeof(struct eb_vmas), |
eef90ccb CW |
73 | GFP_TEMPORARY); |
74 | if (eb == NULL) | |
75 | return eb; | |
76 | ||
77 | eb->and = count - 1; | |
78 | } else | |
79 | eb->and = -args->buffer_count; | |
80 | ||
27173f1f | 81 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
82 | return eb; |
83 | } | |
84 | ||
85 | static void | |
27173f1f | 86 | eb_reset(struct eb_vmas *eb) |
67731b87 | 87 | { |
eef90ccb CW |
88 | if (eb->and >= 0) |
89 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
90 | } |
91 | ||
3b96eff4 | 92 | static int |
27173f1f BW |
93 | eb_lookup_vmas(struct eb_vmas *eb, |
94 | struct drm_i915_gem_exec_object2 *exec, | |
95 | const struct drm_i915_gem_execbuffer2 *args, | |
96 | struct i915_address_space *vm, | |
97 | struct drm_file *file) | |
3b96eff4 | 98 | { |
27173f1f BW |
99 | struct drm_i915_gem_object *obj; |
100 | struct list_head objects; | |
9ae9ab52 | 101 | int i, ret; |
3b96eff4 | 102 | |
27173f1f | 103 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 104 | spin_lock(&file->table_lock); |
27173f1f BW |
105 | /* Grab a reference to the object and release the lock so we can lookup |
106 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 107 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
108 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
109 | if (obj == NULL) { | |
110 | spin_unlock(&file->table_lock); | |
111 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
112 | exec[i].handle, i); | |
27173f1f | 113 | ret = -ENOENT; |
9ae9ab52 | 114 | goto err; |
3b96eff4 CW |
115 | } |
116 | ||
27173f1f | 117 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
118 | spin_unlock(&file->table_lock); |
119 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
120 | obj, exec[i].handle, i); | |
27173f1f | 121 | ret = -EINVAL; |
9ae9ab52 | 122 | goto err; |
3b96eff4 CW |
123 | } |
124 | ||
125 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
126 | list_add_tail(&obj->obj_exec_link, &objects); |
127 | } | |
128 | spin_unlock(&file->table_lock); | |
3b96eff4 | 129 | |
27173f1f | 130 | i = 0; |
9ae9ab52 | 131 | while (!list_empty(&objects)) { |
27173f1f | 132 | struct i915_vma *vma; |
6f65e29a | 133 | |
9ae9ab52 CW |
134 | obj = list_first_entry(&objects, |
135 | struct drm_i915_gem_object, | |
136 | obj_exec_link); | |
137 | ||
e656a6cb DV |
138 | /* |
139 | * NOTE: We can leak any vmas created here when something fails | |
140 | * later on. But that's no issue since vma_unbind can deal with | |
141 | * vmas which are not actually bound. And since only | |
142 | * lookup_or_create exists as an interface to get at the vma | |
143 | * from the (obj, vm) we don't run the risk of creating | |
144 | * duplicated vmas for the same vm. | |
145 | */ | |
da51a1e7 | 146 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 147 | if (IS_ERR(vma)) { |
27173f1f BW |
148 | DRM_DEBUG("Failed to lookup VMA\n"); |
149 | ret = PTR_ERR(vma); | |
9ae9ab52 | 150 | goto err; |
27173f1f BW |
151 | } |
152 | ||
9ae9ab52 | 153 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 154 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 155 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
156 | |
157 | vma->exec_entry = &exec[i]; | |
eef90ccb | 158 | if (eb->and < 0) { |
27173f1f | 159 | eb->lut[i] = vma; |
eef90ccb CW |
160 | } else { |
161 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
162 | vma->exec_handle = handle; |
163 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
164 | &eb->buckets[handle & eb->and]); |
165 | } | |
27173f1f | 166 | ++i; |
3b96eff4 | 167 | } |
3b96eff4 | 168 | |
9ae9ab52 | 169 | return 0; |
27173f1f | 170 | |
27173f1f | 171 | |
9ae9ab52 | 172 | err: |
27173f1f BW |
173 | while (!list_empty(&objects)) { |
174 | obj = list_first_entry(&objects, | |
175 | struct drm_i915_gem_object, | |
176 | obj_exec_link); | |
177 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 178 | drm_gem_object_unreference(&obj->base); |
27173f1f | 179 | } |
9ae9ab52 CW |
180 | /* |
181 | * Objects already transfered to the vmas list will be unreferenced by | |
182 | * eb_destroy. | |
183 | */ | |
184 | ||
27173f1f | 185 | return ret; |
3b96eff4 CW |
186 | } |
187 | ||
27173f1f | 188 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 189 | { |
eef90ccb CW |
190 | if (eb->and < 0) { |
191 | if (handle >= -eb->and) | |
192 | return NULL; | |
193 | return eb->lut[handle]; | |
194 | } else { | |
195 | struct hlist_head *head; | |
aa45950b | 196 | struct i915_vma *vma; |
67731b87 | 197 | |
eef90ccb | 198 | head = &eb->buckets[handle & eb->and]; |
aa45950b | 199 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
200 | if (vma->exec_handle == handle) |
201 | return vma; | |
eef90ccb CW |
202 | } |
203 | return NULL; | |
204 | } | |
67731b87 CW |
205 | } |
206 | ||
a415d355 CW |
207 | static void |
208 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
209 | { | |
210 | struct drm_i915_gem_exec_object2 *entry; | |
211 | struct drm_i915_gem_object *obj = vma->obj; | |
212 | ||
213 | if (!drm_mm_node_allocated(&vma->node)) | |
214 | return; | |
215 | ||
216 | entry = vma->exec_entry; | |
217 | ||
218 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
219 | i915_gem_object_unpin_fence(obj); | |
220 | ||
221 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 222 | vma->pin_count--; |
a415d355 | 223 | |
de4e783a | 224 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
225 | } |
226 | ||
227 | static void eb_destroy(struct eb_vmas *eb) | |
228 | { | |
27173f1f BW |
229 | while (!list_empty(&eb->vmas)) { |
230 | struct i915_vma *vma; | |
bcffc3fa | 231 | |
27173f1f BW |
232 | vma = list_first_entry(&eb->vmas, |
233 | struct i915_vma, | |
bcffc3fa | 234 | exec_list); |
27173f1f | 235 | list_del_init(&vma->exec_list); |
a415d355 | 236 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 237 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 238 | } |
67731b87 CW |
239 | kfree(eb); |
240 | } | |
241 | ||
dabdfe02 CW |
242 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
243 | { | |
2cc86b82 CW |
244 | return (HAS_LLC(obj->base.dev) || |
245 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
dabdfe02 CW |
246 | obj->cache_level != I915_CACHE_NONE); |
247 | } | |
248 | ||
934acce3 MW |
249 | /* Used to convert any address to canonical form. |
250 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
251 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
252 | * addresses to be in a canonical form: | |
253 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
254 | * canonical form [63:48] == [47]." | |
255 | */ | |
256 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
257 | static inline uint64_t gen8_canonical_addr(uint64_t address) | |
258 | { | |
259 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
260 | } | |
261 | ||
262 | static inline uint64_t gen8_noncanonical_addr(uint64_t address) | |
263 | { | |
264 | return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1); | |
265 | } | |
266 | ||
267 | static inline uint64_t | |
268 | relocation_target(struct drm_i915_gem_relocation_entry *reloc, | |
269 | uint64_t target_offset) | |
270 | { | |
271 | return gen8_canonical_addr((int)reloc->delta + target_offset); | |
272 | } | |
273 | ||
5032d871 RB |
274 | static int |
275 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
276 | struct drm_i915_gem_relocation_entry *reloc, |
277 | uint64_t target_offset) | |
5032d871 | 278 | { |
3c94ceee | 279 | struct drm_device *dev = obj->base.dev; |
5032d871 | 280 | uint32_t page_offset = offset_in_page(reloc->offset); |
934acce3 | 281 | uint64_t delta = relocation_target(reloc, target_offset); |
5032d871 | 282 | char *vaddr; |
8b78f0e5 | 283 | int ret; |
5032d871 | 284 | |
2cc86b82 | 285 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
286 | if (ret) |
287 | return ret; | |
288 | ||
033908ae | 289 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
5032d871 | 290 | reloc->offset >> PAGE_SHIFT)); |
d9ceb957 | 291 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
292 | |
293 | if (INTEL_INFO(dev)->gen >= 8) { | |
294 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
295 | ||
296 | if (page_offset == 0) { | |
297 | kunmap_atomic(vaddr); | |
033908ae | 298 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
3c94ceee BW |
299 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
300 | } | |
301 | ||
d9ceb957 | 302 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
303 | } |
304 | ||
5032d871 RB |
305 | kunmap_atomic(vaddr); |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static int | |
311 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
312 | struct drm_i915_gem_relocation_entry *reloc, |
313 | uint64_t target_offset) | |
5032d871 RB |
314 | { |
315 | struct drm_device *dev = obj->base.dev; | |
316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
934acce3 | 317 | uint64_t delta = relocation_target(reloc, target_offset); |
906843c3 | 318 | uint64_t offset; |
5032d871 | 319 | void __iomem *reloc_page; |
8b78f0e5 | 320 | int ret; |
5032d871 RB |
321 | |
322 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
323 | if (ret) | |
324 | return ret; | |
325 | ||
326 | ret = i915_gem_object_put_fence(obj); | |
327 | if (ret) | |
328 | return ret; | |
329 | ||
330 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
331 | offset = i915_gem_obj_ggtt_offset(obj); |
332 | offset += reloc->offset; | |
5032d871 | 333 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
906843c3 CW |
334 | offset & PAGE_MASK); |
335 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
336 | |
337 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 338 | offset += sizeof(uint32_t); |
3c94ceee | 339 | |
906843c3 | 340 | if (offset_in_page(offset) == 0) { |
3c94ceee | 341 | io_mapping_unmap_atomic(reloc_page); |
906843c3 CW |
342 | reloc_page = |
343 | io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
344 | offset); | |
3c94ceee BW |
345 | } |
346 | ||
906843c3 CW |
347 | iowrite32(upper_32_bits(delta), |
348 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
349 | } |
350 | ||
5032d871 RB |
351 | io_mapping_unmap_atomic(reloc_page); |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
edf4427b CW |
356 | static void |
357 | clflush_write32(void *addr, uint32_t value) | |
358 | { | |
359 | /* This is not a fast path, so KISS. */ | |
360 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
361 | *(uint32_t *)addr = value; | |
362 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
363 | } | |
364 | ||
365 | static int | |
366 | relocate_entry_clflush(struct drm_i915_gem_object *obj, | |
367 | struct drm_i915_gem_relocation_entry *reloc, | |
368 | uint64_t target_offset) | |
369 | { | |
370 | struct drm_device *dev = obj->base.dev; | |
371 | uint32_t page_offset = offset_in_page(reloc->offset); | |
934acce3 | 372 | uint64_t delta = relocation_target(reloc, target_offset); |
edf4427b CW |
373 | char *vaddr; |
374 | int ret; | |
375 | ||
376 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
377 | if (ret) | |
378 | return ret; | |
379 | ||
033908ae | 380 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
381 | reloc->offset >> PAGE_SHIFT)); |
382 | clflush_write32(vaddr + page_offset, lower_32_bits(delta)); | |
383 | ||
384 | if (INTEL_INFO(dev)->gen >= 8) { | |
385 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
386 | ||
387 | if (page_offset == 0) { | |
388 | kunmap_atomic(vaddr); | |
033908ae | 389 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
390 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
391 | } | |
392 | ||
393 | clflush_write32(vaddr + page_offset, upper_32_bits(delta)); | |
394 | } | |
395 | ||
396 | kunmap_atomic(vaddr); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
54cf91dc CW |
401 | static int |
402 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 403 | struct eb_vmas *eb, |
3e7a0322 | 404 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
405 | { |
406 | struct drm_device *dev = obj->base.dev; | |
407 | struct drm_gem_object *target_obj; | |
149c8407 | 408 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 409 | struct i915_vma *target_vma; |
d9ceb957 | 410 | uint64_t target_offset; |
8b78f0e5 | 411 | int ret; |
54cf91dc | 412 | |
67731b87 | 413 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
414 | target_vma = eb_get_vma(eb, reloc->target_handle); |
415 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 416 | return -ENOENT; |
27173f1f BW |
417 | target_i915_obj = target_vma->obj; |
418 | target_obj = &target_vma->obj->base; | |
54cf91dc | 419 | |
934acce3 | 420 | target_offset = gen8_canonical_addr(target_vma->node.start); |
54cf91dc | 421 | |
e844b990 EA |
422 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
423 | * pipe_control writes because the gpu doesn't properly redirect them | |
424 | * through the ppgtt for non_secure batchbuffers. */ | |
425 | if (unlikely(IS_GEN6(dev) && | |
0875546c | 426 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 427 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 428 | PIN_GLOBAL); |
fe14d5f4 TU |
429 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
430 | return ret; | |
431 | } | |
e844b990 | 432 | |
54cf91dc | 433 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 434 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 435 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
436 | "obj %p target %d offset %d " |
437 | "read %08x write %08x", | |
438 | obj, reloc->target_handle, | |
439 | (int) reloc->offset, | |
440 | reloc->read_domains, | |
441 | reloc->write_domain); | |
8b78f0e5 | 442 | return -EINVAL; |
54cf91dc | 443 | } |
4ca4a250 DV |
444 | if (unlikely((reloc->write_domain | reloc->read_domains) |
445 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 446 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
447 | "obj %p target %d offset %d " |
448 | "read %08x write %08x", | |
449 | obj, reloc->target_handle, | |
450 | (int) reloc->offset, | |
451 | reloc->read_domains, | |
452 | reloc->write_domain); | |
8b78f0e5 | 453 | return -EINVAL; |
54cf91dc | 454 | } |
54cf91dc CW |
455 | |
456 | target_obj->pending_read_domains |= reloc->read_domains; | |
457 | target_obj->pending_write_domain |= reloc->write_domain; | |
458 | ||
459 | /* If the relocation already has the right value in it, no | |
460 | * more work needs to be done. | |
461 | */ | |
462 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 463 | return 0; |
54cf91dc CW |
464 | |
465 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
466 | if (unlikely(reloc->offset > |
467 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 468 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
469 | "obj %p target %d offset %d size %d.\n", |
470 | obj, reloc->target_handle, | |
471 | (int) reloc->offset, | |
472 | (int) obj->base.size); | |
8b78f0e5 | 473 | return -EINVAL; |
54cf91dc | 474 | } |
b8f7ab17 | 475 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 476 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
477 | "obj %p target %d offset %d.\n", |
478 | obj, reloc->target_handle, | |
479 | (int) reloc->offset); | |
8b78f0e5 | 480 | return -EINVAL; |
54cf91dc CW |
481 | } |
482 | ||
dabdfe02 | 483 | /* We can't wait for rendering with pagefaults disabled */ |
32d82067 | 484 | if (obj->active && pagefault_disabled()) |
dabdfe02 CW |
485 | return -EFAULT; |
486 | ||
5032d871 | 487 | if (use_cpu_reloc(obj)) |
d9ceb957 | 488 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
edf4427b | 489 | else if (obj->map_and_fenceable) |
d9ceb957 | 490 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
edf4427b CW |
491 | else if (cpu_has_clflush) |
492 | ret = relocate_entry_clflush(obj, reloc, target_offset); | |
493 | else { | |
494 | WARN_ONCE(1, "Impossible case in relocation handling\n"); | |
495 | ret = -ENODEV; | |
496 | } | |
54cf91dc | 497 | |
d4d36014 DV |
498 | if (ret) |
499 | return ret; | |
500 | ||
54cf91dc CW |
501 | /* and update the user's relocation entry */ |
502 | reloc->presumed_offset = target_offset; | |
503 | ||
67731b87 | 504 | return 0; |
54cf91dc CW |
505 | } |
506 | ||
507 | static int | |
27173f1f BW |
508 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
509 | struct eb_vmas *eb) | |
54cf91dc | 510 | { |
1d83f442 CW |
511 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
512 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 513 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 514 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 515 | int remain, ret; |
54cf91dc | 516 | |
2bb4629a | 517 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 518 | |
1d83f442 CW |
519 | remain = entry->relocation_count; |
520 | while (remain) { | |
521 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
522 | int count = remain; | |
523 | if (count > ARRAY_SIZE(stack_reloc)) | |
524 | count = ARRAY_SIZE(stack_reloc); | |
525 | remain -= count; | |
526 | ||
527 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
528 | return -EFAULT; |
529 | ||
1d83f442 CW |
530 | do { |
531 | u64 offset = r->presumed_offset; | |
54cf91dc | 532 | |
3e7a0322 | 533 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
534 | if (ret) |
535 | return ret; | |
536 | ||
537 | if (r->presumed_offset != offset && | |
538 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
539 | &r->presumed_offset, | |
540 | sizeof(r->presumed_offset))) { | |
541 | return -EFAULT; | |
542 | } | |
543 | ||
544 | user_relocs++; | |
545 | r++; | |
546 | } while (--count); | |
54cf91dc CW |
547 | } |
548 | ||
549 | return 0; | |
1d83f442 | 550 | #undef N_RELOC |
54cf91dc CW |
551 | } |
552 | ||
553 | static int | |
27173f1f BW |
554 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
555 | struct eb_vmas *eb, | |
556 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 557 | { |
27173f1f | 558 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
559 | int i, ret; |
560 | ||
561 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 562 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
563 | if (ret) |
564 | return ret; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static int | |
17601cbc | 571 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 572 | { |
27173f1f | 573 | struct i915_vma *vma; |
d4aeee77 CW |
574 | int ret = 0; |
575 | ||
576 | /* This is the fast path and we cannot handle a pagefault whilst | |
577 | * holding the struct mutex lest the user pass in the relocations | |
578 | * contained within a mmaped bo. For in such a case we, the page | |
579 | * fault handler would call i915_gem_fault() and we would try to | |
580 | * acquire the struct mutex again. Obviously this is bad and so | |
581 | * lockdep complains vehemently. | |
582 | */ | |
583 | pagefault_disable(); | |
27173f1f BW |
584 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
585 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 586 | if (ret) |
d4aeee77 | 587 | break; |
54cf91dc | 588 | } |
d4aeee77 | 589 | pagefault_enable(); |
54cf91dc | 590 | |
d4aeee77 | 591 | return ret; |
54cf91dc CW |
592 | } |
593 | ||
edf4427b CW |
594 | static bool only_mappable_for_reloc(unsigned int flags) |
595 | { | |
596 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
597 | __EXEC_OBJECT_NEEDS_MAP; | |
598 | } | |
599 | ||
1690e1eb | 600 | static int |
27173f1f | 601 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 602 | struct intel_engine_cs *ring, |
27173f1f | 603 | bool *need_reloc) |
1690e1eb | 604 | { |
6f65e29a | 605 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 606 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 607 | uint64_t flags; |
1690e1eb CW |
608 | int ret; |
609 | ||
0875546c | 610 | flags = PIN_USER; |
0229da32 DV |
611 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
612 | flags |= PIN_GLOBAL; | |
613 | ||
edf4427b | 614 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
615 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
616 | * limit address to the first 4GBs for unflagged objects. | |
617 | */ | |
618 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
619 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
620 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
621 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
622 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
623 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
624 | if (entry->flags & EXEC_OBJECT_PINNED) |
625 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
626 | if ((flags & PIN_MAPPABLE) == 0) |
627 | flags |= PIN_HIGH; | |
edf4427b | 628 | } |
1ec9e26d DV |
629 | |
630 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
edf4427b CW |
631 | if ((ret == -ENOSPC || ret == -E2BIG) && |
632 | only_mappable_for_reloc(entry->flags)) | |
633 | ret = i915_gem_object_pin(obj, vma->vm, | |
634 | entry->alignment, | |
0229da32 | 635 | flags & ~PIN_MAPPABLE); |
1690e1eb CW |
636 | if (ret) |
637 | return ret; | |
638 | ||
7788a765 CW |
639 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
640 | ||
82b6b6d7 CW |
641 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
642 | ret = i915_gem_object_get_fence(obj); | |
643 | if (ret) | |
644 | return ret; | |
9a5a53b3 | 645 | |
82b6b6d7 CW |
646 | if (i915_gem_object_pin_fence(obj)) |
647 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
648 | } |
649 | ||
27173f1f BW |
650 | if (entry->offset != vma->node.start) { |
651 | entry->offset = vma->node.start; | |
ed5982e6 DV |
652 | *need_reloc = true; |
653 | } | |
654 | ||
655 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
656 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
657 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
658 | } | |
659 | ||
1690e1eb | 660 | return 0; |
7788a765 | 661 | } |
1690e1eb | 662 | |
d23db88c | 663 | static bool |
e6a84468 | 664 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
665 | { |
666 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 667 | |
e6a84468 CW |
668 | if (entry->relocation_count == 0) |
669 | return false; | |
670 | ||
671 | if (!i915_is_ggtt(vma->vm)) | |
672 | return false; | |
673 | ||
674 | /* See also use_cpu_reloc() */ | |
675 | if (HAS_LLC(vma->obj->base.dev)) | |
676 | return false; | |
677 | ||
678 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
679 | return false; | |
680 | ||
681 | return true; | |
682 | } | |
683 | ||
684 | static bool | |
685 | eb_vma_misplaced(struct i915_vma *vma) | |
686 | { | |
687 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
688 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 689 | |
e6a84468 | 690 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
d23db88c CW |
691 | !i915_is_ggtt(vma->vm)); |
692 | ||
693 | if (entry->alignment && | |
694 | vma->node.start & (entry->alignment - 1)) | |
695 | return true; | |
696 | ||
506a8e87 CW |
697 | if (entry->flags & EXEC_OBJECT_PINNED && |
698 | vma->node.start != entry->offset) | |
699 | return true; | |
700 | ||
d23db88c CW |
701 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
702 | vma->node.start < BATCH_OFFSET_BIAS) | |
703 | return true; | |
704 | ||
edf4427b CW |
705 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
706 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) | |
707 | return !only_mappable_for_reloc(entry->flags); | |
708 | ||
101b506a MT |
709 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
710 | (vma->node.start + vma->node.size - 1) >> 32) | |
711 | return true; | |
712 | ||
d23db88c CW |
713 | return false; |
714 | } | |
715 | ||
54cf91dc | 716 | static int |
a4872ba6 | 717 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 718 | struct list_head *vmas, |
b1b38278 | 719 | struct intel_context *ctx, |
ed5982e6 | 720 | bool *need_relocs) |
54cf91dc | 721 | { |
432e58ed | 722 | struct drm_i915_gem_object *obj; |
27173f1f | 723 | struct i915_vma *vma; |
68c8c17f | 724 | struct i915_address_space *vm; |
27173f1f | 725 | struct list_head ordered_vmas; |
506a8e87 | 726 | struct list_head pinned_vmas; |
7788a765 CW |
727 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
728 | int retry; | |
6fe4f140 | 729 | |
227f782e CW |
730 | i915_gem_retire_requests_ring(ring); |
731 | ||
68c8c17f BW |
732 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
733 | ||
27173f1f | 734 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 735 | INIT_LIST_HEAD(&pinned_vmas); |
27173f1f | 736 | while (!list_empty(vmas)) { |
6fe4f140 CW |
737 | struct drm_i915_gem_exec_object2 *entry; |
738 | bool need_fence, need_mappable; | |
739 | ||
27173f1f BW |
740 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
741 | obj = vma->obj; | |
742 | entry = vma->exec_entry; | |
6fe4f140 | 743 | |
b1b38278 DW |
744 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
745 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
746 | ||
82b6b6d7 CW |
747 | if (!has_fenced_gpu_access) |
748 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 749 | need_fence = |
6fe4f140 CW |
750 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
751 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 752 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 753 | |
506a8e87 CW |
754 | if (entry->flags & EXEC_OBJECT_PINNED) |
755 | list_move_tail(&vma->exec_list, &pinned_vmas); | |
756 | else if (need_mappable) { | |
e6a84468 | 757 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
27173f1f | 758 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 759 | } else |
27173f1f | 760 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 761 | |
ed5982e6 | 762 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 763 | obj->base.pending_write_domain = 0; |
6fe4f140 | 764 | } |
27173f1f | 765 | list_splice(&ordered_vmas, vmas); |
506a8e87 | 766 | list_splice(&pinned_vmas, vmas); |
54cf91dc CW |
767 | |
768 | /* Attempt to pin all of the buffers into the GTT. | |
769 | * This is done in 3 phases: | |
770 | * | |
771 | * 1a. Unbind all objects that do not match the GTT constraints for | |
772 | * the execbuffer (fenceable, mappable, alignment etc). | |
773 | * 1b. Increment pin count for already bound objects. | |
774 | * 2. Bind new objects. | |
775 | * 3. Decrement pin count. | |
776 | * | |
7788a765 | 777 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
778 | * room for the earlier objects *unless* we need to defragment. |
779 | */ | |
780 | retry = 0; | |
781 | do { | |
7788a765 | 782 | int ret = 0; |
54cf91dc CW |
783 | |
784 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 785 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 786 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
787 | continue; |
788 | ||
e6a84468 | 789 | if (eb_vma_misplaced(vma)) |
27173f1f | 790 | ret = i915_vma_unbind(vma); |
54cf91dc | 791 | else |
27173f1f | 792 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 793 | if (ret) |
54cf91dc | 794 | goto err; |
54cf91dc CW |
795 | } |
796 | ||
797 | /* Bind fresh objects */ | |
27173f1f BW |
798 | list_for_each_entry(vma, vmas, exec_list) { |
799 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 800 | continue; |
54cf91dc | 801 | |
27173f1f | 802 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
803 | if (ret) |
804 | goto err; | |
54cf91dc CW |
805 | } |
806 | ||
a415d355 | 807 | err: |
6c085a72 | 808 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
809 | return ret; |
810 | ||
a415d355 CW |
811 | /* Decrement pin count for bound objects */ |
812 | list_for_each_entry(vma, vmas, exec_list) | |
813 | i915_gem_execbuffer_unreserve_vma(vma); | |
814 | ||
68c8c17f | 815 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
816 | if (ret) |
817 | return ret; | |
54cf91dc CW |
818 | } while (1); |
819 | } | |
820 | ||
821 | static int | |
822 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 823 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 824 | struct drm_file *file, |
a4872ba6 | 825 | struct intel_engine_cs *ring, |
27173f1f | 826 | struct eb_vmas *eb, |
b1b38278 DW |
827 | struct drm_i915_gem_exec_object2 *exec, |
828 | struct intel_context *ctx) | |
54cf91dc CW |
829 | { |
830 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
831 | struct i915_address_space *vm; |
832 | struct i915_vma *vma; | |
ed5982e6 | 833 | bool need_relocs; |
dd6864a4 | 834 | int *reloc_offset; |
54cf91dc | 835 | int i, total, ret; |
b205ca57 | 836 | unsigned count = args->buffer_count; |
54cf91dc | 837 | |
27173f1f BW |
838 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
839 | ||
67731b87 | 840 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
841 | while (!list_empty(&eb->vmas)) { |
842 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
843 | list_del_init(&vma->exec_list); | |
a415d355 | 844 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 845 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
846 | } |
847 | ||
54cf91dc CW |
848 | mutex_unlock(&dev->struct_mutex); |
849 | ||
850 | total = 0; | |
851 | for (i = 0; i < count; i++) | |
432e58ed | 852 | total += exec[i].relocation_count; |
54cf91dc | 853 | |
dd6864a4 | 854 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 855 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
856 | if (reloc == NULL || reloc_offset == NULL) { |
857 | drm_free_large(reloc); | |
858 | drm_free_large(reloc_offset); | |
54cf91dc CW |
859 | mutex_lock(&dev->struct_mutex); |
860 | return -ENOMEM; | |
861 | } | |
862 | ||
863 | total = 0; | |
864 | for (i = 0; i < count; i++) { | |
865 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
866 | u64 invalid_offset = (u64)-1; |
867 | int j; | |
54cf91dc | 868 | |
2bb4629a | 869 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
870 | |
871 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 872 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
873 | ret = -EFAULT; |
874 | mutex_lock(&dev->struct_mutex); | |
875 | goto err; | |
876 | } | |
877 | ||
262b6d36 CW |
878 | /* As we do not update the known relocation offsets after |
879 | * relocating (due to the complexities in lock handling), | |
880 | * we need to mark them as invalid now so that we force the | |
881 | * relocation processing next time. Just in case the target | |
882 | * object is evicted and then rebound into its old | |
883 | * presumed_offset before the next execbuffer - if that | |
884 | * happened we would make the mistake of assuming that the | |
885 | * relocations were valid. | |
886 | */ | |
887 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
888 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
889 | &invalid_offset, | |
890 | sizeof(invalid_offset))) { | |
262b6d36 CW |
891 | ret = -EFAULT; |
892 | mutex_lock(&dev->struct_mutex); | |
893 | goto err; | |
894 | } | |
895 | } | |
896 | ||
dd6864a4 | 897 | reloc_offset[i] = total; |
432e58ed | 898 | total += exec[i].relocation_count; |
54cf91dc CW |
899 | } |
900 | ||
901 | ret = i915_mutex_lock_interruptible(dev); | |
902 | if (ret) { | |
903 | mutex_lock(&dev->struct_mutex); | |
904 | goto err; | |
905 | } | |
906 | ||
67731b87 | 907 | /* reacquire the objects */ |
67731b87 | 908 | eb_reset(eb); |
27173f1f | 909 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
910 | if (ret) |
911 | goto err; | |
67731b87 | 912 | |
ed5982e6 | 913 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
b1b38278 | 914 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); |
54cf91dc CW |
915 | if (ret) |
916 | goto err; | |
917 | ||
27173f1f BW |
918 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
919 | int offset = vma->exec_entry - exec; | |
920 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
921 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
922 | if (ret) |
923 | goto err; | |
54cf91dc CW |
924 | } |
925 | ||
926 | /* Leave the user relocations as are, this is the painfully slow path, | |
927 | * and we want to avoid the complication of dropping the lock whilst | |
928 | * having buffers reserved in the aperture and so causing spurious | |
929 | * ENOSPC for random operations. | |
930 | */ | |
931 | ||
932 | err: | |
933 | drm_free_large(reloc); | |
dd6864a4 | 934 | drm_free_large(reloc_offset); |
54cf91dc CW |
935 | return ret; |
936 | } | |
937 | ||
54cf91dc | 938 | static int |
535fbe82 | 939 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 940 | struct list_head *vmas) |
54cf91dc | 941 | { |
535fbe82 | 942 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
27173f1f | 943 | struct i915_vma *vma; |
6ac42f41 | 944 | uint32_t flush_domains = 0; |
000433b6 | 945 | bool flush_chipset = false; |
432e58ed | 946 | int ret; |
54cf91dc | 947 | |
27173f1f BW |
948 | list_for_each_entry(vma, vmas, exec_list) { |
949 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 CW |
950 | |
951 | if (obj->active & other_rings) { | |
91af127f | 952 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
953 | if (ret) |
954 | return ret; | |
955 | } | |
6ac42f41 DV |
956 | |
957 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 958 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 959 | |
6ac42f41 | 960 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
961 | } |
962 | ||
000433b6 | 963 | if (flush_chipset) |
535fbe82 | 964 | i915_gem_chipset_flush(req->ring->dev); |
6ac42f41 DV |
965 | |
966 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
967 | wmb(); | |
968 | ||
09cf7c9a CW |
969 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
970 | * any residual writes from the previous batch. | |
971 | */ | |
2f20055d | 972 | return intel_ring_invalidate_all_caches(req); |
54cf91dc CW |
973 | } |
974 | ||
432e58ed CW |
975 | static bool |
976 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 977 | { |
ed5982e6 DV |
978 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
979 | return false; | |
980 | ||
2f5945bc CW |
981 | /* Kernel clipping was a DRI1 misfeature */ |
982 | if (exec->num_cliprects || exec->cliprects_ptr) | |
983 | return false; | |
984 | ||
985 | if (exec->DR4 == 0xffffffff) { | |
986 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
987 | exec->DR4 = 0; | |
988 | } | |
989 | if (exec->DR1 || exec->DR4) | |
990 | return false; | |
991 | ||
992 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
993 | return false; | |
994 | ||
995 | return true; | |
54cf91dc CW |
996 | } |
997 | ||
998 | static int | |
ad19f10b CW |
999 | validate_exec_list(struct drm_device *dev, |
1000 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
1001 | int count) |
1002 | { | |
b205ca57 DV |
1003 | unsigned relocs_total = 0; |
1004 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
1005 | unsigned invalid_flags; |
1006 | int i; | |
1007 | ||
1008 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
1009 | if (USES_FULL_PPGTT(dev)) | |
1010 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
1011 | |
1012 | for (i = 0; i < count; i++) { | |
2bb4629a | 1013 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1014 | int length; /* limited by fault_in_pages_readable() */ |
1015 | ||
ad19f10b | 1016 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
1017 | return -EINVAL; |
1018 | ||
934acce3 MW |
1019 | /* Offset can be used as input (EXEC_OBJECT_PINNED), reject |
1020 | * any non-page-aligned or non-canonical addresses. | |
1021 | */ | |
1022 | if (exec[i].flags & EXEC_OBJECT_PINNED) { | |
1023 | if (exec[i].offset != | |
1024 | gen8_canonical_addr(exec[i].offset & PAGE_MASK)) | |
1025 | return -EINVAL; | |
1026 | ||
1027 | /* From drm_mm perspective address space is continuous, | |
1028 | * so from this point we're always using non-canonical | |
1029 | * form internally. | |
1030 | */ | |
1031 | exec[i].offset = gen8_noncanonical_addr(exec[i].offset); | |
1032 | } | |
1033 | ||
55a9785d CW |
1034 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
1035 | return -EINVAL; | |
1036 | ||
3118a4f6 KC |
1037 | /* First check for malicious input causing overflow in |
1038 | * the worst case where we need to allocate the entire | |
1039 | * relocation tree as a single array. | |
1040 | */ | |
1041 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1042 | return -EINVAL; |
3118a4f6 | 1043 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1044 | |
1045 | length = exec[i].relocation_count * | |
1046 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1047 | /* |
1048 | * We must check that the entire relocation array is safe | |
1049 | * to read, but since we may need to update the presumed | |
1050 | * offsets during execution, check for full write access. | |
1051 | */ | |
54cf91dc CW |
1052 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1053 | return -EFAULT; | |
1054 | ||
d330a953 | 1055 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1056 | if (fault_in_multipages_readable(ptr, length)) |
1057 | return -EFAULT; | |
1058 | } | |
54cf91dc CW |
1059 | } |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
273497e5 | 1064 | static struct intel_context * |
d299cce7 | 1065 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 1066 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 1067 | { |
273497e5 | 1068 | struct intel_context *ctx = NULL; |
d299cce7 MK |
1069 | struct i915_ctx_hang_stats *hs; |
1070 | ||
821d66dd | 1071 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
1072 | return ERR_PTR(-EINVAL); |
1073 | ||
41bde553 | 1074 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 1075 | if (IS_ERR(ctx)) |
41bde553 | 1076 | return ctx; |
d299cce7 | 1077 | |
41bde553 | 1078 | hs = &ctx->hang_stats; |
d299cce7 MK |
1079 | if (hs->banned) { |
1080 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 1081 | return ERR_PTR(-EIO); |
d299cce7 MK |
1082 | } |
1083 | ||
ec3e9963 | 1084 | if (i915.enable_execlists && !ctx->engine[ring->id].state) { |
e84fe803 | 1085 | int ret = intel_lr_context_deferred_alloc(ctx, ring); |
ec3e9963 OM |
1086 | if (ret) { |
1087 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
1088 | return ERR_PTR(ret); | |
1089 | } | |
1090 | } | |
1091 | ||
41bde553 | 1092 | return ctx; |
d299cce7 MK |
1093 | } |
1094 | ||
ba8b7ccb | 1095 | void |
27173f1f | 1096 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1097 | struct drm_i915_gem_request *req) |
432e58ed | 1098 | { |
8a8edb59 | 1099 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
27173f1f | 1100 | struct i915_vma *vma; |
432e58ed | 1101 | |
27173f1f | 1102 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 1103 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 1104 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
1105 | u32 old_read = obj->base.read_domains; |
1106 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1107 | |
51bc1404 | 1108 | obj->dirty = 1; /* be paranoid */ |
432e58ed | 1109 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
1110 | if (obj->base.write_domain == 0) |
1111 | obj->base.pending_read_domains |= obj->base.read_domains; | |
1112 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1113 | |
b2af0376 | 1114 | i915_vma_move_to_active(vma, req); |
432e58ed | 1115 | if (obj->base.write_domain) { |
97b2a6a1 | 1116 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 | 1117 | |
77a0d1ca | 1118 | intel_fb_obj_invalidate(obj, ORIGIN_CS); |
c8725f3d CW |
1119 | |
1120 | /* update for the implicit flush after a batch */ | |
1121 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 1122 | } |
82b6b6d7 | 1123 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 1124 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 CW |
1125 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
1126 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
1127 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
1128 | &dev_priv->mm.fence_list); | |
1129 | } | |
1130 | } | |
432e58ed | 1131 | |
db53a302 | 1132 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1133 | } |
1134 | } | |
1135 | ||
ba8b7ccb | 1136 | void |
adeca76d | 1137 | i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params) |
54cf91dc | 1138 | { |
cc889e0f | 1139 | /* Unconditionally force add_request to emit a full flush. */ |
adeca76d | 1140 | params->ring->gpu_caches_dirty = true; |
54cf91dc | 1141 | |
432e58ed | 1142 | /* Add a breadcrumb for the completion of the batch buffer */ |
fcfa423c | 1143 | __i915_add_request(params->request, params->batch_obj, true); |
432e58ed | 1144 | } |
54cf91dc | 1145 | |
ae662d31 EA |
1146 | static int |
1147 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
2f20055d | 1148 | struct drm_i915_gem_request *req) |
ae662d31 | 1149 | { |
2f20055d | 1150 | struct intel_engine_cs *ring = req->ring; |
50227e1c | 1151 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1152 | int ret, i; |
1153 | ||
9d662da8 DV |
1154 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1155 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1156 | return -EINVAL; | |
1157 | } | |
ae662d31 | 1158 | |
5fb9de1a | 1159 | ret = intel_ring_begin(req, 4 * 3); |
ae662d31 EA |
1160 | if (ret) |
1161 | return ret; | |
1162 | ||
1163 | for (i = 0; i < 4; i++) { | |
1164 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 1165 | intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i)); |
ae662d31 EA |
1166 | intel_ring_emit(ring, 0); |
1167 | } | |
1168 | ||
1169 | intel_ring_advance(ring); | |
1170 | ||
1171 | return 0; | |
1172 | } | |
1173 | ||
71745376 BV |
1174 | static struct drm_i915_gem_object* |
1175 | i915_gem_execbuffer_parse(struct intel_engine_cs *ring, | |
1176 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, | |
1177 | struct eb_vmas *eb, | |
1178 | struct drm_i915_gem_object *batch_obj, | |
1179 | u32 batch_start_offset, | |
1180 | u32 batch_len, | |
17cabf57 | 1181 | bool is_master) |
71745376 | 1182 | { |
71745376 | 1183 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1184 | struct i915_vma *vma; |
71745376 BV |
1185 | int ret; |
1186 | ||
06fbca71 | 1187 | shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool, |
17cabf57 | 1188 | PAGE_ALIGN(batch_len)); |
71745376 BV |
1189 | if (IS_ERR(shadow_batch_obj)) |
1190 | return shadow_batch_obj; | |
1191 | ||
1192 | ret = i915_parse_cmds(ring, | |
1193 | batch_obj, | |
1194 | shadow_batch_obj, | |
1195 | batch_start_offset, | |
1196 | batch_len, | |
1197 | is_master); | |
17cabf57 CW |
1198 | if (ret) |
1199 | goto err; | |
71745376 | 1200 | |
17cabf57 CW |
1201 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); |
1202 | if (ret) | |
1203 | goto err; | |
71745376 | 1204 | |
de4e783a CW |
1205 | i915_gem_object_unpin_pages(shadow_batch_obj); |
1206 | ||
17cabf57 | 1207 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1208 | |
17cabf57 CW |
1209 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1210 | vma->exec_entry = shadow_exec_entry; | |
de4e783a | 1211 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
17cabf57 CW |
1212 | drm_gem_object_reference(&shadow_batch_obj->base); |
1213 | list_add_tail(&vma->exec_list, &eb->vmas); | |
71745376 | 1214 | |
17cabf57 CW |
1215 | shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
1216 | ||
1217 | return shadow_batch_obj; | |
71745376 | 1218 | |
17cabf57 | 1219 | err: |
de4e783a | 1220 | i915_gem_object_unpin_pages(shadow_batch_obj); |
17cabf57 CW |
1221 | if (ret == -EACCES) /* unhandled chained batch */ |
1222 | return batch_obj; | |
1223 | else | |
1224 | return ERR_PTR(ret); | |
71745376 | 1225 | } |
5c6c6003 | 1226 | |
a83014d3 | 1227 | int |
5f19e2bf | 1228 | i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 1229 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1230 | struct list_head *vmas) |
78382593 | 1231 | { |
5f19e2bf JH |
1232 | struct drm_device *dev = params->dev; |
1233 | struct intel_engine_cs *ring = params->ring; | |
78382593 | 1234 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf | 1235 | u64 exec_start, exec_len; |
78382593 OM |
1236 | int instp_mode; |
1237 | u32 instp_mask; | |
2f5945bc | 1238 | int ret; |
78382593 | 1239 | |
535fbe82 | 1240 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 | 1241 | if (ret) |
2f5945bc | 1242 | return ret; |
78382593 | 1243 | |
ba01cc93 | 1244 | ret = i915_switch_context(params->request); |
78382593 | 1245 | if (ret) |
2f5945bc | 1246 | return ret; |
78382593 | 1247 | |
5f19e2bf | 1248 | WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id), |
9258811c | 1249 | "%s didn't clear reload\n", ring->name); |
563222a7 | 1250 | |
78382593 OM |
1251 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
1252 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1253 | switch (instp_mode) { | |
1254 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1255 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1256 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1257 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
1258 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
2f5945bc | 1259 | return -EINVAL; |
78382593 OM |
1260 | } |
1261 | ||
1262 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1263 | if (INTEL_INFO(dev)->gen < 4) { | |
1264 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
2f5945bc | 1265 | return -EINVAL; |
78382593 OM |
1266 | } |
1267 | ||
1268 | if (INTEL_INFO(dev)->gen > 5 && | |
1269 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1270 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
2f5945bc | 1271 | return -EINVAL; |
78382593 OM |
1272 | } |
1273 | ||
1274 | /* The HW changed the meaning on this bit on gen6 */ | |
1275 | if (INTEL_INFO(dev)->gen >= 6) | |
1276 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1277 | } | |
1278 | break; | |
1279 | default: | |
1280 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
2f5945bc | 1281 | return -EINVAL; |
78382593 OM |
1282 | } |
1283 | ||
1284 | if (ring == &dev_priv->ring[RCS] && | |
2f5945bc | 1285 | instp_mode != dev_priv->relative_constants_mode) { |
5fb9de1a | 1286 | ret = intel_ring_begin(params->request, 4); |
78382593 | 1287 | if (ret) |
2f5945bc | 1288 | return ret; |
78382593 OM |
1289 | |
1290 | intel_ring_emit(ring, MI_NOOP); | |
1291 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 1292 | intel_ring_emit_reg(ring, INSTPM); |
78382593 OM |
1293 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); |
1294 | intel_ring_advance(ring); | |
1295 | ||
1296 | dev_priv->relative_constants_mode = instp_mode; | |
1297 | } | |
1298 | ||
1299 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
2f20055d | 1300 | ret = i915_reset_gen7_sol_offsets(dev, params->request); |
78382593 | 1301 | if (ret) |
2f5945bc | 1302 | return ret; |
78382593 OM |
1303 | } |
1304 | ||
5f19e2bf JH |
1305 | exec_len = args->batch_len; |
1306 | exec_start = params->batch_obj_vm_offset + | |
1307 | params->args_batch_start_offset; | |
1308 | ||
9d611c03 VS |
1309 | if (exec_len == 0) |
1310 | exec_len = params->batch_obj->base.size; | |
1311 | ||
2f5945bc CW |
1312 | ret = ring->dispatch_execbuffer(params->request, |
1313 | exec_start, exec_len, | |
1314 | params->dispatch_flags); | |
1315 | if (ret) | |
1316 | return ret; | |
78382593 | 1317 | |
95c24161 | 1318 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
78382593 | 1319 | |
8a8edb59 | 1320 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 1321 | i915_gem_execbuffer_retire_commands(params); |
78382593 | 1322 | |
2f5945bc | 1323 | return 0; |
78382593 OM |
1324 | } |
1325 | ||
a8ebba75 ZY |
1326 | /** |
1327 | * Find one BSD ring to dispatch the corresponding BSD command. | |
de1add36 | 1328 | * The ring index is returned. |
a8ebba75 | 1329 | */ |
de1add36 TU |
1330 | static unsigned int |
1331 | gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file *file) | |
a8ebba75 | 1332 | { |
a8ebba75 ZY |
1333 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1334 | ||
de1add36 TU |
1335 | /* Check whether the file_priv has already selected one ring. */ |
1336 | if ((int)file_priv->bsd_ring < 0) { | |
1337 | /* If not, use the ping-pong mechanism to select one. */ | |
1338 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1339 | file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index; | |
1340 | dev_priv->mm.bsd_ring_dispatch_index ^= 1; | |
1341 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
a8ebba75 | 1342 | } |
de1add36 TU |
1343 | |
1344 | return file_priv->bsd_ring; | |
a8ebba75 ZY |
1345 | } |
1346 | ||
d23db88c CW |
1347 | static struct drm_i915_gem_object * |
1348 | eb_get_batch(struct eb_vmas *eb) | |
1349 | { | |
1350 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1351 | ||
1352 | /* | |
1353 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1354 | * to negative relocation deltas. Usually that works out ok since the | |
1355 | * relocate address is still positive, except when the batch is placed | |
1356 | * very low in the GTT. Ensure this doesn't happen. | |
1357 | * | |
1358 | * Note that actual hangs have only been observed on gen7, but for | |
1359 | * paranoia do it everywhere. | |
1360 | */ | |
506a8e87 CW |
1361 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) |
1362 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
d23db88c CW |
1363 | |
1364 | return vma->obj; | |
1365 | } | |
1366 | ||
de1add36 TU |
1367 | #define I915_USER_RINGS (4) |
1368 | ||
1369 | static const enum intel_ring_id user_ring_map[I915_USER_RINGS + 1] = { | |
1370 | [I915_EXEC_DEFAULT] = RCS, | |
1371 | [I915_EXEC_RENDER] = RCS, | |
1372 | [I915_EXEC_BLT] = BCS, | |
1373 | [I915_EXEC_BSD] = VCS, | |
1374 | [I915_EXEC_VEBOX] = VECS | |
1375 | }; | |
1376 | ||
1377 | static int | |
1378 | eb_select_ring(struct drm_i915_private *dev_priv, | |
1379 | struct drm_file *file, | |
1380 | struct drm_i915_gem_execbuffer2 *args, | |
1381 | struct intel_engine_cs **ring) | |
1382 | { | |
1383 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
1384 | ||
1385 | if (user_ring_id > I915_USER_RINGS) { | |
1386 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
1387 | return -EINVAL; | |
1388 | } | |
1389 | ||
1390 | if ((user_ring_id != I915_EXEC_BSD) && | |
1391 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1392 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1393 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
1394 | return -EINVAL; | |
1395 | } | |
1396 | ||
1397 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
1398 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
1399 | ||
1400 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
1401 | bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file); | |
1402 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && | |
1403 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
1404 | bsd_idx--; | |
1405 | } else { | |
1406 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
1407 | bsd_idx); | |
1408 | return -EINVAL; | |
1409 | } | |
1410 | ||
1411 | *ring = &dev_priv->ring[_VCS(bsd_idx)]; | |
1412 | } else { | |
1413 | *ring = &dev_priv->ring[user_ring_map[user_ring_id]]; | |
1414 | } | |
1415 | ||
1416 | if (!intel_ring_initialized(*ring)) { | |
1417 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); | |
1418 | return -EINVAL; | |
1419 | } | |
1420 | ||
1421 | return 0; | |
1422 | } | |
1423 | ||
54cf91dc CW |
1424 | static int |
1425 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1426 | struct drm_file *file, | |
1427 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1428 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1429 | { |
50227e1c | 1430 | struct drm_i915_private *dev_priv = dev->dev_private; |
26827088 | 1431 | struct drm_i915_gem_request *req = NULL; |
27173f1f | 1432 | struct eb_vmas *eb; |
54cf91dc | 1433 | struct drm_i915_gem_object *batch_obj; |
78a42377 | 1434 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
a4872ba6 | 1435 | struct intel_engine_cs *ring; |
273497e5 | 1436 | struct intel_context *ctx; |
41bde553 | 1437 | struct i915_address_space *vm; |
5f19e2bf JH |
1438 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1439 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1440 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1441 | u32 dispatch_flags; |
78382593 | 1442 | int ret; |
ed5982e6 | 1443 | bool need_relocs; |
54cf91dc | 1444 | |
ed5982e6 | 1445 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1446 | return -EINVAL; |
432e58ed | 1447 | |
ad19f10b | 1448 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1449 | if (ret) |
1450 | return ret; | |
1451 | ||
8e004efc | 1452 | dispatch_flags = 0; |
d7d4eedd CW |
1453 | if (args->flags & I915_EXEC_SECURE) { |
1454 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1455 | return -EPERM; | |
1456 | ||
8e004efc | 1457 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1458 | } |
b45305fc | 1459 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1460 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1461 | |
de1add36 TU |
1462 | ret = eb_select_ring(dev_priv, file, args, &ring); |
1463 | if (ret) | |
1464 | return ret; | |
54cf91dc CW |
1465 | |
1466 | if (args->buffer_count < 1) { | |
ff240199 | 1467 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1468 | return -EINVAL; |
1469 | } | |
54cf91dc | 1470 | |
a9ed33ca AJ |
1471 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
1472 | if (!HAS_RESOURCE_STREAMER(dev)) { | |
1473 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); | |
1474 | return -EINVAL; | |
1475 | } | |
1476 | if (ring->id != RCS) { | |
1477 | DRM_DEBUG("RS is not available on %s\n", | |
1478 | ring->name); | |
1479 | return -EINVAL; | |
1480 | } | |
1481 | ||
1482 | dispatch_flags |= I915_DISPATCH_RS; | |
1483 | } | |
1484 | ||
f65c9168 PZ |
1485 | intel_runtime_pm_get(dev_priv); |
1486 | ||
54cf91dc CW |
1487 | ret = i915_mutex_lock_interruptible(dev); |
1488 | if (ret) | |
1489 | goto pre_mutex_err; | |
1490 | ||
7c9c4b8f | 1491 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1492 | if (IS_ERR(ctx)) { |
d299cce7 | 1493 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1494 | ret = PTR_ERR(ctx); |
d299cce7 | 1495 | goto pre_mutex_err; |
935f38d6 | 1496 | } |
41bde553 BW |
1497 | |
1498 | i915_gem_context_reference(ctx); | |
1499 | ||
ae6c4806 DV |
1500 | if (ctx->ppgtt) |
1501 | vm = &ctx->ppgtt->base; | |
1502 | else | |
7e0d96bc | 1503 | vm = &dev_priv->gtt.base; |
d299cce7 | 1504 | |
5f19e2bf JH |
1505 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1506 | ||
17601cbc | 1507 | eb = eb_create(args); |
67731b87 | 1508 | if (eb == NULL) { |
935f38d6 | 1509 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1510 | mutex_unlock(&dev->struct_mutex); |
1511 | ret = -ENOMEM; | |
1512 | goto pre_mutex_err; | |
1513 | } | |
1514 | ||
54cf91dc | 1515 | /* Look up object handles */ |
27173f1f | 1516 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1517 | if (ret) |
1518 | goto err; | |
54cf91dc | 1519 | |
6fe4f140 | 1520 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1521 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1522 | |
54cf91dc | 1523 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1524 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
b1b38278 | 1525 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); |
54cf91dc CW |
1526 | if (ret) |
1527 | goto err; | |
1528 | ||
1529 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1530 | if (need_relocs) |
17601cbc | 1531 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1532 | if (ret) { |
1533 | if (ret == -EFAULT) { | |
ed5982e6 | 1534 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
b1b38278 | 1535 | eb, exec, ctx); |
54cf91dc CW |
1536 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1537 | } | |
1538 | if (ret) | |
1539 | goto err; | |
1540 | } | |
1541 | ||
1542 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1543 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1544 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1545 | ret = -EINVAL; |
1546 | goto err; | |
1547 | } | |
54cf91dc | 1548 | |
5f19e2bf | 1549 | params->args_batch_start_offset = args->batch_start_offset; |
743e78c1 | 1550 | if (i915_needs_cmd_parser(ring) && args->batch_len) { |
c7c7372e RP |
1551 | struct drm_i915_gem_object *parsed_batch_obj; |
1552 | ||
1553 | parsed_batch_obj = i915_gem_execbuffer_parse(ring, | |
71745376 BV |
1554 | &shadow_exec_entry, |
1555 | eb, | |
1556 | batch_obj, | |
1557 | args->batch_start_offset, | |
1558 | args->batch_len, | |
17cabf57 | 1559 | file->is_master); |
c7c7372e RP |
1560 | if (IS_ERR(parsed_batch_obj)) { |
1561 | ret = PTR_ERR(parsed_batch_obj); | |
78a42377 BV |
1562 | goto err; |
1563 | } | |
17cabf57 CW |
1564 | |
1565 | /* | |
c7c7372e RP |
1566 | * parsed_batch_obj == batch_obj means batch not fully parsed: |
1567 | * Accept, but don't promote to secure. | |
17cabf57 | 1568 | */ |
17cabf57 | 1569 | |
c7c7372e RP |
1570 | if (parsed_batch_obj != batch_obj) { |
1571 | /* | |
1572 | * Batch parsed and accepted: | |
1573 | * | |
1574 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1575 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1576 | * the dispatch_execbuffer implementations. We | |
1577 | * specifically don't want that set on batches the | |
1578 | * command parser has accepted. | |
1579 | */ | |
1580 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1581 | params->args_batch_start_offset = 0; |
c7c7372e RP |
1582 | batch_obj = parsed_batch_obj; |
1583 | } | |
351e3db2 BV |
1584 | } |
1585 | ||
78a42377 BV |
1586 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1587 | ||
d7d4eedd CW |
1588 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1589 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1590 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1591 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
da51a1e7 DV |
1592 | /* |
1593 | * So on first glance it looks freaky that we pin the batch here | |
1594 | * outside of the reservation loop. But: | |
1595 | * - The batch is already pinned into the relevant ppgtt, so we | |
1596 | * already have the backing storage fully allocated. | |
1597 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1598 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1599 | * fitting due to fragmentation. |
1600 | * So this is actually safe. | |
1601 | */ | |
1602 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1603 | if (ret) | |
1604 | goto err; | |
d7d4eedd | 1605 | |
5f19e2bf | 1606 | params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1607 | } else |
5f19e2bf | 1608 | params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1609 | |
0c8dac88 | 1610 | /* Allocate a request for this batch buffer nice and early. */ |
26827088 DG |
1611 | req = i915_gem_request_alloc(ring, ctx); |
1612 | if (IS_ERR(req)) { | |
1613 | ret = PTR_ERR(req); | |
0c8dac88 | 1614 | goto err_batch_unpin; |
26827088 | 1615 | } |
0c8dac88 | 1616 | |
26827088 | 1617 | ret = i915_gem_request_add_to_client(req, file); |
fcfa423c JH |
1618 | if (ret) |
1619 | goto err_batch_unpin; | |
1620 | ||
5f19e2bf JH |
1621 | /* |
1622 | * Save assorted stuff away to pass through to *_submission(). | |
1623 | * NB: This data should be 'persistent' and not local as it will | |
1624 | * kept around beyond the duration of the IOCTL once the GPU | |
1625 | * scheduler arrives. | |
1626 | */ | |
1627 | params->dev = dev; | |
1628 | params->file = file; | |
1629 | params->ring = ring; | |
1630 | params->dispatch_flags = dispatch_flags; | |
1631 | params->batch_obj = batch_obj; | |
1632 | params->ctx = ctx; | |
26827088 | 1633 | params->request = req; |
5f19e2bf JH |
1634 | |
1635 | ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas); | |
54cf91dc | 1636 | |
0c8dac88 | 1637 | err_batch_unpin: |
da51a1e7 DV |
1638 | /* |
1639 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1640 | * batch vma for correctness. For less ugly and less fragility this | |
1641 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1642 | * active. | |
1643 | */ | |
8e004efc | 1644 | if (dispatch_flags & I915_DISPATCH_SECURE) |
da51a1e7 | 1645 | i915_gem_object_ggtt_unpin(batch_obj); |
0c8dac88 | 1646 | |
54cf91dc | 1647 | err: |
41bde553 BW |
1648 | /* the request owns the ref now */ |
1649 | i915_gem_context_unreference(ctx); | |
67731b87 | 1650 | eb_destroy(eb); |
54cf91dc | 1651 | |
6a6ae79a JH |
1652 | /* |
1653 | * If the request was created but not successfully submitted then it | |
1654 | * must be freed again. If it was submitted then it is being tracked | |
1655 | * on the active request list and no clean up is required here. | |
1656 | */ | |
26827088 DG |
1657 | if (ret && req) |
1658 | i915_gem_request_cancel(req); | |
6a6ae79a | 1659 | |
54cf91dc CW |
1660 | mutex_unlock(&dev->struct_mutex); |
1661 | ||
1662 | pre_mutex_err: | |
f65c9168 PZ |
1663 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1664 | * is really idle. */ | |
1665 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1666 | return ret; |
1667 | } | |
1668 | ||
1669 | /* | |
1670 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1671 | * list array and passes it to the real function. | |
1672 | */ | |
1673 | int | |
1674 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1675 | struct drm_file *file) | |
1676 | { | |
1677 | struct drm_i915_gem_execbuffer *args = data; | |
1678 | struct drm_i915_gem_execbuffer2 exec2; | |
1679 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1680 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1681 | int ret, i; | |
1682 | ||
54cf91dc | 1683 | if (args->buffer_count < 1) { |
ff240199 | 1684 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1685 | return -EINVAL; |
1686 | } | |
1687 | ||
1688 | /* Copy in the exec list from userland */ | |
1689 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1690 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1691 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1692 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1693 | args->buffer_count); |
1694 | drm_free_large(exec_list); | |
1695 | drm_free_large(exec2_list); | |
1696 | return -ENOMEM; | |
1697 | } | |
1698 | ret = copy_from_user(exec_list, | |
2bb4629a | 1699 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1700 | sizeof(*exec_list) * args->buffer_count); |
1701 | if (ret != 0) { | |
ff240199 | 1702 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1703 | args->buffer_count, ret); |
1704 | drm_free_large(exec_list); | |
1705 | drm_free_large(exec2_list); | |
1706 | return -EFAULT; | |
1707 | } | |
1708 | ||
1709 | for (i = 0; i < args->buffer_count; i++) { | |
1710 | exec2_list[i].handle = exec_list[i].handle; | |
1711 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1712 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1713 | exec2_list[i].alignment = exec_list[i].alignment; | |
1714 | exec2_list[i].offset = exec_list[i].offset; | |
1715 | if (INTEL_INFO(dev)->gen < 4) | |
1716 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1717 | else | |
1718 | exec2_list[i].flags = 0; | |
1719 | } | |
1720 | ||
1721 | exec2.buffers_ptr = args->buffers_ptr; | |
1722 | exec2.buffer_count = args->buffer_count; | |
1723 | exec2.batch_start_offset = args->batch_start_offset; | |
1724 | exec2.batch_len = args->batch_len; | |
1725 | exec2.DR1 = args->DR1; | |
1726 | exec2.DR4 = args->DR4; | |
1727 | exec2.num_cliprects = args->num_cliprects; | |
1728 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1729 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1730 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1731 | |
41bde553 | 1732 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1733 | if (!ret) { |
9aab8bff CW |
1734 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1735 | to_user_ptr(args->buffers_ptr); | |
1736 | ||
54cf91dc | 1737 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 1738 | for (i = 0; i < args->buffer_count; i++) { |
934acce3 MW |
1739 | exec2_list[i].offset = |
1740 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1741 | ret = __copy_to_user(&user_exec_list[i].offset, |
1742 | &exec2_list[i].offset, | |
1743 | sizeof(user_exec_list[i].offset)); | |
1744 | if (ret) { | |
1745 | ret = -EFAULT; | |
1746 | DRM_DEBUG("failed to copy %d exec entries " | |
1747 | "back to user (%d)\n", | |
1748 | args->buffer_count, ret); | |
1749 | break; | |
1750 | } | |
54cf91dc CW |
1751 | } |
1752 | } | |
1753 | ||
1754 | drm_free_large(exec_list); | |
1755 | drm_free_large(exec2_list); | |
1756 | return ret; | |
1757 | } | |
1758 | ||
1759 | int | |
1760 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1761 | struct drm_file *file) | |
1762 | { | |
1763 | struct drm_i915_gem_execbuffer2 *args = data; | |
1764 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1765 | int ret; | |
1766 | ||
ed8cd3b2 XW |
1767 | if (args->buffer_count < 1 || |
1768 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1769 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1770 | return -EINVAL; |
1771 | } | |
1772 | ||
9cb34664 DV |
1773 | if (args->rsvd2 != 0) { |
1774 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1775 | return -EINVAL; | |
1776 | } | |
1777 | ||
8408c282 | 1778 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1779 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1780 | if (exec2_list == NULL) |
1781 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1782 | args->buffer_count); | |
54cf91dc | 1783 | if (exec2_list == NULL) { |
ff240199 | 1784 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1785 | args->buffer_count); |
1786 | return -ENOMEM; | |
1787 | } | |
1788 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1789 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1790 | sizeof(*exec2_list) * args->buffer_count); |
1791 | if (ret != 0) { | |
ff240199 | 1792 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1793 | args->buffer_count, ret); |
1794 | drm_free_large(exec2_list); | |
1795 | return -EFAULT; | |
1796 | } | |
1797 | ||
41bde553 | 1798 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1799 | if (!ret) { |
1800 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1801 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1802 | to_user_ptr(args->buffers_ptr); |
1803 | int i; | |
1804 | ||
1805 | for (i = 0; i < args->buffer_count; i++) { | |
934acce3 MW |
1806 | exec2_list[i].offset = |
1807 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1808 | ret = __copy_to_user(&user_exec_list[i].offset, |
1809 | &exec2_list[i].offset, | |
1810 | sizeof(user_exec_list[i].offset)); | |
1811 | if (ret) { | |
1812 | ret = -EFAULT; | |
1813 | DRM_DEBUG("failed to copy %d exec entries " | |
1814 | "back to user\n", | |
1815 | args->buffer_count); | |
1816 | break; | |
1817 | } | |
54cf91dc CW |
1818 | } |
1819 | } | |
1820 | ||
1821 | drm_free_large(exec2_list); | |
1822 | return ret; | |
1823 | } |