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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
a415d355 CW |
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 38 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c CW |
39 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
40 | ||
41 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 42 | |
27173f1f BW |
43 | struct eb_vmas { |
44 | struct list_head vmas; | |
67731b87 | 45 | int and; |
eef90ccb | 46 | union { |
27173f1f | 47 | struct i915_vma *lut[0]; |
eef90ccb CW |
48 | struct hlist_head buckets[0]; |
49 | }; | |
67731b87 CW |
50 | }; |
51 | ||
27173f1f | 52 | static struct eb_vmas * |
17601cbc | 53 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 54 | { |
27173f1f | 55 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
56 | |
57 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 58 | unsigned size = args->buffer_count; |
27173f1f BW |
59 | size *= sizeof(struct i915_vma *); |
60 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
61 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
62 | } | |
63 | ||
64 | if (eb == NULL) { | |
b205ca57 DV |
65 | unsigned size = args->buffer_count; |
66 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 67 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
68 | while (count > 2*size) |
69 | count >>= 1; | |
70 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 71 | sizeof(struct eb_vmas), |
eef90ccb CW |
72 | GFP_TEMPORARY); |
73 | if (eb == NULL) | |
74 | return eb; | |
75 | ||
76 | eb->and = count - 1; | |
77 | } else | |
78 | eb->and = -args->buffer_count; | |
79 | ||
27173f1f | 80 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
81 | return eb; |
82 | } | |
83 | ||
84 | static void | |
27173f1f | 85 | eb_reset(struct eb_vmas *eb) |
67731b87 | 86 | { |
eef90ccb CW |
87 | if (eb->and >= 0) |
88 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
89 | } |
90 | ||
3b96eff4 | 91 | static int |
27173f1f BW |
92 | eb_lookup_vmas(struct eb_vmas *eb, |
93 | struct drm_i915_gem_exec_object2 *exec, | |
94 | const struct drm_i915_gem_execbuffer2 *args, | |
95 | struct i915_address_space *vm, | |
96 | struct drm_file *file) | |
3b96eff4 | 97 | { |
27173f1f BW |
98 | struct drm_i915_gem_object *obj; |
99 | struct list_head objects; | |
9ae9ab52 | 100 | int i, ret; |
3b96eff4 | 101 | |
27173f1f | 102 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 103 | spin_lock(&file->table_lock); |
27173f1f BW |
104 | /* Grab a reference to the object and release the lock so we can lookup |
105 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 106 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
107 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
108 | if (obj == NULL) { | |
109 | spin_unlock(&file->table_lock); | |
110 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
111 | exec[i].handle, i); | |
27173f1f | 112 | ret = -ENOENT; |
9ae9ab52 | 113 | goto err; |
3b96eff4 CW |
114 | } |
115 | ||
27173f1f | 116 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
117 | spin_unlock(&file->table_lock); |
118 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
119 | obj, exec[i].handle, i); | |
27173f1f | 120 | ret = -EINVAL; |
9ae9ab52 | 121 | goto err; |
3b96eff4 CW |
122 | } |
123 | ||
124 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
125 | list_add_tail(&obj->obj_exec_link, &objects); |
126 | } | |
127 | spin_unlock(&file->table_lock); | |
3b96eff4 | 128 | |
27173f1f | 129 | i = 0; |
9ae9ab52 | 130 | while (!list_empty(&objects)) { |
27173f1f | 131 | struct i915_vma *vma; |
6f65e29a | 132 | |
9ae9ab52 CW |
133 | obj = list_first_entry(&objects, |
134 | struct drm_i915_gem_object, | |
135 | obj_exec_link); | |
136 | ||
e656a6cb DV |
137 | /* |
138 | * NOTE: We can leak any vmas created here when something fails | |
139 | * later on. But that's no issue since vma_unbind can deal with | |
140 | * vmas which are not actually bound. And since only | |
141 | * lookup_or_create exists as an interface to get at the vma | |
142 | * from the (obj, vm) we don't run the risk of creating | |
143 | * duplicated vmas for the same vm. | |
144 | */ | |
da51a1e7 | 145 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 146 | if (IS_ERR(vma)) { |
27173f1f BW |
147 | DRM_DEBUG("Failed to lookup VMA\n"); |
148 | ret = PTR_ERR(vma); | |
9ae9ab52 | 149 | goto err; |
27173f1f BW |
150 | } |
151 | ||
9ae9ab52 | 152 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 153 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 154 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
155 | |
156 | vma->exec_entry = &exec[i]; | |
eef90ccb | 157 | if (eb->and < 0) { |
27173f1f | 158 | eb->lut[i] = vma; |
eef90ccb CW |
159 | } else { |
160 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
161 | vma->exec_handle = handle; |
162 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
163 | &eb->buckets[handle & eb->and]); |
164 | } | |
27173f1f | 165 | ++i; |
3b96eff4 | 166 | } |
3b96eff4 | 167 | |
9ae9ab52 | 168 | return 0; |
27173f1f | 169 | |
27173f1f | 170 | |
9ae9ab52 | 171 | err: |
27173f1f BW |
172 | while (!list_empty(&objects)) { |
173 | obj = list_first_entry(&objects, | |
174 | struct drm_i915_gem_object, | |
175 | obj_exec_link); | |
176 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 177 | drm_gem_object_unreference(&obj->base); |
27173f1f | 178 | } |
9ae9ab52 CW |
179 | /* |
180 | * Objects already transfered to the vmas list will be unreferenced by | |
181 | * eb_destroy. | |
182 | */ | |
183 | ||
27173f1f | 184 | return ret; |
3b96eff4 CW |
185 | } |
186 | ||
27173f1f | 187 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 188 | { |
eef90ccb CW |
189 | if (eb->and < 0) { |
190 | if (handle >= -eb->and) | |
191 | return NULL; | |
192 | return eb->lut[handle]; | |
193 | } else { | |
194 | struct hlist_head *head; | |
195 | struct hlist_node *node; | |
67731b87 | 196 | |
eef90ccb CW |
197 | head = &eb->buckets[handle & eb->and]; |
198 | hlist_for_each(node, head) { | |
27173f1f | 199 | struct i915_vma *vma; |
67731b87 | 200 | |
27173f1f BW |
201 | vma = hlist_entry(node, struct i915_vma, exec_node); |
202 | if (vma->exec_handle == handle) | |
203 | return vma; | |
eef90ccb CW |
204 | } |
205 | return NULL; | |
206 | } | |
67731b87 CW |
207 | } |
208 | ||
a415d355 CW |
209 | static void |
210 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
211 | { | |
212 | struct drm_i915_gem_exec_object2 *entry; | |
213 | struct drm_i915_gem_object *obj = vma->obj; | |
214 | ||
215 | if (!drm_mm_node_allocated(&vma->node)) | |
216 | return; | |
217 | ||
218 | entry = vma->exec_entry; | |
219 | ||
220 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
221 | i915_gem_object_unpin_fence(obj); | |
222 | ||
223 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 224 | vma->pin_count--; |
a415d355 | 225 | |
de4e783a | 226 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
227 | } |
228 | ||
229 | static void eb_destroy(struct eb_vmas *eb) | |
230 | { | |
27173f1f BW |
231 | while (!list_empty(&eb->vmas)) { |
232 | struct i915_vma *vma; | |
bcffc3fa | 233 | |
27173f1f BW |
234 | vma = list_first_entry(&eb->vmas, |
235 | struct i915_vma, | |
bcffc3fa | 236 | exec_list); |
27173f1f | 237 | list_del_init(&vma->exec_list); |
a415d355 | 238 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 239 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 240 | } |
67731b87 CW |
241 | kfree(eb); |
242 | } | |
243 | ||
dabdfe02 CW |
244 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
245 | { | |
2cc86b82 CW |
246 | return (HAS_LLC(obj->base.dev) || |
247 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
dabdfe02 CW |
248 | obj->cache_level != I915_CACHE_NONE); |
249 | } | |
250 | ||
5032d871 RB |
251 | static int |
252 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
253 | struct drm_i915_gem_relocation_entry *reloc, |
254 | uint64_t target_offset) | |
5032d871 | 255 | { |
3c94ceee | 256 | struct drm_device *dev = obj->base.dev; |
5032d871 | 257 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 258 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 259 | char *vaddr; |
8b78f0e5 | 260 | int ret; |
5032d871 | 261 | |
2cc86b82 | 262 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
263 | if (ret) |
264 | return ret; | |
265 | ||
266 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
267 | reloc->offset >> PAGE_SHIFT)); | |
d9ceb957 | 268 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
269 | |
270 | if (INTEL_INFO(dev)->gen >= 8) { | |
271 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
272 | ||
273 | if (page_offset == 0) { | |
274 | kunmap_atomic(vaddr); | |
275 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
276 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
277 | } | |
278 | ||
d9ceb957 | 279 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
280 | } |
281 | ||
5032d871 RB |
282 | kunmap_atomic(vaddr); |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | static int | |
288 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
289 | struct drm_i915_gem_relocation_entry *reloc, |
290 | uint64_t target_offset) | |
5032d871 RB |
291 | { |
292 | struct drm_device *dev = obj->base.dev; | |
293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 294 | uint64_t delta = reloc->delta + target_offset; |
906843c3 | 295 | uint64_t offset; |
5032d871 | 296 | void __iomem *reloc_page; |
8b78f0e5 | 297 | int ret; |
5032d871 RB |
298 | |
299 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
300 | if (ret) | |
301 | return ret; | |
302 | ||
303 | ret = i915_gem_object_put_fence(obj); | |
304 | if (ret) | |
305 | return ret; | |
306 | ||
307 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
308 | offset = i915_gem_obj_ggtt_offset(obj); |
309 | offset += reloc->offset; | |
5032d871 | 310 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
906843c3 CW |
311 | offset & PAGE_MASK); |
312 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
313 | |
314 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 315 | offset += sizeof(uint32_t); |
3c94ceee | 316 | |
906843c3 | 317 | if (offset_in_page(offset) == 0) { |
3c94ceee | 318 | io_mapping_unmap_atomic(reloc_page); |
906843c3 CW |
319 | reloc_page = |
320 | io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
321 | offset); | |
3c94ceee BW |
322 | } |
323 | ||
906843c3 CW |
324 | iowrite32(upper_32_bits(delta), |
325 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
326 | } |
327 | ||
5032d871 RB |
328 | io_mapping_unmap_atomic(reloc_page); |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
edf4427b CW |
333 | static void |
334 | clflush_write32(void *addr, uint32_t value) | |
335 | { | |
336 | /* This is not a fast path, so KISS. */ | |
337 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
338 | *(uint32_t *)addr = value; | |
339 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
340 | } | |
341 | ||
342 | static int | |
343 | relocate_entry_clflush(struct drm_i915_gem_object *obj, | |
344 | struct drm_i915_gem_relocation_entry *reloc, | |
345 | uint64_t target_offset) | |
346 | { | |
347 | struct drm_device *dev = obj->base.dev; | |
348 | uint32_t page_offset = offset_in_page(reloc->offset); | |
349 | uint64_t delta = (int)reloc->delta + target_offset; | |
350 | char *vaddr; | |
351 | int ret; | |
352 | ||
353 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
354 | if (ret) | |
355 | return ret; | |
356 | ||
357 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
358 | reloc->offset >> PAGE_SHIFT)); | |
359 | clflush_write32(vaddr + page_offset, lower_32_bits(delta)); | |
360 | ||
361 | if (INTEL_INFO(dev)->gen >= 8) { | |
362 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
363 | ||
364 | if (page_offset == 0) { | |
365 | kunmap_atomic(vaddr); | |
366 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
367 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
368 | } | |
369 | ||
370 | clflush_write32(vaddr + page_offset, upper_32_bits(delta)); | |
371 | } | |
372 | ||
373 | kunmap_atomic(vaddr); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
54cf91dc CW |
378 | static int |
379 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 380 | struct eb_vmas *eb, |
3e7a0322 | 381 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
382 | { |
383 | struct drm_device *dev = obj->base.dev; | |
384 | struct drm_gem_object *target_obj; | |
149c8407 | 385 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 386 | struct i915_vma *target_vma; |
d9ceb957 | 387 | uint64_t target_offset; |
8b78f0e5 | 388 | int ret; |
54cf91dc | 389 | |
67731b87 | 390 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
391 | target_vma = eb_get_vma(eb, reloc->target_handle); |
392 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 393 | return -ENOENT; |
27173f1f BW |
394 | target_i915_obj = target_vma->obj; |
395 | target_obj = &target_vma->obj->base; | |
54cf91dc | 396 | |
5ce09725 | 397 | target_offset = target_vma->node.start; |
54cf91dc | 398 | |
e844b990 EA |
399 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
400 | * pipe_control writes because the gpu doesn't properly redirect them | |
401 | * through the ppgtt for non_secure batchbuffers. */ | |
402 | if (unlikely(IS_GEN6(dev) && | |
0875546c | 403 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 404 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 405 | PIN_GLOBAL); |
fe14d5f4 TU |
406 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
407 | return ret; | |
408 | } | |
e844b990 | 409 | |
54cf91dc | 410 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 411 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 412 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
413 | "obj %p target %d offset %d " |
414 | "read %08x write %08x", | |
415 | obj, reloc->target_handle, | |
416 | (int) reloc->offset, | |
417 | reloc->read_domains, | |
418 | reloc->write_domain); | |
8b78f0e5 | 419 | return -EINVAL; |
54cf91dc | 420 | } |
4ca4a250 DV |
421 | if (unlikely((reloc->write_domain | reloc->read_domains) |
422 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 423 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
424 | "obj %p target %d offset %d " |
425 | "read %08x write %08x", | |
426 | obj, reloc->target_handle, | |
427 | (int) reloc->offset, | |
428 | reloc->read_domains, | |
429 | reloc->write_domain); | |
8b78f0e5 | 430 | return -EINVAL; |
54cf91dc | 431 | } |
54cf91dc CW |
432 | |
433 | target_obj->pending_read_domains |= reloc->read_domains; | |
434 | target_obj->pending_write_domain |= reloc->write_domain; | |
435 | ||
436 | /* If the relocation already has the right value in it, no | |
437 | * more work needs to be done. | |
438 | */ | |
439 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 440 | return 0; |
54cf91dc CW |
441 | |
442 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
443 | if (unlikely(reloc->offset > |
444 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 445 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
446 | "obj %p target %d offset %d size %d.\n", |
447 | obj, reloc->target_handle, | |
448 | (int) reloc->offset, | |
449 | (int) obj->base.size); | |
8b78f0e5 | 450 | return -EINVAL; |
54cf91dc | 451 | } |
b8f7ab17 | 452 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 453 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
454 | "obj %p target %d offset %d.\n", |
455 | obj, reloc->target_handle, | |
456 | (int) reloc->offset); | |
8b78f0e5 | 457 | return -EINVAL; |
54cf91dc CW |
458 | } |
459 | ||
dabdfe02 CW |
460 | /* We can't wait for rendering with pagefaults disabled */ |
461 | if (obj->active && in_atomic()) | |
462 | return -EFAULT; | |
463 | ||
5032d871 | 464 | if (use_cpu_reloc(obj)) |
d9ceb957 | 465 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
edf4427b | 466 | else if (obj->map_and_fenceable) |
d9ceb957 | 467 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
edf4427b CW |
468 | else if (cpu_has_clflush) |
469 | ret = relocate_entry_clflush(obj, reloc, target_offset); | |
470 | else { | |
471 | WARN_ONCE(1, "Impossible case in relocation handling\n"); | |
472 | ret = -ENODEV; | |
473 | } | |
54cf91dc | 474 | |
d4d36014 DV |
475 | if (ret) |
476 | return ret; | |
477 | ||
54cf91dc CW |
478 | /* and update the user's relocation entry */ |
479 | reloc->presumed_offset = target_offset; | |
480 | ||
67731b87 | 481 | return 0; |
54cf91dc CW |
482 | } |
483 | ||
484 | static int | |
27173f1f BW |
485 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
486 | struct eb_vmas *eb) | |
54cf91dc | 487 | { |
1d83f442 CW |
488 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
489 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 490 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 491 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 492 | int remain, ret; |
54cf91dc | 493 | |
2bb4629a | 494 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 495 | |
1d83f442 CW |
496 | remain = entry->relocation_count; |
497 | while (remain) { | |
498 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
499 | int count = remain; | |
500 | if (count > ARRAY_SIZE(stack_reloc)) | |
501 | count = ARRAY_SIZE(stack_reloc); | |
502 | remain -= count; | |
503 | ||
504 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
505 | return -EFAULT; |
506 | ||
1d83f442 CW |
507 | do { |
508 | u64 offset = r->presumed_offset; | |
54cf91dc | 509 | |
3e7a0322 | 510 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
511 | if (ret) |
512 | return ret; | |
513 | ||
514 | if (r->presumed_offset != offset && | |
515 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
516 | &r->presumed_offset, | |
517 | sizeof(r->presumed_offset))) { | |
518 | return -EFAULT; | |
519 | } | |
520 | ||
521 | user_relocs++; | |
522 | r++; | |
523 | } while (--count); | |
54cf91dc CW |
524 | } |
525 | ||
526 | return 0; | |
1d83f442 | 527 | #undef N_RELOC |
54cf91dc CW |
528 | } |
529 | ||
530 | static int | |
27173f1f BW |
531 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
532 | struct eb_vmas *eb, | |
533 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 534 | { |
27173f1f | 535 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
536 | int i, ret; |
537 | ||
538 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 539 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
540 | if (ret) |
541 | return ret; | |
542 | } | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static int | |
17601cbc | 548 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 549 | { |
27173f1f | 550 | struct i915_vma *vma; |
d4aeee77 CW |
551 | int ret = 0; |
552 | ||
553 | /* This is the fast path and we cannot handle a pagefault whilst | |
554 | * holding the struct mutex lest the user pass in the relocations | |
555 | * contained within a mmaped bo. For in such a case we, the page | |
556 | * fault handler would call i915_gem_fault() and we would try to | |
557 | * acquire the struct mutex again. Obviously this is bad and so | |
558 | * lockdep complains vehemently. | |
559 | */ | |
560 | pagefault_disable(); | |
27173f1f BW |
561 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
562 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 563 | if (ret) |
d4aeee77 | 564 | break; |
54cf91dc | 565 | } |
d4aeee77 | 566 | pagefault_enable(); |
54cf91dc | 567 | |
d4aeee77 | 568 | return ret; |
54cf91dc CW |
569 | } |
570 | ||
edf4427b CW |
571 | static bool only_mappable_for_reloc(unsigned int flags) |
572 | { | |
573 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
574 | __EXEC_OBJECT_NEEDS_MAP; | |
575 | } | |
576 | ||
1690e1eb | 577 | static int |
27173f1f | 578 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 579 | struct intel_engine_cs *ring, |
27173f1f | 580 | bool *need_reloc) |
1690e1eb | 581 | { |
6f65e29a | 582 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 583 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 584 | uint64_t flags; |
1690e1eb CW |
585 | int ret; |
586 | ||
0875546c | 587 | flags = PIN_USER; |
0229da32 DV |
588 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
589 | flags |= PIN_GLOBAL; | |
590 | ||
edf4427b CW |
591 | if (!drm_mm_node_allocated(&vma->node)) { |
592 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) | |
593 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
594 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
595 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
596 | } | |
1ec9e26d DV |
597 | |
598 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
edf4427b CW |
599 | if ((ret == -ENOSPC || ret == -E2BIG) && |
600 | only_mappable_for_reloc(entry->flags)) | |
601 | ret = i915_gem_object_pin(obj, vma->vm, | |
602 | entry->alignment, | |
0229da32 | 603 | flags & ~PIN_MAPPABLE); |
1690e1eb CW |
604 | if (ret) |
605 | return ret; | |
606 | ||
7788a765 CW |
607 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
608 | ||
82b6b6d7 CW |
609 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
610 | ret = i915_gem_object_get_fence(obj); | |
611 | if (ret) | |
612 | return ret; | |
9a5a53b3 | 613 | |
82b6b6d7 CW |
614 | if (i915_gem_object_pin_fence(obj)) |
615 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
616 | } |
617 | ||
27173f1f BW |
618 | if (entry->offset != vma->node.start) { |
619 | entry->offset = vma->node.start; | |
ed5982e6 DV |
620 | *need_reloc = true; |
621 | } | |
622 | ||
623 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
624 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
625 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
626 | } | |
627 | ||
1690e1eb | 628 | return 0; |
7788a765 | 629 | } |
1690e1eb | 630 | |
d23db88c | 631 | static bool |
e6a84468 | 632 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
633 | { |
634 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 635 | |
e6a84468 CW |
636 | if (entry->relocation_count == 0) |
637 | return false; | |
638 | ||
639 | if (!i915_is_ggtt(vma->vm)) | |
640 | return false; | |
641 | ||
642 | /* See also use_cpu_reloc() */ | |
643 | if (HAS_LLC(vma->obj->base.dev)) | |
644 | return false; | |
645 | ||
646 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
647 | return false; | |
648 | ||
649 | return true; | |
650 | } | |
651 | ||
652 | static bool | |
653 | eb_vma_misplaced(struct i915_vma *vma) | |
654 | { | |
655 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
656 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 657 | |
e6a84468 | 658 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
d23db88c CW |
659 | !i915_is_ggtt(vma->vm)); |
660 | ||
661 | if (entry->alignment && | |
662 | vma->node.start & (entry->alignment - 1)) | |
663 | return true; | |
664 | ||
d23db88c CW |
665 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
666 | vma->node.start < BATCH_OFFSET_BIAS) | |
667 | return true; | |
668 | ||
edf4427b CW |
669 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
670 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) | |
671 | return !only_mappable_for_reloc(entry->flags); | |
672 | ||
d23db88c CW |
673 | return false; |
674 | } | |
675 | ||
54cf91dc | 676 | static int |
a4872ba6 | 677 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 678 | struct list_head *vmas, |
ed5982e6 | 679 | bool *need_relocs) |
54cf91dc | 680 | { |
432e58ed | 681 | struct drm_i915_gem_object *obj; |
27173f1f | 682 | struct i915_vma *vma; |
68c8c17f | 683 | struct i915_address_space *vm; |
27173f1f | 684 | struct list_head ordered_vmas; |
7788a765 CW |
685 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
686 | int retry; | |
6fe4f140 | 687 | |
227f782e CW |
688 | i915_gem_retire_requests_ring(ring); |
689 | ||
68c8c17f BW |
690 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
691 | ||
27173f1f BW |
692 | INIT_LIST_HEAD(&ordered_vmas); |
693 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
694 | struct drm_i915_gem_exec_object2 *entry; |
695 | bool need_fence, need_mappable; | |
696 | ||
27173f1f BW |
697 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
698 | obj = vma->obj; | |
699 | entry = vma->exec_entry; | |
6fe4f140 | 700 | |
82b6b6d7 CW |
701 | if (!has_fenced_gpu_access) |
702 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 703 | need_fence = |
6fe4f140 CW |
704 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
705 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 706 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 707 | |
e6a84468 CW |
708 | if (need_mappable) { |
709 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; | |
27173f1f | 710 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 711 | } else |
27173f1f | 712 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 713 | |
ed5982e6 | 714 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 715 | obj->base.pending_write_domain = 0; |
6fe4f140 | 716 | } |
27173f1f | 717 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
718 | |
719 | /* Attempt to pin all of the buffers into the GTT. | |
720 | * This is done in 3 phases: | |
721 | * | |
722 | * 1a. Unbind all objects that do not match the GTT constraints for | |
723 | * the execbuffer (fenceable, mappable, alignment etc). | |
724 | * 1b. Increment pin count for already bound objects. | |
725 | * 2. Bind new objects. | |
726 | * 3. Decrement pin count. | |
727 | * | |
7788a765 | 728 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
729 | * room for the earlier objects *unless* we need to defragment. |
730 | */ | |
731 | retry = 0; | |
732 | do { | |
7788a765 | 733 | int ret = 0; |
54cf91dc CW |
734 | |
735 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 736 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 737 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
738 | continue; |
739 | ||
e6a84468 | 740 | if (eb_vma_misplaced(vma)) |
27173f1f | 741 | ret = i915_vma_unbind(vma); |
54cf91dc | 742 | else |
27173f1f | 743 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 744 | if (ret) |
54cf91dc | 745 | goto err; |
54cf91dc CW |
746 | } |
747 | ||
748 | /* Bind fresh objects */ | |
27173f1f BW |
749 | list_for_each_entry(vma, vmas, exec_list) { |
750 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 751 | continue; |
54cf91dc | 752 | |
27173f1f | 753 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
754 | if (ret) |
755 | goto err; | |
54cf91dc CW |
756 | } |
757 | ||
a415d355 | 758 | err: |
6c085a72 | 759 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
760 | return ret; |
761 | ||
a415d355 CW |
762 | /* Decrement pin count for bound objects */ |
763 | list_for_each_entry(vma, vmas, exec_list) | |
764 | i915_gem_execbuffer_unreserve_vma(vma); | |
765 | ||
68c8c17f | 766 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
767 | if (ret) |
768 | return ret; | |
54cf91dc CW |
769 | } while (1); |
770 | } | |
771 | ||
772 | static int | |
773 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 774 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 775 | struct drm_file *file, |
a4872ba6 | 776 | struct intel_engine_cs *ring, |
27173f1f BW |
777 | struct eb_vmas *eb, |
778 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
779 | { |
780 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
781 | struct i915_address_space *vm; |
782 | struct i915_vma *vma; | |
ed5982e6 | 783 | bool need_relocs; |
dd6864a4 | 784 | int *reloc_offset; |
54cf91dc | 785 | int i, total, ret; |
b205ca57 | 786 | unsigned count = args->buffer_count; |
54cf91dc | 787 | |
27173f1f BW |
788 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
789 | ||
67731b87 | 790 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
791 | while (!list_empty(&eb->vmas)) { |
792 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
793 | list_del_init(&vma->exec_list); | |
a415d355 | 794 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 795 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
796 | } |
797 | ||
54cf91dc CW |
798 | mutex_unlock(&dev->struct_mutex); |
799 | ||
800 | total = 0; | |
801 | for (i = 0; i < count; i++) | |
432e58ed | 802 | total += exec[i].relocation_count; |
54cf91dc | 803 | |
dd6864a4 | 804 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 805 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
806 | if (reloc == NULL || reloc_offset == NULL) { |
807 | drm_free_large(reloc); | |
808 | drm_free_large(reloc_offset); | |
54cf91dc CW |
809 | mutex_lock(&dev->struct_mutex); |
810 | return -ENOMEM; | |
811 | } | |
812 | ||
813 | total = 0; | |
814 | for (i = 0; i < count; i++) { | |
815 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
816 | u64 invalid_offset = (u64)-1; |
817 | int j; | |
54cf91dc | 818 | |
2bb4629a | 819 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
820 | |
821 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 822 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
823 | ret = -EFAULT; |
824 | mutex_lock(&dev->struct_mutex); | |
825 | goto err; | |
826 | } | |
827 | ||
262b6d36 CW |
828 | /* As we do not update the known relocation offsets after |
829 | * relocating (due to the complexities in lock handling), | |
830 | * we need to mark them as invalid now so that we force the | |
831 | * relocation processing next time. Just in case the target | |
832 | * object is evicted and then rebound into its old | |
833 | * presumed_offset before the next execbuffer - if that | |
834 | * happened we would make the mistake of assuming that the | |
835 | * relocations were valid. | |
836 | */ | |
837 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
838 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
839 | &invalid_offset, | |
840 | sizeof(invalid_offset))) { | |
262b6d36 CW |
841 | ret = -EFAULT; |
842 | mutex_lock(&dev->struct_mutex); | |
843 | goto err; | |
844 | } | |
845 | } | |
846 | ||
dd6864a4 | 847 | reloc_offset[i] = total; |
432e58ed | 848 | total += exec[i].relocation_count; |
54cf91dc CW |
849 | } |
850 | ||
851 | ret = i915_mutex_lock_interruptible(dev); | |
852 | if (ret) { | |
853 | mutex_lock(&dev->struct_mutex); | |
854 | goto err; | |
855 | } | |
856 | ||
67731b87 | 857 | /* reacquire the objects */ |
67731b87 | 858 | eb_reset(eb); |
27173f1f | 859 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
860 | if (ret) |
861 | goto err; | |
67731b87 | 862 | |
ed5982e6 | 863 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 864 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
865 | if (ret) |
866 | goto err; | |
867 | ||
27173f1f BW |
868 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
869 | int offset = vma->exec_entry - exec; | |
870 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
871 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
872 | if (ret) |
873 | goto err; | |
54cf91dc CW |
874 | } |
875 | ||
876 | /* Leave the user relocations as are, this is the painfully slow path, | |
877 | * and we want to avoid the complication of dropping the lock whilst | |
878 | * having buffers reserved in the aperture and so causing spurious | |
879 | * ENOSPC for random operations. | |
880 | */ | |
881 | ||
882 | err: | |
883 | drm_free_large(reloc); | |
dd6864a4 | 884 | drm_free_large(reloc_offset); |
54cf91dc CW |
885 | return ret; |
886 | } | |
887 | ||
54cf91dc | 888 | static int |
a4872ba6 | 889 | i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, |
27173f1f | 890 | struct list_head *vmas) |
54cf91dc | 891 | { |
27173f1f | 892 | struct i915_vma *vma; |
6ac42f41 | 893 | uint32_t flush_domains = 0; |
000433b6 | 894 | bool flush_chipset = false; |
432e58ed | 895 | int ret; |
54cf91dc | 896 | |
27173f1f BW |
897 | list_for_each_entry(vma, vmas, exec_list) { |
898 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 899 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
900 | if (ret) |
901 | return ret; | |
6ac42f41 DV |
902 | |
903 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 904 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 905 | |
6ac42f41 | 906 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
907 | } |
908 | ||
000433b6 | 909 | if (flush_chipset) |
e76e9aeb | 910 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
911 | |
912 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
913 | wmb(); | |
914 | ||
09cf7c9a CW |
915 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
916 | * any residual writes from the previous batch. | |
917 | */ | |
a7b9761d | 918 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
919 | } |
920 | ||
432e58ed CW |
921 | static bool |
922 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 923 | { |
ed5982e6 DV |
924 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
925 | return false; | |
926 | ||
432e58ed | 927 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
928 | } |
929 | ||
930 | static int | |
ad19f10b CW |
931 | validate_exec_list(struct drm_device *dev, |
932 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
933 | int count) |
934 | { | |
b205ca57 DV |
935 | unsigned relocs_total = 0; |
936 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
937 | unsigned invalid_flags; |
938 | int i; | |
939 | ||
940 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
941 | if (USES_FULL_PPGTT(dev)) | |
942 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
943 | |
944 | for (i = 0; i < count; i++) { | |
2bb4629a | 945 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
946 | int length; /* limited by fault_in_pages_readable() */ |
947 | ||
ad19f10b | 948 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
949 | return -EINVAL; |
950 | ||
3118a4f6 KC |
951 | /* First check for malicious input causing overflow in |
952 | * the worst case where we need to allocate the entire | |
953 | * relocation tree as a single array. | |
954 | */ | |
955 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 956 | return -EINVAL; |
3118a4f6 | 957 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
958 | |
959 | length = exec[i].relocation_count * | |
960 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
961 | /* |
962 | * We must check that the entire relocation array is safe | |
963 | * to read, but since we may need to update the presumed | |
964 | * offsets during execution, check for full write access. | |
965 | */ | |
54cf91dc CW |
966 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
967 | return -EFAULT; | |
968 | ||
d330a953 | 969 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
970 | if (fault_in_multipages_readable(ptr, length)) |
971 | return -EFAULT; | |
972 | } | |
54cf91dc CW |
973 | } |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
273497e5 | 978 | static struct intel_context * |
d299cce7 | 979 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 980 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 981 | { |
273497e5 | 982 | struct intel_context *ctx = NULL; |
d299cce7 MK |
983 | struct i915_ctx_hang_stats *hs; |
984 | ||
821d66dd | 985 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
986 | return ERR_PTR(-EINVAL); |
987 | ||
41bde553 | 988 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 989 | if (IS_ERR(ctx)) |
41bde553 | 990 | return ctx; |
d299cce7 | 991 | |
41bde553 | 992 | hs = &ctx->hang_stats; |
d299cce7 MK |
993 | if (hs->banned) { |
994 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 995 | return ERR_PTR(-EIO); |
d299cce7 MK |
996 | } |
997 | ||
ec3e9963 OM |
998 | if (i915.enable_execlists && !ctx->engine[ring->id].state) { |
999 | int ret = intel_lr_context_deferred_create(ctx, ring); | |
1000 | if (ret) { | |
1001 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
1002 | return ERR_PTR(ret); | |
1003 | } | |
1004 | } | |
1005 | ||
41bde553 | 1006 | return ctx; |
d299cce7 MK |
1007 | } |
1008 | ||
ba8b7ccb | 1009 | void |
27173f1f | 1010 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
a4872ba6 | 1011 | struct intel_engine_cs *ring) |
432e58ed | 1012 | { |
97b2a6a1 | 1013 | struct drm_i915_gem_request *req = intel_ring_get_request(ring); |
27173f1f | 1014 | struct i915_vma *vma; |
432e58ed | 1015 | |
27173f1f | 1016 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 1017 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 1018 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
1019 | u32 old_read = obj->base.read_domains; |
1020 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1021 | |
432e58ed | 1022 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
1023 | if (obj->base.write_domain == 0) |
1024 | obj->base.pending_read_domains |= obj->base.read_domains; | |
1025 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1026 | |
e2d05a8b | 1027 | i915_vma_move_to_active(vma, ring); |
432e58ed CW |
1028 | if (obj->base.write_domain) { |
1029 | obj->dirty = 1; | |
97b2a6a1 | 1030 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 | 1031 | |
a4001f1b | 1032 | intel_fb_obj_invalidate(obj, ring, ORIGIN_CS); |
c8725f3d CW |
1033 | |
1034 | /* update for the implicit flush after a batch */ | |
1035 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 1036 | } |
82b6b6d7 | 1037 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 1038 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 CW |
1039 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
1040 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
1041 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
1042 | &dev_priv->mm.fence_list); | |
1043 | } | |
1044 | } | |
432e58ed | 1045 | |
db53a302 | 1046 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1047 | } |
1048 | } | |
1049 | ||
ba8b7ccb | 1050 | void |
54cf91dc | 1051 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
432e58ed | 1052 | struct drm_file *file, |
a4872ba6 | 1053 | struct intel_engine_cs *ring, |
7d736f4f | 1054 | struct drm_i915_gem_object *obj) |
54cf91dc | 1055 | { |
cc889e0f DV |
1056 | /* Unconditionally force add_request to emit a full flush. */ |
1057 | ring->gpu_caches_dirty = true; | |
54cf91dc | 1058 | |
432e58ed | 1059 | /* Add a breadcrumb for the completion of the batch buffer */ |
9400ae5c | 1060 | (void)__i915_add_request(ring, file, obj); |
432e58ed | 1061 | } |
54cf91dc | 1062 | |
ae662d31 EA |
1063 | static int |
1064 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
a4872ba6 | 1065 | struct intel_engine_cs *ring) |
ae662d31 | 1066 | { |
50227e1c | 1067 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1068 | int ret, i; |
1069 | ||
9d662da8 DV |
1070 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1071 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1072 | return -EINVAL; | |
1073 | } | |
ae662d31 EA |
1074 | |
1075 | ret = intel_ring_begin(ring, 4 * 3); | |
1076 | if (ret) | |
1077 | return ret; | |
1078 | ||
1079 | for (i = 0; i < 4; i++) { | |
1080 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1081 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1082 | intel_ring_emit(ring, 0); | |
1083 | } | |
1084 | ||
1085 | intel_ring_advance(ring); | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
5c6c6003 CW |
1090 | static int |
1091 | i915_emit_box(struct intel_engine_cs *ring, | |
1092 | struct drm_clip_rect *box, | |
1093 | int DR1, int DR4) | |
1094 | { | |
1095 | int ret; | |
1096 | ||
1097 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || | |
1098 | box->y2 <= 0 || box->x2 <= 0) { | |
1099 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
1100 | box->x1, box->y1, box->x2, box->y2); | |
1101 | return -EINVAL; | |
1102 | } | |
1103 | ||
1104 | if (INTEL_INFO(ring->dev)->gen >= 4) { | |
1105 | ret = intel_ring_begin(ring, 4); | |
1106 | if (ret) | |
1107 | return ret; | |
1108 | ||
1109 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965); | |
1110 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1111 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1112 | intel_ring_emit(ring, DR4); | |
1113 | } else { | |
1114 | ret = intel_ring_begin(ring, 6); | |
1115 | if (ret) | |
1116 | return ret; | |
1117 | ||
1118 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO); | |
1119 | intel_ring_emit(ring, DR1); | |
1120 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1121 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1122 | intel_ring_emit(ring, DR4); | |
1123 | intel_ring_emit(ring, 0); | |
1124 | } | |
1125 | intel_ring_advance(ring); | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
71745376 BV |
1130 | static struct drm_i915_gem_object* |
1131 | i915_gem_execbuffer_parse(struct intel_engine_cs *ring, | |
1132 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, | |
1133 | struct eb_vmas *eb, | |
1134 | struct drm_i915_gem_object *batch_obj, | |
1135 | u32 batch_start_offset, | |
1136 | u32 batch_len, | |
17cabf57 | 1137 | bool is_master) |
71745376 | 1138 | { |
71745376 | 1139 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1140 | struct i915_vma *vma; |
71745376 BV |
1141 | int ret; |
1142 | ||
06fbca71 | 1143 | shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool, |
17cabf57 | 1144 | PAGE_ALIGN(batch_len)); |
71745376 BV |
1145 | if (IS_ERR(shadow_batch_obj)) |
1146 | return shadow_batch_obj; | |
1147 | ||
1148 | ret = i915_parse_cmds(ring, | |
1149 | batch_obj, | |
1150 | shadow_batch_obj, | |
1151 | batch_start_offset, | |
1152 | batch_len, | |
1153 | is_master); | |
17cabf57 CW |
1154 | if (ret) |
1155 | goto err; | |
71745376 | 1156 | |
17cabf57 CW |
1157 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); |
1158 | if (ret) | |
1159 | goto err; | |
71745376 | 1160 | |
de4e783a CW |
1161 | i915_gem_object_unpin_pages(shadow_batch_obj); |
1162 | ||
17cabf57 | 1163 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1164 | |
17cabf57 CW |
1165 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1166 | vma->exec_entry = shadow_exec_entry; | |
de4e783a | 1167 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
17cabf57 CW |
1168 | drm_gem_object_reference(&shadow_batch_obj->base); |
1169 | list_add_tail(&vma->exec_list, &eb->vmas); | |
71745376 | 1170 | |
17cabf57 CW |
1171 | shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
1172 | ||
1173 | return shadow_batch_obj; | |
71745376 | 1174 | |
17cabf57 | 1175 | err: |
de4e783a | 1176 | i915_gem_object_unpin_pages(shadow_batch_obj); |
17cabf57 CW |
1177 | if (ret == -EACCES) /* unhandled chained batch */ |
1178 | return batch_obj; | |
1179 | else | |
1180 | return ERR_PTR(ret); | |
71745376 | 1181 | } |
5c6c6003 | 1182 | |
a83014d3 OM |
1183 | int |
1184 | i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, | |
1185 | struct intel_engine_cs *ring, | |
1186 | struct intel_context *ctx, | |
1187 | struct drm_i915_gem_execbuffer2 *args, | |
1188 | struct list_head *vmas, | |
1189 | struct drm_i915_gem_object *batch_obj, | |
8e004efc | 1190 | u64 exec_start, u32 dispatch_flags) |
78382593 OM |
1191 | { |
1192 | struct drm_clip_rect *cliprects = NULL; | |
1193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1194 | u64 exec_len; | |
1195 | int instp_mode; | |
1196 | u32 instp_mask; | |
1197 | int i, ret = 0; | |
1198 | ||
1199 | if (args->num_cliprects != 0) { | |
1200 | if (ring != &dev_priv->ring[RCS]) { | |
1201 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); | |
1202 | return -EINVAL; | |
1203 | } | |
1204 | ||
1205 | if (INTEL_INFO(dev)->gen >= 5) { | |
1206 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1207 | return -EINVAL; | |
1208 | } | |
1209 | ||
1210 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { | |
1211 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1212 | args->num_cliprects); | |
1213 | return -EINVAL; | |
1214 | } | |
1215 | ||
1216 | cliprects = kcalloc(args->num_cliprects, | |
1217 | sizeof(*cliprects), | |
1218 | GFP_KERNEL); | |
1219 | if (cliprects == NULL) { | |
1220 | ret = -ENOMEM; | |
1221 | goto error; | |
1222 | } | |
1223 | ||
1224 | if (copy_from_user(cliprects, | |
1225 | to_user_ptr(args->cliprects_ptr), | |
1226 | sizeof(*cliprects)*args->num_cliprects)) { | |
1227 | ret = -EFAULT; | |
1228 | goto error; | |
1229 | } | |
1230 | } else { | |
1231 | if (args->DR4 == 0xffffffff) { | |
1232 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1233 | args->DR4 = 0; | |
1234 | } | |
1235 | ||
1236 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
1237 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
1238 | return -EINVAL; | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | ret = i915_gem_execbuffer_move_to_gpu(ring, vmas); | |
1243 | if (ret) | |
1244 | goto error; | |
1245 | ||
1246 | ret = i915_switch_context(ring, ctx); | |
1247 | if (ret) | |
1248 | goto error; | |
1249 | ||
9258811c DV |
1250 | WARN(ctx->ppgtt && ctx->ppgtt->pd_dirty_rings & (1<<ring->id), |
1251 | "%s didn't clear reload\n", ring->name); | |
563222a7 | 1252 | |
78382593 OM |
1253 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
1254 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1255 | switch (instp_mode) { | |
1256 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1257 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1258 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1259 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
1260 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
1261 | ret = -EINVAL; | |
1262 | goto error; | |
1263 | } | |
1264 | ||
1265 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1266 | if (INTEL_INFO(dev)->gen < 4) { | |
1267 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
1268 | ret = -EINVAL; | |
1269 | goto error; | |
1270 | } | |
1271 | ||
1272 | if (INTEL_INFO(dev)->gen > 5 && | |
1273 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1274 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
1275 | ret = -EINVAL; | |
1276 | goto error; | |
1277 | } | |
1278 | ||
1279 | /* The HW changed the meaning on this bit on gen6 */ | |
1280 | if (INTEL_INFO(dev)->gen >= 6) | |
1281 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1282 | } | |
1283 | break; | |
1284 | default: | |
1285 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
1286 | ret = -EINVAL; | |
1287 | goto error; | |
1288 | } | |
1289 | ||
1290 | if (ring == &dev_priv->ring[RCS] && | |
1291 | instp_mode != dev_priv->relative_constants_mode) { | |
1292 | ret = intel_ring_begin(ring, 4); | |
1293 | if (ret) | |
1294 | goto error; | |
1295 | ||
1296 | intel_ring_emit(ring, MI_NOOP); | |
1297 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1298 | intel_ring_emit(ring, INSTPM); | |
1299 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1300 | intel_ring_advance(ring); | |
1301 | ||
1302 | dev_priv->relative_constants_mode = instp_mode; | |
1303 | } | |
1304 | ||
1305 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
1306 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1307 | if (ret) | |
1308 | goto error; | |
1309 | } | |
1310 | ||
1311 | exec_len = args->batch_len; | |
1312 | if (cliprects) { | |
1313 | for (i = 0; i < args->num_cliprects; i++) { | |
5c6c6003 | 1314 | ret = i915_emit_box(ring, &cliprects[i], |
78382593 OM |
1315 | args->DR1, args->DR4); |
1316 | if (ret) | |
1317 | goto error; | |
1318 | ||
1319 | ret = ring->dispatch_execbuffer(ring, | |
1320 | exec_start, exec_len, | |
8e004efc | 1321 | dispatch_flags); |
78382593 OM |
1322 | if (ret) |
1323 | goto error; | |
1324 | } | |
1325 | } else { | |
1326 | ret = ring->dispatch_execbuffer(ring, | |
1327 | exec_start, exec_len, | |
8e004efc | 1328 | dispatch_flags); |
78382593 OM |
1329 | if (ret) |
1330 | return ret; | |
1331 | } | |
1332 | ||
8e004efc | 1333 | trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags); |
78382593 OM |
1334 | |
1335 | i915_gem_execbuffer_move_to_active(vmas, ring); | |
1336 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); | |
1337 | ||
1338 | error: | |
1339 | kfree(cliprects); | |
1340 | return ret; | |
1341 | } | |
1342 | ||
a8ebba75 ZY |
1343 | /** |
1344 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1345 | * The Ring ID is returned. | |
1346 | */ | |
1347 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1348 | struct drm_file *file) | |
1349 | { | |
1350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1351 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1352 | ||
1353 | /* Check whether the file_priv is using one ring */ | |
1354 | if (file_priv->bsd_ring) | |
1355 | return file_priv->bsd_ring->id; | |
1356 | else { | |
1357 | /* If no, use the ping-pong mechanism to select one ring */ | |
1358 | int ring_id; | |
1359 | ||
1360 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1361 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1362 | ring_id = VCS; |
bdf1e7e3 | 1363 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1364 | } else { |
1365 | ring_id = VCS2; | |
bdf1e7e3 | 1366 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1367 | } |
1368 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1369 | mutex_unlock(&dev->struct_mutex); | |
1370 | return ring_id; | |
1371 | } | |
1372 | } | |
1373 | ||
d23db88c CW |
1374 | static struct drm_i915_gem_object * |
1375 | eb_get_batch(struct eb_vmas *eb) | |
1376 | { | |
1377 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1378 | ||
1379 | /* | |
1380 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1381 | * to negative relocation deltas. Usually that works out ok since the | |
1382 | * relocate address is still positive, except when the batch is placed | |
1383 | * very low in the GTT. Ensure this doesn't happen. | |
1384 | * | |
1385 | * Note that actual hangs have only been observed on gen7, but for | |
1386 | * paranoia do it everywhere. | |
1387 | */ | |
1388 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
1389 | ||
1390 | return vma->obj; | |
1391 | } | |
1392 | ||
54cf91dc CW |
1393 | static int |
1394 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1395 | struct drm_file *file, | |
1396 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1397 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1398 | { |
50227e1c | 1399 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1400 | struct eb_vmas *eb; |
54cf91dc | 1401 | struct drm_i915_gem_object *batch_obj; |
78a42377 | 1402 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
a4872ba6 | 1403 | struct intel_engine_cs *ring; |
273497e5 | 1404 | struct intel_context *ctx; |
41bde553 | 1405 | struct i915_address_space *vm; |
d299cce7 | 1406 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
78382593 | 1407 | u64 exec_start = args->batch_start_offset; |
8e004efc | 1408 | u32 dispatch_flags; |
78382593 | 1409 | int ret; |
ed5982e6 | 1410 | bool need_relocs; |
54cf91dc | 1411 | |
ed5982e6 | 1412 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1413 | return -EINVAL; |
432e58ed | 1414 | |
ad19f10b | 1415 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1416 | if (ret) |
1417 | return ret; | |
1418 | ||
8e004efc | 1419 | dispatch_flags = 0; |
d7d4eedd CW |
1420 | if (args->flags & I915_EXEC_SECURE) { |
1421 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1422 | return -EPERM; | |
1423 | ||
8e004efc | 1424 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1425 | } |
b45305fc | 1426 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1427 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1428 | |
b1a93306 | 1429 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1430 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1431 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1432 | return -EINVAL; | |
1433 | } | |
ca01b12b | 1434 | |
8d360dff ZG |
1435 | if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) && |
1436 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1437 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1438 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
1439 | return -EINVAL; | |
1440 | } | |
1441 | ||
ca01b12b BW |
1442 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) |
1443 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1444 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1445 | if (HAS_BSD2(dev)) { | |
1446 | int ring_id; | |
8d360dff ZG |
1447 | |
1448 | switch (args->flags & I915_EXEC_BSD_MASK) { | |
1449 | case I915_EXEC_BSD_DEFAULT: | |
1450 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1451 | ring = &dev_priv->ring[ring_id]; | |
1452 | break; | |
1453 | case I915_EXEC_BSD_RING1: | |
1454 | ring = &dev_priv->ring[VCS]; | |
1455 | break; | |
1456 | case I915_EXEC_BSD_RING2: | |
1457 | ring = &dev_priv->ring[VCS2]; | |
1458 | break; | |
1459 | default: | |
1460 | DRM_DEBUG("execbuf with unknown bsd ring: %d\n", | |
1461 | (int)(args->flags & I915_EXEC_BSD_MASK)); | |
1462 | return -EINVAL; | |
1463 | } | |
a8ebba75 ZY |
1464 | } else |
1465 | ring = &dev_priv->ring[VCS]; | |
1466 | } else | |
ca01b12b BW |
1467 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1468 | ||
a15817cf CW |
1469 | if (!intel_ring_initialized(ring)) { |
1470 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1471 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1472 | return -EINVAL; | |
1473 | } | |
54cf91dc CW |
1474 | |
1475 | if (args->buffer_count < 1) { | |
ff240199 | 1476 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1477 | return -EINVAL; |
1478 | } | |
54cf91dc | 1479 | |
f65c9168 PZ |
1480 | intel_runtime_pm_get(dev_priv); |
1481 | ||
54cf91dc CW |
1482 | ret = i915_mutex_lock_interruptible(dev); |
1483 | if (ret) | |
1484 | goto pre_mutex_err; | |
1485 | ||
7c9c4b8f | 1486 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1487 | if (IS_ERR(ctx)) { |
d299cce7 | 1488 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1489 | ret = PTR_ERR(ctx); |
d299cce7 | 1490 | goto pre_mutex_err; |
935f38d6 | 1491 | } |
41bde553 BW |
1492 | |
1493 | i915_gem_context_reference(ctx); | |
1494 | ||
ae6c4806 DV |
1495 | if (ctx->ppgtt) |
1496 | vm = &ctx->ppgtt->base; | |
1497 | else | |
7e0d96bc | 1498 | vm = &dev_priv->gtt.base; |
d299cce7 | 1499 | |
17601cbc | 1500 | eb = eb_create(args); |
67731b87 | 1501 | if (eb == NULL) { |
935f38d6 | 1502 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1503 | mutex_unlock(&dev->struct_mutex); |
1504 | ret = -ENOMEM; | |
1505 | goto pre_mutex_err; | |
1506 | } | |
1507 | ||
54cf91dc | 1508 | /* Look up object handles */ |
27173f1f | 1509 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1510 | if (ret) |
1511 | goto err; | |
54cf91dc | 1512 | |
6fe4f140 | 1513 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1514 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1515 | |
54cf91dc | 1516 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1517 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1518 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1519 | if (ret) |
1520 | goto err; | |
1521 | ||
1522 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1523 | if (need_relocs) |
17601cbc | 1524 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1525 | if (ret) { |
1526 | if (ret == -EFAULT) { | |
ed5982e6 | 1527 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1528 | eb, exec); |
54cf91dc CW |
1529 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1530 | } | |
1531 | if (ret) | |
1532 | goto err; | |
1533 | } | |
1534 | ||
1535 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1536 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1537 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1538 | ret = -EINVAL; |
1539 | goto err; | |
1540 | } | |
54cf91dc | 1541 | |
743e78c1 | 1542 | if (i915_needs_cmd_parser(ring) && args->batch_len) { |
71745376 BV |
1543 | batch_obj = i915_gem_execbuffer_parse(ring, |
1544 | &shadow_exec_entry, | |
1545 | eb, | |
1546 | batch_obj, | |
1547 | args->batch_start_offset, | |
1548 | args->batch_len, | |
17cabf57 | 1549 | file->is_master); |
71745376 BV |
1550 | if (IS_ERR(batch_obj)) { |
1551 | ret = PTR_ERR(batch_obj); | |
78a42377 BV |
1552 | goto err; |
1553 | } | |
17cabf57 CW |
1554 | |
1555 | /* | |
1556 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1557 | * bit from MI_BATCH_BUFFER_START commands issued in the | |
1558 | * dispatch_execbuffer implementations. We specifically | |
1559 | * don't want that set when the command parser is | |
1560 | * enabled. | |
17cabf57 | 1561 | */ |
c6b8a4bc | 1562 | dispatch_flags |= I915_DISPATCH_SECURE; |
17cabf57 CW |
1563 | |
1564 | exec_start = 0; | |
351e3db2 BV |
1565 | } |
1566 | ||
78a42377 BV |
1567 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1568 | ||
d7d4eedd CW |
1569 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1570 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1571 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1572 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
da51a1e7 DV |
1573 | /* |
1574 | * So on first glance it looks freaky that we pin the batch here | |
1575 | * outside of the reservation loop. But: | |
1576 | * - The batch is already pinned into the relevant ppgtt, so we | |
1577 | * already have the backing storage fully allocated. | |
1578 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1579 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1580 | * fitting due to fragmentation. |
1581 | * So this is actually safe. | |
1582 | */ | |
1583 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1584 | if (ret) | |
1585 | goto err; | |
d7d4eedd | 1586 | |
7e0d96bc | 1587 | exec_start += i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1588 | } else |
7e0d96bc | 1589 | exec_start += i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1590 | |
f3dc74c0 JH |
1591 | ret = dev_priv->gt.execbuf_submit(dev, file, ring, ctx, args, |
1592 | &eb->vmas, batch_obj, exec_start, | |
1593 | dispatch_flags); | |
54cf91dc | 1594 | |
da51a1e7 DV |
1595 | /* |
1596 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1597 | * batch vma for correctness. For less ugly and less fragility this | |
1598 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1599 | * active. | |
1600 | */ | |
8e004efc | 1601 | if (dispatch_flags & I915_DISPATCH_SECURE) |
da51a1e7 | 1602 | i915_gem_object_ggtt_unpin(batch_obj); |
54cf91dc | 1603 | err: |
41bde553 BW |
1604 | /* the request owns the ref now */ |
1605 | i915_gem_context_unreference(ctx); | |
67731b87 | 1606 | eb_destroy(eb); |
54cf91dc CW |
1607 | |
1608 | mutex_unlock(&dev->struct_mutex); | |
1609 | ||
1610 | pre_mutex_err: | |
f65c9168 PZ |
1611 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1612 | * is really idle. */ | |
1613 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1614 | return ret; |
1615 | } | |
1616 | ||
1617 | /* | |
1618 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1619 | * list array and passes it to the real function. | |
1620 | */ | |
1621 | int | |
1622 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1623 | struct drm_file *file) | |
1624 | { | |
1625 | struct drm_i915_gem_execbuffer *args = data; | |
1626 | struct drm_i915_gem_execbuffer2 exec2; | |
1627 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1628 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1629 | int ret, i; | |
1630 | ||
54cf91dc | 1631 | if (args->buffer_count < 1) { |
ff240199 | 1632 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1633 | return -EINVAL; |
1634 | } | |
1635 | ||
1636 | /* Copy in the exec list from userland */ | |
1637 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1638 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1639 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1640 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1641 | args->buffer_count); |
1642 | drm_free_large(exec_list); | |
1643 | drm_free_large(exec2_list); | |
1644 | return -ENOMEM; | |
1645 | } | |
1646 | ret = copy_from_user(exec_list, | |
2bb4629a | 1647 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1648 | sizeof(*exec_list) * args->buffer_count); |
1649 | if (ret != 0) { | |
ff240199 | 1650 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1651 | args->buffer_count, ret); |
1652 | drm_free_large(exec_list); | |
1653 | drm_free_large(exec2_list); | |
1654 | return -EFAULT; | |
1655 | } | |
1656 | ||
1657 | for (i = 0; i < args->buffer_count; i++) { | |
1658 | exec2_list[i].handle = exec_list[i].handle; | |
1659 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1660 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1661 | exec2_list[i].alignment = exec_list[i].alignment; | |
1662 | exec2_list[i].offset = exec_list[i].offset; | |
1663 | if (INTEL_INFO(dev)->gen < 4) | |
1664 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1665 | else | |
1666 | exec2_list[i].flags = 0; | |
1667 | } | |
1668 | ||
1669 | exec2.buffers_ptr = args->buffers_ptr; | |
1670 | exec2.buffer_count = args->buffer_count; | |
1671 | exec2.batch_start_offset = args->batch_start_offset; | |
1672 | exec2.batch_len = args->batch_len; | |
1673 | exec2.DR1 = args->DR1; | |
1674 | exec2.DR4 = args->DR4; | |
1675 | exec2.num_cliprects = args->num_cliprects; | |
1676 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1677 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1678 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1679 | |
41bde553 | 1680 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1681 | if (!ret) { |
9aab8bff CW |
1682 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1683 | to_user_ptr(args->buffers_ptr); | |
1684 | ||
54cf91dc | 1685 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff CW |
1686 | for (i = 0; i < args->buffer_count; i++) { |
1687 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1688 | &exec2_list[i].offset, | |
1689 | sizeof(user_exec_list[i].offset)); | |
1690 | if (ret) { | |
1691 | ret = -EFAULT; | |
1692 | DRM_DEBUG("failed to copy %d exec entries " | |
1693 | "back to user (%d)\n", | |
1694 | args->buffer_count, ret); | |
1695 | break; | |
1696 | } | |
54cf91dc CW |
1697 | } |
1698 | } | |
1699 | ||
1700 | drm_free_large(exec_list); | |
1701 | drm_free_large(exec2_list); | |
1702 | return ret; | |
1703 | } | |
1704 | ||
1705 | int | |
1706 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1707 | struct drm_file *file) | |
1708 | { | |
1709 | struct drm_i915_gem_execbuffer2 *args = data; | |
1710 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1711 | int ret; | |
1712 | ||
ed8cd3b2 XW |
1713 | if (args->buffer_count < 1 || |
1714 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1715 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1716 | return -EINVAL; |
1717 | } | |
1718 | ||
9cb34664 DV |
1719 | if (args->rsvd2 != 0) { |
1720 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1721 | return -EINVAL; | |
1722 | } | |
1723 | ||
8408c282 | 1724 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1725 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1726 | if (exec2_list == NULL) |
1727 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1728 | args->buffer_count); | |
54cf91dc | 1729 | if (exec2_list == NULL) { |
ff240199 | 1730 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1731 | args->buffer_count); |
1732 | return -ENOMEM; | |
1733 | } | |
1734 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1735 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1736 | sizeof(*exec2_list) * args->buffer_count); |
1737 | if (ret != 0) { | |
ff240199 | 1738 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1739 | args->buffer_count, ret); |
1740 | drm_free_large(exec2_list); | |
1741 | return -EFAULT; | |
1742 | } | |
1743 | ||
41bde553 | 1744 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1745 | if (!ret) { |
1746 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1747 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1748 | to_user_ptr(args->buffers_ptr); |
1749 | int i; | |
1750 | ||
1751 | for (i = 0; i < args->buffer_count; i++) { | |
1752 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1753 | &exec2_list[i].offset, | |
1754 | sizeof(user_exec_list[i].offset)); | |
1755 | if (ret) { | |
1756 | ret = -EFAULT; | |
1757 | DRM_DEBUG("failed to copy %d exec entries " | |
1758 | "back to user\n", | |
1759 | args->buffer_count); | |
1760 | break; | |
1761 | } | |
54cf91dc CW |
1762 | } |
1763 | } | |
1764 | ||
1765 | drm_free_large(exec2_list); | |
1766 | return ret; | |
1767 | } |