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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
ad778f89 CW |
29 | #include <linux/dma_remapping.h> |
30 | #include <linux/reservation.h> | |
fec0445c | 31 | #include <linux/sync_file.h> |
ad778f89 CW |
32 | #include <linux/uaccess.h> |
33 | ||
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
ad778f89 | 36 | |
54cf91dc | 37 | #include "i915_drv.h" |
57822dc6 | 38 | #include "i915_gem_clflush.h" |
54cf91dc CW |
39 | #include "i915_trace.h" |
40 | #include "intel_drv.h" | |
5d723d7a | 41 | #include "intel_frontbuffer.h" |
54cf91dc | 42 | |
7dd4f672 CW |
43 | enum { |
44 | FORCE_CPU_RELOC = 1, | |
45 | FORCE_GTT_RELOC, | |
46 | FORCE_GPU_RELOC, | |
47 | #define DBG_FORCE_RELOC 0 /* choose one of the above! */ | |
48 | }; | |
d50415cc | 49 | |
dade2a61 CW |
50 | #define __EXEC_OBJECT_HAS_REF BIT(31) |
51 | #define __EXEC_OBJECT_HAS_PIN BIT(30) | |
52 | #define __EXEC_OBJECT_HAS_FENCE BIT(29) | |
53 | #define __EXEC_OBJECT_NEEDS_MAP BIT(28) | |
54 | #define __EXEC_OBJECT_NEEDS_BIAS BIT(27) | |
55 | #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ | |
2889caa9 CW |
56 | #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) |
57 | ||
58 | #define __EXEC_HAS_RELOC BIT(31) | |
59 | #define __EXEC_VALIDATED BIT(30) | |
60 | #define UPDATE PIN_OFFSET_FIXED | |
d23db88c CW |
61 | |
62 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 63 | |
650bc635 CW |
64 | #define __I915_EXEC_ILLEGAL_FLAGS \ |
65 | (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK) | |
5b043f4e | 66 | |
2889caa9 CW |
67 | /** |
68 | * DOC: User command execution | |
69 | * | |
70 | * Userspace submits commands to be executed on the GPU as an instruction | |
71 | * stream within a GEM object we call a batchbuffer. This instructions may | |
72 | * refer to other GEM objects containing auxiliary state such as kernels, | |
73 | * samplers, render targets and even secondary batchbuffers. Userspace does | |
74 | * not know where in the GPU memory these objects reside and so before the | |
75 | * batchbuffer is passed to the GPU for execution, those addresses in the | |
76 | * batchbuffer and auxiliary objects are updated. This is known as relocation, | |
77 | * or patching. To try and avoid having to relocate each object on the next | |
78 | * execution, userspace is told the location of those objects in this pass, | |
79 | * but this remains just a hint as the kernel may choose a new location for | |
80 | * any object in the future. | |
81 | * | |
82 | * Processing an execbuf ioctl is conceptually split up into a few phases. | |
83 | * | |
84 | * 1. Validation - Ensure all the pointers, handles and flags are valid. | |
85 | * 2. Reservation - Assign GPU address space for every object | |
86 | * 3. Relocation - Update any addresses to point to the final locations | |
87 | * 4. Serialisation - Order the request with respect to its dependencies | |
88 | * 5. Construction - Construct a request to execute the batchbuffer | |
89 | * 6. Submission (at some point in the future execution) | |
90 | * | |
91 | * Reserving resources for the execbuf is the most complicated phase. We | |
92 | * neither want to have to migrate the object in the address space, nor do | |
93 | * we want to have to update any relocations pointing to this object. Ideally, | |
94 | * we want to leave the object where it is and for all the existing relocations | |
95 | * to match. If the object is given a new address, or if userspace thinks the | |
96 | * object is elsewhere, we have to parse all the relocation entries and update | |
97 | * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that | |
98 | * all the target addresses in all of its objects match the value in the | |
99 | * relocation entries and that they all match the presumed offsets given by the | |
100 | * list of execbuffer objects. Using this knowledge, we know that if we haven't | |
101 | * moved any buffers, all the relocation entries are valid and we can skip | |
102 | * the update. (If userspace is wrong, the likely outcome is an impromptu GPU | |
103 | * hang.) The requirement for using I915_EXEC_NO_RELOC are: | |
104 | * | |
105 | * The addresses written in the objects must match the corresponding | |
106 | * reloc.presumed_offset which in turn must match the corresponding | |
107 | * execobject.offset. | |
108 | * | |
109 | * Any render targets written to in the batch must be flagged with | |
110 | * EXEC_OBJECT_WRITE. | |
111 | * | |
112 | * To avoid stalling, execobject.offset should match the current | |
113 | * address of that object within the active context. | |
114 | * | |
115 | * The reservation is done is multiple phases. First we try and keep any | |
116 | * object already bound in its current location - so as long as meets the | |
117 | * constraints imposed by the new execbuffer. Any object left unbound after the | |
118 | * first pass is then fitted into any available idle space. If an object does | |
119 | * not fit, all objects are removed from the reservation and the process rerun | |
120 | * after sorting the objects into a priority order (more difficult to fit | |
121 | * objects are tried first). Failing that, the entire VM is cleared and we try | |
122 | * to fit the execbuf once last time before concluding that it simply will not | |
123 | * fit. | |
124 | * | |
125 | * A small complication to all of this is that we allow userspace not only to | |
126 | * specify an alignment and a size for the object in the address space, but | |
127 | * we also allow userspace to specify the exact offset. This objects are | |
128 | * simpler to place (the location is known a priori) all we have to do is make | |
129 | * sure the space is available. | |
130 | * | |
131 | * Once all the objects are in place, patching up the buried pointers to point | |
132 | * to the final locations is a fairly simple job of walking over the relocation | |
133 | * entry arrays, looking up the right address and rewriting the value into | |
134 | * the object. Simple! ... The relocation entries are stored in user memory | |
135 | * and so to access them we have to copy them into a local buffer. That copy | |
136 | * has to avoid taking any pagefaults as they may lead back to a GEM object | |
137 | * requiring the struct_mutex (i.e. recursive deadlock). So once again we split | |
138 | * the relocation into multiple passes. First we try to do everything within an | |
139 | * atomic context (avoid the pagefaults) which requires that we never wait. If | |
140 | * we detect that we may wait, or if we need to fault, then we have to fallback | |
141 | * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm | |
142 | * bells yet?) Dropping the mutex means that we lose all the state we have | |
143 | * built up so far for the execbuf and we must reset any global data. However, | |
144 | * we do leave the objects pinned in their final locations - which is a | |
145 | * potential issue for concurrent execbufs. Once we have left the mutex, we can | |
146 | * allocate and copy all the relocation entries into a large array at our | |
147 | * leisure, reacquire the mutex, reclaim all the objects and other state and | |
148 | * then proceed to update any incorrect addresses with the objects. | |
149 | * | |
150 | * As we process the relocation entries, we maintain a record of whether the | |
151 | * object is being written to. Using NORELOC, we expect userspace to provide | |
152 | * this information instead. We also check whether we can skip the relocation | |
153 | * by comparing the expected value inside the relocation entry with the target's | |
154 | * final address. If they differ, we have to map the current object and rewrite | |
155 | * the 4 or 8 byte pointer within. | |
156 | * | |
157 | * Serialising an execbuf is quite simple according to the rules of the GEM | |
158 | * ABI. Execution within each context is ordered by the order of submission. | |
159 | * Writes to any GEM object are in order of submission and are exclusive. Reads | |
160 | * from a GEM object are unordered with respect to other reads, but ordered by | |
161 | * writes. A write submitted after a read cannot occur before the read, and | |
162 | * similarly any read submitted after a write cannot occur before the write. | |
163 | * Writes are ordered between engines such that only one write occurs at any | |
164 | * time (completing any reads beforehand) - using semaphores where available | |
165 | * and CPU serialisation otherwise. Other GEM access obey the same rules, any | |
166 | * write (either via mmaps using set-domain, or via pwrite) must flush all GPU | |
167 | * reads before starting, and any read (either using set-domain or pread) must | |
168 | * flush all GPU writes before starting. (Note we only employ a barrier before, | |
169 | * we currently rely on userspace not concurrently starting a new execution | |
170 | * whilst reading or writing to an object. This may be an advantage or not | |
171 | * depending on how much you trust userspace not to shoot themselves in the | |
172 | * foot.) Serialisation may just result in the request being inserted into | |
173 | * a DAG awaiting its turn, but most simple is to wait on the CPU until | |
174 | * all dependencies are resolved. | |
175 | * | |
176 | * After all of that, is just a matter of closing the request and handing it to | |
177 | * the hardware (well, leaving it in a queue to be executed). However, we also | |
178 | * offer the ability for batchbuffers to be run with elevated privileges so | |
179 | * that they access otherwise hidden registers. (Used to adjust L3 cache etc.) | |
180 | * Before any batch is given extra privileges we first must check that it | |
181 | * contains no nefarious instructions, we check that each instruction is from | |
182 | * our whitelist and all registers are also from an allowed list. We first | |
183 | * copy the user's batchbuffer to a shadow (so that the user doesn't have | |
184 | * access to it, either by the CPU or GPU as we scan it) and then parse each | |
185 | * instruction. If everything is ok, we set a flag telling the hardware to run | |
186 | * the batchbuffer in trusted mode, otherwise the ioctl is rejected. | |
187 | */ | |
188 | ||
650bc635 | 189 | struct i915_execbuffer { |
2889caa9 CW |
190 | struct drm_i915_private *i915; /** i915 backpointer */ |
191 | struct drm_file *file; /** per-file lookup tables and limits */ | |
192 | struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */ | |
193 | struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */ | |
194 | ||
195 | struct intel_engine_cs *engine; /** engine to queue the request to */ | |
196 | struct i915_gem_context *ctx; /** context for building the request */ | |
197 | struct i915_address_space *vm; /** GTT and vma for the request */ | |
198 | ||
199 | struct drm_i915_gem_request *request; /** our request to build */ | |
200 | struct i915_vma *batch; /** identity of the batch obj/vma */ | |
201 | ||
202 | /** actual size of execobj[] as we may extend it for the cmdparser */ | |
203 | unsigned int buffer_count; | |
204 | ||
205 | /** list of vma not yet bound during reservation phase */ | |
206 | struct list_head unbound; | |
207 | ||
208 | /** list of vma that have execobj.relocation_count */ | |
209 | struct list_head relocs; | |
210 | ||
211 | /** | |
212 | * Track the most recently used object for relocations, as we | |
213 | * frequently have to perform multiple relocations within the same | |
214 | * obj/page | |
215 | */ | |
650bc635 | 216 | struct reloc_cache { |
2889caa9 CW |
217 | struct drm_mm_node node; /** temporary GTT binding */ |
218 | unsigned long vaddr; /** Current kmap address */ | |
219 | unsigned long page; /** Currently mapped page index */ | |
7dd4f672 | 220 | unsigned int gen; /** Cached value of INTEL_GEN */ |
650bc635 | 221 | bool use_64bit_reloc : 1; |
2889caa9 CW |
222 | bool has_llc : 1; |
223 | bool has_fence : 1; | |
224 | bool needs_unfenced : 1; | |
7dd4f672 CW |
225 | |
226 | struct drm_i915_gem_request *rq; | |
227 | u32 *rq_cmd; | |
228 | unsigned int rq_size; | |
650bc635 | 229 | } reloc_cache; |
2889caa9 CW |
230 | |
231 | u64 invalid_flags; /** Set of execobj.flags that are invalid */ | |
232 | u32 context_flags; /** Set of execobj.flags to insert from the ctx */ | |
233 | ||
234 | u32 batch_start_offset; /** Location within object of batch */ | |
235 | u32 batch_len; /** Length of batch within object */ | |
236 | u32 batch_flags; /** Flags composed for emit_bb_start() */ | |
237 | ||
238 | /** | |
239 | * Indicate either the size of the hastable used to resolve | |
240 | * relocation handles, or if negative that we are using a direct | |
241 | * index into the execobj[]. | |
242 | */ | |
243 | int lut_size; | |
244 | struct hlist_head *buckets; /** ht for relocation handles */ | |
67731b87 CW |
245 | }; |
246 | ||
4ff4b44c CW |
247 | /* |
248 | * As an alternative to creating a hashtable of handle-to-vma for a batch, | |
249 | * we used the last available reserved field in the execobject[] and stash | |
250 | * a link from the execobj to its vma. | |
251 | */ | |
252 | #define __exec_to_vma(ee) (ee)->rsvd2 | |
253 | #define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee)) | |
254 | ||
2889caa9 CW |
255 | /* |
256 | * Used to convert any address to canonical form. | |
257 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
258 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
259 | * addresses to be in a canonical form: | |
260 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
261 | * canonical form [63:48] == [47]." | |
262 | */ | |
263 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
264 | static inline u64 gen8_canonical_addr(u64 address) | |
265 | { | |
266 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
267 | } | |
268 | ||
269 | static inline u64 gen8_noncanonical_addr(u64 address) | |
270 | { | |
271 | return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0); | |
272 | } | |
273 | ||
650bc635 | 274 | static int eb_create(struct i915_execbuffer *eb) |
67731b87 | 275 | { |
2889caa9 CW |
276 | if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { |
277 | unsigned int size = 1 + ilog2(eb->buffer_count); | |
4ff4b44c | 278 | |
2889caa9 CW |
279 | /* |
280 | * Without a 1:1 association between relocation handles and | |
281 | * the execobject[] index, we instead create a hashtable. | |
282 | * We size it dynamically based on available memory, starting | |
283 | * first with 1:1 assocative hash and scaling back until | |
284 | * the allocation succeeds. | |
285 | * | |
286 | * Later on we use a positive lut_size to indicate we are | |
287 | * using this hashtable, and a negative value to indicate a | |
288 | * direct lookup. | |
289 | */ | |
4ff4b44c | 290 | do { |
4ec654bf CW |
291 | unsigned int flags; |
292 | ||
293 | /* While we can still reduce the allocation size, don't | |
294 | * raise a warning and allow the allocation to fail. | |
295 | * On the last pass though, we want to try as hard | |
296 | * as possible to perform the allocation and warn | |
297 | * if it fails. | |
298 | */ | |
299 | flags = GFP_TEMPORARY; | |
300 | if (size > 1) | |
301 | flags |= __GFP_NORETRY | __GFP_NOWARN; | |
302 | ||
4ff4b44c | 303 | eb->buckets = kzalloc(sizeof(struct hlist_head) << size, |
4ec654bf | 304 | flags); |
4ff4b44c CW |
305 | if (eb->buckets) |
306 | break; | |
307 | } while (--size); | |
308 | ||
4ec654bf CW |
309 | if (unlikely(!size)) |
310 | return -ENOMEM; | |
eef90ccb | 311 | |
2889caa9 | 312 | eb->lut_size = size; |
650bc635 | 313 | } else { |
2889caa9 | 314 | eb->lut_size = -eb->buffer_count; |
650bc635 | 315 | } |
eef90ccb | 316 | |
650bc635 | 317 | return 0; |
67731b87 CW |
318 | } |
319 | ||
2889caa9 CW |
320 | static bool |
321 | eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, | |
322 | const struct i915_vma *vma) | |
323 | { | |
324 | if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) | |
325 | return true; | |
326 | ||
327 | if (vma->node.size < entry->pad_to_size) | |
328 | return true; | |
329 | ||
330 | if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) | |
331 | return true; | |
332 | ||
333 | if (entry->flags & EXEC_OBJECT_PINNED && | |
334 | vma->node.start != entry->offset) | |
335 | return true; | |
336 | ||
337 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && | |
338 | vma->node.start < BATCH_OFFSET_BIAS) | |
339 | return true; | |
340 | ||
341 | if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && | |
342 | (vma->node.start + vma->node.size - 1) >> 32) | |
343 | return true; | |
344 | ||
345 | return false; | |
346 | } | |
347 | ||
348 | static inline void | |
349 | eb_pin_vma(struct i915_execbuffer *eb, | |
350 | struct drm_i915_gem_exec_object2 *entry, | |
351 | struct i915_vma *vma) | |
352 | { | |
353 | u64 flags; | |
354 | ||
616d9cee CW |
355 | if (vma->node.size) |
356 | flags = vma->node.start; | |
357 | else | |
358 | flags = entry->offset & PIN_OFFSET_MASK; | |
359 | ||
360 | flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; | |
2889caa9 CW |
361 | if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_GTT)) |
362 | flags |= PIN_GLOBAL; | |
616d9cee | 363 | |
2889caa9 CW |
364 | if (unlikely(i915_vma_pin(vma, 0, 0, flags))) |
365 | return; | |
366 | ||
367 | if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { | |
368 | if (unlikely(i915_vma_get_fence(vma))) { | |
369 | i915_vma_unpin(vma); | |
370 | return; | |
371 | } | |
372 | ||
373 | if (i915_vma_pin_fence(vma)) | |
374 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
375 | } | |
376 | ||
377 | entry->flags |= __EXEC_OBJECT_HAS_PIN; | |
378 | } | |
379 | ||
d55495b4 CW |
380 | static inline void |
381 | __eb_unreserve_vma(struct i915_vma *vma, | |
382 | const struct drm_i915_gem_exec_object2 *entry) | |
383 | { | |
2889caa9 CW |
384 | GEM_BUG_ON(!(entry->flags & __EXEC_OBJECT_HAS_PIN)); |
385 | ||
d55495b4 CW |
386 | if (unlikely(entry->flags & __EXEC_OBJECT_HAS_FENCE)) |
387 | i915_vma_unpin_fence(vma); | |
388 | ||
2889caa9 | 389 | __i915_vma_unpin(vma); |
d55495b4 CW |
390 | } |
391 | ||
2889caa9 CW |
392 | static inline void |
393 | eb_unreserve_vma(struct i915_vma *vma, | |
394 | struct drm_i915_gem_exec_object2 *entry) | |
d55495b4 | 395 | { |
2889caa9 CW |
396 | if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) |
397 | return; | |
d55495b4 CW |
398 | |
399 | __eb_unreserve_vma(vma, entry); | |
2889caa9 | 400 | entry->flags &= ~__EXEC_OBJECT_RESERVED; |
d55495b4 CW |
401 | } |
402 | ||
2889caa9 CW |
403 | static int |
404 | eb_validate_vma(struct i915_execbuffer *eb, | |
405 | struct drm_i915_gem_exec_object2 *entry, | |
406 | struct i915_vma *vma) | |
67731b87 | 407 | { |
2889caa9 CW |
408 | if (unlikely(entry->flags & eb->invalid_flags)) |
409 | return -EINVAL; | |
d55495b4 | 410 | |
2889caa9 CW |
411 | if (unlikely(entry->alignment && !is_power_of_2(entry->alignment))) |
412 | return -EINVAL; | |
413 | ||
414 | /* | |
415 | * Offset can be used as input (EXEC_OBJECT_PINNED), reject | |
416 | * any non-page-aligned or non-canonical addresses. | |
417 | */ | |
418 | if (unlikely(entry->flags & EXEC_OBJECT_PINNED && | |
419 | entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK))) | |
420 | return -EINVAL; | |
421 | ||
422 | /* pad_to_size was once a reserved field, so sanitize it */ | |
423 | if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) { | |
424 | if (unlikely(offset_in_page(entry->pad_to_size))) | |
425 | return -EINVAL; | |
426 | } else { | |
427 | entry->pad_to_size = 0; | |
d55495b4 CW |
428 | } |
429 | ||
2889caa9 CW |
430 | if (unlikely(vma->exec_entry)) { |
431 | DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n", | |
432 | entry->handle, (int)(entry - eb->exec)); | |
433 | return -EINVAL; | |
434 | } | |
435 | ||
436 | /* | |
437 | * From drm_mm perspective address space is continuous, | |
438 | * so from this point we're always using non-canonical | |
439 | * form internally. | |
440 | */ | |
441 | entry->offset = gen8_noncanonical_addr(entry->offset); | |
442 | ||
443 | return 0; | |
67731b87 CW |
444 | } |
445 | ||
2889caa9 CW |
446 | static int |
447 | eb_add_vma(struct i915_execbuffer *eb, | |
448 | struct drm_i915_gem_exec_object2 *entry, | |
449 | struct i915_vma *vma) | |
59bfa124 | 450 | { |
2889caa9 CW |
451 | int err; |
452 | ||
453 | GEM_BUG_ON(i915_vma_is_closed(vma)); | |
454 | ||
455 | if (!(eb->args->flags & __EXEC_VALIDATED)) { | |
456 | err = eb_validate_vma(eb, entry, vma); | |
457 | if (unlikely(err)) | |
458 | return err; | |
4ff4b44c | 459 | } |
4ff4b44c | 460 | |
4ec654bf | 461 | if (eb->lut_size > 0) { |
2889caa9 | 462 | vma->exec_handle = entry->handle; |
4ff4b44c | 463 | hlist_add_head(&vma->exec_node, |
2889caa9 CW |
464 | &eb->buckets[hash_32(entry->handle, |
465 | eb->lut_size)]); | |
4ff4b44c | 466 | } |
59bfa124 | 467 | |
2889caa9 CW |
468 | if (entry->relocation_count) |
469 | list_add_tail(&vma->reloc_link, &eb->relocs); | |
470 | ||
471 | if (!eb->reloc_cache.has_fence) { | |
472 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
473 | } else { | |
474 | if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || | |
475 | eb->reloc_cache.needs_unfenced) && | |
476 | i915_gem_object_is_tiled(vma->obj)) | |
477 | entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; | |
478 | } | |
479 | ||
480 | if (!(entry->flags & EXEC_OBJECT_PINNED)) | |
481 | entry->flags |= eb->context_flags; | |
482 | ||
483 | /* | |
484 | * Stash a pointer from the vma to execobj, so we can query its flags, | |
485 | * size, alignment etc as provided by the user. Also we stash a pointer | |
486 | * to the vma inside the execobj so that we can use a direct lookup | |
487 | * to find the right target VMA when doing relocations. | |
488 | */ | |
489 | vma->exec_entry = entry; | |
dade2a61 | 490 | __exec_to_vma(entry) = (uintptr_t)vma; |
2889caa9 CW |
491 | |
492 | err = 0; | |
616d9cee | 493 | eb_pin_vma(eb, entry, vma); |
2889caa9 CW |
494 | if (eb_vma_misplaced(entry, vma)) { |
495 | eb_unreserve_vma(vma, entry); | |
496 | ||
497 | list_add_tail(&vma->exec_link, &eb->unbound); | |
498 | if (drm_mm_node_allocated(&vma->node)) | |
499 | err = i915_vma_unbind(vma); | |
500 | } else { | |
501 | if (entry->offset != vma->node.start) { | |
502 | entry->offset = vma->node.start | UPDATE; | |
503 | eb->args->flags |= __EXEC_HAS_RELOC; | |
504 | } | |
505 | } | |
506 | return err; | |
507 | } | |
508 | ||
509 | static inline int use_cpu_reloc(const struct reloc_cache *cache, | |
510 | const struct drm_i915_gem_object *obj) | |
511 | { | |
512 | if (!i915_gem_object_has_struct_page(obj)) | |
513 | return false; | |
514 | ||
7dd4f672 CW |
515 | if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) |
516 | return true; | |
517 | ||
518 | if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) | |
519 | return false; | |
2889caa9 CW |
520 | |
521 | return (cache->has_llc || | |
522 | obj->cache_dirty || | |
523 | obj->cache_level != I915_CACHE_NONE); | |
524 | } | |
525 | ||
526 | static int eb_reserve_vma(const struct i915_execbuffer *eb, | |
527 | struct i915_vma *vma) | |
528 | { | |
529 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
530 | u64 flags; | |
531 | int err; | |
532 | ||
533 | flags = PIN_USER | PIN_NONBLOCK; | |
534 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) | |
535 | flags |= PIN_GLOBAL; | |
536 | ||
537 | /* | |
538 | * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, | |
539 | * limit address to the first 4GBs for unflagged objects. | |
540 | */ | |
541 | if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) | |
542 | flags |= PIN_ZONE_4G; | |
543 | ||
544 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) | |
545 | flags |= PIN_MAPPABLE; | |
546 | ||
547 | if (entry->flags & EXEC_OBJECT_PINNED) { | |
548 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
549 | flags &= ~PIN_NONBLOCK; /* force overlapping PINNED checks */ | |
550 | } else if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) { | |
551 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
552 | } | |
553 | ||
554 | err = i915_vma_pin(vma, entry->pad_to_size, entry->alignment, flags); | |
555 | if (err) | |
556 | return err; | |
557 | ||
558 | if (entry->offset != vma->node.start) { | |
559 | entry->offset = vma->node.start | UPDATE; | |
560 | eb->args->flags |= __EXEC_HAS_RELOC; | |
561 | } | |
562 | ||
2889caa9 CW |
563 | if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { |
564 | err = i915_vma_get_fence(vma); | |
565 | if (unlikely(err)) { | |
566 | i915_vma_unpin(vma); | |
567 | return err; | |
568 | } | |
569 | ||
570 | if (i915_vma_pin_fence(vma)) | |
571 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
572 | } | |
573 | ||
bed8d1c8 CW |
574 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
575 | GEM_BUG_ON(eb_vma_misplaced(entry, vma)); | |
576 | ||
2889caa9 CW |
577 | return 0; |
578 | } | |
579 | ||
580 | static int eb_reserve(struct i915_execbuffer *eb) | |
581 | { | |
582 | const unsigned int count = eb->buffer_count; | |
583 | struct list_head last; | |
584 | struct i915_vma *vma; | |
585 | unsigned int i, pass; | |
586 | int err; | |
587 | ||
588 | /* | |
589 | * Attempt to pin all of the buffers into the GTT. | |
590 | * This is done in 3 phases: | |
591 | * | |
592 | * 1a. Unbind all objects that do not match the GTT constraints for | |
593 | * the execbuffer (fenceable, mappable, alignment etc). | |
594 | * 1b. Increment pin count for already bound objects. | |
595 | * 2. Bind new objects. | |
596 | * 3. Decrement pin count. | |
597 | * | |
598 | * This avoid unnecessary unbinding of later objects in order to make | |
599 | * room for the earlier objects *unless* we need to defragment. | |
600 | */ | |
601 | ||
602 | pass = 0; | |
603 | err = 0; | |
604 | do { | |
605 | list_for_each_entry(vma, &eb->unbound, exec_link) { | |
606 | err = eb_reserve_vma(eb, vma); | |
607 | if (err) | |
608 | break; | |
609 | } | |
610 | if (err != -ENOSPC) | |
611 | return err; | |
612 | ||
613 | /* Resort *all* the objects into priority order */ | |
614 | INIT_LIST_HEAD(&eb->unbound); | |
615 | INIT_LIST_HEAD(&last); | |
616 | for (i = 0; i < count; i++) { | |
617 | struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; | |
618 | ||
619 | if (entry->flags & EXEC_OBJECT_PINNED && | |
620 | entry->flags & __EXEC_OBJECT_HAS_PIN) | |
621 | continue; | |
622 | ||
623 | vma = exec_to_vma(entry); | |
624 | eb_unreserve_vma(vma, entry); | |
625 | ||
626 | if (entry->flags & EXEC_OBJECT_PINNED) | |
627 | list_add(&vma->exec_link, &eb->unbound); | |
628 | else if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) | |
629 | list_add_tail(&vma->exec_link, &eb->unbound); | |
630 | else | |
631 | list_add_tail(&vma->exec_link, &last); | |
632 | } | |
633 | list_splice_tail(&last, &eb->unbound); | |
634 | ||
635 | switch (pass++) { | |
636 | case 0: | |
637 | break; | |
638 | ||
639 | case 1: | |
640 | /* Too fragmented, unbind everything and retry */ | |
641 | err = i915_gem_evict_vm(eb->vm); | |
642 | if (err) | |
643 | return err; | |
644 | break; | |
645 | ||
646 | default: | |
647 | return -ENOSPC; | |
648 | } | |
649 | } while (1); | |
4ff4b44c | 650 | } |
59bfa124 | 651 | |
4ff4b44c | 652 | static inline struct hlist_head * |
2889caa9 | 653 | ht_head(const struct i915_gem_context_vma_lut *lut, u32 handle) |
4ff4b44c | 654 | { |
2889caa9 | 655 | return &lut->ht[hash_32(handle, lut->ht_bits)]; |
4ff4b44c CW |
656 | } |
657 | ||
658 | static inline bool | |
2889caa9 | 659 | ht_needs_resize(const struct i915_gem_context_vma_lut *lut) |
4ff4b44c | 660 | { |
2889caa9 CW |
661 | return (4*lut->ht_count > 3*lut->ht_size || |
662 | 4*lut->ht_count + 1 < lut->ht_size); | |
59bfa124 CW |
663 | } |
664 | ||
2889caa9 CW |
665 | static unsigned int eb_batch_index(const struct i915_execbuffer *eb) |
666 | { | |
1a71cf2f CW |
667 | if (eb->args->flags & I915_EXEC_BATCH_FIRST) |
668 | return 0; | |
669 | else | |
670 | return eb->buffer_count - 1; | |
2889caa9 CW |
671 | } |
672 | ||
673 | static int eb_select_context(struct i915_execbuffer *eb) | |
674 | { | |
675 | struct i915_gem_context *ctx; | |
676 | ||
677 | ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1); | |
678 | if (unlikely(IS_ERR(ctx))) | |
679 | return PTR_ERR(ctx); | |
680 | ||
681 | if (unlikely(i915_gem_context_is_banned(ctx))) { | |
682 | DRM_DEBUG("Context %u tried to submit while banned\n", | |
683 | ctx->user_handle); | |
684 | return -EIO; | |
685 | } | |
686 | ||
687 | eb->ctx = i915_gem_context_get(ctx); | |
688 | eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base; | |
689 | ||
690 | eb->context_flags = 0; | |
691 | if (ctx->flags & CONTEXT_NO_ZEROMAP) | |
692 | eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | static int eb_lookup_vmas(struct i915_execbuffer *eb) | |
3b96eff4 | 698 | { |
4ff4b44c | 699 | #define INTERMEDIATE BIT(0) |
2889caa9 CW |
700 | const unsigned int count = eb->buffer_count; |
701 | struct i915_gem_context_vma_lut *lut = &eb->ctx->vma_lut; | |
4ff4b44c | 702 | struct i915_vma *vma; |
2889caa9 CW |
703 | struct idr *idr; |
704 | unsigned int i; | |
4ff4b44c | 705 | int slow_pass = -1; |
2889caa9 | 706 | int err; |
3b96eff4 | 707 | |
2889caa9 CW |
708 | INIT_LIST_HEAD(&eb->relocs); |
709 | INIT_LIST_HEAD(&eb->unbound); | |
d55495b4 | 710 | |
2889caa9 CW |
711 | if (unlikely(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)) |
712 | flush_work(&lut->resize); | |
713 | GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); | |
4ff4b44c CW |
714 | |
715 | for (i = 0; i < count; i++) { | |
716 | __exec_to_vma(&eb->exec[i]) = 0; | |
717 | ||
718 | hlist_for_each_entry(vma, | |
2889caa9 | 719 | ht_head(lut, eb->exec[i].handle), |
4ff4b44c CW |
720 | ctx_node) { |
721 | if (vma->ctx_handle != eb->exec[i].handle) | |
722 | continue; | |
723 | ||
2889caa9 CW |
724 | err = eb_add_vma(eb, &eb->exec[i], vma); |
725 | if (unlikely(err)) | |
726 | return err; | |
4ff4b44c CW |
727 | |
728 | goto next_vma; | |
729 | } | |
730 | ||
731 | if (slow_pass < 0) | |
732 | slow_pass = i; | |
733 | next_vma: ; | |
734 | } | |
735 | ||
736 | if (slow_pass < 0) | |
2889caa9 | 737 | goto out; |
4ff4b44c | 738 | |
650bc635 | 739 | spin_lock(&eb->file->table_lock); |
2889caa9 CW |
740 | /* |
741 | * Grab a reference to the object and release the lock so we can lookup | |
742 | * or create the VMA without using GFP_ATOMIC | |
743 | */ | |
744 | idr = &eb->file->object_idr; | |
4ff4b44c CW |
745 | for (i = slow_pass; i < count; i++) { |
746 | struct drm_i915_gem_object *obj; | |
3b96eff4 | 747 | |
4ff4b44c CW |
748 | if (__exec_to_vma(&eb->exec[i])) |
749 | continue; | |
750 | ||
2889caa9 | 751 | obj = to_intel_bo(idr_find(idr, eb->exec[i].handle)); |
4ff4b44c | 752 | if (unlikely(!obj)) { |
650bc635 | 753 | spin_unlock(&eb->file->table_lock); |
4ff4b44c CW |
754 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
755 | eb->exec[i].handle, i); | |
2889caa9 CW |
756 | err = -ENOENT; |
757 | goto err; | |
3b96eff4 CW |
758 | } |
759 | ||
4ff4b44c | 760 | __exec_to_vma(&eb->exec[i]) = INTERMEDIATE | (uintptr_t)obj; |
27173f1f | 761 | } |
650bc635 | 762 | spin_unlock(&eb->file->table_lock); |
3b96eff4 | 763 | |
4ff4b44c CW |
764 | for (i = slow_pass; i < count; i++) { |
765 | struct drm_i915_gem_object *obj; | |
6f65e29a | 766 | |
2889caa9 | 767 | if (!(__exec_to_vma(&eb->exec[i]) & INTERMEDIATE)) |
4ff4b44c | 768 | continue; |
9ae9ab52 | 769 | |
e656a6cb DV |
770 | /* |
771 | * NOTE: We can leak any vmas created here when something fails | |
772 | * later on. But that's no issue since vma_unbind can deal with | |
773 | * vmas which are not actually bound. And since only | |
774 | * lookup_or_create exists as an interface to get at the vma | |
775 | * from the (obj, vm) we don't run the risk of creating | |
776 | * duplicated vmas for the same vm. | |
777 | */ | |
2889caa9 | 778 | obj = u64_to_ptr(typeof(*obj), |
4ff4b44c | 779 | __exec_to_vma(&eb->exec[i]) & ~INTERMEDIATE); |
650bc635 | 780 | vma = i915_vma_instance(obj, eb->vm, NULL); |
058d88c4 | 781 | if (unlikely(IS_ERR(vma))) { |
27173f1f | 782 | DRM_DEBUG("Failed to lookup VMA\n"); |
2889caa9 CW |
783 | err = PTR_ERR(vma); |
784 | goto err; | |
27173f1f BW |
785 | } |
786 | ||
4ff4b44c CW |
787 | /* First come, first served */ |
788 | if (!vma->ctx) { | |
789 | vma->ctx = eb->ctx; | |
790 | vma->ctx_handle = eb->exec[i].handle; | |
791 | hlist_add_head(&vma->ctx_node, | |
2889caa9 CW |
792 | ht_head(lut, eb->exec[i].handle)); |
793 | lut->ht_count++; | |
794 | lut->ht_size |= I915_CTX_RESIZE_IN_PROGRESS; | |
4ff4b44c CW |
795 | if (i915_vma_is_ggtt(vma)) { |
796 | GEM_BUG_ON(obj->vma_hashed); | |
797 | obj->vma_hashed = vma; | |
798 | } | |
dade2a61 CW |
799 | |
800 | i915_vma_get(vma); | |
eef90ccb | 801 | } |
4ff4b44c | 802 | |
2889caa9 CW |
803 | err = eb_add_vma(eb, &eb->exec[i], vma); |
804 | if (unlikely(err)) | |
805 | goto err; | |
dade2a61 CW |
806 | |
807 | /* Only after we validated the user didn't use our bits */ | |
808 | if (vma->ctx != eb->ctx) { | |
809 | i915_vma_get(vma); | |
810 | eb->exec[i].flags |= __EXEC_OBJECT_HAS_REF; | |
811 | } | |
4ff4b44c CW |
812 | } |
813 | ||
2889caa9 CW |
814 | if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) { |
815 | if (ht_needs_resize(lut)) | |
816 | queue_work(system_highpri_wq, &lut->resize); | |
817 | else | |
818 | lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; | |
3b96eff4 | 819 | } |
3b96eff4 | 820 | |
2889caa9 CW |
821 | out: |
822 | /* take note of the batch buffer before we might reorder the lists */ | |
823 | i = eb_batch_index(eb); | |
824 | eb->batch = exec_to_vma(&eb->exec[i]); | |
27173f1f | 825 | |
9ae9ab52 | 826 | /* |
4ff4b44c CW |
827 | * SNA is doing fancy tricks with compressing batch buffers, which leads |
828 | * to negative relocation deltas. Usually that works out ok since the | |
829 | * relocate address is still positive, except when the batch is placed | |
830 | * very low in the GTT. Ensure this doesn't happen. | |
831 | * | |
832 | * Note that actual hangs have only been observed on gen7, but for | |
833 | * paranoia do it everywhere. | |
9ae9ab52 | 834 | */ |
2889caa9 CW |
835 | if (!(eb->exec[i].flags & EXEC_OBJECT_PINNED)) |
836 | eb->exec[i].flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
837 | if (eb->reloc_cache.has_fence) | |
838 | eb->exec[i].flags |= EXEC_OBJECT_NEEDS_FENCE; | |
9ae9ab52 | 839 | |
2889caa9 CW |
840 | eb->args->flags |= __EXEC_VALIDATED; |
841 | return eb_reserve(eb); | |
842 | ||
843 | err: | |
844 | for (i = slow_pass; i < count; i++) { | |
845 | if (__exec_to_vma(&eb->exec[i]) & INTERMEDIATE) | |
846 | __exec_to_vma(&eb->exec[i]) = 0; | |
847 | } | |
848 | lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; | |
849 | return err; | |
850 | #undef INTERMEDIATE | |
3b96eff4 CW |
851 | } |
852 | ||
4ff4b44c | 853 | static struct i915_vma * |
2889caa9 | 854 | eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) |
67731b87 | 855 | { |
2889caa9 CW |
856 | if (eb->lut_size < 0) { |
857 | if (handle >= -eb->lut_size) | |
eef90ccb | 858 | return NULL; |
4ff4b44c | 859 | return exec_to_vma(&eb->exec[handle]); |
eef90ccb CW |
860 | } else { |
861 | struct hlist_head *head; | |
aa45950b | 862 | struct i915_vma *vma; |
67731b87 | 863 | |
2889caa9 | 864 | head = &eb->buckets[hash_32(handle, eb->lut_size)]; |
aa45950b | 865 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
866 | if (vma->exec_handle == handle) |
867 | return vma; | |
eef90ccb CW |
868 | } |
869 | return NULL; | |
870 | } | |
67731b87 CW |
871 | } |
872 | ||
2889caa9 | 873 | static void eb_release_vmas(const struct i915_execbuffer *eb) |
a415d355 | 874 | { |
2889caa9 CW |
875 | const unsigned int count = eb->buffer_count; |
876 | unsigned int i; | |
877 | ||
878 | for (i = 0; i < count; i++) { | |
879 | struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; | |
880 | struct i915_vma *vma = exec_to_vma(entry); | |
650bc635 | 881 | |
2889caa9 | 882 | if (!vma) |
d55495b4 | 883 | continue; |
bcffc3fa | 884 | |
2889caa9 | 885 | GEM_BUG_ON(vma->exec_entry != entry); |
172ae5b4 | 886 | vma->exec_entry = NULL; |
bdbbf7d6 | 887 | __exec_to_vma(entry) = 0; |
9e53d9be | 888 | |
dade2a61 CW |
889 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) |
890 | __eb_unreserve_vma(vma, entry); | |
891 | ||
892 | if (entry->flags & __EXEC_OBJECT_HAS_REF) | |
893 | i915_vma_put(vma); | |
d50415cc | 894 | |
dade2a61 CW |
895 | entry->flags &= |
896 | ~(__EXEC_OBJECT_RESERVED | __EXEC_OBJECT_HAS_REF); | |
2889caa9 | 897 | } |
dabdfe02 CW |
898 | } |
899 | ||
2889caa9 | 900 | static void eb_reset_vmas(const struct i915_execbuffer *eb) |
934acce3 | 901 | { |
2889caa9 | 902 | eb_release_vmas(eb); |
4ec654bf | 903 | if (eb->lut_size > 0) |
2889caa9 CW |
904 | memset(eb->buckets, 0, |
905 | sizeof(struct hlist_head) << eb->lut_size); | |
934acce3 MW |
906 | } |
907 | ||
2889caa9 | 908 | static void eb_destroy(const struct i915_execbuffer *eb) |
934acce3 | 909 | { |
7dd4f672 CW |
910 | GEM_BUG_ON(eb->reloc_cache.rq); |
911 | ||
4ec654bf | 912 | if (eb->lut_size > 0) |
2889caa9 | 913 | kfree(eb->buckets); |
934acce3 MW |
914 | } |
915 | ||
2889caa9 | 916 | static inline u64 |
d50415cc | 917 | relocation_target(const struct drm_i915_gem_relocation_entry *reloc, |
2889caa9 | 918 | const struct i915_vma *target) |
934acce3 | 919 | { |
2889caa9 | 920 | return gen8_canonical_addr((int)reloc->delta + target->node.start); |
934acce3 MW |
921 | } |
922 | ||
d50415cc CW |
923 | static void reloc_cache_init(struct reloc_cache *cache, |
924 | struct drm_i915_private *i915) | |
5032d871 | 925 | { |
31a39207 | 926 | cache->page = -1; |
d50415cc | 927 | cache->vaddr = 0; |
dfc5148f | 928 | /* Must be a variable in the struct to allow GCC to unroll. */ |
7dd4f672 | 929 | cache->gen = INTEL_GEN(i915); |
2889caa9 | 930 | cache->has_llc = HAS_LLC(i915); |
dfc5148f | 931 | cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); |
7dd4f672 CW |
932 | cache->has_fence = cache->gen < 4; |
933 | cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; | |
e8cb909a | 934 | cache->node.allocated = false; |
7dd4f672 CW |
935 | cache->rq = NULL; |
936 | cache->rq_size = 0; | |
d50415cc | 937 | } |
5032d871 | 938 | |
d50415cc CW |
939 | static inline void *unmask_page(unsigned long p) |
940 | { | |
941 | return (void *)(uintptr_t)(p & PAGE_MASK); | |
942 | } | |
943 | ||
944 | static inline unsigned int unmask_flags(unsigned long p) | |
945 | { | |
946 | return p & ~PAGE_MASK; | |
31a39207 CW |
947 | } |
948 | ||
d50415cc CW |
949 | #define KMAP 0x4 /* after CLFLUSH_FLAGS */ |
950 | ||
650bc635 CW |
951 | static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) |
952 | { | |
953 | struct drm_i915_private *i915 = | |
954 | container_of(cache, struct i915_execbuffer, reloc_cache)->i915; | |
955 | return &i915->ggtt; | |
956 | } | |
957 | ||
7dd4f672 CW |
958 | static void reloc_gpu_flush(struct reloc_cache *cache) |
959 | { | |
960 | GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32)); | |
961 | cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END; | |
962 | i915_gem_object_unpin_map(cache->rq->batch->obj); | |
963 | i915_gem_chipset_flush(cache->rq->i915); | |
964 | ||
965 | __i915_add_request(cache->rq, true); | |
966 | cache->rq = NULL; | |
967 | } | |
968 | ||
650bc635 | 969 | static void reloc_cache_reset(struct reloc_cache *cache) |
31a39207 | 970 | { |
d50415cc | 971 | void *vaddr; |
5032d871 | 972 | |
7dd4f672 CW |
973 | if (cache->rq) |
974 | reloc_gpu_flush(cache); | |
975 | ||
31a39207 CW |
976 | if (!cache->vaddr) |
977 | return; | |
3c94ceee | 978 | |
d50415cc CW |
979 | vaddr = unmask_page(cache->vaddr); |
980 | if (cache->vaddr & KMAP) { | |
981 | if (cache->vaddr & CLFLUSH_AFTER) | |
982 | mb(); | |
3c94ceee | 983 | |
d50415cc CW |
984 | kunmap_atomic(vaddr); |
985 | i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm); | |
986 | } else { | |
e8cb909a | 987 | wmb(); |
d50415cc | 988 | io_mapping_unmap_atomic((void __iomem *)vaddr); |
e8cb909a | 989 | if (cache->node.allocated) { |
650bc635 | 990 | struct i915_ggtt *ggtt = cache_to_ggtt(cache); |
e8cb909a CW |
991 | |
992 | ggtt->base.clear_range(&ggtt->base, | |
993 | cache->node.start, | |
4fb84d99 | 994 | cache->node.size); |
e8cb909a CW |
995 | drm_mm_remove_node(&cache->node); |
996 | } else { | |
997 | i915_vma_unpin((struct i915_vma *)cache->node.mm); | |
3c94ceee | 998 | } |
31a39207 | 999 | } |
650bc635 CW |
1000 | |
1001 | cache->vaddr = 0; | |
1002 | cache->page = -1; | |
31a39207 CW |
1003 | } |
1004 | ||
1005 | static void *reloc_kmap(struct drm_i915_gem_object *obj, | |
1006 | struct reloc_cache *cache, | |
2889caa9 | 1007 | unsigned long page) |
31a39207 | 1008 | { |
d50415cc CW |
1009 | void *vaddr; |
1010 | ||
1011 | if (cache->vaddr) { | |
1012 | kunmap_atomic(unmask_page(cache->vaddr)); | |
1013 | } else { | |
1014 | unsigned int flushes; | |
2889caa9 | 1015 | int err; |
31a39207 | 1016 | |
2889caa9 CW |
1017 | err = i915_gem_obj_prepare_shmem_write(obj, &flushes); |
1018 | if (err) | |
1019 | return ERR_PTR(err); | |
d50415cc CW |
1020 | |
1021 | BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); | |
1022 | BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); | |
3c94ceee | 1023 | |
d50415cc CW |
1024 | cache->vaddr = flushes | KMAP; |
1025 | cache->node.mm = (void *)obj; | |
1026 | if (flushes) | |
1027 | mb(); | |
3c94ceee BW |
1028 | } |
1029 | ||
d50415cc CW |
1030 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); |
1031 | cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; | |
31a39207 | 1032 | cache->page = page; |
5032d871 | 1033 | |
d50415cc | 1034 | return vaddr; |
5032d871 RB |
1035 | } |
1036 | ||
d50415cc CW |
1037 | static void *reloc_iomap(struct drm_i915_gem_object *obj, |
1038 | struct reloc_cache *cache, | |
2889caa9 | 1039 | unsigned long page) |
5032d871 | 1040 | { |
650bc635 | 1041 | struct i915_ggtt *ggtt = cache_to_ggtt(cache); |
e8cb909a | 1042 | unsigned long offset; |
d50415cc | 1043 | void *vaddr; |
5032d871 | 1044 | |
d50415cc | 1045 | if (cache->vaddr) { |
615e5000 | 1046 | io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); |
d50415cc CW |
1047 | } else { |
1048 | struct i915_vma *vma; | |
2889caa9 | 1049 | int err; |
5032d871 | 1050 | |
2889caa9 | 1051 | if (use_cpu_reloc(cache, obj)) |
d50415cc | 1052 | return NULL; |
3c94ceee | 1053 | |
2889caa9 CW |
1054 | err = i915_gem_object_set_to_gtt_domain(obj, true); |
1055 | if (err) | |
1056 | return ERR_PTR(err); | |
3c94ceee | 1057 | |
d50415cc CW |
1058 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
1059 | PIN_MAPPABLE | PIN_NONBLOCK); | |
e8cb909a CW |
1060 | if (IS_ERR(vma)) { |
1061 | memset(&cache->node, 0, sizeof(cache->node)); | |
2889caa9 | 1062 | err = drm_mm_insert_node_in_range |
e8cb909a | 1063 | (&ggtt->base.mm, &cache->node, |
f51455d4 | 1064 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, |
e8cb909a | 1065 | 0, ggtt->mappable_end, |
4e64e553 | 1066 | DRM_MM_INSERT_LOW); |
2889caa9 | 1067 | if (err) /* no inactive aperture space, use cpu reloc */ |
c92fa4fe | 1068 | return NULL; |
e8cb909a | 1069 | } else { |
2889caa9 CW |
1070 | err = i915_vma_put_fence(vma); |
1071 | if (err) { | |
e8cb909a | 1072 | i915_vma_unpin(vma); |
2889caa9 | 1073 | return ERR_PTR(err); |
e8cb909a | 1074 | } |
5032d871 | 1075 | |
e8cb909a CW |
1076 | cache->node.start = vma->node.start; |
1077 | cache->node.mm = (void *)vma; | |
3c94ceee | 1078 | } |
e8cb909a | 1079 | } |
3c94ceee | 1080 | |
e8cb909a CW |
1081 | offset = cache->node.start; |
1082 | if (cache->node.allocated) { | |
fc099090 | 1083 | wmb(); |
e8cb909a CW |
1084 | ggtt->base.insert_page(&ggtt->base, |
1085 | i915_gem_object_get_dma_address(obj, page), | |
1086 | offset, I915_CACHE_NONE, 0); | |
1087 | } else { | |
1088 | offset += page << PAGE_SHIFT; | |
3c94ceee BW |
1089 | } |
1090 | ||
650bc635 CW |
1091 | vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable, |
1092 | offset); | |
d50415cc CW |
1093 | cache->page = page; |
1094 | cache->vaddr = (unsigned long)vaddr; | |
5032d871 | 1095 | |
d50415cc | 1096 | return vaddr; |
5032d871 RB |
1097 | } |
1098 | ||
d50415cc CW |
1099 | static void *reloc_vaddr(struct drm_i915_gem_object *obj, |
1100 | struct reloc_cache *cache, | |
2889caa9 | 1101 | unsigned long page) |
edf4427b | 1102 | { |
d50415cc | 1103 | void *vaddr; |
5032d871 | 1104 | |
d50415cc CW |
1105 | if (cache->page == page) { |
1106 | vaddr = unmask_page(cache->vaddr); | |
1107 | } else { | |
1108 | vaddr = NULL; | |
1109 | if ((cache->vaddr & KMAP) == 0) | |
1110 | vaddr = reloc_iomap(obj, cache, page); | |
1111 | if (!vaddr) | |
1112 | vaddr = reloc_kmap(obj, cache, page); | |
3c94ceee BW |
1113 | } |
1114 | ||
d50415cc | 1115 | return vaddr; |
edf4427b CW |
1116 | } |
1117 | ||
d50415cc | 1118 | static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) |
edf4427b | 1119 | { |
d50415cc CW |
1120 | if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { |
1121 | if (flushes & CLFLUSH_BEFORE) { | |
1122 | clflushopt(addr); | |
1123 | mb(); | |
1124 | } | |
edf4427b | 1125 | |
d50415cc | 1126 | *addr = value; |
edf4427b | 1127 | |
2889caa9 CW |
1128 | /* |
1129 | * Writes to the same cacheline are serialised by the CPU | |
d50415cc CW |
1130 | * (including clflush). On the write path, we only require |
1131 | * that it hits memory in an orderly fashion and place | |
1132 | * mb barriers at the start and end of the relocation phase | |
1133 | * to ensure ordering of clflush wrt to the system. | |
1134 | */ | |
1135 | if (flushes & CLFLUSH_AFTER) | |
1136 | clflushopt(addr); | |
1137 | } else | |
1138 | *addr = value; | |
edf4427b | 1139 | } |
edf4427b | 1140 | |
7dd4f672 CW |
1141 | static int __reloc_gpu_alloc(struct i915_execbuffer *eb, |
1142 | struct i915_vma *vma, | |
1143 | unsigned int len) | |
1144 | { | |
1145 | struct reloc_cache *cache = &eb->reloc_cache; | |
1146 | struct drm_i915_gem_object *obj; | |
1147 | struct drm_i915_gem_request *rq; | |
1148 | struct i915_vma *batch; | |
1149 | u32 *cmd; | |
1150 | int err; | |
1151 | ||
1152 | GEM_BUG_ON(vma->obj->base.write_domain & I915_GEM_DOMAIN_CPU); | |
1153 | ||
1154 | obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE); | |
1155 | if (IS_ERR(obj)) | |
1156 | return PTR_ERR(obj); | |
1157 | ||
1158 | cmd = i915_gem_object_pin_map(obj, | |
1159 | cache->has_llc ? I915_MAP_WB : I915_MAP_WC); | |
1160 | i915_gem_object_unpin_pages(obj); | |
1161 | if (IS_ERR(cmd)) | |
1162 | return PTR_ERR(cmd); | |
1163 | ||
1164 | err = i915_gem_object_set_to_wc_domain(obj, false); | |
1165 | if (err) | |
1166 | goto err_unmap; | |
1167 | ||
1168 | batch = i915_vma_instance(obj, vma->vm, NULL); | |
1169 | if (IS_ERR(batch)) { | |
1170 | err = PTR_ERR(batch); | |
1171 | goto err_unmap; | |
1172 | } | |
1173 | ||
1174 | err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK); | |
1175 | if (err) | |
1176 | goto err_unmap; | |
1177 | ||
1178 | rq = i915_gem_request_alloc(eb->engine, eb->ctx); | |
1179 | if (IS_ERR(rq)) { | |
1180 | err = PTR_ERR(rq); | |
1181 | goto err_unpin; | |
1182 | } | |
1183 | ||
1184 | err = i915_gem_request_await_object(rq, vma->obj, true); | |
1185 | if (err) | |
1186 | goto err_request; | |
1187 | ||
1188 | err = eb->engine->emit_flush(rq, EMIT_INVALIDATE); | |
1189 | if (err) | |
1190 | goto err_request; | |
1191 | ||
1192 | err = i915_switch_context(rq); | |
1193 | if (err) | |
1194 | goto err_request; | |
1195 | ||
1196 | err = eb->engine->emit_bb_start(rq, | |
1197 | batch->node.start, PAGE_SIZE, | |
1198 | cache->gen > 5 ? 0 : I915_DISPATCH_SECURE); | |
1199 | if (err) | |
1200 | goto err_request; | |
1201 | ||
95ff7c7d | 1202 | GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true)); |
7dd4f672 | 1203 | i915_vma_move_to_active(batch, rq, 0); |
95ff7c7d CW |
1204 | reservation_object_lock(batch->resv, NULL); |
1205 | reservation_object_add_excl_fence(batch->resv, &rq->fence); | |
1206 | reservation_object_unlock(batch->resv); | |
7dd4f672 CW |
1207 | i915_vma_unpin(batch); |
1208 | ||
b88eb199 | 1209 | i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); |
95ff7c7d CW |
1210 | reservation_object_lock(vma->resv, NULL); |
1211 | reservation_object_add_excl_fence(vma->resv, &rq->fence); | |
1212 | reservation_object_unlock(vma->resv); | |
7dd4f672 CW |
1213 | |
1214 | rq->batch = batch; | |
1215 | ||
1216 | cache->rq = rq; | |
1217 | cache->rq_cmd = cmd; | |
1218 | cache->rq_size = 0; | |
1219 | ||
1220 | /* Return with batch mapping (cmd) still pinned */ | |
1221 | return 0; | |
1222 | ||
1223 | err_request: | |
1224 | i915_add_request(rq); | |
1225 | err_unpin: | |
1226 | i915_vma_unpin(batch); | |
1227 | err_unmap: | |
1228 | i915_gem_object_unpin_map(obj); | |
1229 | return err; | |
1230 | } | |
1231 | ||
1232 | static u32 *reloc_gpu(struct i915_execbuffer *eb, | |
1233 | struct i915_vma *vma, | |
1234 | unsigned int len) | |
1235 | { | |
1236 | struct reloc_cache *cache = &eb->reloc_cache; | |
1237 | u32 *cmd; | |
1238 | ||
1239 | if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1)) | |
1240 | reloc_gpu_flush(cache); | |
1241 | ||
1242 | if (unlikely(!cache->rq)) { | |
1243 | int err; | |
1244 | ||
1245 | err = __reloc_gpu_alloc(eb, vma, len); | |
1246 | if (unlikely(err)) | |
1247 | return ERR_PTR(err); | |
1248 | } | |
1249 | ||
1250 | cmd = cache->rq_cmd + cache->rq_size; | |
1251 | cache->rq_size += len; | |
1252 | ||
1253 | return cmd; | |
1254 | } | |
1255 | ||
2889caa9 CW |
1256 | static u64 |
1257 | relocate_entry(struct i915_vma *vma, | |
d50415cc | 1258 | const struct drm_i915_gem_relocation_entry *reloc, |
2889caa9 CW |
1259 | struct i915_execbuffer *eb, |
1260 | const struct i915_vma *target) | |
edf4427b | 1261 | { |
d50415cc | 1262 | u64 offset = reloc->offset; |
2889caa9 CW |
1263 | u64 target_offset = relocation_target(reloc, target); |
1264 | bool wide = eb->reloc_cache.use_64bit_reloc; | |
d50415cc | 1265 | void *vaddr; |
edf4427b | 1266 | |
7dd4f672 CW |
1267 | if (!eb->reloc_cache.vaddr && |
1268 | (DBG_FORCE_RELOC == FORCE_GPU_RELOC || | |
95ff7c7d | 1269 | !reservation_object_test_signaled_rcu(vma->resv, true))) { |
7dd4f672 CW |
1270 | const unsigned int gen = eb->reloc_cache.gen; |
1271 | unsigned int len; | |
1272 | u32 *batch; | |
1273 | u64 addr; | |
1274 | ||
1275 | if (wide) | |
1276 | len = offset & 7 ? 8 : 5; | |
1277 | else if (gen >= 4) | |
1278 | len = 4; | |
1279 | else if (gen >= 3) | |
1280 | len = 3; | |
1281 | else /* On gen2 MI_STORE_DWORD_IMM uses a physical address */ | |
1282 | goto repeat; | |
1283 | ||
1284 | batch = reloc_gpu(eb, vma, len); | |
1285 | if (IS_ERR(batch)) | |
1286 | goto repeat; | |
1287 | ||
1288 | addr = gen8_canonical_addr(vma->node.start + offset); | |
1289 | if (wide) { | |
1290 | if (offset & 7) { | |
1291 | *batch++ = MI_STORE_DWORD_IMM_GEN4; | |
1292 | *batch++ = lower_32_bits(addr); | |
1293 | *batch++ = upper_32_bits(addr); | |
1294 | *batch++ = lower_32_bits(target_offset); | |
1295 | ||
1296 | addr = gen8_canonical_addr(addr + 4); | |
1297 | ||
1298 | *batch++ = MI_STORE_DWORD_IMM_GEN4; | |
1299 | *batch++ = lower_32_bits(addr); | |
1300 | *batch++ = upper_32_bits(addr); | |
1301 | *batch++ = upper_32_bits(target_offset); | |
1302 | } else { | |
1303 | *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1; | |
1304 | *batch++ = lower_32_bits(addr); | |
1305 | *batch++ = upper_32_bits(addr); | |
1306 | *batch++ = lower_32_bits(target_offset); | |
1307 | *batch++ = upper_32_bits(target_offset); | |
1308 | } | |
1309 | } else if (gen >= 6) { | |
1310 | *batch++ = MI_STORE_DWORD_IMM_GEN4; | |
1311 | *batch++ = 0; | |
1312 | *batch++ = addr; | |
1313 | *batch++ = target_offset; | |
1314 | } else if (gen >= 4) { | |
1315 | *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; | |
1316 | *batch++ = 0; | |
1317 | *batch++ = addr; | |
1318 | *batch++ = target_offset; | |
1319 | } else { | |
1320 | *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
1321 | *batch++ = addr; | |
1322 | *batch++ = target_offset; | |
1323 | } | |
1324 | ||
1325 | goto out; | |
1326 | } | |
1327 | ||
d50415cc | 1328 | repeat: |
95ff7c7d | 1329 | vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT); |
d50415cc CW |
1330 | if (IS_ERR(vaddr)) |
1331 | return PTR_ERR(vaddr); | |
1332 | ||
1333 | clflush_write32(vaddr + offset_in_page(offset), | |
1334 | lower_32_bits(target_offset), | |
2889caa9 | 1335 | eb->reloc_cache.vaddr); |
d50415cc CW |
1336 | |
1337 | if (wide) { | |
1338 | offset += sizeof(u32); | |
1339 | target_offset >>= 32; | |
1340 | wide = false; | |
1341 | goto repeat; | |
edf4427b | 1342 | } |
edf4427b | 1343 | |
7dd4f672 | 1344 | out: |
2889caa9 | 1345 | return target->node.start | UPDATE; |
edf4427b | 1346 | } |
edf4427b | 1347 | |
2889caa9 CW |
1348 | static u64 |
1349 | eb_relocate_entry(struct i915_execbuffer *eb, | |
1350 | struct i915_vma *vma, | |
1351 | const struct drm_i915_gem_relocation_entry *reloc) | |
54cf91dc | 1352 | { |
507d977f | 1353 | struct i915_vma *target; |
2889caa9 | 1354 | int err; |
54cf91dc | 1355 | |
67731b87 | 1356 | /* we've already hold a reference to all valid objects */ |
507d977f CW |
1357 | target = eb_get_vma(eb, reloc->target_handle); |
1358 | if (unlikely(!target)) | |
54cf91dc | 1359 | return -ENOENT; |
e844b990 | 1360 | |
54cf91dc | 1361 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 1362 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 1363 | DRM_DEBUG("reloc with multiple write domains: " |
507d977f | 1364 | "target %d offset %d " |
54cf91dc | 1365 | "read %08x write %08x", |
507d977f | 1366 | reloc->target_handle, |
54cf91dc CW |
1367 | (int) reloc->offset, |
1368 | reloc->read_domains, | |
1369 | reloc->write_domain); | |
8b78f0e5 | 1370 | return -EINVAL; |
54cf91dc | 1371 | } |
4ca4a250 DV |
1372 | if (unlikely((reloc->write_domain | reloc->read_domains) |
1373 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 1374 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
507d977f | 1375 | "target %d offset %d " |
54cf91dc | 1376 | "read %08x write %08x", |
507d977f | 1377 | reloc->target_handle, |
54cf91dc CW |
1378 | (int) reloc->offset, |
1379 | reloc->read_domains, | |
1380 | reloc->write_domain); | |
8b78f0e5 | 1381 | return -EINVAL; |
54cf91dc | 1382 | } |
54cf91dc | 1383 | |
2889caa9 | 1384 | if (reloc->write_domain) { |
507d977f CW |
1385 | target->exec_entry->flags |= EXEC_OBJECT_WRITE; |
1386 | ||
2889caa9 CW |
1387 | /* |
1388 | * Sandybridge PPGTT errata: We need a global gtt mapping | |
1389 | * for MI and pipe_control writes because the gpu doesn't | |
1390 | * properly redirect them through the ppgtt for non_secure | |
1391 | * batchbuffers. | |
1392 | */ | |
1393 | if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
1394 | IS_GEN6(eb->i915)) { | |
1395 | err = i915_vma_bind(target, target->obj->cache_level, | |
1396 | PIN_GLOBAL); | |
1397 | if (WARN_ONCE(err, | |
1398 | "Unexpected failure to bind target VMA!")) | |
1399 | return err; | |
1400 | } | |
507d977f | 1401 | } |
54cf91dc | 1402 | |
2889caa9 CW |
1403 | /* |
1404 | * If the relocation already has the right value in it, no | |
54cf91dc CW |
1405 | * more work needs to be done. |
1406 | */ | |
7dd4f672 CW |
1407 | if (!DBG_FORCE_RELOC && |
1408 | gen8_canonical_addr(target->node.start) == reloc->presumed_offset) | |
67731b87 | 1409 | return 0; |
54cf91dc CW |
1410 | |
1411 | /* Check that the relocation address is valid... */ | |
3c94ceee | 1412 | if (unlikely(reloc->offset > |
507d977f | 1413 | vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) { |
ff240199 | 1414 | DRM_DEBUG("Relocation beyond object bounds: " |
507d977f CW |
1415 | "target %d offset %d size %d.\n", |
1416 | reloc->target_handle, | |
1417 | (int)reloc->offset, | |
1418 | (int)vma->size); | |
8b78f0e5 | 1419 | return -EINVAL; |
54cf91dc | 1420 | } |
b8f7ab17 | 1421 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 1422 | DRM_DEBUG("Relocation not 4-byte aligned: " |
507d977f CW |
1423 | "target %d offset %d.\n", |
1424 | reloc->target_handle, | |
1425 | (int)reloc->offset); | |
8b78f0e5 | 1426 | return -EINVAL; |
54cf91dc CW |
1427 | } |
1428 | ||
071750e5 CW |
1429 | /* |
1430 | * If we write into the object, we need to force the synchronisation | |
1431 | * barrier, either with an asynchronous clflush or if we executed the | |
1432 | * patching using the GPU (though that should be serialised by the | |
1433 | * timeline). To be completely sure, and since we are required to | |
1434 | * do relocations we are already stalling, disable the user's opt | |
1435 | * of our synchronisation. | |
1436 | */ | |
1437 | vma->exec_entry->flags &= ~EXEC_OBJECT_ASYNC; | |
1438 | ||
54cf91dc | 1439 | /* and update the user's relocation entry */ |
2889caa9 | 1440 | return relocate_entry(vma, reloc, eb, target); |
54cf91dc CW |
1441 | } |
1442 | ||
2889caa9 | 1443 | static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma) |
54cf91dc | 1444 | { |
1d83f442 | 1445 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
2889caa9 CW |
1446 | struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; |
1447 | struct drm_i915_gem_relocation_entry __user *urelocs; | |
1448 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
1449 | unsigned int remain; | |
54cf91dc | 1450 | |
2889caa9 | 1451 | urelocs = u64_to_user_ptr(entry->relocs_ptr); |
1d83f442 | 1452 | remain = entry->relocation_count; |
2889caa9 CW |
1453 | if (unlikely(remain > N_RELOC(ULONG_MAX))) |
1454 | return -EINVAL; | |
ebc0808f | 1455 | |
2889caa9 CW |
1456 | /* |
1457 | * We must check that the entire relocation array is safe | |
1458 | * to read. However, if the array is not writable the user loses | |
1459 | * the updated relocation values. | |
1460 | */ | |
7728124a | 1461 | if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs)))) |
2889caa9 CW |
1462 | return -EFAULT; |
1463 | ||
1464 | do { | |
1465 | struct drm_i915_gem_relocation_entry *r = stack; | |
1466 | unsigned int count = | |
1467 | min_t(unsigned int, remain, ARRAY_SIZE(stack)); | |
1468 | unsigned int copied; | |
1d83f442 | 1469 | |
2889caa9 CW |
1470 | /* |
1471 | * This is the fast path and we cannot handle a pagefault | |
ebc0808f CW |
1472 | * whilst holding the struct mutex lest the user pass in the |
1473 | * relocations contained within a mmaped bo. For in such a case | |
1474 | * we, the page fault handler would call i915_gem_fault() and | |
1475 | * we would try to acquire the struct mutex again. Obviously | |
1476 | * this is bad and so lockdep complains vehemently. | |
1477 | */ | |
1478 | pagefault_disable(); | |
2889caa9 | 1479 | copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0])); |
ebc0808f | 1480 | pagefault_enable(); |
2889caa9 CW |
1481 | if (unlikely(copied)) { |
1482 | remain = -EFAULT; | |
31a39207 CW |
1483 | goto out; |
1484 | } | |
54cf91dc | 1485 | |
2889caa9 | 1486 | remain -= count; |
1d83f442 | 1487 | do { |
2889caa9 | 1488 | u64 offset = eb_relocate_entry(eb, vma, r); |
54cf91dc | 1489 | |
2889caa9 CW |
1490 | if (likely(offset == 0)) { |
1491 | } else if ((s64)offset < 0) { | |
1492 | remain = (int)offset; | |
31a39207 | 1493 | goto out; |
2889caa9 CW |
1494 | } else { |
1495 | /* | |
1496 | * Note that reporting an error now | |
1497 | * leaves everything in an inconsistent | |
1498 | * state as we have *already* changed | |
1499 | * the relocation value inside the | |
1500 | * object. As we have not changed the | |
1501 | * reloc.presumed_offset or will not | |
1502 | * change the execobject.offset, on the | |
1503 | * call we may not rewrite the value | |
1504 | * inside the object, leaving it | |
1505 | * dangling and causing a GPU hang. Unless | |
1506 | * userspace dynamically rebuilds the | |
1507 | * relocations on each execbuf rather than | |
1508 | * presume a static tree. | |
1509 | * | |
1510 | * We did previously check if the relocations | |
1511 | * were writable (access_ok), an error now | |
1512 | * would be a strange race with mprotect, | |
1513 | * having already demonstrated that we | |
1514 | * can read from this userspace address. | |
1515 | */ | |
1516 | offset = gen8_canonical_addr(offset & ~UPDATE); | |
1517 | __put_user(offset, | |
1518 | &urelocs[r-stack].presumed_offset); | |
1d83f442 | 1519 | } |
2889caa9 CW |
1520 | } while (r++, --count); |
1521 | urelocs += ARRAY_SIZE(stack); | |
1522 | } while (remain); | |
31a39207 | 1523 | out: |
650bc635 | 1524 | reloc_cache_reset(&eb->reloc_cache); |
2889caa9 | 1525 | return remain; |
54cf91dc CW |
1526 | } |
1527 | ||
1528 | static int | |
2889caa9 | 1529 | eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma) |
54cf91dc | 1530 | { |
27173f1f | 1531 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
2889caa9 CW |
1532 | struct drm_i915_gem_relocation_entry *relocs = |
1533 | u64_to_ptr(typeof(*relocs), entry->relocs_ptr); | |
1534 | unsigned int i; | |
1535 | int err; | |
54cf91dc CW |
1536 | |
1537 | for (i = 0; i < entry->relocation_count; i++) { | |
2889caa9 | 1538 | u64 offset = eb_relocate_entry(eb, vma, &relocs[i]); |
d4aeee77 | 1539 | |
2889caa9 CW |
1540 | if ((s64)offset < 0) { |
1541 | err = (int)offset; | |
1542 | goto err; | |
1543 | } | |
54cf91dc | 1544 | } |
2889caa9 CW |
1545 | err = 0; |
1546 | err: | |
1547 | reloc_cache_reset(&eb->reloc_cache); | |
1548 | return err; | |
edf4427b CW |
1549 | } |
1550 | ||
2889caa9 | 1551 | static int check_relocations(const struct drm_i915_gem_exec_object2 *entry) |
1690e1eb | 1552 | { |
2889caa9 CW |
1553 | const char __user *addr, *end; |
1554 | unsigned long size; | |
1555 | char __maybe_unused c; | |
1690e1eb | 1556 | |
2889caa9 CW |
1557 | size = entry->relocation_count; |
1558 | if (size == 0) | |
1559 | return 0; | |
7788a765 | 1560 | |
2889caa9 CW |
1561 | if (size > N_RELOC(ULONG_MAX)) |
1562 | return -EINVAL; | |
9a5a53b3 | 1563 | |
2889caa9 CW |
1564 | addr = u64_to_user_ptr(entry->relocs_ptr); |
1565 | size *= sizeof(struct drm_i915_gem_relocation_entry); | |
1566 | if (!access_ok(VERIFY_READ, addr, size)) | |
1567 | return -EFAULT; | |
1690e1eb | 1568 | |
2889caa9 CW |
1569 | end = addr + size; |
1570 | for (; addr < end; addr += PAGE_SIZE) { | |
1571 | int err = __get_user(c, addr); | |
1572 | if (err) | |
1573 | return err; | |
ed5982e6 | 1574 | } |
2889caa9 | 1575 | return __get_user(c, end - 1); |
7788a765 | 1576 | } |
1690e1eb | 1577 | |
2889caa9 | 1578 | static int eb_copy_relocations(const struct i915_execbuffer *eb) |
d23db88c | 1579 | { |
2889caa9 CW |
1580 | const unsigned int count = eb->buffer_count; |
1581 | unsigned int i; | |
1582 | int err; | |
e6a84468 | 1583 | |
2889caa9 CW |
1584 | for (i = 0; i < count; i++) { |
1585 | const unsigned int nreloc = eb->exec[i].relocation_count; | |
1586 | struct drm_i915_gem_relocation_entry __user *urelocs; | |
1587 | struct drm_i915_gem_relocation_entry *relocs; | |
1588 | unsigned long size; | |
1589 | unsigned long copied; | |
e6a84468 | 1590 | |
2889caa9 CW |
1591 | if (nreloc == 0) |
1592 | continue; | |
e6a84468 | 1593 | |
2889caa9 CW |
1594 | err = check_relocations(&eb->exec[i]); |
1595 | if (err) | |
1596 | goto err; | |
d23db88c | 1597 | |
2889caa9 CW |
1598 | urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr); |
1599 | size = nreloc * sizeof(*relocs); | |
d23db88c | 1600 | |
2889caa9 CW |
1601 | relocs = kvmalloc_array(size, 1, GFP_TEMPORARY); |
1602 | if (!relocs) { | |
1603 | kvfree(relocs); | |
1604 | err = -ENOMEM; | |
1605 | goto err; | |
1606 | } | |
d23db88c | 1607 | |
2889caa9 CW |
1608 | /* copy_from_user is limited to < 4GiB */ |
1609 | copied = 0; | |
1610 | do { | |
1611 | unsigned int len = | |
1612 | min_t(u64, BIT_ULL(31), size - copied); | |
1613 | ||
1614 | if (__copy_from_user((char *)relocs + copied, | |
1615 | (char *)urelocs + copied, | |
1616 | len)) { | |
1617 | kvfree(relocs); | |
1618 | err = -EFAULT; | |
1619 | goto err; | |
1620 | } | |
91b2db6f | 1621 | |
2889caa9 CW |
1622 | copied += len; |
1623 | } while (copied < size); | |
506a8e87 | 1624 | |
2889caa9 CW |
1625 | /* |
1626 | * As we do not update the known relocation offsets after | |
1627 | * relocating (due to the complexities in lock handling), | |
1628 | * we need to mark them as invalid now so that we force the | |
1629 | * relocation processing next time. Just in case the target | |
1630 | * object is evicted and then rebound into its old | |
1631 | * presumed_offset before the next execbuffer - if that | |
1632 | * happened we would make the mistake of assuming that the | |
1633 | * relocations were valid. | |
1634 | */ | |
1635 | user_access_begin(); | |
1636 | for (copied = 0; copied < nreloc; copied++) | |
1637 | unsafe_put_user(-1, | |
1638 | &urelocs[copied].presumed_offset, | |
1639 | end_user); | |
1640 | end_user: | |
1641 | user_access_end(); | |
d23db88c | 1642 | |
2889caa9 CW |
1643 | eb->exec[i].relocs_ptr = (uintptr_t)relocs; |
1644 | } | |
edf4427b | 1645 | |
2889caa9 | 1646 | return 0; |
101b506a | 1647 | |
2889caa9 CW |
1648 | err: |
1649 | while (i--) { | |
1650 | struct drm_i915_gem_relocation_entry *relocs = | |
1651 | u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr); | |
1652 | if (eb->exec[i].relocation_count) | |
1653 | kvfree(relocs); | |
1654 | } | |
1655 | return err; | |
d23db88c CW |
1656 | } |
1657 | ||
2889caa9 | 1658 | static int eb_prefault_relocations(const struct i915_execbuffer *eb) |
54cf91dc | 1659 | { |
2889caa9 CW |
1660 | const unsigned int count = eb->buffer_count; |
1661 | unsigned int i; | |
54cf91dc | 1662 | |
2889caa9 CW |
1663 | if (unlikely(i915.prefault_disable)) |
1664 | return 0; | |
54cf91dc | 1665 | |
2889caa9 CW |
1666 | for (i = 0; i < count; i++) { |
1667 | int err; | |
54cf91dc | 1668 | |
2889caa9 CW |
1669 | err = check_relocations(&eb->exec[i]); |
1670 | if (err) | |
1671 | return err; | |
1672 | } | |
a415d355 | 1673 | |
2889caa9 | 1674 | return 0; |
54cf91dc CW |
1675 | } |
1676 | ||
2889caa9 | 1677 | static noinline int eb_relocate_slow(struct i915_execbuffer *eb) |
54cf91dc | 1678 | { |
650bc635 | 1679 | struct drm_device *dev = &eb->i915->drm; |
2889caa9 | 1680 | bool have_copy = false; |
27173f1f | 1681 | struct i915_vma *vma; |
2889caa9 CW |
1682 | int err = 0; |
1683 | ||
1684 | repeat: | |
1685 | if (signal_pending(current)) { | |
1686 | err = -ERESTARTSYS; | |
1687 | goto out; | |
1688 | } | |
27173f1f | 1689 | |
67731b87 | 1690 | /* We may process another execbuffer during the unlock... */ |
2889caa9 | 1691 | eb_reset_vmas(eb); |
54cf91dc CW |
1692 | mutex_unlock(&dev->struct_mutex); |
1693 | ||
2889caa9 CW |
1694 | /* |
1695 | * We take 3 passes through the slowpatch. | |
1696 | * | |
1697 | * 1 - we try to just prefault all the user relocation entries and | |
1698 | * then attempt to reuse the atomic pagefault disabled fast path again. | |
1699 | * | |
1700 | * 2 - we copy the user entries to a local buffer here outside of the | |
1701 | * local and allow ourselves to wait upon any rendering before | |
1702 | * relocations | |
1703 | * | |
1704 | * 3 - we already have a local copy of the relocation entries, but | |
1705 | * were interrupted (EAGAIN) whilst waiting for the objects, try again. | |
1706 | */ | |
1707 | if (!err) { | |
1708 | err = eb_prefault_relocations(eb); | |
1709 | } else if (!have_copy) { | |
1710 | err = eb_copy_relocations(eb); | |
1711 | have_copy = err == 0; | |
1712 | } else { | |
1713 | cond_resched(); | |
1714 | err = 0; | |
54cf91dc | 1715 | } |
2889caa9 CW |
1716 | if (err) { |
1717 | mutex_lock(&dev->struct_mutex); | |
1718 | goto out; | |
54cf91dc CW |
1719 | } |
1720 | ||
8a2421bd CW |
1721 | /* A frequent cause for EAGAIN are currently unavailable client pages */ |
1722 | flush_workqueue(eb->i915->mm.userptr_wq); | |
1723 | ||
2889caa9 CW |
1724 | err = i915_mutex_lock_interruptible(dev); |
1725 | if (err) { | |
54cf91dc | 1726 | mutex_lock(&dev->struct_mutex); |
2889caa9 | 1727 | goto out; |
54cf91dc CW |
1728 | } |
1729 | ||
67731b87 | 1730 | /* reacquire the objects */ |
2889caa9 CW |
1731 | err = eb_lookup_vmas(eb); |
1732 | if (err) | |
3b96eff4 | 1733 | goto err; |
67731b87 | 1734 | |
2889caa9 CW |
1735 | list_for_each_entry(vma, &eb->relocs, reloc_link) { |
1736 | if (!have_copy) { | |
1737 | pagefault_disable(); | |
1738 | err = eb_relocate_vma(eb, vma); | |
1739 | pagefault_enable(); | |
1740 | if (err) | |
1741 | goto repeat; | |
1742 | } else { | |
1743 | err = eb_relocate_vma_slow(eb, vma); | |
1744 | if (err) | |
1745 | goto err; | |
1746 | } | |
54cf91dc CW |
1747 | } |
1748 | ||
2889caa9 CW |
1749 | /* |
1750 | * Leave the user relocations as are, this is the painfully slow path, | |
54cf91dc CW |
1751 | * and we want to avoid the complication of dropping the lock whilst |
1752 | * having buffers reserved in the aperture and so causing spurious | |
1753 | * ENOSPC for random operations. | |
1754 | */ | |
1755 | ||
1756 | err: | |
2889caa9 CW |
1757 | if (err == -EAGAIN) |
1758 | goto repeat; | |
1759 | ||
1760 | out: | |
1761 | if (have_copy) { | |
1762 | const unsigned int count = eb->buffer_count; | |
1763 | unsigned int i; | |
1764 | ||
1765 | for (i = 0; i < count; i++) { | |
1766 | const struct drm_i915_gem_exec_object2 *entry = | |
1767 | &eb->exec[i]; | |
1768 | struct drm_i915_gem_relocation_entry *relocs; | |
1769 | ||
1770 | if (!entry->relocation_count) | |
1771 | continue; | |
1772 | ||
1773 | relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); | |
1774 | kvfree(relocs); | |
1775 | } | |
1776 | } | |
1777 | ||
adf27835 | 1778 | return err; |
54cf91dc CW |
1779 | } |
1780 | ||
2889caa9 | 1781 | static int eb_relocate(struct i915_execbuffer *eb) |
54cf91dc | 1782 | { |
2889caa9 CW |
1783 | if (eb_lookup_vmas(eb)) |
1784 | goto slow; | |
1785 | ||
1786 | /* The objects are in their final locations, apply the relocations. */ | |
1787 | if (eb->args->flags & __EXEC_HAS_RELOC) { | |
1788 | struct i915_vma *vma; | |
1789 | ||
1790 | list_for_each_entry(vma, &eb->relocs, reloc_link) { | |
1791 | if (eb_relocate_vma(eb, vma)) | |
1792 | goto slow; | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | return 0; | |
1797 | ||
1798 | slow: | |
1799 | return eb_relocate_slow(eb); | |
1800 | } | |
1801 | ||
95ff7c7d | 1802 | static void eb_export_fence(struct i915_vma *vma, |
2889caa9 CW |
1803 | struct drm_i915_gem_request *req, |
1804 | unsigned int flags) | |
1805 | { | |
95ff7c7d | 1806 | struct reservation_object *resv = vma->resv; |
2889caa9 CW |
1807 | |
1808 | /* | |
1809 | * Ignore errors from failing to allocate the new fence, we can't | |
1810 | * handle an error right now. Worst case should be missed | |
1811 | * synchronisation leading to rendering corruption. | |
1812 | */ | |
1813 | reservation_object_lock(resv, NULL); | |
1814 | if (flags & EXEC_OBJECT_WRITE) | |
1815 | reservation_object_add_excl_fence(resv, &req->fence); | |
1816 | else if (reservation_object_reserve_shared(resv) == 0) | |
1817 | reservation_object_add_shared_fence(resv, &req->fence); | |
1818 | reservation_object_unlock(resv); | |
1819 | } | |
1820 | ||
1821 | static int eb_move_to_gpu(struct i915_execbuffer *eb) | |
1822 | { | |
1823 | const unsigned int count = eb->buffer_count; | |
1824 | unsigned int i; | |
1825 | int err; | |
54cf91dc | 1826 | |
2889caa9 | 1827 | for (i = 0; i < count; i++) { |
7b98da66 | 1828 | struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; |
2889caa9 | 1829 | struct i915_vma *vma = exec_to_vma(entry); |
27173f1f | 1830 | struct drm_i915_gem_object *obj = vma->obj; |
03ade511 | 1831 | |
2889caa9 | 1832 | if (entry->flags & EXEC_OBJECT_CAPTURE) { |
b0fd47ad CW |
1833 | struct i915_gem_capture_list *capture; |
1834 | ||
1835 | capture = kmalloc(sizeof(*capture), GFP_KERNEL); | |
1836 | if (unlikely(!capture)) | |
1837 | return -ENOMEM; | |
1838 | ||
650bc635 | 1839 | capture->next = eb->request->capture_list; |
b0fd47ad | 1840 | capture->vma = vma; |
650bc635 | 1841 | eb->request->capture_list = capture; |
b0fd47ad CW |
1842 | } |
1843 | ||
7b98da66 CW |
1844 | if (unlikely(obj->cache_dirty && !obj->cache_coherent)) { |
1845 | if (i915_gem_clflush_object(obj, 0)) | |
1846 | entry->flags &= ~EXEC_OBJECT_ASYNC; | |
1847 | } | |
1848 | ||
2889caa9 CW |
1849 | if (entry->flags & EXEC_OBJECT_ASYNC) |
1850 | goto skip_flushes; | |
77ae9957 | 1851 | |
2889caa9 CW |
1852 | err = i915_gem_request_await_object |
1853 | (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE); | |
1854 | if (err) | |
1855 | return err; | |
1856 | ||
1857 | skip_flushes: | |
1858 | i915_vma_move_to_active(vma, eb->request, entry->flags); | |
1859 | __eb_unreserve_vma(vma, entry); | |
1860 | vma->exec_entry = NULL; | |
1861 | } | |
1862 | ||
1863 | for (i = 0; i < count; i++) { | |
1864 | const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; | |
1865 | struct i915_vma *vma = exec_to_vma(entry); | |
1866 | ||
95ff7c7d | 1867 | eb_export_fence(vma, eb->request, entry->flags); |
dade2a61 CW |
1868 | if (unlikely(entry->flags & __EXEC_OBJECT_HAS_REF)) |
1869 | i915_vma_put(vma); | |
c59a333f | 1870 | } |
2889caa9 | 1871 | eb->exec = NULL; |
c59a333f | 1872 | |
dcd79934 | 1873 | /* Unconditionally flush any chipset caches (for streaming writes). */ |
650bc635 | 1874 | i915_gem_chipset_flush(eb->i915); |
6ac42f41 | 1875 | |
c7fe7d25 | 1876 | /* Unconditionally invalidate GPU caches and TLBs. */ |
650bc635 | 1877 | return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE); |
54cf91dc CW |
1878 | } |
1879 | ||
2889caa9 | 1880 | static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) |
54cf91dc | 1881 | { |
650bc635 | 1882 | if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS) |
ed5982e6 DV |
1883 | return false; |
1884 | ||
2f5945bc CW |
1885 | /* Kernel clipping was a DRI1 misfeature */ |
1886 | if (exec->num_cliprects || exec->cliprects_ptr) | |
1887 | return false; | |
1888 | ||
1889 | if (exec->DR4 == 0xffffffff) { | |
1890 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1891 | exec->DR4 = 0; | |
1892 | } | |
1893 | if (exec->DR1 || exec->DR4) | |
1894 | return false; | |
1895 | ||
1896 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
1897 | return false; | |
1898 | ||
1899 | return true; | |
54cf91dc CW |
1900 | } |
1901 | ||
5cf3d280 CW |
1902 | void i915_vma_move_to_active(struct i915_vma *vma, |
1903 | struct drm_i915_gem_request *req, | |
1904 | unsigned int flags) | |
1905 | { | |
1906 | struct drm_i915_gem_object *obj = vma->obj; | |
1907 | const unsigned int idx = req->engine->id; | |
1908 | ||
81147b07 | 1909 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5cf3d280 CW |
1910 | GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); |
1911 | ||
2889caa9 CW |
1912 | /* |
1913 | * Add a reference if we're newly entering the active list. | |
b0decaf7 CW |
1914 | * The order in which we add operations to the retirement queue is |
1915 | * vital here: mark_active adds to the start of the callback list, | |
1916 | * such that subsequent callbacks are called first. Therefore we | |
1917 | * add the active reference first and queue for it to be dropped | |
1918 | * *last*. | |
1919 | */ | |
d07f0e59 CW |
1920 | if (!i915_vma_is_active(vma)) |
1921 | obj->active_count++; | |
1922 | i915_vma_set_active(vma, idx); | |
1923 | i915_gem_active_set(&vma->last_read[idx], req); | |
1924 | list_move_tail(&vma->vm_link, &vma->vm->active_list); | |
5cf3d280 | 1925 | |
e27ab73d | 1926 | obj->base.write_domain = 0; |
5cf3d280 | 1927 | if (flags & EXEC_OBJECT_WRITE) { |
e27ab73d CW |
1928 | obj->base.write_domain = I915_GEM_DOMAIN_RENDER; |
1929 | ||
5b8c8aec CW |
1930 | if (intel_fb_obj_invalidate(obj, ORIGIN_CS)) |
1931 | i915_gem_active_set(&obj->frontbuffer_write, req); | |
5cf3d280 | 1932 | |
e27ab73d | 1933 | obj->base.read_domains = 0; |
5cf3d280 | 1934 | } |
e27ab73d | 1935 | obj->base.read_domains |= I915_GEM_GPU_DOMAINS; |
5cf3d280 | 1936 | |
49ef5294 CW |
1937 | if (flags & EXEC_OBJECT_NEEDS_FENCE) |
1938 | i915_gem_active_set(&vma->last_fence, req); | |
5cf3d280 CW |
1939 | } |
1940 | ||
2889caa9 | 1941 | static int i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req) |
ae662d31 | 1942 | { |
73dec95e TU |
1943 | u32 *cs; |
1944 | int i; | |
ae662d31 | 1945 | |
b5321f30 | 1946 | if (!IS_GEN7(req->i915) || req->engine->id != RCS) { |
9d662da8 DV |
1947 | DRM_DEBUG("sol reset is gen7/rcs only\n"); |
1948 | return -EINVAL; | |
1949 | } | |
ae662d31 | 1950 | |
2889caa9 | 1951 | cs = intel_ring_begin(req, 4 * 2 + 2); |
73dec95e TU |
1952 | if (IS_ERR(cs)) |
1953 | return PTR_ERR(cs); | |
ae662d31 | 1954 | |
2889caa9 | 1955 | *cs++ = MI_LOAD_REGISTER_IMM(4); |
ae662d31 | 1956 | for (i = 0; i < 4; i++) { |
73dec95e TU |
1957 | *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); |
1958 | *cs++ = 0; | |
ae662d31 | 1959 | } |
2889caa9 | 1960 | *cs++ = MI_NOOP; |
73dec95e | 1961 | intel_ring_advance(req, cs); |
ae662d31 EA |
1962 | |
1963 | return 0; | |
1964 | } | |
1965 | ||
650bc635 | 1966 | static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master) |
71745376 | 1967 | { |
71745376 | 1968 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1969 | struct i915_vma *vma; |
2889caa9 | 1970 | int err; |
71745376 | 1971 | |
650bc635 CW |
1972 | shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, |
1973 | PAGE_ALIGN(eb->batch_len)); | |
71745376 | 1974 | if (IS_ERR(shadow_batch_obj)) |
59bfa124 | 1975 | return ERR_CAST(shadow_batch_obj); |
71745376 | 1976 | |
2889caa9 | 1977 | err = intel_engine_cmd_parser(eb->engine, |
650bc635 | 1978 | eb->batch->obj, |
33a051a5 | 1979 | shadow_batch_obj, |
650bc635 CW |
1980 | eb->batch_start_offset, |
1981 | eb->batch_len, | |
33a051a5 | 1982 | is_master); |
2889caa9 CW |
1983 | if (err) { |
1984 | if (err == -EACCES) /* unhandled chained batch */ | |
058d88c4 CW |
1985 | vma = NULL; |
1986 | else | |
2889caa9 | 1987 | vma = ERR_PTR(err); |
058d88c4 CW |
1988 | goto out; |
1989 | } | |
71745376 | 1990 | |
058d88c4 CW |
1991 | vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0); |
1992 | if (IS_ERR(vma)) | |
1993 | goto out; | |
de4e783a | 1994 | |
650bc635 | 1995 | vma->exec_entry = |
2889caa9 CW |
1996 | memset(&eb->exec[eb->buffer_count++], |
1997 | 0, sizeof(*vma->exec_entry)); | |
dade2a61 | 1998 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF; |
2889caa9 | 1999 | __exec_to_vma(vma->exec_entry) = (uintptr_t)i915_vma_get(vma); |
71745376 | 2000 | |
058d88c4 | 2001 | out: |
de4e783a | 2002 | i915_gem_object_unpin_pages(shadow_batch_obj); |
058d88c4 | 2003 | return vma; |
71745376 | 2004 | } |
5c6c6003 | 2005 | |
c8659efa | 2006 | static void |
2889caa9 | 2007 | add_to_client(struct drm_i915_gem_request *req, struct drm_file *file) |
c8659efa CW |
2008 | { |
2009 | req->file_priv = file->driver_priv; | |
2010 | list_add_tail(&req->client_link, &req->file_priv->mm.request_list); | |
2011 | } | |
2012 | ||
2889caa9 | 2013 | static int eb_submit(struct i915_execbuffer *eb) |
78382593 | 2014 | { |
2889caa9 | 2015 | int err; |
78382593 | 2016 | |
2889caa9 CW |
2017 | err = eb_move_to_gpu(eb); |
2018 | if (err) | |
2019 | return err; | |
78382593 | 2020 | |
2889caa9 CW |
2021 | err = i915_switch_context(eb->request); |
2022 | if (err) | |
2023 | return err; | |
78382593 | 2024 | |
650bc635 | 2025 | if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) { |
2889caa9 CW |
2026 | err = i915_reset_gen7_sol_offsets(eb->request); |
2027 | if (err) | |
2028 | return err; | |
78382593 OM |
2029 | } |
2030 | ||
2889caa9 | 2031 | err = eb->engine->emit_bb_start(eb->request, |
650bc635 CW |
2032 | eb->batch->node.start + |
2033 | eb->batch_start_offset, | |
2034 | eb->batch_len, | |
2889caa9 CW |
2035 | eb->batch_flags); |
2036 | if (err) | |
2037 | return err; | |
78382593 | 2038 | |
2f5945bc | 2039 | return 0; |
78382593 OM |
2040 | } |
2041 | ||
a8ebba75 ZY |
2042 | /** |
2043 | * Find one BSD ring to dispatch the corresponding BSD command. | |
c80ff16e | 2044 | * The engine index is returned. |
a8ebba75 | 2045 | */ |
de1add36 | 2046 | static unsigned int |
c80ff16e CW |
2047 | gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, |
2048 | struct drm_file *file) | |
a8ebba75 | 2049 | { |
a8ebba75 ZY |
2050 | struct drm_i915_file_private *file_priv = file->driver_priv; |
2051 | ||
de1add36 | 2052 | /* Check whether the file_priv has already selected one ring. */ |
6f633402 JL |
2053 | if ((int)file_priv->bsd_engine < 0) |
2054 | file_priv->bsd_engine = atomic_fetch_xor(1, | |
2055 | &dev_priv->mm.bsd_engine_dispatch_index); | |
d23db88c | 2056 | |
c80ff16e | 2057 | return file_priv->bsd_engine; |
d23db88c CW |
2058 | } |
2059 | ||
de1add36 TU |
2060 | #define I915_USER_RINGS (4) |
2061 | ||
117897f4 | 2062 | static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { |
de1add36 TU |
2063 | [I915_EXEC_DEFAULT] = RCS, |
2064 | [I915_EXEC_RENDER] = RCS, | |
2065 | [I915_EXEC_BLT] = BCS, | |
2066 | [I915_EXEC_BSD] = VCS, | |
2067 | [I915_EXEC_VEBOX] = VECS | |
2068 | }; | |
2069 | ||
f8ca0c07 DG |
2070 | static struct intel_engine_cs * |
2071 | eb_select_engine(struct drm_i915_private *dev_priv, | |
2072 | struct drm_file *file, | |
2073 | struct drm_i915_gem_execbuffer2 *args) | |
de1add36 TU |
2074 | { |
2075 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
f8ca0c07 | 2076 | struct intel_engine_cs *engine; |
de1add36 TU |
2077 | |
2078 | if (user_ring_id > I915_USER_RINGS) { | |
2079 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
f8ca0c07 | 2080 | return NULL; |
de1add36 TU |
2081 | } |
2082 | ||
2083 | if ((user_ring_id != I915_EXEC_BSD) && | |
2084 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
2085 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
2086 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
f8ca0c07 | 2087 | return NULL; |
de1add36 TU |
2088 | } |
2089 | ||
2090 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
2091 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
2092 | ||
2093 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
c80ff16e | 2094 | bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file); |
de1add36 TU |
2095 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && |
2096 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 2097 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
2098 | bsd_idx--; |
2099 | } else { | |
2100 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
2101 | bsd_idx); | |
f8ca0c07 | 2102 | return NULL; |
de1add36 TU |
2103 | } |
2104 | ||
3b3f1650 | 2105 | engine = dev_priv->engine[_VCS(bsd_idx)]; |
de1add36 | 2106 | } else { |
3b3f1650 | 2107 | engine = dev_priv->engine[user_ring_map[user_ring_id]]; |
de1add36 TU |
2108 | } |
2109 | ||
3b3f1650 | 2110 | if (!engine) { |
de1add36 | 2111 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); |
f8ca0c07 | 2112 | return NULL; |
de1add36 TU |
2113 | } |
2114 | ||
f8ca0c07 | 2115 | return engine; |
de1add36 TU |
2116 | } |
2117 | ||
54cf91dc | 2118 | static int |
650bc635 | 2119 | i915_gem_do_execbuffer(struct drm_device *dev, |
54cf91dc CW |
2120 | struct drm_file *file, |
2121 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 2122 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 2123 | { |
650bc635 | 2124 | struct i915_execbuffer eb; |
fec0445c CW |
2125 | struct dma_fence *in_fence = NULL; |
2126 | struct sync_file *out_fence = NULL; | |
2127 | int out_fence_fd = -1; | |
2889caa9 | 2128 | int err; |
432e58ed | 2129 | |
2889caa9 CW |
2130 | BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & |
2131 | ~__EXEC_OBJECT_UNKNOWN_FLAGS); | |
54cf91dc | 2132 | |
650bc635 CW |
2133 | eb.i915 = to_i915(dev); |
2134 | eb.file = file; | |
2135 | eb.args = args; | |
7dd4f672 | 2136 | if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) |
2889caa9 | 2137 | args->flags |= __EXEC_HAS_RELOC; |
650bc635 | 2138 | eb.exec = exec; |
2889caa9 CW |
2139 | eb.ctx = NULL; |
2140 | eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
2141 | if (USES_FULL_PPGTT(eb.i915)) | |
2142 | eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
650bc635 CW |
2143 | reloc_cache_init(&eb.reloc_cache, eb.i915); |
2144 | ||
2889caa9 | 2145 | eb.buffer_count = args->buffer_count; |
650bc635 CW |
2146 | eb.batch_start_offset = args->batch_start_offset; |
2147 | eb.batch_len = args->batch_len; | |
2148 | ||
2889caa9 | 2149 | eb.batch_flags = 0; |
d7d4eedd | 2150 | if (args->flags & I915_EXEC_SECURE) { |
b3ac9f25 | 2151 | if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) |
d7d4eedd CW |
2152 | return -EPERM; |
2153 | ||
2889caa9 | 2154 | eb.batch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 2155 | } |
b45305fc | 2156 | if (args->flags & I915_EXEC_IS_PINNED) |
2889caa9 | 2157 | eb.batch_flags |= I915_DISPATCH_PINNED; |
54cf91dc | 2158 | |
650bc635 CW |
2159 | eb.engine = eb_select_engine(eb.i915, file, args); |
2160 | if (!eb.engine) | |
54cf91dc | 2161 | return -EINVAL; |
54cf91dc | 2162 | |
a9ed33ca | 2163 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
650bc635 | 2164 | if (!HAS_RESOURCE_STREAMER(eb.i915)) { |
a9ed33ca AJ |
2165 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); |
2166 | return -EINVAL; | |
2167 | } | |
650bc635 | 2168 | if (eb.engine->id != RCS) { |
a9ed33ca | 2169 | DRM_DEBUG("RS is not available on %s\n", |
650bc635 | 2170 | eb.engine->name); |
a9ed33ca AJ |
2171 | return -EINVAL; |
2172 | } | |
2173 | ||
2889caa9 | 2174 | eb.batch_flags |= I915_DISPATCH_RS; |
a9ed33ca AJ |
2175 | } |
2176 | ||
fec0445c CW |
2177 | if (args->flags & I915_EXEC_FENCE_IN) { |
2178 | in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); | |
4a04e371 DCS |
2179 | if (!in_fence) |
2180 | return -EINVAL; | |
fec0445c CW |
2181 | } |
2182 | ||
2183 | if (args->flags & I915_EXEC_FENCE_OUT) { | |
2184 | out_fence_fd = get_unused_fd_flags(O_CLOEXEC); | |
2185 | if (out_fence_fd < 0) { | |
2889caa9 | 2186 | err = out_fence_fd; |
4a04e371 | 2187 | goto err_in_fence; |
fec0445c CW |
2188 | } |
2189 | } | |
2190 | ||
4ec654bf CW |
2191 | err = eb_create(&eb); |
2192 | if (err) | |
2193 | goto err_out_fence; | |
2194 | ||
2195 | GEM_BUG_ON(!eb.lut_size); | |
2889caa9 CW |
2196 | |
2197 | /* | |
2198 | * Take a local wakeref for preparing to dispatch the execbuf as | |
67d97da3 CW |
2199 | * we expect to access the hardware fairly frequently in the |
2200 | * process. Upon first dispatch, we acquire another prolonged | |
2201 | * wakeref that we hold until the GPU has been idle for at least | |
2202 | * 100ms. | |
2203 | */ | |
650bc635 | 2204 | intel_runtime_pm_get(eb.i915); |
2889caa9 CW |
2205 | err = i915_mutex_lock_interruptible(dev); |
2206 | if (err) | |
2207 | goto err_rpm; | |
f65c9168 | 2208 | |
2889caa9 CW |
2209 | err = eb_select_context(&eb); |
2210 | if (unlikely(err)) | |
2211 | goto err_unlock; | |
54cf91dc | 2212 | |
2889caa9 | 2213 | err = eb_relocate(&eb); |
adf27835 | 2214 | if (err) { |
2889caa9 CW |
2215 | /* |
2216 | * If the user expects the execobject.offset and | |
2217 | * reloc.presumed_offset to be an exact match, | |
2218 | * as for using NO_RELOC, then we cannot update | |
2219 | * the execobject.offset until we have completed | |
2220 | * relocation. | |
2221 | */ | |
2222 | args->flags &= ~__EXEC_HAS_RELOC; | |
2889caa9 | 2223 | goto err_vma; |
adf27835 | 2224 | } |
54cf91dc | 2225 | |
2889caa9 | 2226 | if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) { |
ff240199 | 2227 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
2889caa9 CW |
2228 | err = -EINVAL; |
2229 | goto err_vma; | |
54cf91dc | 2230 | } |
650bc635 CW |
2231 | if (eb.batch_start_offset > eb.batch->size || |
2232 | eb.batch_len > eb.batch->size - eb.batch_start_offset) { | |
0b537272 | 2233 | DRM_DEBUG("Attempting to use out-of-bounds batch\n"); |
2889caa9 CW |
2234 | err = -EINVAL; |
2235 | goto err_vma; | |
0b537272 | 2236 | } |
54cf91dc | 2237 | |
650bc635 | 2238 | if (eb.engine->needs_cmd_parser && eb.batch_len) { |
59bfa124 CW |
2239 | struct i915_vma *vma; |
2240 | ||
650bc635 | 2241 | vma = eb_parse(&eb, drm_is_current_master(file)); |
59bfa124 | 2242 | if (IS_ERR(vma)) { |
2889caa9 CW |
2243 | err = PTR_ERR(vma); |
2244 | goto err_vma; | |
78a42377 | 2245 | } |
17cabf57 | 2246 | |
59bfa124 | 2247 | if (vma) { |
c7c7372e RP |
2248 | /* |
2249 | * Batch parsed and accepted: | |
2250 | * | |
2251 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
2252 | * bit from MI_BATCH_BUFFER_START commands issued in | |
2253 | * the dispatch_execbuffer implementations. We | |
2254 | * specifically don't want that set on batches the | |
2255 | * command parser has accepted. | |
2256 | */ | |
2889caa9 | 2257 | eb.batch_flags |= I915_DISPATCH_SECURE; |
650bc635 CW |
2258 | eb.batch_start_offset = 0; |
2259 | eb.batch = vma; | |
c7c7372e | 2260 | } |
351e3db2 BV |
2261 | } |
2262 | ||
650bc635 CW |
2263 | if (eb.batch_len == 0) |
2264 | eb.batch_len = eb.batch->size - eb.batch_start_offset; | |
78a42377 | 2265 | |
2889caa9 CW |
2266 | /* |
2267 | * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure | |
d7d4eedd | 2268 | * batch" bit. Hence we need to pin secure batches into the global gtt. |
28cf5415 | 2269 | * hsw should have this fixed, but bdw mucks it up again. */ |
2889caa9 | 2270 | if (eb.batch_flags & I915_DISPATCH_SECURE) { |
058d88c4 | 2271 | struct i915_vma *vma; |
59bfa124 | 2272 | |
da51a1e7 DV |
2273 | /* |
2274 | * So on first glance it looks freaky that we pin the batch here | |
2275 | * outside of the reservation loop. But: | |
2276 | * - The batch is already pinned into the relevant ppgtt, so we | |
2277 | * already have the backing storage fully allocated. | |
2278 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 2279 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
2280 | * fitting due to fragmentation. |
2281 | * So this is actually safe. | |
2282 | */ | |
2889caa9 | 2283 | vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0); |
058d88c4 | 2284 | if (IS_ERR(vma)) { |
2889caa9 CW |
2285 | err = PTR_ERR(vma); |
2286 | goto err_vma; | |
058d88c4 | 2287 | } |
d7d4eedd | 2288 | |
650bc635 | 2289 | eb.batch = vma; |
59bfa124 | 2290 | } |
d7d4eedd | 2291 | |
7dd4f672 CW |
2292 | /* All GPU relocation batches must be submitted prior to the user rq */ |
2293 | GEM_BUG_ON(eb.reloc_cache.rq); | |
2294 | ||
0c8dac88 | 2295 | /* Allocate a request for this batch buffer nice and early. */ |
650bc635 CW |
2296 | eb.request = i915_gem_request_alloc(eb.engine, eb.ctx); |
2297 | if (IS_ERR(eb.request)) { | |
2889caa9 | 2298 | err = PTR_ERR(eb.request); |
0c8dac88 | 2299 | goto err_batch_unpin; |
26827088 | 2300 | } |
0c8dac88 | 2301 | |
fec0445c | 2302 | if (in_fence) { |
2889caa9 CW |
2303 | err = i915_gem_request_await_dma_fence(eb.request, in_fence); |
2304 | if (err < 0) | |
fec0445c CW |
2305 | goto err_request; |
2306 | } | |
2307 | ||
2308 | if (out_fence_fd != -1) { | |
650bc635 | 2309 | out_fence = sync_file_create(&eb.request->fence); |
fec0445c | 2310 | if (!out_fence) { |
2889caa9 | 2311 | err = -ENOMEM; |
fec0445c CW |
2312 | goto err_request; |
2313 | } | |
2314 | } | |
2315 | ||
2889caa9 CW |
2316 | /* |
2317 | * Whilst this request exists, batch_obj will be on the | |
17f298cf CW |
2318 | * active_list, and so will hold the active reference. Only when this |
2319 | * request is retired will the the batch_obj be moved onto the | |
2320 | * inactive_list and lose its active reference. Hence we do not need | |
2321 | * to explicitly hold another reference here. | |
2322 | */ | |
650bc635 | 2323 | eb.request->batch = eb.batch; |
5f19e2bf | 2324 | |
2889caa9 CW |
2325 | trace_i915_gem_request_queue(eb.request, eb.batch_flags); |
2326 | err = eb_submit(&eb); | |
aa9b7810 | 2327 | err_request: |
2889caa9 | 2328 | __i915_add_request(eb.request, err == 0); |
650bc635 | 2329 | add_to_client(eb.request, file); |
c8659efa | 2330 | |
fec0445c | 2331 | if (out_fence) { |
2889caa9 | 2332 | if (err == 0) { |
fec0445c CW |
2333 | fd_install(out_fence_fd, out_fence->file); |
2334 | args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */ | |
2335 | args->rsvd2 |= (u64)out_fence_fd << 32; | |
2336 | out_fence_fd = -1; | |
2337 | } else { | |
2338 | fput(out_fence->file); | |
2339 | } | |
2340 | } | |
54cf91dc | 2341 | |
0c8dac88 | 2342 | err_batch_unpin: |
2889caa9 | 2343 | if (eb.batch_flags & I915_DISPATCH_SECURE) |
650bc635 | 2344 | i915_vma_unpin(eb.batch); |
2889caa9 CW |
2345 | err_vma: |
2346 | if (eb.exec) | |
2347 | eb_release_vmas(&eb); | |
2348 | i915_gem_context_put(eb.ctx); | |
2349 | err_unlock: | |
54cf91dc | 2350 | mutex_unlock(&dev->struct_mutex); |
2889caa9 | 2351 | err_rpm: |
650bc635 | 2352 | intel_runtime_pm_put(eb.i915); |
2889caa9 | 2353 | eb_destroy(&eb); |
4ec654bf | 2354 | err_out_fence: |
fec0445c CW |
2355 | if (out_fence_fd != -1) |
2356 | put_unused_fd(out_fence_fd); | |
4a04e371 | 2357 | err_in_fence: |
fec0445c | 2358 | dma_fence_put(in_fence); |
2889caa9 | 2359 | return err; |
54cf91dc CW |
2360 | } |
2361 | ||
2362 | /* | |
2363 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
2364 | * list array and passes it to the real function. | |
2365 | */ | |
2366 | int | |
2367 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
2368 | struct drm_file *file) | |
2369 | { | |
2889caa9 | 2370 | const size_t sz = sizeof(struct drm_i915_gem_exec_object2); |
54cf91dc CW |
2371 | struct drm_i915_gem_execbuffer *args = data; |
2372 | struct drm_i915_gem_execbuffer2 exec2; | |
2373 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
2374 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
2889caa9 CW |
2375 | unsigned int i; |
2376 | int err; | |
54cf91dc | 2377 | |
2889caa9 CW |
2378 | if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) { |
2379 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); | |
54cf91dc CW |
2380 | return -EINVAL; |
2381 | } | |
2382 | ||
2889caa9 CW |
2383 | exec2.buffers_ptr = args->buffers_ptr; |
2384 | exec2.buffer_count = args->buffer_count; | |
2385 | exec2.batch_start_offset = args->batch_start_offset; | |
2386 | exec2.batch_len = args->batch_len; | |
2387 | exec2.DR1 = args->DR1; | |
2388 | exec2.DR4 = args->DR4; | |
2389 | exec2.num_cliprects = args->num_cliprects; | |
2390 | exec2.cliprects_ptr = args->cliprects_ptr; | |
2391 | exec2.flags = I915_EXEC_RENDER; | |
2392 | i915_execbuffer2_set_context_id(exec2, 0); | |
2393 | ||
2394 | if (!i915_gem_check_execbuffer(&exec2)) | |
2395 | return -EINVAL; | |
2396 | ||
54cf91dc | 2397 | /* Copy in the exec list from userland */ |
2889caa9 CW |
2398 | exec_list = kvmalloc_array(args->buffer_count, sizeof(*exec_list), |
2399 | __GFP_NOWARN | GFP_TEMPORARY); | |
2400 | exec2_list = kvmalloc_array(args->buffer_count + 1, sz, | |
2401 | __GFP_NOWARN | GFP_TEMPORARY); | |
54cf91dc | 2402 | if (exec_list == NULL || exec2_list == NULL) { |
ff240199 | 2403 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc | 2404 | args->buffer_count); |
2098105e MH |
2405 | kvfree(exec_list); |
2406 | kvfree(exec2_list); | |
54cf91dc CW |
2407 | return -ENOMEM; |
2408 | } | |
2889caa9 | 2409 | err = copy_from_user(exec_list, |
3ed605bc | 2410 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc | 2411 | sizeof(*exec_list) * args->buffer_count); |
2889caa9 | 2412 | if (err) { |
ff240199 | 2413 | DRM_DEBUG("copy %d exec entries failed %d\n", |
2889caa9 | 2414 | args->buffer_count, err); |
2098105e MH |
2415 | kvfree(exec_list); |
2416 | kvfree(exec2_list); | |
54cf91dc CW |
2417 | return -EFAULT; |
2418 | } | |
2419 | ||
2420 | for (i = 0; i < args->buffer_count; i++) { | |
2421 | exec2_list[i].handle = exec_list[i].handle; | |
2422 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
2423 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
2424 | exec2_list[i].alignment = exec_list[i].alignment; | |
2425 | exec2_list[i].offset = exec_list[i].offset; | |
f0836b72 | 2426 | if (INTEL_GEN(to_i915(dev)) < 4) |
54cf91dc CW |
2427 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
2428 | else | |
2429 | exec2_list[i].flags = 0; | |
2430 | } | |
2431 | ||
2889caa9 CW |
2432 | err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list); |
2433 | if (exec2.flags & __EXEC_HAS_RELOC) { | |
9aab8bff | 2434 | struct drm_i915_gem_exec_object __user *user_exec_list = |
3ed605bc | 2435 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff | 2436 | |
54cf91dc | 2437 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 2438 | for (i = 0; i < args->buffer_count; i++) { |
2889caa9 CW |
2439 | if (!(exec2_list[i].offset & UPDATE)) |
2440 | continue; | |
2441 | ||
934acce3 | 2442 | exec2_list[i].offset = |
2889caa9 CW |
2443 | gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK); |
2444 | exec2_list[i].offset &= PIN_OFFSET_MASK; | |
2445 | if (__copy_to_user(&user_exec_list[i].offset, | |
2446 | &exec2_list[i].offset, | |
2447 | sizeof(user_exec_list[i].offset))) | |
9aab8bff | 2448 | break; |
54cf91dc CW |
2449 | } |
2450 | } | |
2451 | ||
2098105e MH |
2452 | kvfree(exec_list); |
2453 | kvfree(exec2_list); | |
2889caa9 | 2454 | return err; |
54cf91dc CW |
2455 | } |
2456 | ||
2457 | int | |
2458 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
2459 | struct drm_file *file) | |
2460 | { | |
2889caa9 | 2461 | const size_t sz = sizeof(struct drm_i915_gem_exec_object2); |
54cf91dc | 2462 | struct drm_i915_gem_execbuffer2 *args = data; |
2889caa9 CW |
2463 | struct drm_i915_gem_exec_object2 *exec2_list; |
2464 | int err; | |
54cf91dc | 2465 | |
2889caa9 | 2466 | if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) { |
ff240199 | 2467 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
2468 | return -EINVAL; |
2469 | } | |
2470 | ||
2889caa9 CW |
2471 | if (!i915_gem_check_execbuffer(args)) |
2472 | return -EINVAL; | |
2473 | ||
2474 | /* Allocate an extra slot for use by the command parser */ | |
2475 | exec2_list = kvmalloc_array(args->buffer_count + 1, sz, | |
2476 | __GFP_NOWARN | GFP_TEMPORARY); | |
54cf91dc | 2477 | if (exec2_list == NULL) { |
ff240199 | 2478 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
2479 | args->buffer_count); |
2480 | return -ENOMEM; | |
2481 | } | |
2889caa9 CW |
2482 | if (copy_from_user(exec2_list, |
2483 | u64_to_user_ptr(args->buffers_ptr), | |
2484 | sizeof(*exec2_list) * args->buffer_count)) { | |
2485 | DRM_DEBUG("copy %d exec entries failed\n", args->buffer_count); | |
2098105e | 2486 | kvfree(exec2_list); |
54cf91dc CW |
2487 | return -EFAULT; |
2488 | } | |
2489 | ||
2889caa9 CW |
2490 | err = i915_gem_do_execbuffer(dev, file, args, exec2_list); |
2491 | ||
2492 | /* | |
2493 | * Now that we have begun execution of the batchbuffer, we ignore | |
2494 | * any new error after this point. Also given that we have already | |
2495 | * updated the associated relocations, we try to write out the current | |
2496 | * object locations irrespective of any error. | |
2497 | */ | |
2498 | if (args->flags & __EXEC_HAS_RELOC) { | |
d593d992 | 2499 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
2889caa9 CW |
2500 | u64_to_user_ptr(args->buffers_ptr); |
2501 | unsigned int i; | |
9aab8bff | 2502 | |
2889caa9 CW |
2503 | /* Copy the new buffer offsets back to the user's exec list. */ |
2504 | user_access_begin(); | |
9aab8bff | 2505 | for (i = 0; i < args->buffer_count; i++) { |
2889caa9 CW |
2506 | if (!(exec2_list[i].offset & UPDATE)) |
2507 | continue; | |
2508 | ||
934acce3 | 2509 | exec2_list[i].offset = |
2889caa9 CW |
2510 | gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK); |
2511 | unsafe_put_user(exec2_list[i].offset, | |
2512 | &user_exec_list[i].offset, | |
2513 | end_user); | |
54cf91dc | 2514 | } |
2889caa9 CW |
2515 | end_user: |
2516 | user_access_end(); | |
54cf91dc CW |
2517 | } |
2518 | ||
2889caa9 | 2519 | args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS; |
2098105e | 2520 | kvfree(exec2_list); |
2889caa9 | 2521 | return err; |
54cf91dc | 2522 | } |