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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | #include "i915_trace.h" | |
34 | #include "intel_drv.h" | |
35 | ||
36 | struct change_domains { | |
37 | uint32_t invalidate_domains; | |
38 | uint32_t flush_domains; | |
39 | uint32_t flush_rings; | |
40 | }; | |
41 | ||
42 | /* | |
43 | * Set the next domain for the specified object. This | |
44 | * may not actually perform the necessary flushing/invaliding though, | |
45 | * as that may want to be batched with other set_domain operations | |
46 | * | |
47 | * This is (we hope) the only really tricky part of gem. The goal | |
48 | * is fairly simple -- track which caches hold bits of the object | |
49 | * and make sure they remain coherent. A few concrete examples may | |
50 | * help to explain how it works. For shorthand, we use the notation | |
51 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
52 | * a pair of read and write domain masks. | |
53 | * | |
54 | * Case 1: the batch buffer | |
55 | * | |
56 | * 1. Allocated | |
57 | * 2. Written by CPU | |
58 | * 3. Mapped to GTT | |
59 | * 4. Read by GPU | |
60 | * 5. Unmapped from GTT | |
61 | * 6. Freed | |
62 | * | |
63 | * Let's take these a step at a time | |
64 | * | |
65 | * 1. Allocated | |
66 | * Pages allocated from the kernel may still have | |
67 | * cache contents, so we set them to (CPU, CPU) always. | |
68 | * 2. Written by CPU (using pwrite) | |
69 | * The pwrite function calls set_domain (CPU, CPU) and | |
70 | * this function does nothing (as nothing changes) | |
71 | * 3. Mapped by GTT | |
72 | * This function asserts that the object is not | |
73 | * currently in any GPU-based read or write domains | |
74 | * 4. Read by GPU | |
75 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
76 | * As write_domain is zero, this function adds in the | |
77 | * current read domains (CPU+COMMAND, 0). | |
78 | * flush_domains is set to CPU. | |
79 | * invalidate_domains is set to COMMAND | |
80 | * clflush is run to get data out of the CPU caches | |
81 | * then i915_dev_set_domain calls i915_gem_flush to | |
82 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
83 | * 5. Unmapped from GTT | |
84 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
85 | * flush_domains and invalidate_domains end up both zero | |
86 | * so no flushing/invalidating happens | |
87 | * 6. Freed | |
88 | * yay, done | |
89 | * | |
90 | * Case 2: The shared render buffer | |
91 | * | |
92 | * 1. Allocated | |
93 | * 2. Mapped to GTT | |
94 | * 3. Read/written by GPU | |
95 | * 4. set_domain to (CPU,CPU) | |
96 | * 5. Read/written by CPU | |
97 | * 6. Read/written by GPU | |
98 | * | |
99 | * 1. Allocated | |
100 | * Same as last example, (CPU, CPU) | |
101 | * 2. Mapped to GTT | |
102 | * Nothing changes (assertions find that it is not in the GPU) | |
103 | * 3. Read/written by GPU | |
104 | * execbuffer calls set_domain (RENDER, RENDER) | |
105 | * flush_domains gets CPU | |
106 | * invalidate_domains gets GPU | |
107 | * clflush (obj) | |
108 | * MI_FLUSH and drm_agp_chipset_flush | |
109 | * 4. set_domain (CPU, CPU) | |
110 | * flush_domains gets GPU | |
111 | * invalidate_domains gets CPU | |
112 | * wait_rendering (obj) to make sure all drawing is complete. | |
113 | * This will include an MI_FLUSH to get the data from GPU | |
114 | * to memory | |
115 | * clflush (obj) to invalidate the CPU cache | |
116 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
117 | * 5. Read/written by CPU | |
118 | * cache lines are loaded and dirtied | |
119 | * 6. Read written by GPU | |
120 | * Same as last GPU access | |
121 | * | |
122 | * Case 3: The constant buffer | |
123 | * | |
124 | * 1. Allocated | |
125 | * 2. Written by CPU | |
126 | * 3. Read by GPU | |
127 | * 4. Updated (written) by CPU again | |
128 | * 5. Read by GPU | |
129 | * | |
130 | * 1. Allocated | |
131 | * (CPU, CPU) | |
132 | * 2. Written by CPU | |
133 | * (CPU, CPU) | |
134 | * 3. Read by GPU | |
135 | * (CPU+RENDER, 0) | |
136 | * flush_domains = CPU | |
137 | * invalidate_domains = RENDER | |
138 | * clflush (obj) | |
139 | * MI_FLUSH | |
140 | * drm_agp_chipset_flush | |
141 | * 4. Updated (written) by CPU again | |
142 | * (CPU, CPU) | |
143 | * flush_domains = 0 (no previous write domain) | |
144 | * invalidate_domains = 0 (no new read domains) | |
145 | * 5. Read by GPU | |
146 | * (CPU+RENDER, 0) | |
147 | * flush_domains = CPU | |
148 | * invalidate_domains = RENDER | |
149 | * clflush (obj) | |
150 | * MI_FLUSH | |
151 | * drm_agp_chipset_flush | |
152 | */ | |
153 | static void | |
154 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, | |
155 | struct intel_ring_buffer *ring, | |
156 | struct change_domains *cd) | |
157 | { | |
158 | uint32_t invalidate_domains = 0, flush_domains = 0; | |
159 | ||
160 | /* | |
161 | * If the object isn't moving to a new write domain, | |
162 | * let the object stay in multiple read domains | |
163 | */ | |
164 | if (obj->base.pending_write_domain == 0) | |
165 | obj->base.pending_read_domains |= obj->base.read_domains; | |
166 | ||
167 | /* | |
168 | * Flush the current write domain if | |
169 | * the new read domains don't match. Invalidate | |
170 | * any read domains which differ from the old | |
171 | * write domain | |
172 | */ | |
173 | if (obj->base.write_domain && | |
174 | (((obj->base.write_domain != obj->base.pending_read_domains || | |
175 | obj->ring != ring)) || | |
176 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { | |
177 | flush_domains |= obj->base.write_domain; | |
178 | invalidate_domains |= | |
179 | obj->base.pending_read_domains & ~obj->base.write_domain; | |
180 | } | |
181 | /* | |
182 | * Invalidate any read caches which may have | |
183 | * stale data. That is, any new read domains. | |
184 | */ | |
185 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; | |
186 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) | |
187 | i915_gem_clflush_object(obj); | |
188 | ||
189 | /* blow away mappings if mapped through GTT */ | |
190 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) | |
191 | i915_gem_release_mmap(obj); | |
192 | ||
193 | /* The actual obj->write_domain will be updated with | |
194 | * pending_write_domain after we emit the accumulated flush for all | |
195 | * of our domain changes in execbuffers (which clears objects' | |
196 | * write_domains). So if we have a current write domain that we | |
197 | * aren't changing, set pending_write_domain to that. | |
198 | */ | |
199 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) | |
200 | obj->base.pending_write_domain = obj->base.write_domain; | |
201 | ||
202 | cd->invalidate_domains |= invalidate_domains; | |
203 | cd->flush_domains |= flush_domains; | |
204 | if (flush_domains & I915_GEM_GPU_DOMAINS) | |
205 | cd->flush_rings |= obj->ring->id; | |
206 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) | |
207 | cd->flush_rings |= ring->id; | |
208 | } | |
209 | ||
210 | static int | |
211 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
212 | struct drm_file *file_priv, | |
213 | struct drm_i915_gem_exec_object2 *entry, | |
214 | struct drm_i915_gem_relocation_entry *reloc) | |
215 | { | |
216 | struct drm_device *dev = obj->base.dev; | |
217 | struct drm_gem_object *target_obj; | |
218 | uint32_t target_offset; | |
219 | int ret = -EINVAL; | |
220 | ||
221 | target_obj = drm_gem_object_lookup(dev, file_priv, | |
222 | reloc->target_handle); | |
223 | if (target_obj == NULL) | |
224 | return -ENOENT; | |
225 | ||
226 | target_offset = to_intel_bo(target_obj)->gtt_offset; | |
227 | ||
228 | #if WATCH_RELOC | |
229 | DRM_INFO("%s: obj %p offset %08x target %d " | |
230 | "read %08x write %08x gtt %08x " | |
231 | "presumed %08x delta %08x\n", | |
232 | __func__, | |
233 | obj, | |
234 | (int) reloc->offset, | |
235 | (int) reloc->target_handle, | |
236 | (int) reloc->read_domains, | |
237 | (int) reloc->write_domain, | |
238 | (int) target_offset, | |
239 | (int) reloc->presumed_offset, | |
240 | reloc->delta); | |
241 | #endif | |
242 | ||
243 | /* The target buffer should have appeared before us in the | |
244 | * exec_object list, so it should have a GTT space bound by now. | |
245 | */ | |
246 | if (target_offset == 0) { | |
247 | DRM_ERROR("No GTT space found for object %d\n", | |
248 | reloc->target_handle); | |
249 | goto err; | |
250 | } | |
251 | ||
252 | /* Validate that the target is in a valid r/w GPU domain */ | |
253 | if (reloc->write_domain & (reloc->write_domain - 1)) { | |
254 | DRM_ERROR("reloc with multiple write domains: " | |
255 | "obj %p target %d offset %d " | |
256 | "read %08x write %08x", | |
257 | obj, reloc->target_handle, | |
258 | (int) reloc->offset, | |
259 | reloc->read_domains, | |
260 | reloc->write_domain); | |
261 | goto err; | |
262 | } | |
263 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || | |
264 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
265 | DRM_ERROR("reloc with read/write CPU domains: " | |
266 | "obj %p target %d offset %d " | |
267 | "read %08x write %08x", | |
268 | obj, reloc->target_handle, | |
269 | (int) reloc->offset, | |
270 | reloc->read_domains, | |
271 | reloc->write_domain); | |
272 | goto err; | |
273 | } | |
274 | if (reloc->write_domain && target_obj->pending_write_domain && | |
275 | reloc->write_domain != target_obj->pending_write_domain) { | |
276 | DRM_ERROR("Write domain conflict: " | |
277 | "obj %p target %d offset %d " | |
278 | "new %08x old %08x\n", | |
279 | obj, reloc->target_handle, | |
280 | (int) reloc->offset, | |
281 | reloc->write_domain, | |
282 | target_obj->pending_write_domain); | |
283 | goto err; | |
284 | } | |
285 | ||
286 | target_obj->pending_read_domains |= reloc->read_domains; | |
287 | target_obj->pending_write_domain |= reloc->write_domain; | |
288 | ||
289 | /* If the relocation already has the right value in it, no | |
290 | * more work needs to be done. | |
291 | */ | |
292 | if (target_offset == reloc->presumed_offset) | |
293 | goto out; | |
294 | ||
295 | /* Check that the relocation address is valid... */ | |
296 | if (reloc->offset > obj->base.size - 4) { | |
297 | DRM_ERROR("Relocation beyond object bounds: " | |
298 | "obj %p target %d offset %d size %d.\n", | |
299 | obj, reloc->target_handle, | |
300 | (int) reloc->offset, | |
301 | (int) obj->base.size); | |
302 | goto err; | |
303 | } | |
304 | if (reloc->offset & 3) { | |
305 | DRM_ERROR("Relocation not 4-byte aligned: " | |
306 | "obj %p target %d offset %d.\n", | |
307 | obj, reloc->target_handle, | |
308 | (int) reloc->offset); | |
309 | goto err; | |
310 | } | |
311 | ||
312 | /* and points to somewhere within the target object. */ | |
313 | if (reloc->delta >= target_obj->size) { | |
314 | DRM_ERROR("Relocation beyond target object bounds: " | |
315 | "obj %p target %d delta %d size %d.\n", | |
316 | obj, reloc->target_handle, | |
317 | (int) reloc->delta, | |
318 | (int) target_obj->size); | |
319 | goto err; | |
320 | } | |
321 | ||
322 | reloc->delta += target_offset; | |
323 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
324 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; | |
325 | char *vaddr; | |
326 | ||
327 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); | |
328 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
329 | kunmap_atomic(vaddr); | |
330 | } else { | |
331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
332 | uint32_t __iomem *reloc_entry; | |
333 | void __iomem *reloc_page; | |
334 | ||
335 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
336 | if (ret) | |
337 | goto err; | |
338 | ||
339 | /* Map the page containing the relocation we're going to perform. */ | |
340 | reloc->offset += obj->gtt_offset; | |
341 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
342 | reloc->offset & PAGE_MASK); | |
343 | reloc_entry = (uint32_t __iomem *) | |
344 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
345 | iowrite32(reloc->delta, reloc_entry); | |
346 | io_mapping_unmap_atomic(reloc_page); | |
347 | } | |
348 | ||
349 | /* and update the user's relocation entry */ | |
350 | reloc->presumed_offset = target_offset; | |
351 | ||
352 | out: | |
353 | ret = 0; | |
354 | err: | |
355 | drm_gem_object_unreference(target_obj); | |
356 | return ret; | |
357 | } | |
358 | ||
359 | static int | |
360 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
361 | struct drm_file *file_priv, | |
362 | struct drm_i915_gem_exec_object2 *entry) | |
363 | { | |
364 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
365 | int i, ret; | |
366 | ||
367 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
368 | for (i = 0; i < entry->relocation_count; i++) { | |
369 | struct drm_i915_gem_relocation_entry reloc; | |
370 | ||
371 | if (__copy_from_user_inatomic(&reloc, | |
372 | user_relocs+i, | |
373 | sizeof(reloc))) | |
374 | return -EFAULT; | |
375 | ||
376 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &reloc); | |
377 | if (ret) | |
378 | return ret; | |
379 | ||
380 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
381 | &reloc.presumed_offset, | |
382 | sizeof(reloc.presumed_offset))) | |
383 | return -EFAULT; | |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static int | |
390 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
391 | struct drm_file *file_priv, | |
392 | struct drm_i915_gem_exec_object2 *entry, | |
393 | struct drm_i915_gem_relocation_entry *relocs) | |
394 | { | |
395 | int i, ret; | |
396 | ||
397 | for (i = 0; i < entry->relocation_count; i++) { | |
398 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &relocs[i]); | |
399 | if (ret) | |
400 | return ret; | |
401 | } | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | static int | |
407 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
408 | struct drm_file *file, | |
432e58ed CW |
409 | struct list_head *objects, |
410 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc | 411 | { |
432e58ed CW |
412 | struct drm_i915_gem_object *obj; |
413 | int ret; | |
54cf91dc | 414 | |
432e58ed | 415 | list_for_each_entry(obj, objects, exec_list) { |
54cf91dc CW |
416 | obj->base.pending_read_domains = 0; |
417 | obj->base.pending_write_domain = 0; | |
432e58ed | 418 | ret = i915_gem_execbuffer_relocate_object(obj, file, exec++); |
54cf91dc CW |
419 | if (ret) |
420 | return ret; | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static int | |
d9e86c0e | 427 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 428 | struct drm_file *file, |
432e58ed CW |
429 | struct list_head *objects, |
430 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc | 431 | { |
432e58ed CW |
432 | struct drm_i915_gem_object *obj; |
433 | struct drm_i915_gem_exec_object2 *entry; | |
434 | int ret, retry; | |
54cf91dc CW |
435 | |
436 | /* Attempt to pin all of the buffers into the GTT. | |
437 | * This is done in 3 phases: | |
438 | * | |
439 | * 1a. Unbind all objects that do not match the GTT constraints for | |
440 | * the execbuffer (fenceable, mappable, alignment etc). | |
441 | * 1b. Increment pin count for already bound objects. | |
442 | * 2. Bind new objects. | |
443 | * 3. Decrement pin count. | |
444 | * | |
445 | * This avoid unnecessary unbinding of later objects in order to makr | |
446 | * room for the earlier objects *unless* we need to defragment. | |
447 | */ | |
448 | retry = 0; | |
449 | do { | |
450 | ret = 0; | |
451 | ||
452 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed CW |
453 | entry = exec; |
454 | list_for_each_entry(obj, objects, exec_list) { | |
54cf91dc CW |
455 | bool need_fence, need_mappable; |
456 | ||
432e58ed CW |
457 | if (!obj->gtt_space) { |
458 | entry++; | |
54cf91dc | 459 | continue; |
432e58ed | 460 | } |
54cf91dc CW |
461 | |
462 | need_fence = | |
463 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
464 | obj->tiling_mode != I915_TILING_NONE; | |
465 | need_mappable = | |
466 | entry->relocation_count ? true : need_fence; | |
467 | ||
468 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
469 | (need_mappable && !obj->map_and_fenceable)) | |
470 | ret = i915_gem_object_unbind(obj); | |
471 | else | |
472 | ret = i915_gem_object_pin(obj, | |
473 | entry->alignment, | |
474 | need_mappable); | |
432e58ed | 475 | if (ret) |
54cf91dc | 476 | goto err; |
432e58ed CW |
477 | |
478 | entry++; | |
54cf91dc CW |
479 | } |
480 | ||
481 | /* Bind fresh objects */ | |
432e58ed CW |
482 | entry = exec; |
483 | list_for_each_entry(obj, objects, exec_list) { | |
54cf91dc CW |
484 | bool need_fence; |
485 | ||
486 | need_fence = | |
487 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
488 | obj->tiling_mode != I915_TILING_NONE; | |
489 | ||
490 | if (!obj->gtt_space) { | |
491 | bool need_mappable = | |
492 | entry->relocation_count ? true : need_fence; | |
493 | ||
494 | ret = i915_gem_object_pin(obj, | |
495 | entry->alignment, | |
496 | need_mappable); | |
497 | if (ret) | |
498 | break; | |
499 | } | |
500 | ||
501 | if (need_fence) { | |
d9e86c0e CW |
502 | ret = i915_gem_object_get_fence(obj, ring, 1); |
503 | if (ret) | |
504 | break; | |
505 | } else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
506 | obj->tiling_mode == I915_TILING_NONE) { | |
507 | /* XXX pipelined! */ | |
508 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc CW |
509 | if (ret) |
510 | break; | |
54cf91dc | 511 | } |
432e58ed | 512 | obj->pending_fenced_gpu_access = need_fence; |
54cf91dc CW |
513 | |
514 | entry->offset = obj->gtt_offset; | |
432e58ed | 515 | entry++; |
54cf91dc CW |
516 | } |
517 | ||
432e58ed CW |
518 | /* Decrement pin count for bound objects */ |
519 | list_for_each_entry(obj, objects, exec_list) { | |
54cf91dc CW |
520 | if (obj->gtt_space) |
521 | i915_gem_object_unpin(obj); | |
522 | } | |
523 | ||
524 | if (ret != -ENOSPC || retry > 1) | |
525 | return ret; | |
526 | ||
527 | /* First attempt, just clear anything that is purgeable. | |
528 | * Second attempt, clear the entire GTT. | |
529 | */ | |
d9e86c0e | 530 | ret = i915_gem_evict_everything(ring->dev, retry == 0); |
54cf91dc CW |
531 | if (ret) |
532 | return ret; | |
533 | ||
534 | retry++; | |
535 | } while (1); | |
432e58ed CW |
536 | |
537 | err: | |
602606a4 CW |
538 | obj = list_entry(obj->exec_list.prev, |
539 | struct drm_i915_gem_object, | |
540 | exec_list); | |
432e58ed CW |
541 | while (objects != &obj->exec_list) { |
542 | if (obj->gtt_space) | |
543 | i915_gem_object_unpin(obj); | |
544 | ||
545 | obj = list_entry(obj->exec_list.prev, | |
546 | struct drm_i915_gem_object, | |
547 | exec_list); | |
548 | } | |
549 | ||
550 | return ret; | |
54cf91dc CW |
551 | } |
552 | ||
553 | static int | |
554 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
555 | struct drm_file *file, | |
d9e86c0e | 556 | struct intel_ring_buffer *ring, |
432e58ed CW |
557 | struct list_head *objects, |
558 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
559 | int count) |
560 | { | |
561 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 562 | struct drm_i915_gem_object *obj; |
54cf91dc CW |
563 | int i, total, ret; |
564 | ||
54cf91dc CW |
565 | mutex_unlock(&dev->struct_mutex); |
566 | ||
567 | total = 0; | |
568 | for (i = 0; i < count; i++) | |
432e58ed | 569 | total += exec[i].relocation_count; |
54cf91dc CW |
570 | |
571 | reloc = drm_malloc_ab(total, sizeof(*reloc)); | |
572 | if (reloc == NULL) { | |
573 | mutex_lock(&dev->struct_mutex); | |
574 | return -ENOMEM; | |
575 | } | |
576 | ||
577 | total = 0; | |
578 | for (i = 0; i < count; i++) { | |
579 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
580 | ||
432e58ed | 581 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
582 | |
583 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 584 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
585 | ret = -EFAULT; |
586 | mutex_lock(&dev->struct_mutex); | |
587 | goto err; | |
588 | } | |
589 | ||
432e58ed | 590 | total += exec[i].relocation_count; |
54cf91dc CW |
591 | } |
592 | ||
593 | ret = i915_mutex_lock_interruptible(dev); | |
594 | if (ret) { | |
595 | mutex_lock(&dev->struct_mutex); | |
596 | goto err; | |
597 | } | |
598 | ||
d9e86c0e | 599 | ret = i915_gem_execbuffer_reserve(ring, file, objects, exec); |
54cf91dc CW |
600 | if (ret) |
601 | goto err; | |
602 | ||
603 | total = 0; | |
432e58ed | 604 | list_for_each_entry(obj, objects, exec_list) { |
54cf91dc CW |
605 | obj->base.pending_read_domains = 0; |
606 | obj->base.pending_write_domain = 0; | |
607 | ret = i915_gem_execbuffer_relocate_object_slow(obj, file, | |
432e58ed | 608 | exec, |
54cf91dc CW |
609 | reloc + total); |
610 | if (ret) | |
611 | goto err; | |
612 | ||
432e58ed CW |
613 | total += exec->relocation_count; |
614 | exec++; | |
54cf91dc CW |
615 | } |
616 | ||
617 | /* Leave the user relocations as are, this is the painfully slow path, | |
618 | * and we want to avoid the complication of dropping the lock whilst | |
619 | * having buffers reserved in the aperture and so causing spurious | |
620 | * ENOSPC for random operations. | |
621 | */ | |
622 | ||
623 | err: | |
624 | drm_free_large(reloc); | |
625 | return ret; | |
626 | } | |
627 | ||
628 | static void | |
629 | i915_gem_execbuffer_flush(struct drm_device *dev, | |
630 | uint32_t invalidate_domains, | |
631 | uint32_t flush_domains, | |
632 | uint32_t flush_rings) | |
633 | { | |
634 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 635 | int i; |
54cf91dc CW |
636 | |
637 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
638 | intel_gtt_chipset_flush(); | |
639 | ||
640 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { | |
1ec14ad3 CW |
641 | for (i = 0; i < I915_NUM_RINGS; i++) |
642 | if (flush_rings & (1 << i)) | |
643 | i915_gem_flush_ring(dev, &dev_priv->ring[i], | |
644 | invalidate_domains, | |
645 | flush_domains); | |
54cf91dc CW |
646 | } |
647 | } | |
648 | ||
1ec14ad3 CW |
649 | static int |
650 | i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj, | |
651 | struct intel_ring_buffer *to) | |
652 | { | |
653 | struct intel_ring_buffer *from = obj->ring; | |
654 | u32 seqno; | |
655 | int ret, idx; | |
656 | ||
657 | if (from == NULL || to == from) | |
658 | return 0; | |
659 | ||
660 | if (INTEL_INFO(obj->base.dev)->gen < 6) | |
661 | return i915_gem_object_wait_rendering(obj, true); | |
662 | ||
663 | idx = intel_ring_sync_index(from, to); | |
664 | ||
665 | seqno = obj->last_rendering_seqno; | |
666 | if (seqno <= from->sync_seqno[idx]) | |
667 | return 0; | |
668 | ||
669 | if (seqno == from->outstanding_lazy_request) { | |
670 | struct drm_i915_gem_request *request; | |
671 | ||
672 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
673 | if (request == NULL) | |
674 | return -ENOMEM; | |
675 | ||
676 | ret = i915_add_request(obj->base.dev, NULL, request, from); | |
677 | if (ret) { | |
678 | kfree(request); | |
679 | return ret; | |
680 | } | |
681 | ||
682 | seqno = request->seqno; | |
683 | } | |
684 | ||
685 | from->sync_seqno[idx] = seqno; | |
686 | return intel_ring_sync(to, from, seqno - 1); | |
687 | } | |
54cf91dc CW |
688 | |
689 | static int | |
432e58ed CW |
690 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
691 | struct list_head *objects) | |
54cf91dc | 692 | { |
432e58ed | 693 | struct drm_i915_gem_object *obj; |
54cf91dc | 694 | struct change_domains cd; |
432e58ed | 695 | int ret; |
54cf91dc CW |
696 | |
697 | cd.invalidate_domains = 0; | |
698 | cd.flush_domains = 0; | |
699 | cd.flush_rings = 0; | |
432e58ed CW |
700 | list_for_each_entry(obj, objects, exec_list) |
701 | i915_gem_object_set_to_gpu_domain(obj, ring, &cd); | |
54cf91dc CW |
702 | |
703 | if (cd.invalidate_domains | cd.flush_domains) { | |
704 | #if WATCH_EXEC | |
705 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
706 | __func__, | |
707 | cd.invalidate_domains, | |
708 | cd.flush_domains); | |
709 | #endif | |
432e58ed | 710 | i915_gem_execbuffer_flush(ring->dev, |
54cf91dc CW |
711 | cd.invalidate_domains, |
712 | cd.flush_domains, | |
713 | cd.flush_rings); | |
714 | } | |
715 | ||
432e58ed | 716 | list_for_each_entry(obj, objects, exec_list) { |
1ec14ad3 CW |
717 | ret = i915_gem_execbuffer_sync_rings(obj, ring); |
718 | if (ret) | |
719 | return ret; | |
54cf91dc CW |
720 | } |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
432e58ed CW |
725 | static bool |
726 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 727 | { |
432e58ed | 728 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
729 | } |
730 | ||
731 | static int | |
732 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
733 | int count) | |
734 | { | |
735 | int i; | |
736 | ||
737 | for (i = 0; i < count; i++) { | |
738 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
739 | int length; /* limited by fault_in_pages_readable() */ | |
740 | ||
741 | /* First check for malicious input causing overflow */ | |
742 | if (exec[i].relocation_count > | |
743 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
744 | return -EINVAL; | |
745 | ||
746 | length = exec[i].relocation_count * | |
747 | sizeof(struct drm_i915_gem_relocation_entry); | |
748 | if (!access_ok(VERIFY_READ, ptr, length)) | |
749 | return -EFAULT; | |
750 | ||
751 | /* we may also need to update the presumed offsets */ | |
752 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
753 | return -EFAULT; | |
754 | ||
755 | if (fault_in_pages_readable(ptr, length)) | |
756 | return -EFAULT; | |
757 | } | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
432e58ed CW |
762 | static int |
763 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, | |
764 | struct list_head *objects) | |
765 | { | |
766 | struct drm_i915_gem_object *obj; | |
767 | int flips; | |
768 | ||
769 | /* Check for any pending flips. As we only maintain a flip queue depth | |
770 | * of 1, we can simply insert a WAIT for the next display flip prior | |
771 | * to executing the batch and avoid stalling the CPU. | |
772 | */ | |
773 | flips = 0; | |
774 | list_for_each_entry(obj, objects, exec_list) { | |
775 | if (obj->base.write_domain) | |
776 | flips |= atomic_read(&obj->pending_flip); | |
777 | } | |
778 | if (flips) { | |
779 | int plane, flip_mask, ret; | |
780 | ||
781 | for (plane = 0; flips >> plane; plane++) { | |
782 | if (((flips >> plane) & 1) == 0) | |
783 | continue; | |
784 | ||
785 | if (plane) | |
786 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
787 | else | |
788 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
789 | ||
790 | ret = intel_ring_begin(ring, 2); | |
791 | if (ret) | |
792 | return ret; | |
793 | ||
794 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
795 | intel_ring_emit(ring, MI_NOOP); | |
796 | intel_ring_advance(ring); | |
797 | } | |
798 | } | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | static void | |
804 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
805 | struct intel_ring_buffer *ring, |
806 | u32 seqno) | |
432e58ed CW |
807 | { |
808 | struct drm_i915_gem_object *obj; | |
809 | ||
810 | list_for_each_entry(obj, objects, exec_list) { | |
811 | obj->base.read_domains = obj->base.pending_read_domains; | |
812 | obj->base.write_domain = obj->base.pending_write_domain; | |
813 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
814 | ||
1ec14ad3 | 815 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
816 | if (obj->base.write_domain) { |
817 | obj->dirty = 1; | |
87ca9c8a | 818 | obj->pending_gpu_write = true; |
432e58ed CW |
819 | list_move_tail(&obj->gpu_write_list, |
820 | &ring->gpu_write_list); | |
821 | intel_mark_busy(ring->dev, obj); | |
822 | } | |
823 | ||
824 | trace_i915_gem_object_change_domain(obj, | |
825 | obj->base.read_domains, | |
826 | obj->base.write_domain); | |
827 | } | |
828 | } | |
829 | ||
54cf91dc CW |
830 | static void |
831 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 832 | struct drm_file *file, |
54cf91dc CW |
833 | struct intel_ring_buffer *ring) |
834 | { | |
432e58ed CW |
835 | struct drm_i915_gem_request *request; |
836 | u32 flush_domains; | |
54cf91dc | 837 | |
432e58ed CW |
838 | /* |
839 | * Ensure that the commands in the batch buffer are | |
840 | * finished before the interrupt fires. | |
841 | * | |
842 | * The sampler always gets flushed on i965 (sigh). | |
843 | */ | |
844 | flush_domains = 0; | |
54cf91dc CW |
845 | if (INTEL_INFO(dev)->gen >= 4) |
846 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
847 | ||
848 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); | |
54cf91dc | 849 | |
432e58ed CW |
850 | /* Add a breadcrumb for the completion of the batch buffer */ |
851 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
852 | if (request == NULL || i915_add_request(dev, file, request, ring)) { | |
853 | i915_gem_next_request_seqno(dev, ring); | |
854 | kfree(request); | |
855 | } | |
856 | } | |
54cf91dc CW |
857 | |
858 | static int | |
859 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
860 | struct drm_file *file, | |
861 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 862 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
863 | { |
864 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 865 | struct list_head objects; |
54cf91dc CW |
866 | struct drm_i915_gem_object *batch_obj; |
867 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 868 | struct intel_ring_buffer *ring; |
c4e7a414 | 869 | u32 exec_start, exec_len; |
1ec14ad3 | 870 | u32 seqno; |
432e58ed | 871 | int ret, i; |
54cf91dc | 872 | |
432e58ed CW |
873 | if (!i915_gem_check_execbuffer(args)) { |
874 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
875 | return -EINVAL; | |
876 | } | |
877 | ||
878 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
879 | if (ret) |
880 | return ret; | |
881 | ||
882 | #if WATCH_EXEC | |
883 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
884 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
885 | #endif | |
886 | switch (args->flags & I915_EXEC_RING_MASK) { | |
887 | case I915_EXEC_DEFAULT: | |
888 | case I915_EXEC_RENDER: | |
1ec14ad3 | 889 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
890 | break; |
891 | case I915_EXEC_BSD: | |
892 | if (!HAS_BSD(dev)) { | |
893 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); | |
894 | return -EINVAL; | |
895 | } | |
1ec14ad3 | 896 | ring = &dev_priv->ring[VCS]; |
54cf91dc CW |
897 | break; |
898 | case I915_EXEC_BLT: | |
899 | if (!HAS_BLT(dev)) { | |
900 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
901 | return -EINVAL; | |
902 | } | |
1ec14ad3 | 903 | ring = &dev_priv->ring[BCS]; |
54cf91dc CW |
904 | break; |
905 | default: | |
906 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
907 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
908 | return -EINVAL; | |
909 | } | |
910 | ||
911 | if (args->buffer_count < 1) { | |
912 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
913 | return -EINVAL; | |
914 | } | |
54cf91dc CW |
915 | |
916 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 917 | if (ring != &dev_priv->ring[RCS]) { |
c4e7a414 CW |
918 | DRM_ERROR("clip rectangles are only valid with the render ring\n"); |
919 | return -EINVAL; | |
920 | } | |
921 | ||
432e58ed | 922 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
923 | GFP_KERNEL); |
924 | if (cliprects == NULL) { | |
925 | ret = -ENOMEM; | |
926 | goto pre_mutex_err; | |
927 | } | |
928 | ||
432e58ed CW |
929 | if (copy_from_user(cliprects, |
930 | (struct drm_clip_rect __user *)(uintptr_t) | |
931 | args->cliprects_ptr, | |
932 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
933 | ret = -EFAULT; |
934 | goto pre_mutex_err; | |
935 | } | |
936 | } | |
937 | ||
54cf91dc CW |
938 | ret = i915_mutex_lock_interruptible(dev); |
939 | if (ret) | |
940 | goto pre_mutex_err; | |
941 | ||
942 | if (dev_priv->mm.suspended) { | |
943 | mutex_unlock(&dev->struct_mutex); | |
944 | ret = -EBUSY; | |
945 | goto pre_mutex_err; | |
946 | } | |
947 | ||
948 | /* Look up object handles */ | |
432e58ed | 949 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
950 | for (i = 0; i < args->buffer_count; i++) { |
951 | struct drm_i915_gem_object *obj; | |
952 | ||
432e58ed CW |
953 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
954 | exec[i].handle)); | |
54cf91dc CW |
955 | if (obj == NULL) { |
956 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
432e58ed | 957 | exec[i].handle, i); |
54cf91dc | 958 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
959 | ret = -ENOENT; |
960 | goto err; | |
961 | } | |
54cf91dc | 962 | |
432e58ed CW |
963 | if (!list_empty(&obj->exec_list)) { |
964 | DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n", | |
965 | obj, exec[i].handle, i); | |
54cf91dc CW |
966 | ret = -EINVAL; |
967 | goto err; | |
968 | } | |
432e58ed CW |
969 | |
970 | list_add_tail(&obj->exec_list, &objects); | |
54cf91dc CW |
971 | } |
972 | ||
973 | /* Move the objects en-masse into the GTT, evicting if necessary. */ | |
d9e86c0e | 974 | ret = i915_gem_execbuffer_reserve(ring, file, &objects, exec); |
54cf91dc CW |
975 | if (ret) |
976 | goto err; | |
977 | ||
978 | /* The objects are in their final locations, apply the relocations. */ | |
432e58ed | 979 | ret = i915_gem_execbuffer_relocate(dev, file, &objects, exec); |
54cf91dc CW |
980 | if (ret) { |
981 | if (ret == -EFAULT) { | |
d9e86c0e | 982 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
432e58ed | 983 | &objects, exec, |
54cf91dc CW |
984 | args->buffer_count); |
985 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
986 | } | |
987 | if (ret) | |
988 | goto err; | |
989 | } | |
990 | ||
991 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
432e58ed CW |
992 | batch_obj = list_entry(objects.prev, |
993 | struct drm_i915_gem_object, | |
994 | exec_list); | |
54cf91dc CW |
995 | if (batch_obj->base.pending_write_domain) { |
996 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
997 | ret = -EINVAL; | |
998 | goto err; | |
999 | } | |
1000 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1001 | ||
432e58ed CW |
1002 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1003 | if (ret) | |
54cf91dc | 1004 | goto err; |
54cf91dc | 1005 | |
432e58ed | 1006 | ret = i915_gem_execbuffer_wait_for_flips(ring, &objects); |
54cf91dc CW |
1007 | if (ret) |
1008 | goto err; | |
1009 | ||
1ec14ad3 CW |
1010 | seqno = i915_gem_next_request_seqno(dev, ring); |
1011 | for (i = 0; i < I915_NUM_RINGS-1; i++) { | |
1012 | if (seqno < ring->sync_seqno[i]) { | |
1013 | /* The GPU can not handle its semaphore value wrapping, | |
1014 | * so every billion or so execbuffers, we need to stall | |
1015 | * the GPU in order to reset the counters. | |
1016 | */ | |
1017 | ret = i915_gpu_idle(dev); | |
1018 | if (ret) | |
1019 | goto err; | |
1020 | ||
1021 | BUG_ON(ring->sync_seqno[i]); | |
1022 | } | |
1023 | } | |
1024 | ||
c4e7a414 CW |
1025 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1026 | exec_len = args->batch_len; | |
1027 | if (cliprects) { | |
1028 | for (i = 0; i < args->num_cliprects; i++) { | |
1029 | ret = i915_emit_box(dev, &cliprects[i], | |
1030 | args->DR1, args->DR4); | |
1031 | if (ret) | |
1032 | goto err; | |
1033 | ||
1034 | ret = ring->dispatch_execbuffer(ring, | |
1035 | exec_start, exec_len); | |
1036 | if (ret) | |
1037 | goto err; | |
1038 | } | |
1039 | } else { | |
1040 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); | |
1041 | if (ret) | |
1042 | goto err; | |
1043 | } | |
54cf91dc | 1044 | |
1ec14ad3 | 1045 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1046 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1047 | |
1048 | err: | |
432e58ed CW |
1049 | while (!list_empty(&objects)) { |
1050 | struct drm_i915_gem_object *obj; | |
1051 | ||
1052 | obj = list_first_entry(&objects, | |
1053 | struct drm_i915_gem_object, | |
1054 | exec_list); | |
1055 | list_del_init(&obj->exec_list); | |
1056 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1057 | } |
1058 | ||
1059 | mutex_unlock(&dev->struct_mutex); | |
1060 | ||
1061 | pre_mutex_err: | |
54cf91dc | 1062 | kfree(cliprects); |
54cf91dc CW |
1063 | return ret; |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1068 | * list array and passes it to the real function. | |
1069 | */ | |
1070 | int | |
1071 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1072 | struct drm_file *file) | |
1073 | { | |
1074 | struct drm_i915_gem_execbuffer *args = data; | |
1075 | struct drm_i915_gem_execbuffer2 exec2; | |
1076 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1077 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1078 | int ret, i; | |
1079 | ||
1080 | #if WATCH_EXEC | |
1081 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
1082 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
1083 | #endif | |
1084 | ||
1085 | if (args->buffer_count < 1) { | |
1086 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | ||
1090 | /* Copy in the exec list from userland */ | |
1091 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1092 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1093 | if (exec_list == NULL || exec2_list == NULL) { | |
1094 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
1095 | args->buffer_count); | |
1096 | drm_free_large(exec_list); | |
1097 | drm_free_large(exec2_list); | |
1098 | return -ENOMEM; | |
1099 | } | |
1100 | ret = copy_from_user(exec_list, | |
1101 | (struct drm_i915_relocation_entry __user *) | |
1102 | (uintptr_t) args->buffers_ptr, | |
1103 | sizeof(*exec_list) * args->buffer_count); | |
1104 | if (ret != 0) { | |
1105 | DRM_ERROR("copy %d exec entries failed %d\n", | |
1106 | args->buffer_count, ret); | |
1107 | drm_free_large(exec_list); | |
1108 | drm_free_large(exec2_list); | |
1109 | return -EFAULT; | |
1110 | } | |
1111 | ||
1112 | for (i = 0; i < args->buffer_count; i++) { | |
1113 | exec2_list[i].handle = exec_list[i].handle; | |
1114 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1115 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1116 | exec2_list[i].alignment = exec_list[i].alignment; | |
1117 | exec2_list[i].offset = exec_list[i].offset; | |
1118 | if (INTEL_INFO(dev)->gen < 4) | |
1119 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1120 | else | |
1121 | exec2_list[i].flags = 0; | |
1122 | } | |
1123 | ||
1124 | exec2.buffers_ptr = args->buffers_ptr; | |
1125 | exec2.buffer_count = args->buffer_count; | |
1126 | exec2.batch_start_offset = args->batch_start_offset; | |
1127 | exec2.batch_len = args->batch_len; | |
1128 | exec2.DR1 = args->DR1; | |
1129 | exec2.DR4 = args->DR4; | |
1130 | exec2.num_cliprects = args->num_cliprects; | |
1131 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1132 | exec2.flags = I915_EXEC_RENDER; | |
1133 | ||
1134 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1135 | if (!ret) { | |
1136 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1137 | for (i = 0; i < args->buffer_count; i++) | |
1138 | exec_list[i].offset = exec2_list[i].offset; | |
1139 | /* ... and back out to userspace */ | |
1140 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1141 | (uintptr_t) args->buffers_ptr, | |
1142 | exec_list, | |
1143 | sizeof(*exec_list) * args->buffer_count); | |
1144 | if (ret) { | |
1145 | ret = -EFAULT; | |
1146 | DRM_ERROR("failed to copy %d exec entries " | |
1147 | "back to user (%d)\n", | |
1148 | args->buffer_count, ret); | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | drm_free_large(exec_list); | |
1153 | drm_free_large(exec2_list); | |
1154 | return ret; | |
1155 | } | |
1156 | ||
1157 | int | |
1158 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1159 | struct drm_file *file) | |
1160 | { | |
1161 | struct drm_i915_gem_execbuffer2 *args = data; | |
1162 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1163 | int ret; | |
1164 | ||
1165 | #if WATCH_EXEC | |
1166 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
1167 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
1168 | #endif | |
1169 | ||
1170 | if (args->buffer_count < 1) { | |
1171 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | ||
1175 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1176 | if (exec2_list == NULL) { | |
1177 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
1178 | args->buffer_count); | |
1179 | return -ENOMEM; | |
1180 | } | |
1181 | ret = copy_from_user(exec2_list, | |
1182 | (struct drm_i915_relocation_entry __user *) | |
1183 | (uintptr_t) args->buffers_ptr, | |
1184 | sizeof(*exec2_list) * args->buffer_count); | |
1185 | if (ret != 0) { | |
1186 | DRM_ERROR("copy %d exec entries failed %d\n", | |
1187 | args->buffer_count, ret); | |
1188 | drm_free_large(exec2_list); | |
1189 | return -EFAULT; | |
1190 | } | |
1191 | ||
1192 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1193 | if (!ret) { | |
1194 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1195 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1196 | (uintptr_t) args->buffers_ptr, | |
1197 | exec2_list, | |
1198 | sizeof(*exec2_list) * args->buffer_count); | |
1199 | if (ret) { | |
1200 | ret = -EFAULT; | |
1201 | DRM_ERROR("failed to copy %d exec entries " | |
1202 | "back to user (%d)\n", | |
1203 | args->buffer_count, ret); | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | drm_free_large(exec2_list); | |
1208 | return ret; | |
1209 | } | |
1210 |