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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
ad778f89 CW |
29 | #include <linux/dma_remapping.h> |
30 | #include <linux/reservation.h> | |
fec0445c | 31 | #include <linux/sync_file.h> |
ad778f89 CW |
32 | #include <linux/uaccess.h> |
33 | ||
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
ad778f89 | 36 | |
54cf91dc | 37 | #include "i915_drv.h" |
57822dc6 | 38 | #include "i915_gem_clflush.h" |
54cf91dc CW |
39 | #include "i915_trace.h" |
40 | #include "intel_drv.h" | |
5d723d7a | 41 | #include "intel_frontbuffer.h" |
54cf91dc | 42 | |
d50415cc CW |
43 | #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */ |
44 | ||
9e2793f6 DG |
45 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
46 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
47 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) | |
48 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) | |
49 | #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */ | |
d23db88c CW |
50 | |
51 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 52 | |
5b043f4e CW |
53 | struct i915_execbuffer_params { |
54 | struct drm_device *dev; | |
55 | struct drm_file *file; | |
59bfa124 CW |
56 | struct i915_vma *batch; |
57 | u32 dispatch_flags; | |
58 | u32 args_batch_start_offset; | |
5b043f4e | 59 | struct intel_engine_cs *engine; |
5b043f4e CW |
60 | struct i915_gem_context *ctx; |
61 | struct drm_i915_gem_request *request; | |
62 | }; | |
63 | ||
27173f1f | 64 | struct eb_vmas { |
d50415cc | 65 | struct drm_i915_private *i915; |
27173f1f | 66 | struct list_head vmas; |
67731b87 | 67 | int and; |
eef90ccb | 68 | union { |
27173f1f | 69 | struct i915_vma *lut[0]; |
eef90ccb CW |
70 | struct hlist_head buckets[0]; |
71 | }; | |
67731b87 CW |
72 | }; |
73 | ||
27173f1f | 74 | static struct eb_vmas * |
d50415cc CW |
75 | eb_create(struct drm_i915_private *i915, |
76 | struct drm_i915_gem_execbuffer2 *args) | |
67731b87 | 77 | { |
27173f1f | 78 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
79 | |
80 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 81 | unsigned size = args->buffer_count; |
27173f1f BW |
82 | size *= sizeof(struct i915_vma *); |
83 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
84 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
85 | } | |
86 | ||
87 | if (eb == NULL) { | |
b205ca57 DV |
88 | unsigned size = args->buffer_count; |
89 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 90 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
91 | while (count > 2*size) |
92 | count >>= 1; | |
93 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 94 | sizeof(struct eb_vmas), |
eef90ccb CW |
95 | GFP_TEMPORARY); |
96 | if (eb == NULL) | |
97 | return eb; | |
98 | ||
99 | eb->and = count - 1; | |
100 | } else | |
101 | eb->and = -args->buffer_count; | |
102 | ||
d50415cc | 103 | eb->i915 = i915; |
27173f1f | 104 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
105 | return eb; |
106 | } | |
107 | ||
108 | static void | |
27173f1f | 109 | eb_reset(struct eb_vmas *eb) |
67731b87 | 110 | { |
eef90ccb CW |
111 | if (eb->and >= 0) |
112 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
113 | } |
114 | ||
59bfa124 CW |
115 | static struct i915_vma * |
116 | eb_get_batch(struct eb_vmas *eb) | |
117 | { | |
118 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
119 | ||
120 | /* | |
121 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
122 | * to negative relocation deltas. Usually that works out ok since the | |
123 | * relocate address is still positive, except when the batch is placed | |
124 | * very low in the GTT. Ensure this doesn't happen. | |
125 | * | |
126 | * Note that actual hangs have only been observed on gen7, but for | |
127 | * paranoia do it everywhere. | |
128 | */ | |
129 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) | |
130 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
131 | ||
132 | return vma; | |
133 | } | |
134 | ||
3b96eff4 | 135 | static int |
27173f1f BW |
136 | eb_lookup_vmas(struct eb_vmas *eb, |
137 | struct drm_i915_gem_exec_object2 *exec, | |
138 | const struct drm_i915_gem_execbuffer2 *args, | |
139 | struct i915_address_space *vm, | |
140 | struct drm_file *file) | |
3b96eff4 | 141 | { |
27173f1f BW |
142 | struct drm_i915_gem_object *obj; |
143 | struct list_head objects; | |
9ae9ab52 | 144 | int i, ret; |
3b96eff4 | 145 | |
27173f1f | 146 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 147 | spin_lock(&file->table_lock); |
27173f1f BW |
148 | /* Grab a reference to the object and release the lock so we can lookup |
149 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 150 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
151 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
152 | if (obj == NULL) { | |
153 | spin_unlock(&file->table_lock); | |
154 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
155 | exec[i].handle, i); | |
27173f1f | 156 | ret = -ENOENT; |
9ae9ab52 | 157 | goto err; |
3b96eff4 CW |
158 | } |
159 | ||
27173f1f | 160 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
161 | spin_unlock(&file->table_lock); |
162 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
163 | obj, exec[i].handle, i); | |
27173f1f | 164 | ret = -EINVAL; |
9ae9ab52 | 165 | goto err; |
3b96eff4 CW |
166 | } |
167 | ||
25dc556a | 168 | i915_gem_object_get(obj); |
27173f1f BW |
169 | list_add_tail(&obj->obj_exec_link, &objects); |
170 | } | |
171 | spin_unlock(&file->table_lock); | |
3b96eff4 | 172 | |
27173f1f | 173 | i = 0; |
9ae9ab52 | 174 | while (!list_empty(&objects)) { |
27173f1f | 175 | struct i915_vma *vma; |
6f65e29a | 176 | |
9ae9ab52 CW |
177 | obj = list_first_entry(&objects, |
178 | struct drm_i915_gem_object, | |
179 | obj_exec_link); | |
180 | ||
e656a6cb DV |
181 | /* |
182 | * NOTE: We can leak any vmas created here when something fails | |
183 | * later on. But that's no issue since vma_unbind can deal with | |
184 | * vmas which are not actually bound. And since only | |
185 | * lookup_or_create exists as an interface to get at the vma | |
186 | * from the (obj, vm) we don't run the risk of creating | |
187 | * duplicated vmas for the same vm. | |
188 | */ | |
718659a6 | 189 | vma = i915_vma_instance(obj, vm, NULL); |
058d88c4 | 190 | if (unlikely(IS_ERR(vma))) { |
27173f1f BW |
191 | DRM_DEBUG("Failed to lookup VMA\n"); |
192 | ret = PTR_ERR(vma); | |
9ae9ab52 | 193 | goto err; |
27173f1f BW |
194 | } |
195 | ||
9ae9ab52 | 196 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 197 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 198 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
199 | |
200 | vma->exec_entry = &exec[i]; | |
eef90ccb | 201 | if (eb->and < 0) { |
27173f1f | 202 | eb->lut[i] = vma; |
eef90ccb CW |
203 | } else { |
204 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
205 | vma->exec_handle = handle; |
206 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
207 | &eb->buckets[handle & eb->and]); |
208 | } | |
27173f1f | 209 | ++i; |
3b96eff4 | 210 | } |
3b96eff4 | 211 | |
9ae9ab52 | 212 | return 0; |
27173f1f | 213 | |
27173f1f | 214 | |
9ae9ab52 | 215 | err: |
27173f1f BW |
216 | while (!list_empty(&objects)) { |
217 | obj = list_first_entry(&objects, | |
218 | struct drm_i915_gem_object, | |
219 | obj_exec_link); | |
220 | list_del_init(&obj->obj_exec_link); | |
f8c417cd | 221 | i915_gem_object_put(obj); |
27173f1f | 222 | } |
9ae9ab52 CW |
223 | /* |
224 | * Objects already transfered to the vmas list will be unreferenced by | |
225 | * eb_destroy. | |
226 | */ | |
227 | ||
27173f1f | 228 | return ret; |
3b96eff4 CW |
229 | } |
230 | ||
27173f1f | 231 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 232 | { |
eef90ccb CW |
233 | if (eb->and < 0) { |
234 | if (handle >= -eb->and) | |
235 | return NULL; | |
236 | return eb->lut[handle]; | |
237 | } else { | |
238 | struct hlist_head *head; | |
aa45950b | 239 | struct i915_vma *vma; |
67731b87 | 240 | |
eef90ccb | 241 | head = &eb->buckets[handle & eb->and]; |
aa45950b | 242 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
243 | if (vma->exec_handle == handle) |
244 | return vma; | |
eef90ccb CW |
245 | } |
246 | return NULL; | |
247 | } | |
67731b87 CW |
248 | } |
249 | ||
a415d355 CW |
250 | static void |
251 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
252 | { | |
253 | struct drm_i915_gem_exec_object2 *entry; | |
a415d355 CW |
254 | |
255 | if (!drm_mm_node_allocated(&vma->node)) | |
256 | return; | |
257 | ||
258 | entry = vma->exec_entry; | |
259 | ||
260 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
49ef5294 | 261 | i915_vma_unpin_fence(vma); |
a415d355 CW |
262 | |
263 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
20dfbde4 | 264 | __i915_vma_unpin(vma); |
a415d355 | 265 | |
de4e783a | 266 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
267 | } |
268 | ||
269 | static void eb_destroy(struct eb_vmas *eb) | |
270 | { | |
27173f1f BW |
271 | while (!list_empty(&eb->vmas)) { |
272 | struct i915_vma *vma; | |
bcffc3fa | 273 | |
27173f1f BW |
274 | vma = list_first_entry(&eb->vmas, |
275 | struct i915_vma, | |
bcffc3fa | 276 | exec_list); |
27173f1f | 277 | list_del_init(&vma->exec_list); |
a415d355 | 278 | i915_gem_execbuffer_unreserve_vma(vma); |
172ae5b4 | 279 | vma->exec_entry = NULL; |
624192cf | 280 | i915_vma_put(vma); |
bcffc3fa | 281 | } |
67731b87 CW |
282 | kfree(eb); |
283 | } | |
284 | ||
dabdfe02 CW |
285 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
286 | { | |
9e53d9be CW |
287 | if (!i915_gem_object_has_struct_page(obj)) |
288 | return false; | |
289 | ||
d50415cc CW |
290 | if (DBG_USE_CPU_RELOC) |
291 | return DBG_USE_CPU_RELOC > 0; | |
292 | ||
0031fb96 | 293 | return (HAS_LLC(to_i915(obj->base.dev)) || |
2cc86b82 | 294 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || |
dabdfe02 CW |
295 | obj->cache_level != I915_CACHE_NONE); |
296 | } | |
297 | ||
934acce3 MW |
298 | /* Used to convert any address to canonical form. |
299 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
300 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
301 | * addresses to be in a canonical form: | |
302 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
303 | * canonical form [63:48] == [47]." | |
304 | */ | |
305 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
306 | static inline uint64_t gen8_canonical_addr(uint64_t address) | |
307 | { | |
308 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
309 | } | |
310 | ||
311 | static inline uint64_t gen8_noncanonical_addr(uint64_t address) | |
312 | { | |
313 | return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1); | |
314 | } | |
315 | ||
316 | static inline uint64_t | |
d50415cc | 317 | relocation_target(const struct drm_i915_gem_relocation_entry *reloc, |
934acce3 MW |
318 | uint64_t target_offset) |
319 | { | |
320 | return gen8_canonical_addr((int)reloc->delta + target_offset); | |
321 | } | |
322 | ||
31a39207 | 323 | struct reloc_cache { |
d50415cc CW |
324 | struct drm_i915_private *i915; |
325 | struct drm_mm_node node; | |
326 | unsigned long vaddr; | |
31a39207 | 327 | unsigned int page; |
d50415cc | 328 | bool use_64bit_reloc; |
31a39207 CW |
329 | }; |
330 | ||
d50415cc CW |
331 | static void reloc_cache_init(struct reloc_cache *cache, |
332 | struct drm_i915_private *i915) | |
5032d871 | 333 | { |
31a39207 | 334 | cache->page = -1; |
d50415cc CW |
335 | cache->vaddr = 0; |
336 | cache->i915 = i915; | |
dfc5148f JL |
337 | /* Must be a variable in the struct to allow GCC to unroll. */ |
338 | cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); | |
e8cb909a | 339 | cache->node.allocated = false; |
d50415cc | 340 | } |
5032d871 | 341 | |
d50415cc CW |
342 | static inline void *unmask_page(unsigned long p) |
343 | { | |
344 | return (void *)(uintptr_t)(p & PAGE_MASK); | |
345 | } | |
346 | ||
347 | static inline unsigned int unmask_flags(unsigned long p) | |
348 | { | |
349 | return p & ~PAGE_MASK; | |
31a39207 CW |
350 | } |
351 | ||
d50415cc CW |
352 | #define KMAP 0x4 /* after CLFLUSH_FLAGS */ |
353 | ||
31a39207 CW |
354 | static void reloc_cache_fini(struct reloc_cache *cache) |
355 | { | |
d50415cc | 356 | void *vaddr; |
5032d871 | 357 | |
31a39207 CW |
358 | if (!cache->vaddr) |
359 | return; | |
3c94ceee | 360 | |
d50415cc CW |
361 | vaddr = unmask_page(cache->vaddr); |
362 | if (cache->vaddr & KMAP) { | |
363 | if (cache->vaddr & CLFLUSH_AFTER) | |
364 | mb(); | |
3c94ceee | 365 | |
d50415cc CW |
366 | kunmap_atomic(vaddr); |
367 | i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm); | |
368 | } else { | |
e8cb909a | 369 | wmb(); |
d50415cc | 370 | io_mapping_unmap_atomic((void __iomem *)vaddr); |
e8cb909a CW |
371 | if (cache->node.allocated) { |
372 | struct i915_ggtt *ggtt = &cache->i915->ggtt; | |
373 | ||
374 | ggtt->base.clear_range(&ggtt->base, | |
375 | cache->node.start, | |
4fb84d99 | 376 | cache->node.size); |
e8cb909a CW |
377 | drm_mm_remove_node(&cache->node); |
378 | } else { | |
379 | i915_vma_unpin((struct i915_vma *)cache->node.mm); | |
3c94ceee | 380 | } |
31a39207 CW |
381 | } |
382 | } | |
383 | ||
384 | static void *reloc_kmap(struct drm_i915_gem_object *obj, | |
385 | struct reloc_cache *cache, | |
386 | int page) | |
387 | { | |
d50415cc CW |
388 | void *vaddr; |
389 | ||
390 | if (cache->vaddr) { | |
391 | kunmap_atomic(unmask_page(cache->vaddr)); | |
392 | } else { | |
393 | unsigned int flushes; | |
394 | int ret; | |
31a39207 | 395 | |
d50415cc CW |
396 | ret = i915_gem_obj_prepare_shmem_write(obj, &flushes); |
397 | if (ret) | |
398 | return ERR_PTR(ret); | |
399 | ||
400 | BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); | |
401 | BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); | |
3c94ceee | 402 | |
d50415cc CW |
403 | cache->vaddr = flushes | KMAP; |
404 | cache->node.mm = (void *)obj; | |
405 | if (flushes) | |
406 | mb(); | |
3c94ceee BW |
407 | } |
408 | ||
d50415cc CW |
409 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); |
410 | cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; | |
31a39207 | 411 | cache->page = page; |
5032d871 | 412 | |
d50415cc | 413 | return vaddr; |
5032d871 RB |
414 | } |
415 | ||
d50415cc CW |
416 | static void *reloc_iomap(struct drm_i915_gem_object *obj, |
417 | struct reloc_cache *cache, | |
418 | int page) | |
5032d871 | 419 | { |
e8cb909a CW |
420 | struct i915_ggtt *ggtt = &cache->i915->ggtt; |
421 | unsigned long offset; | |
d50415cc | 422 | void *vaddr; |
5032d871 | 423 | |
d50415cc | 424 | if (cache->vaddr) { |
615e5000 | 425 | io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); |
d50415cc CW |
426 | } else { |
427 | struct i915_vma *vma; | |
428 | int ret; | |
5032d871 | 429 | |
d50415cc CW |
430 | if (use_cpu_reloc(obj)) |
431 | return NULL; | |
3c94ceee | 432 | |
d50415cc CW |
433 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
434 | if (ret) | |
435 | return ERR_PTR(ret); | |
3c94ceee | 436 | |
d50415cc CW |
437 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
438 | PIN_MAPPABLE | PIN_NONBLOCK); | |
e8cb909a CW |
439 | if (IS_ERR(vma)) { |
440 | memset(&cache->node, 0, sizeof(cache->node)); | |
4e64e553 | 441 | ret = drm_mm_insert_node_in_range |
e8cb909a | 442 | (&ggtt->base.mm, &cache->node, |
f51455d4 | 443 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, |
e8cb909a | 444 | 0, ggtt->mappable_end, |
4e64e553 | 445 | DRM_MM_INSERT_LOW); |
c92fa4fe CW |
446 | if (ret) /* no inactive aperture space, use cpu reloc */ |
447 | return NULL; | |
e8cb909a | 448 | } else { |
49ef5294 | 449 | ret = i915_vma_put_fence(vma); |
e8cb909a CW |
450 | if (ret) { |
451 | i915_vma_unpin(vma); | |
452 | return ERR_PTR(ret); | |
453 | } | |
5032d871 | 454 | |
e8cb909a CW |
455 | cache->node.start = vma->node.start; |
456 | cache->node.mm = (void *)vma; | |
3c94ceee | 457 | } |
e8cb909a | 458 | } |
3c94ceee | 459 | |
e8cb909a CW |
460 | offset = cache->node.start; |
461 | if (cache->node.allocated) { | |
fc099090 | 462 | wmb(); |
e8cb909a CW |
463 | ggtt->base.insert_page(&ggtt->base, |
464 | i915_gem_object_get_dma_address(obj, page), | |
465 | offset, I915_CACHE_NONE, 0); | |
466 | } else { | |
467 | offset += page << PAGE_SHIFT; | |
3c94ceee BW |
468 | } |
469 | ||
615e5000 | 470 | vaddr = (void __force *) io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset); |
d50415cc CW |
471 | cache->page = page; |
472 | cache->vaddr = (unsigned long)vaddr; | |
5032d871 | 473 | |
d50415cc | 474 | return vaddr; |
5032d871 RB |
475 | } |
476 | ||
d50415cc CW |
477 | static void *reloc_vaddr(struct drm_i915_gem_object *obj, |
478 | struct reloc_cache *cache, | |
479 | int page) | |
edf4427b | 480 | { |
d50415cc | 481 | void *vaddr; |
5032d871 | 482 | |
d50415cc CW |
483 | if (cache->page == page) { |
484 | vaddr = unmask_page(cache->vaddr); | |
485 | } else { | |
486 | vaddr = NULL; | |
487 | if ((cache->vaddr & KMAP) == 0) | |
488 | vaddr = reloc_iomap(obj, cache, page); | |
489 | if (!vaddr) | |
490 | vaddr = reloc_kmap(obj, cache, page); | |
3c94ceee BW |
491 | } |
492 | ||
d50415cc | 493 | return vaddr; |
edf4427b CW |
494 | } |
495 | ||
d50415cc | 496 | static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) |
edf4427b | 497 | { |
d50415cc CW |
498 | if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { |
499 | if (flushes & CLFLUSH_BEFORE) { | |
500 | clflushopt(addr); | |
501 | mb(); | |
502 | } | |
edf4427b | 503 | |
d50415cc | 504 | *addr = value; |
edf4427b | 505 | |
d50415cc CW |
506 | /* Writes to the same cacheline are serialised by the CPU |
507 | * (including clflush). On the write path, we only require | |
508 | * that it hits memory in an orderly fashion and place | |
509 | * mb barriers at the start and end of the relocation phase | |
510 | * to ensure ordering of clflush wrt to the system. | |
511 | */ | |
512 | if (flushes & CLFLUSH_AFTER) | |
513 | clflushopt(addr); | |
514 | } else | |
515 | *addr = value; | |
edf4427b | 516 | } |
edf4427b | 517 | |
edf4427b | 518 | static int |
d50415cc CW |
519 | relocate_entry(struct drm_i915_gem_object *obj, |
520 | const struct drm_i915_gem_relocation_entry *reloc, | |
521 | struct reloc_cache *cache, | |
522 | u64 target_offset) | |
edf4427b | 523 | { |
d50415cc CW |
524 | u64 offset = reloc->offset; |
525 | bool wide = cache->use_64bit_reloc; | |
526 | void *vaddr; | |
edf4427b | 527 | |
d50415cc CW |
528 | target_offset = relocation_target(reloc, target_offset); |
529 | repeat: | |
530 | vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT); | |
531 | if (IS_ERR(vaddr)) | |
532 | return PTR_ERR(vaddr); | |
533 | ||
534 | clflush_write32(vaddr + offset_in_page(offset), | |
535 | lower_32_bits(target_offset), | |
536 | cache->vaddr); | |
537 | ||
538 | if (wide) { | |
539 | offset += sizeof(u32); | |
540 | target_offset >>= 32; | |
541 | wide = false; | |
542 | goto repeat; | |
edf4427b | 543 | } |
edf4427b | 544 | |
edf4427b CW |
545 | return 0; |
546 | } | |
edf4427b | 547 | |
54cf91dc | 548 | static int |
611cdf36 | 549 | i915_gem_execbuffer_relocate_entry(struct i915_vma *vma, |
27173f1f | 550 | struct eb_vmas *eb, |
31a39207 CW |
551 | struct drm_i915_gem_relocation_entry *reloc, |
552 | struct reloc_cache *cache) | |
54cf91dc | 553 | { |
611cdf36 | 554 | struct drm_i915_gem_object *obj = vma->obj; |
5db94019 | 555 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
54cf91dc | 556 | struct drm_gem_object *target_obj; |
149c8407 | 557 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 558 | struct i915_vma *target_vma; |
d9ceb957 | 559 | uint64_t target_offset; |
8b78f0e5 | 560 | int ret; |
54cf91dc | 561 | |
67731b87 | 562 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
563 | target_vma = eb_get_vma(eb, reloc->target_handle); |
564 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 565 | return -ENOENT; |
27173f1f BW |
566 | target_i915_obj = target_vma->obj; |
567 | target_obj = &target_vma->obj->base; | |
54cf91dc | 568 | |
934acce3 | 569 | target_offset = gen8_canonical_addr(target_vma->node.start); |
54cf91dc | 570 | |
e844b990 EA |
571 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
572 | * pipe_control writes because the gpu doesn't properly redirect them | |
573 | * through the ppgtt for non_secure batchbuffers. */ | |
5db94019 | 574 | if (unlikely(IS_GEN6(dev_priv) && |
0875546c | 575 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 576 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 577 | PIN_GLOBAL); |
fe14d5f4 TU |
578 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
579 | return ret; | |
580 | } | |
e844b990 | 581 | |
54cf91dc | 582 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 583 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 584 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
585 | "obj %p target %d offset %d " |
586 | "read %08x write %08x", | |
587 | obj, reloc->target_handle, | |
588 | (int) reloc->offset, | |
589 | reloc->read_domains, | |
590 | reloc->write_domain); | |
8b78f0e5 | 591 | return -EINVAL; |
54cf91dc | 592 | } |
4ca4a250 DV |
593 | if (unlikely((reloc->write_domain | reloc->read_domains) |
594 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 595 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
596 | "obj %p target %d offset %d " |
597 | "read %08x write %08x", | |
598 | obj, reloc->target_handle, | |
599 | (int) reloc->offset, | |
600 | reloc->read_domains, | |
601 | reloc->write_domain); | |
8b78f0e5 | 602 | return -EINVAL; |
54cf91dc | 603 | } |
54cf91dc CW |
604 | |
605 | target_obj->pending_read_domains |= reloc->read_domains; | |
606 | target_obj->pending_write_domain |= reloc->write_domain; | |
607 | ||
608 | /* If the relocation already has the right value in it, no | |
609 | * more work needs to be done. | |
610 | */ | |
611 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 612 | return 0; |
54cf91dc CW |
613 | |
614 | /* Check that the relocation address is valid... */ | |
3c94ceee | 615 | if (unlikely(reloc->offset > |
d50415cc | 616 | obj->base.size - (cache->use_64bit_reloc ? 8 : 4))) { |
ff240199 | 617 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
618 | "obj %p target %d offset %d size %d.\n", |
619 | obj, reloc->target_handle, | |
620 | (int) reloc->offset, | |
621 | (int) obj->base.size); | |
8b78f0e5 | 622 | return -EINVAL; |
54cf91dc | 623 | } |
b8f7ab17 | 624 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 625 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
626 | "obj %p target %d offset %d.\n", |
627 | obj, reloc->target_handle, | |
628 | (int) reloc->offset); | |
8b78f0e5 | 629 | return -EINVAL; |
54cf91dc CW |
630 | } |
631 | ||
611cdf36 CW |
632 | /* |
633 | * If we write into the object, we need to force the synchronisation | |
634 | * barrier, either with an asynchronous clflush or if we executed the | |
635 | * patching using the GPU (though that should be serialised by the | |
636 | * timeline). To be completely sure, and since we are required to | |
637 | * do relocations we are already stalling, disable the user's opt | |
638 | * of our synchronisation. | |
639 | */ | |
640 | vma->exec_entry->flags &= ~EXEC_OBJECT_ASYNC; | |
641 | ||
d50415cc | 642 | ret = relocate_entry(obj, reloc, cache, target_offset); |
d4d36014 DV |
643 | if (ret) |
644 | return ret; | |
645 | ||
54cf91dc CW |
646 | /* and update the user's relocation entry */ |
647 | reloc->presumed_offset = target_offset; | |
67731b87 | 648 | return 0; |
54cf91dc CW |
649 | } |
650 | ||
651 | static int | |
27173f1f BW |
652 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
653 | struct eb_vmas *eb) | |
54cf91dc | 654 | { |
1d83f442 CW |
655 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
656 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 657 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 658 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
31a39207 CW |
659 | struct reloc_cache cache; |
660 | int remain, ret = 0; | |
54cf91dc | 661 | |
3ed605bc | 662 | user_relocs = u64_to_user_ptr(entry->relocs_ptr); |
d50415cc | 663 | reloc_cache_init(&cache, eb->i915); |
54cf91dc | 664 | |
1d83f442 CW |
665 | remain = entry->relocation_count; |
666 | while (remain) { | |
667 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
ebc0808f CW |
668 | unsigned long unwritten; |
669 | unsigned int count; | |
670 | ||
671 | count = min_t(unsigned int, remain, ARRAY_SIZE(stack_reloc)); | |
1d83f442 CW |
672 | remain -= count; |
673 | ||
ebc0808f CW |
674 | /* This is the fast path and we cannot handle a pagefault |
675 | * whilst holding the struct mutex lest the user pass in the | |
676 | * relocations contained within a mmaped bo. For in such a case | |
677 | * we, the page fault handler would call i915_gem_fault() and | |
678 | * we would try to acquire the struct mutex again. Obviously | |
679 | * this is bad and so lockdep complains vehemently. | |
680 | */ | |
681 | pagefault_disable(); | |
682 | unwritten = __copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])); | |
683 | pagefault_enable(); | |
684 | if (unlikely(unwritten)) { | |
31a39207 CW |
685 | ret = -EFAULT; |
686 | goto out; | |
687 | } | |
54cf91dc | 688 | |
1d83f442 CW |
689 | do { |
690 | u64 offset = r->presumed_offset; | |
54cf91dc | 691 | |
611cdf36 | 692 | ret = i915_gem_execbuffer_relocate_entry(vma, eb, r, &cache); |
1d83f442 | 693 | if (ret) |
31a39207 | 694 | goto out; |
1d83f442 | 695 | |
ebc0808f CW |
696 | if (r->presumed_offset != offset) { |
697 | pagefault_disable(); | |
698 | unwritten = __put_user(r->presumed_offset, | |
699 | &user_relocs->presumed_offset); | |
700 | pagefault_enable(); | |
701 | if (unlikely(unwritten)) { | |
702 | /* Note that reporting an error now | |
703 | * leaves everything in an inconsistent | |
704 | * state as we have *already* changed | |
705 | * the relocation value inside the | |
706 | * object. As we have not changed the | |
707 | * reloc.presumed_offset or will not | |
708 | * change the execobject.offset, on the | |
709 | * call we may not rewrite the value | |
710 | * inside the object, leaving it | |
711 | * dangling and causing a GPU hang. | |
712 | */ | |
713 | ret = -EFAULT; | |
714 | goto out; | |
715 | } | |
1d83f442 CW |
716 | } |
717 | ||
718 | user_relocs++; | |
719 | r++; | |
720 | } while (--count); | |
54cf91dc CW |
721 | } |
722 | ||
31a39207 CW |
723 | out: |
724 | reloc_cache_fini(&cache); | |
725 | return ret; | |
1d83f442 | 726 | #undef N_RELOC |
54cf91dc CW |
727 | } |
728 | ||
729 | static int | |
27173f1f BW |
730 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
731 | struct eb_vmas *eb, | |
732 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 733 | { |
27173f1f | 734 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
31a39207 CW |
735 | struct reloc_cache cache; |
736 | int i, ret = 0; | |
54cf91dc | 737 | |
d50415cc | 738 | reloc_cache_init(&cache, eb->i915); |
54cf91dc | 739 | for (i = 0; i < entry->relocation_count; i++) { |
611cdf36 | 740 | ret = i915_gem_execbuffer_relocate_entry(vma, eb, &relocs[i], &cache); |
54cf91dc | 741 | if (ret) |
31a39207 | 742 | break; |
54cf91dc | 743 | } |
31a39207 | 744 | reloc_cache_fini(&cache); |
54cf91dc | 745 | |
31a39207 | 746 | return ret; |
54cf91dc CW |
747 | } |
748 | ||
749 | static int | |
17601cbc | 750 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 751 | { |
27173f1f | 752 | struct i915_vma *vma; |
d4aeee77 CW |
753 | int ret = 0; |
754 | ||
27173f1f BW |
755 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
756 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 757 | if (ret) |
d4aeee77 | 758 | break; |
54cf91dc CW |
759 | } |
760 | ||
d4aeee77 | 761 | return ret; |
54cf91dc CW |
762 | } |
763 | ||
edf4427b CW |
764 | static bool only_mappable_for_reloc(unsigned int flags) |
765 | { | |
766 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
767 | __EXEC_OBJECT_NEEDS_MAP; | |
768 | } | |
769 | ||
1690e1eb | 770 | static int |
27173f1f | 771 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
0bc40be8 | 772 | struct intel_engine_cs *engine, |
27173f1f | 773 | bool *need_reloc) |
1690e1eb | 774 | { |
6f65e29a | 775 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 776 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 777 | uint64_t flags; |
1690e1eb CW |
778 | int ret; |
779 | ||
0875546c | 780 | flags = PIN_USER; |
0229da32 DV |
781 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
782 | flags |= PIN_GLOBAL; | |
783 | ||
edf4427b | 784 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
785 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
786 | * limit address to the first 4GBs for unflagged objects. | |
787 | */ | |
788 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
789 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
790 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
791 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
792 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
793 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
794 | if (entry->flags & EXEC_OBJECT_PINNED) |
795 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
796 | if ((flags & PIN_MAPPABLE) == 0) |
797 | flags |= PIN_HIGH; | |
edf4427b | 798 | } |
1ec9e26d | 799 | |
59bfa124 CW |
800 | ret = i915_vma_pin(vma, |
801 | entry->pad_to_size, | |
802 | entry->alignment, | |
803 | flags); | |
804 | if ((ret == -ENOSPC || ret == -E2BIG) && | |
edf4427b | 805 | only_mappable_for_reloc(entry->flags)) |
59bfa124 CW |
806 | ret = i915_vma_pin(vma, |
807 | entry->pad_to_size, | |
808 | entry->alignment, | |
809 | flags & ~PIN_MAPPABLE); | |
1690e1eb CW |
810 | if (ret) |
811 | return ret; | |
812 | ||
7788a765 CW |
813 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
814 | ||
82b6b6d7 | 815 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
49ef5294 | 816 | ret = i915_vma_get_fence(vma); |
82b6b6d7 CW |
817 | if (ret) |
818 | return ret; | |
9a5a53b3 | 819 | |
49ef5294 | 820 | if (i915_vma_pin_fence(vma)) |
82b6b6d7 | 821 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
1690e1eb CW |
822 | } |
823 | ||
27173f1f BW |
824 | if (entry->offset != vma->node.start) { |
825 | entry->offset = vma->node.start; | |
ed5982e6 DV |
826 | *need_reloc = true; |
827 | } | |
828 | ||
829 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
830 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
831 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
832 | } | |
833 | ||
1690e1eb | 834 | return 0; |
7788a765 | 835 | } |
1690e1eb | 836 | |
d23db88c | 837 | static bool |
e6a84468 | 838 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
839 | { |
840 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 841 | |
e6a84468 CW |
842 | if (entry->relocation_count == 0) |
843 | return false; | |
844 | ||
3272db53 | 845 | if (!i915_vma_is_ggtt(vma)) |
e6a84468 CW |
846 | return false; |
847 | ||
848 | /* See also use_cpu_reloc() */ | |
0031fb96 | 849 | if (HAS_LLC(to_i915(vma->obj->base.dev))) |
e6a84468 CW |
850 | return false; |
851 | ||
852 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
853 | return false; | |
854 | ||
855 | return true; | |
856 | } | |
857 | ||
858 | static bool | |
859 | eb_vma_misplaced(struct i915_vma *vma) | |
860 | { | |
861 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 862 | |
3272db53 CW |
863 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
864 | !i915_vma_is_ggtt(vma)); | |
d23db88c | 865 | |
f51455d4 | 866 | if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) |
d23db88c CW |
867 | return true; |
868 | ||
91b2db6f CW |
869 | if (vma->node.size < entry->pad_to_size) |
870 | return true; | |
871 | ||
506a8e87 CW |
872 | if (entry->flags & EXEC_OBJECT_PINNED && |
873 | vma->node.start != entry->offset) | |
874 | return true; | |
875 | ||
d23db88c CW |
876 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
877 | vma->node.start < BATCH_OFFSET_BIAS) | |
878 | return true; | |
879 | ||
edf4427b | 880 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
05a20d09 CW |
881 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
882 | !i915_vma_is_map_and_fenceable(vma)) | |
edf4427b CW |
883 | return !only_mappable_for_reloc(entry->flags); |
884 | ||
101b506a MT |
885 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
886 | (vma->node.start + vma->node.size - 1) >> 32) | |
887 | return true; | |
888 | ||
d23db88c CW |
889 | return false; |
890 | } | |
891 | ||
54cf91dc | 892 | static int |
0bc40be8 | 893 | i915_gem_execbuffer_reserve(struct intel_engine_cs *engine, |
27173f1f | 894 | struct list_head *vmas, |
e2efd130 | 895 | struct i915_gem_context *ctx, |
ed5982e6 | 896 | bool *need_relocs) |
54cf91dc | 897 | { |
432e58ed | 898 | struct drm_i915_gem_object *obj; |
27173f1f | 899 | struct i915_vma *vma; |
68c8c17f | 900 | struct i915_address_space *vm; |
27173f1f | 901 | struct list_head ordered_vmas; |
506a8e87 | 902 | struct list_head pinned_vmas; |
c033666a | 903 | bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4; |
f4ce766f | 904 | bool needs_unfenced_map = INTEL_INFO(engine->i915)->unfenced_needs_alignment; |
7788a765 | 905 | int retry; |
6fe4f140 | 906 | |
68c8c17f BW |
907 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
908 | ||
27173f1f | 909 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 910 | INIT_LIST_HEAD(&pinned_vmas); |
27173f1f | 911 | while (!list_empty(vmas)) { |
6fe4f140 CW |
912 | struct drm_i915_gem_exec_object2 *entry; |
913 | bool need_fence, need_mappable; | |
914 | ||
27173f1f BW |
915 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
916 | obj = vma->obj; | |
917 | entry = vma->exec_entry; | |
6fe4f140 | 918 | |
b1b38278 DW |
919 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
920 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
921 | ||
82b6b6d7 CW |
922 | if (!has_fenced_gpu_access) |
923 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 924 | need_fence = |
f4ce766f CW |
925 | (entry->flags & EXEC_OBJECT_NEEDS_FENCE || |
926 | needs_unfenced_map) && | |
3e510a8e | 927 | i915_gem_object_is_tiled(obj); |
27173f1f | 928 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 929 | |
506a8e87 CW |
930 | if (entry->flags & EXEC_OBJECT_PINNED) |
931 | list_move_tail(&vma->exec_list, &pinned_vmas); | |
932 | else if (need_mappable) { | |
e6a84468 | 933 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
27173f1f | 934 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 935 | } else |
27173f1f | 936 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 937 | |
ed5982e6 | 938 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 939 | obj->base.pending_write_domain = 0; |
6fe4f140 | 940 | } |
27173f1f | 941 | list_splice(&ordered_vmas, vmas); |
506a8e87 | 942 | list_splice(&pinned_vmas, vmas); |
54cf91dc CW |
943 | |
944 | /* Attempt to pin all of the buffers into the GTT. | |
945 | * This is done in 3 phases: | |
946 | * | |
947 | * 1a. Unbind all objects that do not match the GTT constraints for | |
948 | * the execbuffer (fenceable, mappable, alignment etc). | |
949 | * 1b. Increment pin count for already bound objects. | |
950 | * 2. Bind new objects. | |
951 | * 3. Decrement pin count. | |
952 | * | |
7788a765 | 953 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
954 | * room for the earlier objects *unless* we need to defragment. |
955 | */ | |
956 | retry = 0; | |
957 | do { | |
7788a765 | 958 | int ret = 0; |
54cf91dc CW |
959 | |
960 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 961 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 962 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
963 | continue; |
964 | ||
e6a84468 | 965 | if (eb_vma_misplaced(vma)) |
27173f1f | 966 | ret = i915_vma_unbind(vma); |
54cf91dc | 967 | else |
0bc40be8 TU |
968 | ret = i915_gem_execbuffer_reserve_vma(vma, |
969 | engine, | |
970 | need_relocs); | |
432e58ed | 971 | if (ret) |
54cf91dc | 972 | goto err; |
54cf91dc CW |
973 | } |
974 | ||
975 | /* Bind fresh objects */ | |
27173f1f BW |
976 | list_for_each_entry(vma, vmas, exec_list) { |
977 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 978 | continue; |
54cf91dc | 979 | |
0bc40be8 TU |
980 | ret = i915_gem_execbuffer_reserve_vma(vma, engine, |
981 | need_relocs); | |
7788a765 CW |
982 | if (ret) |
983 | goto err; | |
54cf91dc CW |
984 | } |
985 | ||
a415d355 | 986 | err: |
6c085a72 | 987 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
988 | return ret; |
989 | ||
a415d355 CW |
990 | /* Decrement pin count for bound objects */ |
991 | list_for_each_entry(vma, vmas, exec_list) | |
992 | i915_gem_execbuffer_unreserve_vma(vma); | |
993 | ||
68c8c17f | 994 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
995 | if (ret) |
996 | return ret; | |
54cf91dc CW |
997 | } while (1); |
998 | } | |
999 | ||
1000 | static int | |
1001 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 1002 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 1003 | struct drm_file *file, |
0bc40be8 | 1004 | struct intel_engine_cs *engine, |
27173f1f | 1005 | struct eb_vmas *eb, |
b1b38278 | 1006 | struct drm_i915_gem_exec_object2 *exec, |
e2efd130 | 1007 | struct i915_gem_context *ctx) |
54cf91dc CW |
1008 | { |
1009 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
1010 | struct i915_address_space *vm; |
1011 | struct i915_vma *vma; | |
ed5982e6 | 1012 | bool need_relocs; |
dd6864a4 | 1013 | int *reloc_offset; |
54cf91dc | 1014 | int i, total, ret; |
b205ca57 | 1015 | unsigned count = args->buffer_count; |
54cf91dc | 1016 | |
27173f1f BW |
1017 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
1018 | ||
67731b87 | 1019 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
1020 | while (!list_empty(&eb->vmas)) { |
1021 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
1022 | list_del_init(&vma->exec_list); | |
a415d355 | 1023 | i915_gem_execbuffer_unreserve_vma(vma); |
624192cf | 1024 | i915_vma_put(vma); |
67731b87 CW |
1025 | } |
1026 | ||
54cf91dc CW |
1027 | mutex_unlock(&dev->struct_mutex); |
1028 | ||
1029 | total = 0; | |
1030 | for (i = 0; i < count; i++) | |
432e58ed | 1031 | total += exec[i].relocation_count; |
54cf91dc | 1032 | |
dd6864a4 | 1033 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 1034 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
1035 | if (reloc == NULL || reloc_offset == NULL) { |
1036 | drm_free_large(reloc); | |
1037 | drm_free_large(reloc_offset); | |
54cf91dc CW |
1038 | mutex_lock(&dev->struct_mutex); |
1039 | return -ENOMEM; | |
1040 | } | |
1041 | ||
1042 | total = 0; | |
1043 | for (i = 0; i < count; i++) { | |
1044 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
1045 | u64 invalid_offset = (u64)-1; |
1046 | int j; | |
54cf91dc | 1047 | |
3ed605bc | 1048 | user_relocs = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1049 | |
1050 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 1051 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
1052 | ret = -EFAULT; |
1053 | mutex_lock(&dev->struct_mutex); | |
1054 | goto err; | |
1055 | } | |
1056 | ||
262b6d36 CW |
1057 | /* As we do not update the known relocation offsets after |
1058 | * relocating (due to the complexities in lock handling), | |
1059 | * we need to mark them as invalid now so that we force the | |
1060 | * relocation processing next time. Just in case the target | |
1061 | * object is evicted and then rebound into its old | |
1062 | * presumed_offset before the next execbuffer - if that | |
1063 | * happened we would make the mistake of assuming that the | |
1064 | * relocations were valid. | |
1065 | */ | |
1066 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
1067 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
1068 | &invalid_offset, | |
1069 | sizeof(invalid_offset))) { | |
262b6d36 CW |
1070 | ret = -EFAULT; |
1071 | mutex_lock(&dev->struct_mutex); | |
1072 | goto err; | |
1073 | } | |
1074 | } | |
1075 | ||
dd6864a4 | 1076 | reloc_offset[i] = total; |
432e58ed | 1077 | total += exec[i].relocation_count; |
54cf91dc CW |
1078 | } |
1079 | ||
1080 | ret = i915_mutex_lock_interruptible(dev); | |
1081 | if (ret) { | |
1082 | mutex_lock(&dev->struct_mutex); | |
1083 | goto err; | |
1084 | } | |
1085 | ||
67731b87 | 1086 | /* reacquire the objects */ |
67731b87 | 1087 | eb_reset(eb); |
27173f1f | 1088 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1089 | if (ret) |
1090 | goto err; | |
67731b87 | 1091 | |
ed5982e6 | 1092 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
0bc40be8 TU |
1093 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
1094 | &need_relocs); | |
54cf91dc CW |
1095 | if (ret) |
1096 | goto err; | |
1097 | ||
27173f1f BW |
1098 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
1099 | int offset = vma->exec_entry - exec; | |
1100 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
1101 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
1102 | if (ret) |
1103 | goto err; | |
54cf91dc CW |
1104 | } |
1105 | ||
1106 | /* Leave the user relocations as are, this is the painfully slow path, | |
1107 | * and we want to avoid the complication of dropping the lock whilst | |
1108 | * having buffers reserved in the aperture and so causing spurious | |
1109 | * ENOSPC for random operations. | |
1110 | */ | |
1111 | ||
1112 | err: | |
1113 | drm_free_large(reloc); | |
dd6864a4 | 1114 | drm_free_large(reloc_offset); |
54cf91dc CW |
1115 | return ret; |
1116 | } | |
1117 | ||
54cf91dc | 1118 | static int |
535fbe82 | 1119 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 1120 | struct list_head *vmas) |
54cf91dc | 1121 | { |
27173f1f | 1122 | struct i915_vma *vma; |
432e58ed | 1123 | int ret; |
54cf91dc | 1124 | |
27173f1f BW |
1125 | list_for_each_entry(vma, vmas, exec_list) { |
1126 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 | 1127 | |
77ae9957 CW |
1128 | if (vma->exec_entry->flags & EXEC_OBJECT_ASYNC) |
1129 | continue; | |
1130 | ||
57822dc6 CW |
1131 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) { |
1132 | i915_gem_clflush_object(obj, 0); | |
1133 | obj->base.write_domain = 0; | |
1134 | } | |
1135 | ||
d07f0e59 CW |
1136 | ret = i915_gem_request_await_object |
1137 | (req, obj, obj->base.pending_write_domain); | |
1138 | if (ret) | |
1139 | return ret; | |
c59a333f CW |
1140 | } |
1141 | ||
dcd79934 CW |
1142 | /* Unconditionally flush any chipset caches (for streaming writes). */ |
1143 | i915_gem_chipset_flush(req->engine->i915); | |
6ac42f41 | 1144 | |
c7fe7d25 | 1145 | /* Unconditionally invalidate GPU caches and TLBs. */ |
7c9cf4e3 | 1146 | return req->engine->emit_flush(req, EMIT_INVALIDATE); |
54cf91dc CW |
1147 | } |
1148 | ||
432e58ed CW |
1149 | static bool |
1150 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 1151 | { |
ed5982e6 DV |
1152 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
1153 | return false; | |
1154 | ||
2f5945bc CW |
1155 | /* Kernel clipping was a DRI1 misfeature */ |
1156 | if (exec->num_cliprects || exec->cliprects_ptr) | |
1157 | return false; | |
1158 | ||
1159 | if (exec->DR4 == 0xffffffff) { | |
1160 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1161 | exec->DR4 = 0; | |
1162 | } | |
1163 | if (exec->DR1 || exec->DR4) | |
1164 | return false; | |
1165 | ||
1166 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
1167 | return false; | |
1168 | ||
1169 | return true; | |
54cf91dc CW |
1170 | } |
1171 | ||
1172 | static int | |
ad19f10b CW |
1173 | validate_exec_list(struct drm_device *dev, |
1174 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
1175 | int count) |
1176 | { | |
b205ca57 DV |
1177 | unsigned relocs_total = 0; |
1178 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
1179 | unsigned invalid_flags; |
1180 | int i; | |
1181 | ||
9e2793f6 DG |
1182 | /* INTERNAL flags must not overlap with external ones */ |
1183 | BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS); | |
1184 | ||
ad19f10b CW |
1185 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; |
1186 | if (USES_FULL_PPGTT(dev)) | |
1187 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
1188 | |
1189 | for (i = 0; i < count; i++) { | |
3ed605bc | 1190 | char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1191 | int length; /* limited by fault_in_pages_readable() */ |
1192 | ||
ad19f10b | 1193 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
1194 | return -EINVAL; |
1195 | ||
934acce3 MW |
1196 | /* Offset can be used as input (EXEC_OBJECT_PINNED), reject |
1197 | * any non-page-aligned or non-canonical addresses. | |
1198 | */ | |
1199 | if (exec[i].flags & EXEC_OBJECT_PINNED) { | |
1200 | if (exec[i].offset != | |
1201 | gen8_canonical_addr(exec[i].offset & PAGE_MASK)) | |
1202 | return -EINVAL; | |
934acce3 MW |
1203 | } |
1204 | ||
038c95a3 MW |
1205 | /* From drm_mm perspective address space is continuous, |
1206 | * so from this point we're always using non-canonical | |
1207 | * form internally. | |
1208 | */ | |
1209 | exec[i].offset = gen8_noncanonical_addr(exec[i].offset); | |
1210 | ||
55a9785d CW |
1211 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
1212 | return -EINVAL; | |
1213 | ||
91b2db6f CW |
1214 | /* pad_to_size was once a reserved field, so sanitize it */ |
1215 | if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) { | |
1216 | if (offset_in_page(exec[i].pad_to_size)) | |
1217 | return -EINVAL; | |
1218 | } else { | |
1219 | exec[i].pad_to_size = 0; | |
1220 | } | |
1221 | ||
3118a4f6 KC |
1222 | /* First check for malicious input causing overflow in |
1223 | * the worst case where we need to allocate the entire | |
1224 | * relocation tree as a single array. | |
1225 | */ | |
1226 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1227 | return -EINVAL; |
3118a4f6 | 1228 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1229 | |
1230 | length = exec[i].relocation_count * | |
1231 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1232 | /* |
1233 | * We must check that the entire relocation array is safe | |
1234 | * to read, but since we may need to update the presumed | |
1235 | * offsets during execution, check for full write access. | |
1236 | */ | |
54cf91dc CW |
1237 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1238 | return -EFAULT; | |
1239 | ||
d330a953 | 1240 | if (likely(!i915.prefault_disable)) { |
4bce9f6e | 1241 | if (fault_in_pages_readable(ptr, length)) |
0b74b508 XZ |
1242 | return -EFAULT; |
1243 | } | |
54cf91dc CW |
1244 | } |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
e2efd130 | 1249 | static struct i915_gem_context * |
d299cce7 | 1250 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
0bc40be8 | 1251 | struct intel_engine_cs *engine, const u32 ctx_id) |
d299cce7 | 1252 | { |
f7978a0c | 1253 | struct i915_gem_context *ctx; |
d299cce7 | 1254 | |
ca585b5d | 1255 | ctx = i915_gem_context_lookup(file->driver_priv, ctx_id); |
72ad5c45 | 1256 | if (IS_ERR(ctx)) |
41bde553 | 1257 | return ctx; |
d299cce7 | 1258 | |
6095868a | 1259 | if (i915_gem_context_is_banned(ctx)) { |
d299cce7 | 1260 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); |
41bde553 | 1261 | return ERR_PTR(-EIO); |
d299cce7 MK |
1262 | } |
1263 | ||
41bde553 | 1264 | return ctx; |
d299cce7 MK |
1265 | } |
1266 | ||
7aa6ca61 CW |
1267 | static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
1268 | { | |
1269 | return !(obj->cache_level == I915_CACHE_NONE || | |
1270 | obj->cache_level == I915_CACHE_WT); | |
1271 | } | |
1272 | ||
5cf3d280 CW |
1273 | void i915_vma_move_to_active(struct i915_vma *vma, |
1274 | struct drm_i915_gem_request *req, | |
1275 | unsigned int flags) | |
1276 | { | |
1277 | struct drm_i915_gem_object *obj = vma->obj; | |
1278 | const unsigned int idx = req->engine->id; | |
1279 | ||
81147b07 | 1280 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5cf3d280 CW |
1281 | GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); |
1282 | ||
b0decaf7 CW |
1283 | /* Add a reference if we're newly entering the active list. |
1284 | * The order in which we add operations to the retirement queue is | |
1285 | * vital here: mark_active adds to the start of the callback list, | |
1286 | * such that subsequent callbacks are called first. Therefore we | |
1287 | * add the active reference first and queue for it to be dropped | |
1288 | * *last*. | |
1289 | */ | |
d07f0e59 CW |
1290 | if (!i915_vma_is_active(vma)) |
1291 | obj->active_count++; | |
1292 | i915_vma_set_active(vma, idx); | |
1293 | i915_gem_active_set(&vma->last_read[idx], req); | |
1294 | list_move_tail(&vma->vm_link, &vma->vm->active_list); | |
5cf3d280 CW |
1295 | |
1296 | if (flags & EXEC_OBJECT_WRITE) { | |
5b8c8aec CW |
1297 | if (intel_fb_obj_invalidate(obj, ORIGIN_CS)) |
1298 | i915_gem_active_set(&obj->frontbuffer_write, req); | |
5cf3d280 CW |
1299 | |
1300 | /* update for the implicit flush after a batch */ | |
1301 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
7aa6ca61 CW |
1302 | if (!obj->cache_dirty && gpu_write_needs_clflush(obj)) |
1303 | obj->cache_dirty = true; | |
5cf3d280 CW |
1304 | } |
1305 | ||
49ef5294 CW |
1306 | if (flags & EXEC_OBJECT_NEEDS_FENCE) |
1307 | i915_gem_active_set(&vma->last_fence, req); | |
5cf3d280 CW |
1308 | } |
1309 | ||
ad778f89 CW |
1310 | static void eb_export_fence(struct drm_i915_gem_object *obj, |
1311 | struct drm_i915_gem_request *req, | |
1312 | unsigned int flags) | |
1313 | { | |
d07f0e59 | 1314 | struct reservation_object *resv = obj->resv; |
ad778f89 CW |
1315 | |
1316 | /* Ignore errors from failing to allocate the new fence, we can't | |
1317 | * handle an error right now. Worst case should be missed | |
1318 | * synchronisation leading to rendering corruption. | |
1319 | */ | |
e2989f14 | 1320 | reservation_object_lock(resv, NULL); |
ad778f89 CW |
1321 | if (flags & EXEC_OBJECT_WRITE) |
1322 | reservation_object_add_excl_fence(resv, &req->fence); | |
1323 | else if (reservation_object_reserve_shared(resv) == 0) | |
1324 | reservation_object_add_shared_fence(resv, &req->fence); | |
e2989f14 | 1325 | reservation_object_unlock(resv); |
ad778f89 CW |
1326 | } |
1327 | ||
5b043f4e | 1328 | static void |
27173f1f | 1329 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1330 | struct drm_i915_gem_request *req) |
432e58ed | 1331 | { |
27173f1f | 1332 | struct i915_vma *vma; |
432e58ed | 1333 | |
27173f1f BW |
1334 | list_for_each_entry(vma, vmas, exec_list) { |
1335 | struct drm_i915_gem_object *obj = vma->obj; | |
db53a302 | 1336 | |
432e58ed | 1337 | obj->base.write_domain = obj->base.pending_write_domain; |
5cf3d280 CW |
1338 | if (obj->base.write_domain) |
1339 | vma->exec_entry->flags |= EXEC_OBJECT_WRITE; | |
1340 | else | |
ed5982e6 DV |
1341 | obj->base.pending_read_domains |= obj->base.read_domains; |
1342 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1343 | |
5cf3d280 | 1344 | i915_vma_move_to_active(vma, req, vma->exec_entry->flags); |
ad778f89 | 1345 | eb_export_fence(obj, req, vma->exec_entry->flags); |
432e58ed CW |
1346 | } |
1347 | } | |
1348 | ||
ae662d31 | 1349 | static int |
b5321f30 | 1350 | i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req) |
ae662d31 | 1351 | { |
73dec95e TU |
1352 | u32 *cs; |
1353 | int i; | |
ae662d31 | 1354 | |
b5321f30 | 1355 | if (!IS_GEN7(req->i915) || req->engine->id != RCS) { |
9d662da8 DV |
1356 | DRM_DEBUG("sol reset is gen7/rcs only\n"); |
1357 | return -EINVAL; | |
1358 | } | |
ae662d31 | 1359 | |
73dec95e TU |
1360 | cs = intel_ring_begin(req, 4 * 3); |
1361 | if (IS_ERR(cs)) | |
1362 | return PTR_ERR(cs); | |
ae662d31 EA |
1363 | |
1364 | for (i = 0; i < 4; i++) { | |
73dec95e TU |
1365 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
1366 | *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); | |
1367 | *cs++ = 0; | |
ae662d31 EA |
1368 | } |
1369 | ||
73dec95e | 1370 | intel_ring_advance(req, cs); |
ae662d31 EA |
1371 | |
1372 | return 0; | |
1373 | } | |
1374 | ||
058d88c4 | 1375 | static struct i915_vma * |
0bc40be8 | 1376 | i915_gem_execbuffer_parse(struct intel_engine_cs *engine, |
71745376 | 1377 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, |
71745376 | 1378 | struct drm_i915_gem_object *batch_obj, |
59bfa124 | 1379 | struct eb_vmas *eb, |
71745376 BV |
1380 | u32 batch_start_offset, |
1381 | u32 batch_len, | |
17cabf57 | 1382 | bool is_master) |
71745376 | 1383 | { |
71745376 | 1384 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1385 | struct i915_vma *vma; |
71745376 BV |
1386 | int ret; |
1387 | ||
0bc40be8 | 1388 | shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool, |
17cabf57 | 1389 | PAGE_ALIGN(batch_len)); |
71745376 | 1390 | if (IS_ERR(shadow_batch_obj)) |
59bfa124 | 1391 | return ERR_CAST(shadow_batch_obj); |
71745376 | 1392 | |
33a051a5 CW |
1393 | ret = intel_engine_cmd_parser(engine, |
1394 | batch_obj, | |
1395 | shadow_batch_obj, | |
1396 | batch_start_offset, | |
1397 | batch_len, | |
1398 | is_master); | |
058d88c4 CW |
1399 | if (ret) { |
1400 | if (ret == -EACCES) /* unhandled chained batch */ | |
1401 | vma = NULL; | |
1402 | else | |
1403 | vma = ERR_PTR(ret); | |
1404 | goto out; | |
1405 | } | |
71745376 | 1406 | |
058d88c4 CW |
1407 | vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0); |
1408 | if (IS_ERR(vma)) | |
1409 | goto out; | |
de4e783a | 1410 | |
17cabf57 | 1411 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1412 | |
17cabf57 | 1413 | vma->exec_entry = shadow_exec_entry; |
de4e783a | 1414 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
25dc556a | 1415 | i915_gem_object_get(shadow_batch_obj); |
17cabf57 | 1416 | list_add_tail(&vma->exec_list, &eb->vmas); |
71745376 | 1417 | |
058d88c4 | 1418 | out: |
de4e783a | 1419 | i915_gem_object_unpin_pages(shadow_batch_obj); |
058d88c4 | 1420 | return vma; |
71745376 | 1421 | } |
5c6c6003 | 1422 | |
c8659efa CW |
1423 | static void |
1424 | add_to_client(struct drm_i915_gem_request *req, | |
1425 | struct drm_file *file) | |
1426 | { | |
1427 | req->file_priv = file->driver_priv; | |
1428 | list_add_tail(&req->client_link, &req->file_priv->mm.request_list); | |
1429 | } | |
1430 | ||
5b043f4e CW |
1431 | static int |
1432 | execbuf_submit(struct i915_execbuffer_params *params, | |
1433 | struct drm_i915_gem_execbuffer2 *args, | |
1434 | struct list_head *vmas) | |
78382593 | 1435 | { |
5f19e2bf | 1436 | u64 exec_start, exec_len; |
2f5945bc | 1437 | int ret; |
78382593 | 1438 | |
535fbe82 | 1439 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 | 1440 | if (ret) |
2f5945bc | 1441 | return ret; |
78382593 | 1442 | |
ba01cc93 | 1443 | ret = i915_switch_context(params->request); |
78382593 | 1444 | if (ret) |
2f5945bc | 1445 | return ret; |
78382593 | 1446 | |
ef0f411f KG |
1447 | if (args->flags & I915_EXEC_CONSTANTS_MASK) { |
1448 | DRM_DEBUG("I915_EXEC_CONSTANTS_* unsupported\n"); | |
2f5945bc | 1449 | return -EINVAL; |
78382593 OM |
1450 | } |
1451 | ||
78382593 | 1452 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
b5321f30 | 1453 | ret = i915_reset_gen7_sol_offsets(params->request); |
78382593 | 1454 | if (ret) |
2f5945bc | 1455 | return ret; |
78382593 OM |
1456 | } |
1457 | ||
5f19e2bf | 1458 | exec_len = args->batch_len; |
59bfa124 | 1459 | exec_start = params->batch->node.start + |
5f19e2bf JH |
1460 | params->args_batch_start_offset; |
1461 | ||
9d611c03 | 1462 | if (exec_len == 0) |
0b537272 | 1463 | exec_len = params->batch->size - params->args_batch_start_offset; |
9d611c03 | 1464 | |
803688ba CW |
1465 | ret = params->engine->emit_bb_start(params->request, |
1466 | exec_start, exec_len, | |
1467 | params->dispatch_flags); | |
2f5945bc CW |
1468 | if (ret) |
1469 | return ret; | |
78382593 | 1470 | |
8a8edb59 | 1471 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
78382593 | 1472 | |
2f5945bc | 1473 | return 0; |
78382593 OM |
1474 | } |
1475 | ||
a8ebba75 ZY |
1476 | /** |
1477 | * Find one BSD ring to dispatch the corresponding BSD command. | |
c80ff16e | 1478 | * The engine index is returned. |
a8ebba75 | 1479 | */ |
de1add36 | 1480 | static unsigned int |
c80ff16e CW |
1481 | gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, |
1482 | struct drm_file *file) | |
a8ebba75 | 1483 | { |
a8ebba75 ZY |
1484 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1485 | ||
de1add36 | 1486 | /* Check whether the file_priv has already selected one ring. */ |
6f633402 JL |
1487 | if ((int)file_priv->bsd_engine < 0) |
1488 | file_priv->bsd_engine = atomic_fetch_xor(1, | |
1489 | &dev_priv->mm.bsd_engine_dispatch_index); | |
d23db88c | 1490 | |
c80ff16e | 1491 | return file_priv->bsd_engine; |
d23db88c CW |
1492 | } |
1493 | ||
de1add36 TU |
1494 | #define I915_USER_RINGS (4) |
1495 | ||
117897f4 | 1496 | static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { |
de1add36 TU |
1497 | [I915_EXEC_DEFAULT] = RCS, |
1498 | [I915_EXEC_RENDER] = RCS, | |
1499 | [I915_EXEC_BLT] = BCS, | |
1500 | [I915_EXEC_BSD] = VCS, | |
1501 | [I915_EXEC_VEBOX] = VECS | |
1502 | }; | |
1503 | ||
f8ca0c07 DG |
1504 | static struct intel_engine_cs * |
1505 | eb_select_engine(struct drm_i915_private *dev_priv, | |
1506 | struct drm_file *file, | |
1507 | struct drm_i915_gem_execbuffer2 *args) | |
de1add36 TU |
1508 | { |
1509 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
f8ca0c07 | 1510 | struct intel_engine_cs *engine; |
de1add36 TU |
1511 | |
1512 | if (user_ring_id > I915_USER_RINGS) { | |
1513 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
f8ca0c07 | 1514 | return NULL; |
de1add36 TU |
1515 | } |
1516 | ||
1517 | if ((user_ring_id != I915_EXEC_BSD) && | |
1518 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1519 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1520 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
f8ca0c07 | 1521 | return NULL; |
de1add36 TU |
1522 | } |
1523 | ||
1524 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
1525 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
1526 | ||
1527 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
c80ff16e | 1528 | bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file); |
de1add36 TU |
1529 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && |
1530 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 1531 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
1532 | bsd_idx--; |
1533 | } else { | |
1534 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
1535 | bsd_idx); | |
f8ca0c07 | 1536 | return NULL; |
de1add36 TU |
1537 | } |
1538 | ||
3b3f1650 | 1539 | engine = dev_priv->engine[_VCS(bsd_idx)]; |
de1add36 | 1540 | } else { |
3b3f1650 | 1541 | engine = dev_priv->engine[user_ring_map[user_ring_id]]; |
de1add36 TU |
1542 | } |
1543 | ||
3b3f1650 | 1544 | if (!engine) { |
de1add36 | 1545 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); |
f8ca0c07 | 1546 | return NULL; |
de1add36 TU |
1547 | } |
1548 | ||
f8ca0c07 | 1549 | return engine; |
de1add36 TU |
1550 | } |
1551 | ||
54cf91dc CW |
1552 | static int |
1553 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1554 | struct drm_file *file, | |
1555 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1556 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1557 | { |
72e96d64 JL |
1558 | struct drm_i915_private *dev_priv = to_i915(dev); |
1559 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
27173f1f | 1560 | struct eb_vmas *eb; |
78a42377 | 1561 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
e2f80391 | 1562 | struct intel_engine_cs *engine; |
e2efd130 | 1563 | struct i915_gem_context *ctx; |
41bde553 | 1564 | struct i915_address_space *vm; |
5f19e2bf JH |
1565 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1566 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1567 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1568 | u32 dispatch_flags; |
fec0445c CW |
1569 | struct dma_fence *in_fence = NULL; |
1570 | struct sync_file *out_fence = NULL; | |
1571 | int out_fence_fd = -1; | |
78382593 | 1572 | int ret; |
ed5982e6 | 1573 | bool need_relocs; |
54cf91dc | 1574 | |
ed5982e6 | 1575 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1576 | return -EINVAL; |
432e58ed | 1577 | |
ad19f10b | 1578 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1579 | if (ret) |
1580 | return ret; | |
1581 | ||
8e004efc | 1582 | dispatch_flags = 0; |
d7d4eedd | 1583 | if (args->flags & I915_EXEC_SECURE) { |
b3ac9f25 | 1584 | if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) |
d7d4eedd CW |
1585 | return -EPERM; |
1586 | ||
8e004efc | 1587 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1588 | } |
b45305fc | 1589 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1590 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1591 | |
f8ca0c07 DG |
1592 | engine = eb_select_engine(dev_priv, file, args); |
1593 | if (!engine) | |
1594 | return -EINVAL; | |
54cf91dc CW |
1595 | |
1596 | if (args->buffer_count < 1) { | |
ff240199 | 1597 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1598 | return -EINVAL; |
1599 | } | |
54cf91dc | 1600 | |
a9ed33ca | 1601 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
4805fe82 | 1602 | if (!HAS_RESOURCE_STREAMER(dev_priv)) { |
a9ed33ca AJ |
1603 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); |
1604 | return -EINVAL; | |
1605 | } | |
e2f80391 | 1606 | if (engine->id != RCS) { |
a9ed33ca | 1607 | DRM_DEBUG("RS is not available on %s\n", |
e2f80391 | 1608 | engine->name); |
a9ed33ca AJ |
1609 | return -EINVAL; |
1610 | } | |
1611 | ||
1612 | dispatch_flags |= I915_DISPATCH_RS; | |
1613 | } | |
1614 | ||
fec0445c CW |
1615 | if (args->flags & I915_EXEC_FENCE_IN) { |
1616 | in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); | |
4a04e371 DCS |
1617 | if (!in_fence) |
1618 | return -EINVAL; | |
fec0445c CW |
1619 | } |
1620 | ||
1621 | if (args->flags & I915_EXEC_FENCE_OUT) { | |
1622 | out_fence_fd = get_unused_fd_flags(O_CLOEXEC); | |
1623 | if (out_fence_fd < 0) { | |
1624 | ret = out_fence_fd; | |
4a04e371 | 1625 | goto err_in_fence; |
fec0445c CW |
1626 | } |
1627 | } | |
1628 | ||
67d97da3 CW |
1629 | /* Take a local wakeref for preparing to dispatch the execbuf as |
1630 | * we expect to access the hardware fairly frequently in the | |
1631 | * process. Upon first dispatch, we acquire another prolonged | |
1632 | * wakeref that we hold until the GPU has been idle for at least | |
1633 | * 100ms. | |
1634 | */ | |
f65c9168 PZ |
1635 | intel_runtime_pm_get(dev_priv); |
1636 | ||
54cf91dc CW |
1637 | ret = i915_mutex_lock_interruptible(dev); |
1638 | if (ret) | |
1639 | goto pre_mutex_err; | |
1640 | ||
e2f80391 | 1641 | ctx = i915_gem_validate_context(dev, file, engine, ctx_id); |
72ad5c45 | 1642 | if (IS_ERR(ctx)) { |
d299cce7 | 1643 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1644 | ret = PTR_ERR(ctx); |
d299cce7 | 1645 | goto pre_mutex_err; |
935f38d6 | 1646 | } |
41bde553 | 1647 | |
9a6feaf0 | 1648 | i915_gem_context_get(ctx); |
41bde553 | 1649 | |
ae6c4806 DV |
1650 | if (ctx->ppgtt) |
1651 | vm = &ctx->ppgtt->base; | |
1652 | else | |
72e96d64 | 1653 | vm = &ggtt->base; |
d299cce7 | 1654 | |
5f19e2bf JH |
1655 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1656 | ||
d50415cc | 1657 | eb = eb_create(dev_priv, args); |
67731b87 | 1658 | if (eb == NULL) { |
9a6feaf0 | 1659 | i915_gem_context_put(ctx); |
67731b87 CW |
1660 | mutex_unlock(&dev->struct_mutex); |
1661 | ret = -ENOMEM; | |
1662 | goto pre_mutex_err; | |
1663 | } | |
1664 | ||
54cf91dc | 1665 | /* Look up object handles */ |
27173f1f | 1666 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1667 | if (ret) |
1668 | goto err; | |
54cf91dc | 1669 | |
6fe4f140 | 1670 | /* take note of the batch buffer before we might reorder the lists */ |
59bfa124 | 1671 | params->batch = eb_get_batch(eb); |
6fe4f140 | 1672 | |
54cf91dc | 1673 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1674 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
e2f80391 TU |
1675 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
1676 | &need_relocs); | |
54cf91dc CW |
1677 | if (ret) |
1678 | goto err; | |
1679 | ||
1680 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1681 | if (need_relocs) |
17601cbc | 1682 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1683 | if (ret) { |
1684 | if (ret == -EFAULT) { | |
e2f80391 TU |
1685 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, |
1686 | engine, | |
b1b38278 | 1687 | eb, exec, ctx); |
54cf91dc CW |
1688 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1689 | } | |
1690 | if (ret) | |
1691 | goto err; | |
1692 | } | |
1693 | ||
1694 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
59bfa124 | 1695 | if (params->batch->obj->base.pending_write_domain) { |
ff240199 | 1696 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1697 | ret = -EINVAL; |
1698 | goto err; | |
1699 | } | |
0b537272 CW |
1700 | if (args->batch_start_offset > params->batch->size || |
1701 | args->batch_len > params->batch->size - args->batch_start_offset) { | |
1702 | DRM_DEBUG("Attempting to use out-of-bounds batch\n"); | |
1703 | ret = -EINVAL; | |
1704 | goto err; | |
1705 | } | |
54cf91dc | 1706 | |
5f19e2bf | 1707 | params->args_batch_start_offset = args->batch_start_offset; |
41736a8e | 1708 | if (engine->needs_cmd_parser && args->batch_len) { |
59bfa124 CW |
1709 | struct i915_vma *vma; |
1710 | ||
1711 | vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry, | |
1712 | params->batch->obj, | |
1713 | eb, | |
1714 | args->batch_start_offset, | |
1715 | args->batch_len, | |
1716 | drm_is_current_master(file)); | |
1717 | if (IS_ERR(vma)) { | |
1718 | ret = PTR_ERR(vma); | |
78a42377 BV |
1719 | goto err; |
1720 | } | |
17cabf57 | 1721 | |
59bfa124 | 1722 | if (vma) { |
c7c7372e RP |
1723 | /* |
1724 | * Batch parsed and accepted: | |
1725 | * | |
1726 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1727 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1728 | * the dispatch_execbuffer implementations. We | |
1729 | * specifically don't want that set on batches the | |
1730 | * command parser has accepted. | |
1731 | */ | |
1732 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1733 | params->args_batch_start_offset = 0; |
59bfa124 | 1734 | params->batch = vma; |
c7c7372e | 1735 | } |
351e3db2 BV |
1736 | } |
1737 | ||
59bfa124 | 1738 | params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
78a42377 | 1739 | |
d7d4eedd CW |
1740 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1741 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1742 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1743 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
59bfa124 | 1744 | struct drm_i915_gem_object *obj = params->batch->obj; |
058d88c4 | 1745 | struct i915_vma *vma; |
59bfa124 | 1746 | |
da51a1e7 DV |
1747 | /* |
1748 | * So on first glance it looks freaky that we pin the batch here | |
1749 | * outside of the reservation loop. But: | |
1750 | * - The batch is already pinned into the relevant ppgtt, so we | |
1751 | * already have the backing storage fully allocated. | |
1752 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1753 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1754 | * fitting due to fragmentation. |
1755 | * So this is actually safe. | |
1756 | */ | |
058d88c4 CW |
1757 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); |
1758 | if (IS_ERR(vma)) { | |
1759 | ret = PTR_ERR(vma); | |
da51a1e7 | 1760 | goto err; |
058d88c4 | 1761 | } |
d7d4eedd | 1762 | |
058d88c4 | 1763 | params->batch = vma; |
59bfa124 | 1764 | } |
d7d4eedd | 1765 | |
0c8dac88 | 1766 | /* Allocate a request for this batch buffer nice and early. */ |
8e637178 CW |
1767 | params->request = i915_gem_request_alloc(engine, ctx); |
1768 | if (IS_ERR(params->request)) { | |
1769 | ret = PTR_ERR(params->request); | |
0c8dac88 | 1770 | goto err_batch_unpin; |
26827088 | 1771 | } |
0c8dac88 | 1772 | |
fec0445c CW |
1773 | if (in_fence) { |
1774 | ret = i915_gem_request_await_dma_fence(params->request, | |
1775 | in_fence); | |
1776 | if (ret < 0) | |
1777 | goto err_request; | |
1778 | } | |
1779 | ||
1780 | if (out_fence_fd != -1) { | |
1781 | out_fence = sync_file_create(¶ms->request->fence); | |
1782 | if (!out_fence) { | |
1783 | ret = -ENOMEM; | |
1784 | goto err_request; | |
1785 | } | |
1786 | } | |
1787 | ||
17f298cf CW |
1788 | /* Whilst this request exists, batch_obj will be on the |
1789 | * active_list, and so will hold the active reference. Only when this | |
1790 | * request is retired will the the batch_obj be moved onto the | |
1791 | * inactive_list and lose its active reference. Hence we do not need | |
1792 | * to explicitly hold another reference here. | |
1793 | */ | |
058d88c4 | 1794 | params->request->batch = params->batch; |
17f298cf | 1795 | |
5f19e2bf JH |
1796 | /* |
1797 | * Save assorted stuff away to pass through to *_submission(). | |
1798 | * NB: This data should be 'persistent' and not local as it will | |
1799 | * kept around beyond the duration of the IOCTL once the GPU | |
1800 | * scheduler arrives. | |
1801 | */ | |
1802 | params->dev = dev; | |
1803 | params->file = file; | |
4a570db5 | 1804 | params->engine = engine; |
5f19e2bf | 1805 | params->dispatch_flags = dispatch_flags; |
5f19e2bf JH |
1806 | params->ctx = ctx; |
1807 | ||
1cce8922 TU |
1808 | trace_i915_gem_request_queue(params->request, dispatch_flags); |
1809 | ||
5b043f4e | 1810 | ret = execbuf_submit(params, args, &eb->vmas); |
aa9b7810 | 1811 | err_request: |
17f298cf | 1812 | __i915_add_request(params->request, ret == 0); |
c8659efa CW |
1813 | add_to_client(params->request, file); |
1814 | ||
fec0445c CW |
1815 | if (out_fence) { |
1816 | if (ret == 0) { | |
1817 | fd_install(out_fence_fd, out_fence->file); | |
1818 | args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */ | |
1819 | args->rsvd2 |= (u64)out_fence_fd << 32; | |
1820 | out_fence_fd = -1; | |
1821 | } else { | |
1822 | fput(out_fence->file); | |
1823 | } | |
1824 | } | |
54cf91dc | 1825 | |
0c8dac88 | 1826 | err_batch_unpin: |
da51a1e7 DV |
1827 | /* |
1828 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1829 | * batch vma for correctness. For less ugly and less fragility this | |
1830 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1831 | * active. | |
1832 | */ | |
8e004efc | 1833 | if (dispatch_flags & I915_DISPATCH_SECURE) |
59bfa124 | 1834 | i915_vma_unpin(params->batch); |
54cf91dc | 1835 | err: |
41bde553 | 1836 | /* the request owns the ref now */ |
9a6feaf0 | 1837 | i915_gem_context_put(ctx); |
67731b87 | 1838 | eb_destroy(eb); |
54cf91dc CW |
1839 | |
1840 | mutex_unlock(&dev->struct_mutex); | |
1841 | ||
1842 | pre_mutex_err: | |
f65c9168 PZ |
1843 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1844 | * is really idle. */ | |
1845 | intel_runtime_pm_put(dev_priv); | |
fec0445c CW |
1846 | if (out_fence_fd != -1) |
1847 | put_unused_fd(out_fence_fd); | |
4a04e371 | 1848 | err_in_fence: |
fec0445c | 1849 | dma_fence_put(in_fence); |
54cf91dc CW |
1850 | return ret; |
1851 | } | |
1852 | ||
1853 | /* | |
1854 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1855 | * list array and passes it to the real function. | |
1856 | */ | |
1857 | int | |
1858 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1859 | struct drm_file *file) | |
1860 | { | |
1861 | struct drm_i915_gem_execbuffer *args = data; | |
1862 | struct drm_i915_gem_execbuffer2 exec2; | |
1863 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1864 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1865 | int ret, i; | |
1866 | ||
54cf91dc | 1867 | if (args->buffer_count < 1) { |
ff240199 | 1868 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1869 | return -EINVAL; |
1870 | } | |
1871 | ||
1872 | /* Copy in the exec list from userland */ | |
1873 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1874 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1875 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1876 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1877 | args->buffer_count); |
1878 | drm_free_large(exec_list); | |
1879 | drm_free_large(exec2_list); | |
1880 | return -ENOMEM; | |
1881 | } | |
1882 | ret = copy_from_user(exec_list, | |
3ed605bc | 1883 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1884 | sizeof(*exec_list) * args->buffer_count); |
1885 | if (ret != 0) { | |
ff240199 | 1886 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1887 | args->buffer_count, ret); |
1888 | drm_free_large(exec_list); | |
1889 | drm_free_large(exec2_list); | |
1890 | return -EFAULT; | |
1891 | } | |
1892 | ||
1893 | for (i = 0; i < args->buffer_count; i++) { | |
1894 | exec2_list[i].handle = exec_list[i].handle; | |
1895 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1896 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1897 | exec2_list[i].alignment = exec_list[i].alignment; | |
1898 | exec2_list[i].offset = exec_list[i].offset; | |
f0836b72 | 1899 | if (INTEL_GEN(to_i915(dev)) < 4) |
54cf91dc CW |
1900 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
1901 | else | |
1902 | exec2_list[i].flags = 0; | |
1903 | } | |
1904 | ||
1905 | exec2.buffers_ptr = args->buffers_ptr; | |
1906 | exec2.buffer_count = args->buffer_count; | |
1907 | exec2.batch_start_offset = args->batch_start_offset; | |
1908 | exec2.batch_len = args->batch_len; | |
1909 | exec2.DR1 = args->DR1; | |
1910 | exec2.DR4 = args->DR4; | |
1911 | exec2.num_cliprects = args->num_cliprects; | |
1912 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1913 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1914 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1915 | |
41bde553 | 1916 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1917 | if (!ret) { |
9aab8bff | 1918 | struct drm_i915_gem_exec_object __user *user_exec_list = |
3ed605bc | 1919 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff | 1920 | |
54cf91dc | 1921 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 1922 | for (i = 0; i < args->buffer_count; i++) { |
934acce3 MW |
1923 | exec2_list[i].offset = |
1924 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1925 | ret = __copy_to_user(&user_exec_list[i].offset, |
1926 | &exec2_list[i].offset, | |
1927 | sizeof(user_exec_list[i].offset)); | |
1928 | if (ret) { | |
1929 | ret = -EFAULT; | |
1930 | DRM_DEBUG("failed to copy %d exec entries " | |
1931 | "back to user (%d)\n", | |
1932 | args->buffer_count, ret); | |
1933 | break; | |
1934 | } | |
54cf91dc CW |
1935 | } |
1936 | } | |
1937 | ||
1938 | drm_free_large(exec_list); | |
1939 | drm_free_large(exec2_list); | |
1940 | return ret; | |
1941 | } | |
1942 | ||
1943 | int | |
1944 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1945 | struct drm_file *file) | |
1946 | { | |
1947 | struct drm_i915_gem_execbuffer2 *args = data; | |
1948 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1949 | int ret; | |
1950 | ||
ed8cd3b2 XW |
1951 | if (args->buffer_count < 1 || |
1952 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1953 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1954 | return -EINVAL; |
1955 | } | |
1956 | ||
f2a85e19 CW |
1957 | exec2_list = drm_malloc_gfp(args->buffer_count, |
1958 | sizeof(*exec2_list), | |
1959 | GFP_TEMPORARY); | |
54cf91dc | 1960 | if (exec2_list == NULL) { |
ff240199 | 1961 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1962 | args->buffer_count); |
1963 | return -ENOMEM; | |
1964 | } | |
1965 | ret = copy_from_user(exec2_list, | |
3ed605bc | 1966 | u64_to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1967 | sizeof(*exec2_list) * args->buffer_count); |
1968 | if (ret != 0) { | |
ff240199 | 1969 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1970 | args->buffer_count, ret); |
1971 | drm_free_large(exec2_list); | |
1972 | return -EFAULT; | |
1973 | } | |
1974 | ||
41bde553 | 1975 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1976 | if (!ret) { |
1977 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1978 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
3ed605bc | 1979 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff CW |
1980 | int i; |
1981 | ||
1982 | for (i = 0; i < args->buffer_count; i++) { | |
934acce3 MW |
1983 | exec2_list[i].offset = |
1984 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1985 | ret = __copy_to_user(&user_exec_list[i].offset, |
1986 | &exec2_list[i].offset, | |
1987 | sizeof(user_exec_list[i].offset)); | |
1988 | if (ret) { | |
1989 | ret = -EFAULT; | |
1990 | DRM_DEBUG("failed to copy %d exec entries " | |
1991 | "back to user\n", | |
1992 | args->buffer_count); | |
1993 | break; | |
1994 | } | |
54cf91dc CW |
1995 | } |
1996 | } | |
1997 | ||
1998 | drm_free_large(exec2_list); | |
1999 | return ret; | |
2000 | } |