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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | #include "i915_trace.h" | |
34 | #include "intel_drv.h" | |
f45b5557 | 35 | #include <linux/dma_remapping.h> |
54cf91dc CW |
36 | |
37 | struct change_domains { | |
38 | uint32_t invalidate_domains; | |
39 | uint32_t flush_domains; | |
40 | uint32_t flush_rings; | |
c59a333f | 41 | uint32_t flips; |
54cf91dc CW |
42 | }; |
43 | ||
44 | /* | |
45 | * Set the next domain for the specified object. This | |
46 | * may not actually perform the necessary flushing/invaliding though, | |
47 | * as that may want to be batched with other set_domain operations | |
48 | * | |
49 | * This is (we hope) the only really tricky part of gem. The goal | |
50 | * is fairly simple -- track which caches hold bits of the object | |
51 | * and make sure they remain coherent. A few concrete examples may | |
52 | * help to explain how it works. For shorthand, we use the notation | |
53 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
54 | * a pair of read and write domain masks. | |
55 | * | |
56 | * Case 1: the batch buffer | |
57 | * | |
58 | * 1. Allocated | |
59 | * 2. Written by CPU | |
60 | * 3. Mapped to GTT | |
61 | * 4. Read by GPU | |
62 | * 5. Unmapped from GTT | |
63 | * 6. Freed | |
64 | * | |
65 | * Let's take these a step at a time | |
66 | * | |
67 | * 1. Allocated | |
68 | * Pages allocated from the kernel may still have | |
69 | * cache contents, so we set them to (CPU, CPU) always. | |
70 | * 2. Written by CPU (using pwrite) | |
71 | * The pwrite function calls set_domain (CPU, CPU) and | |
72 | * this function does nothing (as nothing changes) | |
73 | * 3. Mapped by GTT | |
74 | * This function asserts that the object is not | |
75 | * currently in any GPU-based read or write domains | |
76 | * 4. Read by GPU | |
77 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
78 | * As write_domain is zero, this function adds in the | |
79 | * current read domains (CPU+COMMAND, 0). | |
80 | * flush_domains is set to CPU. | |
81 | * invalidate_domains is set to COMMAND | |
82 | * clflush is run to get data out of the CPU caches | |
83 | * then i915_dev_set_domain calls i915_gem_flush to | |
84 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
85 | * 5. Unmapped from GTT | |
86 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
87 | * flush_domains and invalidate_domains end up both zero | |
88 | * so no flushing/invalidating happens | |
89 | * 6. Freed | |
90 | * yay, done | |
91 | * | |
92 | * Case 2: The shared render buffer | |
93 | * | |
94 | * 1. Allocated | |
95 | * 2. Mapped to GTT | |
96 | * 3. Read/written by GPU | |
97 | * 4. set_domain to (CPU,CPU) | |
98 | * 5. Read/written by CPU | |
99 | * 6. Read/written by GPU | |
100 | * | |
101 | * 1. Allocated | |
102 | * Same as last example, (CPU, CPU) | |
103 | * 2. Mapped to GTT | |
104 | * Nothing changes (assertions find that it is not in the GPU) | |
105 | * 3. Read/written by GPU | |
106 | * execbuffer calls set_domain (RENDER, RENDER) | |
107 | * flush_domains gets CPU | |
108 | * invalidate_domains gets GPU | |
109 | * clflush (obj) | |
110 | * MI_FLUSH and drm_agp_chipset_flush | |
111 | * 4. set_domain (CPU, CPU) | |
112 | * flush_domains gets GPU | |
113 | * invalidate_domains gets CPU | |
114 | * wait_rendering (obj) to make sure all drawing is complete. | |
115 | * This will include an MI_FLUSH to get the data from GPU | |
116 | * to memory | |
117 | * clflush (obj) to invalidate the CPU cache | |
118 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
119 | * 5. Read/written by CPU | |
120 | * cache lines are loaded and dirtied | |
121 | * 6. Read written by GPU | |
122 | * Same as last GPU access | |
123 | * | |
124 | * Case 3: The constant buffer | |
125 | * | |
126 | * 1. Allocated | |
127 | * 2. Written by CPU | |
128 | * 3. Read by GPU | |
129 | * 4. Updated (written) by CPU again | |
130 | * 5. Read by GPU | |
131 | * | |
132 | * 1. Allocated | |
133 | * (CPU, CPU) | |
134 | * 2. Written by CPU | |
135 | * (CPU, CPU) | |
136 | * 3. Read by GPU | |
137 | * (CPU+RENDER, 0) | |
138 | * flush_domains = CPU | |
139 | * invalidate_domains = RENDER | |
140 | * clflush (obj) | |
141 | * MI_FLUSH | |
142 | * drm_agp_chipset_flush | |
143 | * 4. Updated (written) by CPU again | |
144 | * (CPU, CPU) | |
145 | * flush_domains = 0 (no previous write domain) | |
146 | * invalidate_domains = 0 (no new read domains) | |
147 | * 5. Read by GPU | |
148 | * (CPU+RENDER, 0) | |
149 | * flush_domains = CPU | |
150 | * invalidate_domains = RENDER | |
151 | * clflush (obj) | |
152 | * MI_FLUSH | |
153 | * drm_agp_chipset_flush | |
154 | */ | |
155 | static void | |
156 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, | |
157 | struct intel_ring_buffer *ring, | |
158 | struct change_domains *cd) | |
159 | { | |
160 | uint32_t invalidate_domains = 0, flush_domains = 0; | |
161 | ||
162 | /* | |
163 | * If the object isn't moving to a new write domain, | |
164 | * let the object stay in multiple read domains | |
165 | */ | |
166 | if (obj->base.pending_write_domain == 0) | |
167 | obj->base.pending_read_domains |= obj->base.read_domains; | |
168 | ||
169 | /* | |
170 | * Flush the current write domain if | |
171 | * the new read domains don't match. Invalidate | |
172 | * any read domains which differ from the old | |
173 | * write domain | |
174 | */ | |
175 | if (obj->base.write_domain && | |
176 | (((obj->base.write_domain != obj->base.pending_read_domains || | |
177 | obj->ring != ring)) || | |
178 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { | |
179 | flush_domains |= obj->base.write_domain; | |
180 | invalidate_domains |= | |
181 | obj->base.pending_read_domains & ~obj->base.write_domain; | |
182 | } | |
183 | /* | |
184 | * Invalidate any read caches which may have | |
185 | * stale data. That is, any new read domains. | |
186 | */ | |
187 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; | |
188 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) | |
189 | i915_gem_clflush_object(obj); | |
190 | ||
c59a333f CW |
191 | if (obj->base.pending_write_domain) |
192 | cd->flips |= atomic_read(&obj->pending_flip); | |
193 | ||
54cf91dc CW |
194 | /* The actual obj->write_domain will be updated with |
195 | * pending_write_domain after we emit the accumulated flush for all | |
196 | * of our domain changes in execbuffers (which clears objects' | |
197 | * write_domains). So if we have a current write domain that we | |
198 | * aren't changing, set pending_write_domain to that. | |
199 | */ | |
200 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) | |
201 | obj->base.pending_write_domain = obj->base.write_domain; | |
202 | ||
203 | cd->invalidate_domains |= invalidate_domains; | |
204 | cd->flush_domains |= flush_domains; | |
205 | if (flush_domains & I915_GEM_GPU_DOMAINS) | |
96154f2f | 206 | cd->flush_rings |= intel_ring_flag(obj->ring); |
54cf91dc | 207 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
96154f2f | 208 | cd->flush_rings |= intel_ring_flag(ring); |
54cf91dc CW |
209 | } |
210 | ||
67731b87 CW |
211 | struct eb_objects { |
212 | int and; | |
213 | struct hlist_head buckets[0]; | |
214 | }; | |
215 | ||
216 | static struct eb_objects * | |
217 | eb_create(int size) | |
218 | { | |
219 | struct eb_objects *eb; | |
220 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
221 | while (count > size) | |
222 | count >>= 1; | |
223 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
224 | sizeof(struct eb_objects), | |
225 | GFP_KERNEL); | |
226 | if (eb == NULL) | |
227 | return eb; | |
228 | ||
229 | eb->and = count - 1; | |
230 | return eb; | |
231 | } | |
232 | ||
233 | static void | |
234 | eb_reset(struct eb_objects *eb) | |
235 | { | |
236 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
237 | } | |
238 | ||
239 | static void | |
240 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
241 | { | |
242 | hlist_add_head(&obj->exec_node, | |
243 | &eb->buckets[obj->exec_handle & eb->and]); | |
244 | } | |
245 | ||
246 | static struct drm_i915_gem_object * | |
247 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
248 | { | |
249 | struct hlist_head *head; | |
250 | struct hlist_node *node; | |
251 | struct drm_i915_gem_object *obj; | |
252 | ||
253 | head = &eb->buckets[handle & eb->and]; | |
254 | hlist_for_each(node, head) { | |
255 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
256 | if (obj->exec_handle == handle) | |
257 | return obj; | |
258 | } | |
259 | ||
260 | return NULL; | |
261 | } | |
262 | ||
263 | static void | |
264 | eb_destroy(struct eb_objects *eb) | |
265 | { | |
266 | kfree(eb); | |
267 | } | |
268 | ||
54cf91dc CW |
269 | static int |
270 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 271 | struct eb_objects *eb, |
54cf91dc CW |
272 | struct drm_i915_gem_relocation_entry *reloc) |
273 | { | |
274 | struct drm_device *dev = obj->base.dev; | |
275 | struct drm_gem_object *target_obj; | |
276 | uint32_t target_offset; | |
277 | int ret = -EINVAL; | |
278 | ||
67731b87 CW |
279 | /* we've already hold a reference to all valid objects */ |
280 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
281 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
282 | return -ENOENT; |
283 | ||
284 | target_offset = to_intel_bo(target_obj)->gtt_offset; | |
285 | ||
54cf91dc CW |
286 | /* The target buffer should have appeared before us in the |
287 | * exec_object list, so it should have a GTT space bound by now. | |
288 | */ | |
b8f7ab17 | 289 | if (unlikely(target_offset == 0)) { |
54cf91dc CW |
290 | DRM_ERROR("No GTT space found for object %d\n", |
291 | reloc->target_handle); | |
67731b87 | 292 | return ret; |
54cf91dc CW |
293 | } |
294 | ||
295 | /* Validate that the target is in a valid r/w GPU domain */ | |
b8f7ab17 | 296 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
54cf91dc CW |
297 | DRM_ERROR("reloc with multiple write domains: " |
298 | "obj %p target %d offset %d " | |
299 | "read %08x write %08x", | |
300 | obj, reloc->target_handle, | |
301 | (int) reloc->offset, | |
302 | reloc->read_domains, | |
303 | reloc->write_domain); | |
67731b87 | 304 | return ret; |
54cf91dc | 305 | } |
b8f7ab17 | 306 | if (unlikely((reloc->write_domain | reloc->read_domains) & I915_GEM_DOMAIN_CPU)) { |
54cf91dc CW |
307 | DRM_ERROR("reloc with read/write CPU domains: " |
308 | "obj %p target %d offset %d " | |
309 | "read %08x write %08x", | |
310 | obj, reloc->target_handle, | |
311 | (int) reloc->offset, | |
312 | reloc->read_domains, | |
313 | reloc->write_domain); | |
67731b87 | 314 | return ret; |
54cf91dc | 315 | } |
b8f7ab17 CW |
316 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
317 | reloc->write_domain != target_obj->pending_write_domain)) { | |
54cf91dc CW |
318 | DRM_ERROR("Write domain conflict: " |
319 | "obj %p target %d offset %d " | |
320 | "new %08x old %08x\n", | |
321 | obj, reloc->target_handle, | |
322 | (int) reloc->offset, | |
323 | reloc->write_domain, | |
324 | target_obj->pending_write_domain); | |
67731b87 | 325 | return ret; |
54cf91dc CW |
326 | } |
327 | ||
328 | target_obj->pending_read_domains |= reloc->read_domains; | |
329 | target_obj->pending_write_domain |= reloc->write_domain; | |
330 | ||
331 | /* If the relocation already has the right value in it, no | |
332 | * more work needs to be done. | |
333 | */ | |
334 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 335 | return 0; |
54cf91dc CW |
336 | |
337 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 338 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
54cf91dc CW |
339 | DRM_ERROR("Relocation beyond object bounds: " |
340 | "obj %p target %d offset %d size %d.\n", | |
341 | obj, reloc->target_handle, | |
342 | (int) reloc->offset, | |
343 | (int) obj->base.size); | |
67731b87 | 344 | return ret; |
54cf91dc | 345 | } |
b8f7ab17 | 346 | if (unlikely(reloc->offset & 3)) { |
54cf91dc CW |
347 | DRM_ERROR("Relocation not 4-byte aligned: " |
348 | "obj %p target %d offset %d.\n", | |
349 | obj, reloc->target_handle, | |
350 | (int) reloc->offset); | |
67731b87 | 351 | return ret; |
54cf91dc CW |
352 | } |
353 | ||
54cf91dc CW |
354 | reloc->delta += target_offset; |
355 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
356 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; | |
357 | char *vaddr; | |
358 | ||
359 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); | |
360 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
361 | kunmap_atomic(vaddr); | |
362 | } else { | |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
364 | uint32_t __iomem *reloc_entry; | |
365 | void __iomem *reloc_page; | |
366 | ||
d4aeee77 CW |
367 | /* We can't wait for rendering with pagefaults disabled */ |
368 | if (obj->active && in_atomic()) | |
369 | return -EFAULT; | |
370 | ||
54cf91dc CW |
371 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
372 | if (ret) | |
67731b87 | 373 | return ret; |
54cf91dc CW |
374 | |
375 | /* Map the page containing the relocation we're going to perform. */ | |
376 | reloc->offset += obj->gtt_offset; | |
377 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
378 | reloc->offset & PAGE_MASK); | |
379 | reloc_entry = (uint32_t __iomem *) | |
380 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
381 | iowrite32(reloc->delta, reloc_entry); | |
382 | io_mapping_unmap_atomic(reloc_page); | |
383 | } | |
384 | ||
385 | /* and update the user's relocation entry */ | |
386 | reloc->presumed_offset = target_offset; | |
387 | ||
67731b87 | 388 | return 0; |
54cf91dc CW |
389 | } |
390 | ||
391 | static int | |
392 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 393 | struct eb_objects *eb) |
54cf91dc CW |
394 | { |
395 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
6fe4f140 | 396 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
397 | int i, ret; |
398 | ||
399 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
400 | for (i = 0; i < entry->relocation_count; i++) { | |
401 | struct drm_i915_gem_relocation_entry reloc; | |
402 | ||
403 | if (__copy_from_user_inatomic(&reloc, | |
404 | user_relocs+i, | |
405 | sizeof(reloc))) | |
406 | return -EFAULT; | |
407 | ||
6fe4f140 | 408 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc); |
54cf91dc CW |
409 | if (ret) |
410 | return ret; | |
411 | ||
412 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
413 | &reloc.presumed_offset, | |
414 | sizeof(reloc.presumed_offset))) | |
415 | return -EFAULT; | |
416 | } | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | static int | |
422 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 423 | struct eb_objects *eb, |
54cf91dc CW |
424 | struct drm_i915_gem_relocation_entry *relocs) |
425 | { | |
6fe4f140 | 426 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
427 | int i, ret; |
428 | ||
429 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 430 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
431 | if (ret) |
432 | return ret; | |
433 | } | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | static int | |
439 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 440 | struct eb_objects *eb, |
6fe4f140 | 441 | struct list_head *objects) |
54cf91dc | 442 | { |
432e58ed | 443 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
444 | int ret = 0; |
445 | ||
446 | /* This is the fast path and we cannot handle a pagefault whilst | |
447 | * holding the struct mutex lest the user pass in the relocations | |
448 | * contained within a mmaped bo. For in such a case we, the page | |
449 | * fault handler would call i915_gem_fault() and we would try to | |
450 | * acquire the struct mutex again. Obviously this is bad and so | |
451 | * lockdep complains vehemently. | |
452 | */ | |
453 | pagefault_disable(); | |
432e58ed | 454 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 455 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 456 | if (ret) |
d4aeee77 | 457 | break; |
54cf91dc | 458 | } |
d4aeee77 | 459 | pagefault_enable(); |
54cf91dc | 460 | |
d4aeee77 | 461 | return ret; |
54cf91dc CW |
462 | } |
463 | ||
1690e1eb CW |
464 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
465 | ||
466 | static int | |
467 | pin_and_fence_object(struct drm_i915_gem_object *obj, | |
468 | struct intel_ring_buffer *ring) | |
469 | { | |
470 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
471 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
472 | bool need_fence, need_mappable; | |
473 | int ret; | |
474 | ||
475 | need_fence = | |
476 | has_fenced_gpu_access && | |
477 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
478 | obj->tiling_mode != I915_TILING_NONE; | |
479 | need_mappable = | |
480 | entry->relocation_count ? true : need_fence; | |
481 | ||
482 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable); | |
483 | if (ret) | |
484 | return ret; | |
485 | ||
486 | if (has_fenced_gpu_access) { | |
487 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
488 | if (obj->tiling_mode) { | |
489 | ret = i915_gem_object_get_fence(obj, ring); | |
490 | if (ret) | |
491 | goto err_unpin; | |
492 | ||
493 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
494 | i915_gem_object_pin_fence(obj); | |
495 | } else { | |
496 | ret = i915_gem_object_put_fence(obj); | |
497 | if (ret) | |
498 | goto err_unpin; | |
499 | } | |
500 | } | |
501 | obj->pending_fenced_gpu_access = need_fence; | |
502 | } | |
503 | ||
504 | entry->offset = obj->gtt_offset; | |
505 | return 0; | |
506 | ||
507 | err_unpin: | |
508 | i915_gem_object_unpin(obj); | |
509 | return ret; | |
510 | } | |
511 | ||
54cf91dc | 512 | static int |
d9e86c0e | 513 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 514 | struct drm_file *file, |
6fe4f140 | 515 | struct list_head *objects) |
54cf91dc | 516 | { |
432e58ed | 517 | struct drm_i915_gem_object *obj; |
432e58ed | 518 | int ret, retry; |
9b3826bf | 519 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
6fe4f140 CW |
520 | struct list_head ordered_objects; |
521 | ||
522 | INIT_LIST_HEAD(&ordered_objects); | |
523 | while (!list_empty(objects)) { | |
524 | struct drm_i915_gem_exec_object2 *entry; | |
525 | bool need_fence, need_mappable; | |
526 | ||
527 | obj = list_first_entry(objects, | |
528 | struct drm_i915_gem_object, | |
529 | exec_list); | |
530 | entry = obj->exec_entry; | |
531 | ||
532 | need_fence = | |
533 | has_fenced_gpu_access && | |
534 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
535 | obj->tiling_mode != I915_TILING_NONE; | |
536 | need_mappable = | |
537 | entry->relocation_count ? true : need_fence; | |
538 | ||
539 | if (need_mappable) | |
540 | list_move(&obj->exec_list, &ordered_objects); | |
541 | else | |
542 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
543 | |
544 | obj->base.pending_read_domains = 0; | |
545 | obj->base.pending_write_domain = 0; | |
6fe4f140 CW |
546 | } |
547 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
548 | |
549 | /* Attempt to pin all of the buffers into the GTT. | |
550 | * This is done in 3 phases: | |
551 | * | |
552 | * 1a. Unbind all objects that do not match the GTT constraints for | |
553 | * the execbuffer (fenceable, mappable, alignment etc). | |
554 | * 1b. Increment pin count for already bound objects. | |
555 | * 2. Bind new objects. | |
556 | * 3. Decrement pin count. | |
557 | * | |
558 | * This avoid unnecessary unbinding of later objects in order to makr | |
559 | * room for the earlier objects *unless* we need to defragment. | |
560 | */ | |
561 | retry = 0; | |
562 | do { | |
563 | ret = 0; | |
564 | ||
565 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 566 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 567 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 568 | bool need_fence, need_mappable; |
1690e1eb | 569 | |
6fe4f140 | 570 | if (!obj->gtt_space) |
54cf91dc CW |
571 | continue; |
572 | ||
573 | need_fence = | |
9b3826bf | 574 | has_fenced_gpu_access && |
54cf91dc CW |
575 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
576 | obj->tiling_mode != I915_TILING_NONE; | |
577 | need_mappable = | |
578 | entry->relocation_count ? true : need_fence; | |
579 | ||
580 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
581 | (need_mappable && !obj->map_and_fenceable)) | |
582 | ret = i915_gem_object_unbind(obj); | |
583 | else | |
1690e1eb | 584 | ret = pin_and_fence_object(obj, ring); |
432e58ed | 585 | if (ret) |
54cf91dc | 586 | goto err; |
54cf91dc CW |
587 | } |
588 | ||
589 | /* Bind fresh objects */ | |
432e58ed | 590 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
591 | if (obj->gtt_space) |
592 | continue; | |
54cf91dc | 593 | |
1690e1eb CW |
594 | ret = pin_and_fence_object(obj, ring); |
595 | if (ret) { | |
596 | int ret_ignore; | |
597 | ||
598 | /* This can potentially raise a harmless | |
599 | * -EINVAL if we failed to bind in the above | |
600 | * call. It cannot raise -EINTR since we know | |
601 | * that the bo is freshly bound and so will | |
602 | * not need to be flushed or waited upon. | |
603 | */ | |
604 | ret_ignore = i915_gem_object_unbind(obj); | |
605 | (void)ret_ignore; | |
606 | WARN_ON(obj->gtt_space); | |
607 | break; | |
54cf91dc | 608 | } |
54cf91dc CW |
609 | } |
610 | ||
432e58ed CW |
611 | /* Decrement pin count for bound objects */ |
612 | list_for_each_entry(obj, objects, exec_list) { | |
1690e1eb CW |
613 | struct drm_i915_gem_exec_object2 *entry; |
614 | ||
615 | if (!obj->gtt_space) | |
616 | continue; | |
617 | ||
618 | entry = obj->exec_entry; | |
619 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
620 | i915_gem_object_unpin_fence(obj); | |
621 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
622 | } | |
623 | ||
624 | i915_gem_object_unpin(obj); | |
54cf91dc CW |
625 | } |
626 | ||
627 | if (ret != -ENOSPC || retry > 1) | |
628 | return ret; | |
629 | ||
630 | /* First attempt, just clear anything that is purgeable. | |
631 | * Second attempt, clear the entire GTT. | |
632 | */ | |
d9e86c0e | 633 | ret = i915_gem_evict_everything(ring->dev, retry == 0); |
54cf91dc CW |
634 | if (ret) |
635 | return ret; | |
636 | ||
637 | retry++; | |
638 | } while (1); | |
432e58ed CW |
639 | |
640 | err: | |
1690e1eb CW |
641 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
642 | struct drm_i915_gem_exec_object2 *entry; | |
643 | ||
644 | if (!obj->gtt_space) | |
645 | continue; | |
646 | ||
647 | entry = obj->exec_entry; | |
648 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
649 | i915_gem_object_unpin_fence(obj); | |
650 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
651 | } | |
432e58ed | 652 | |
1690e1eb | 653 | i915_gem_object_unpin(obj); |
432e58ed CW |
654 | } |
655 | ||
656 | return ret; | |
54cf91dc CW |
657 | } |
658 | ||
659 | static int | |
660 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
661 | struct drm_file *file, | |
d9e86c0e | 662 | struct intel_ring_buffer *ring, |
432e58ed | 663 | struct list_head *objects, |
67731b87 | 664 | struct eb_objects *eb, |
432e58ed | 665 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
666 | int count) |
667 | { | |
668 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 669 | struct drm_i915_gem_object *obj; |
dd6864a4 | 670 | int *reloc_offset; |
54cf91dc CW |
671 | int i, total, ret; |
672 | ||
67731b87 | 673 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 674 | while (!list_empty(objects)) { |
67731b87 CW |
675 | obj = list_first_entry(objects, |
676 | struct drm_i915_gem_object, | |
677 | exec_list); | |
678 | list_del_init(&obj->exec_list); | |
679 | drm_gem_object_unreference(&obj->base); | |
680 | } | |
681 | ||
54cf91dc CW |
682 | mutex_unlock(&dev->struct_mutex); |
683 | ||
684 | total = 0; | |
685 | for (i = 0; i < count; i++) | |
432e58ed | 686 | total += exec[i].relocation_count; |
54cf91dc | 687 | |
dd6864a4 | 688 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 689 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
690 | if (reloc == NULL || reloc_offset == NULL) { |
691 | drm_free_large(reloc); | |
692 | drm_free_large(reloc_offset); | |
54cf91dc CW |
693 | mutex_lock(&dev->struct_mutex); |
694 | return -ENOMEM; | |
695 | } | |
696 | ||
697 | total = 0; | |
698 | for (i = 0; i < count; i++) { | |
699 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
700 | ||
432e58ed | 701 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
702 | |
703 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 704 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
705 | ret = -EFAULT; |
706 | mutex_lock(&dev->struct_mutex); | |
707 | goto err; | |
708 | } | |
709 | ||
dd6864a4 | 710 | reloc_offset[i] = total; |
432e58ed | 711 | total += exec[i].relocation_count; |
54cf91dc CW |
712 | } |
713 | ||
714 | ret = i915_mutex_lock_interruptible(dev); | |
715 | if (ret) { | |
716 | mutex_lock(&dev->struct_mutex); | |
717 | goto err; | |
718 | } | |
719 | ||
67731b87 | 720 | /* reacquire the objects */ |
67731b87 CW |
721 | eb_reset(eb); |
722 | for (i = 0; i < count; i++) { | |
67731b87 CW |
723 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
724 | exec[i].handle)); | |
c8725226 | 725 | if (&obj->base == NULL) { |
67731b87 CW |
726 | DRM_ERROR("Invalid object handle %d at index %d\n", |
727 | exec[i].handle, i); | |
728 | ret = -ENOENT; | |
729 | goto err; | |
730 | } | |
731 | ||
732 | list_add_tail(&obj->exec_list, objects); | |
733 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 734 | obj->exec_entry = &exec[i]; |
67731b87 CW |
735 | eb_add_object(eb, obj); |
736 | } | |
737 | ||
6fe4f140 | 738 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
739 | if (ret) |
740 | goto err; | |
741 | ||
432e58ed | 742 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 743 | int offset = obj->exec_entry - exec; |
67731b87 | 744 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 745 | reloc + reloc_offset[offset]); |
54cf91dc CW |
746 | if (ret) |
747 | goto err; | |
54cf91dc CW |
748 | } |
749 | ||
750 | /* Leave the user relocations as are, this is the painfully slow path, | |
751 | * and we want to avoid the complication of dropping the lock whilst | |
752 | * having buffers reserved in the aperture and so causing spurious | |
753 | * ENOSPC for random operations. | |
754 | */ | |
755 | ||
756 | err: | |
757 | drm_free_large(reloc); | |
dd6864a4 | 758 | drm_free_large(reloc_offset); |
54cf91dc CW |
759 | return ret; |
760 | } | |
761 | ||
88241785 | 762 | static int |
54cf91dc CW |
763 | i915_gem_execbuffer_flush(struct drm_device *dev, |
764 | uint32_t invalidate_domains, | |
765 | uint32_t flush_domains, | |
766 | uint32_t flush_rings) | |
767 | { | |
768 | drm_i915_private_t *dev_priv = dev->dev_private; | |
88241785 | 769 | int i, ret; |
54cf91dc CW |
770 | |
771 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
772 | intel_gtt_chipset_flush(); | |
773 | ||
63256ec5 CW |
774 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
775 | wmb(); | |
776 | ||
54cf91dc | 777 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
1ec14ad3 | 778 | for (i = 0; i < I915_NUM_RINGS; i++) |
88241785 | 779 | if (flush_rings & (1 << i)) { |
db53a302 | 780 | ret = i915_gem_flush_ring(&dev_priv->ring[i], |
88241785 CW |
781 | invalidate_domains, |
782 | flush_domains); | |
783 | if (ret) | |
784 | return ret; | |
785 | } | |
54cf91dc | 786 | } |
88241785 CW |
787 | |
788 | return 0; | |
54cf91dc CW |
789 | } |
790 | ||
f45b5557 ED |
791 | static bool |
792 | intel_enable_semaphores(struct drm_device *dev) | |
793 | { | |
794 | if (INTEL_INFO(dev)->gen < 6) | |
795 | return 0; | |
796 | ||
797 | if (i915_semaphores >= 0) | |
798 | return i915_semaphores; | |
799 | ||
800 | /* Enable semaphores on SNB when IO remapping is off */ | |
801 | if (INTEL_INFO(dev)->gen == 6) | |
802 | return !intel_iommu_enabled; | |
803 | ||
804 | return 1; | |
805 | } | |
806 | ||
1ec14ad3 CW |
807 | static int |
808 | i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj, | |
809 | struct intel_ring_buffer *to) | |
810 | { | |
811 | struct intel_ring_buffer *from = obj->ring; | |
812 | u32 seqno; | |
813 | int ret, idx; | |
814 | ||
815 | if (from == NULL || to == from) | |
816 | return 0; | |
817 | ||
a1656b90 | 818 | /* XXX gpu semaphores are implicated in various hard hangs on SNB */ |
f45b5557 | 819 | if (!intel_enable_semaphores(obj->base.dev)) |
ce453d81 | 820 | return i915_gem_object_wait_rendering(obj); |
1ec14ad3 CW |
821 | |
822 | idx = intel_ring_sync_index(from, to); | |
823 | ||
824 | seqno = obj->last_rendering_seqno; | |
825 | if (seqno <= from->sync_seqno[idx]) | |
826 | return 0; | |
827 | ||
828 | if (seqno == from->outstanding_lazy_request) { | |
829 | struct drm_i915_gem_request *request; | |
830 | ||
831 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
832 | if (request == NULL) | |
833 | return -ENOMEM; | |
834 | ||
db53a302 | 835 | ret = i915_add_request(from, NULL, request); |
1ec14ad3 CW |
836 | if (ret) { |
837 | kfree(request); | |
838 | return ret; | |
839 | } | |
840 | ||
841 | seqno = request->seqno; | |
842 | } | |
843 | ||
844 | from->sync_seqno[idx] = seqno; | |
c8c99b0f BW |
845 | |
846 | return to->sync_to(to, from, seqno - 1); | |
1ec14ad3 | 847 | } |
54cf91dc | 848 | |
c59a333f CW |
849 | static int |
850 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
851 | { | |
852 | u32 plane, flip_mask; | |
853 | int ret; | |
854 | ||
855 | /* Check for any pending flips. As we only maintain a flip queue depth | |
856 | * of 1, we can simply insert a WAIT for the next display flip prior | |
857 | * to executing the batch and avoid stalling the CPU. | |
858 | */ | |
859 | ||
860 | for (plane = 0; flips >> plane; plane++) { | |
861 | if (((flips >> plane) & 1) == 0) | |
862 | continue; | |
863 | ||
864 | if (plane) | |
865 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
866 | else | |
867 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
868 | ||
869 | ret = intel_ring_begin(ring, 2); | |
870 | if (ret) | |
871 | return ret; | |
872 | ||
873 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
874 | intel_ring_emit(ring, MI_NOOP); | |
875 | intel_ring_advance(ring); | |
876 | } | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | ||
54cf91dc | 882 | static int |
432e58ed CW |
883 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
884 | struct list_head *objects) | |
54cf91dc | 885 | { |
432e58ed | 886 | struct drm_i915_gem_object *obj; |
54cf91dc | 887 | struct change_domains cd; |
432e58ed | 888 | int ret; |
54cf91dc | 889 | |
c59a333f | 890 | memset(&cd, 0, sizeof(cd)); |
432e58ed CW |
891 | list_for_each_entry(obj, objects, exec_list) |
892 | i915_gem_object_set_to_gpu_domain(obj, ring, &cd); | |
54cf91dc CW |
893 | |
894 | if (cd.invalidate_domains | cd.flush_domains) { | |
88241785 CW |
895 | ret = i915_gem_execbuffer_flush(ring->dev, |
896 | cd.invalidate_domains, | |
897 | cd.flush_domains, | |
898 | cd.flush_rings); | |
899 | if (ret) | |
900 | return ret; | |
54cf91dc CW |
901 | } |
902 | ||
c59a333f CW |
903 | if (cd.flips) { |
904 | ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips); | |
905 | if (ret) | |
906 | return ret; | |
907 | } | |
908 | ||
432e58ed | 909 | list_for_each_entry(obj, objects, exec_list) { |
1ec14ad3 CW |
910 | ret = i915_gem_execbuffer_sync_rings(obj, ring); |
911 | if (ret) | |
912 | return ret; | |
54cf91dc CW |
913 | } |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
432e58ed CW |
918 | static bool |
919 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 920 | { |
432e58ed | 921 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
922 | } |
923 | ||
924 | static int | |
925 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
926 | int count) | |
927 | { | |
928 | int i; | |
929 | ||
930 | for (i = 0; i < count; i++) { | |
931 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
932 | int length; /* limited by fault_in_pages_readable() */ | |
933 | ||
934 | /* First check for malicious input causing overflow */ | |
935 | if (exec[i].relocation_count > | |
936 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
937 | return -EINVAL; | |
938 | ||
939 | length = exec[i].relocation_count * | |
940 | sizeof(struct drm_i915_gem_relocation_entry); | |
941 | if (!access_ok(VERIFY_READ, ptr, length)) | |
942 | return -EFAULT; | |
943 | ||
944 | /* we may also need to update the presumed offsets */ | |
945 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
946 | return -EFAULT; | |
947 | ||
948 | if (fault_in_pages_readable(ptr, length)) | |
949 | return -EFAULT; | |
950 | } | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
432e58ed CW |
955 | static void |
956 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
957 | struct intel_ring_buffer *ring, |
958 | u32 seqno) | |
432e58ed CW |
959 | { |
960 | struct drm_i915_gem_object *obj; | |
961 | ||
962 | list_for_each_entry(obj, objects, exec_list) { | |
db53a302 CW |
963 | u32 old_read = obj->base.read_domains; |
964 | u32 old_write = obj->base.write_domain; | |
965 | ||
966 | ||
432e58ed CW |
967 | obj->base.read_domains = obj->base.pending_read_domains; |
968 | obj->base.write_domain = obj->base.pending_write_domain; | |
969 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
970 | ||
1ec14ad3 | 971 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
972 | if (obj->base.write_domain) { |
973 | obj->dirty = 1; | |
87ca9c8a | 974 | obj->pending_gpu_write = true; |
432e58ed CW |
975 | list_move_tail(&obj->gpu_write_list, |
976 | &ring->gpu_write_list); | |
977 | intel_mark_busy(ring->dev, obj); | |
978 | } | |
979 | ||
db53a302 | 980 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
981 | } |
982 | } | |
983 | ||
54cf91dc CW |
984 | static void |
985 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 986 | struct drm_file *file, |
54cf91dc CW |
987 | struct intel_ring_buffer *ring) |
988 | { | |
432e58ed | 989 | struct drm_i915_gem_request *request; |
b72f3acb | 990 | u32 invalidate; |
54cf91dc | 991 | |
432e58ed CW |
992 | /* |
993 | * Ensure that the commands in the batch buffer are | |
994 | * finished before the interrupt fires. | |
995 | * | |
996 | * The sampler always gets flushed on i965 (sigh). | |
997 | */ | |
b72f3acb | 998 | invalidate = I915_GEM_DOMAIN_COMMAND; |
54cf91dc | 999 | if (INTEL_INFO(dev)->gen >= 4) |
b72f3acb CW |
1000 | invalidate |= I915_GEM_DOMAIN_SAMPLER; |
1001 | if (ring->flush(ring, invalidate, 0)) { | |
db53a302 | 1002 | i915_gem_next_request_seqno(ring); |
b72f3acb CW |
1003 | return; |
1004 | } | |
54cf91dc | 1005 | |
432e58ed CW |
1006 | /* Add a breadcrumb for the completion of the batch buffer */ |
1007 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
db53a302 CW |
1008 | if (request == NULL || i915_add_request(ring, file, request)) { |
1009 | i915_gem_next_request_seqno(ring); | |
432e58ed CW |
1010 | kfree(request); |
1011 | } | |
1012 | } | |
54cf91dc | 1013 | |
ae662d31 EA |
1014 | static int |
1015 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
1016 | struct intel_ring_buffer *ring) | |
1017 | { | |
1018 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1019 | int ret, i; | |
1020 | ||
1021 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
1022 | return 0; | |
1023 | ||
1024 | ret = intel_ring_begin(ring, 4 * 3); | |
1025 | if (ret) | |
1026 | return ret; | |
1027 | ||
1028 | for (i = 0; i < 4; i++) { | |
1029 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1030 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1031 | intel_ring_emit(ring, 0); | |
1032 | } | |
1033 | ||
1034 | intel_ring_advance(ring); | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | ||
54cf91dc CW |
1039 | static int |
1040 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1041 | struct drm_file *file, | |
1042 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 1043 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
1044 | { |
1045 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 1046 | struct list_head objects; |
67731b87 | 1047 | struct eb_objects *eb; |
54cf91dc CW |
1048 | struct drm_i915_gem_object *batch_obj; |
1049 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 1050 | struct intel_ring_buffer *ring; |
c4e7a414 | 1051 | u32 exec_start, exec_len; |
1ec14ad3 | 1052 | u32 seqno; |
84f9f938 | 1053 | u32 mask; |
72bfa19c | 1054 | int ret, mode, i; |
54cf91dc | 1055 | |
432e58ed CW |
1056 | if (!i915_gem_check_execbuffer(args)) { |
1057 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
1058 | return -EINVAL; | |
1059 | } | |
1060 | ||
1061 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
1062 | if (ret) |
1063 | return ret; | |
1064 | ||
54cf91dc CW |
1065 | switch (args->flags & I915_EXEC_RING_MASK) { |
1066 | case I915_EXEC_DEFAULT: | |
1067 | case I915_EXEC_RENDER: | |
1ec14ad3 | 1068 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
1069 | break; |
1070 | case I915_EXEC_BSD: | |
1071 | if (!HAS_BSD(dev)) { | |
1072 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); | |
1073 | return -EINVAL; | |
1074 | } | |
1ec14ad3 | 1075 | ring = &dev_priv->ring[VCS]; |
54cf91dc CW |
1076 | break; |
1077 | case I915_EXEC_BLT: | |
1078 | if (!HAS_BLT(dev)) { | |
1079 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
1080 | return -EINVAL; | |
1081 | } | |
1ec14ad3 | 1082 | ring = &dev_priv->ring[BCS]; |
54cf91dc CW |
1083 | break; |
1084 | default: | |
1085 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
1086 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | ||
72bfa19c | 1090 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 1091 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
1092 | switch (mode) { |
1093 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1094 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1095 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1096 | if (ring == &dev_priv->ring[RCS] && | |
1097 | mode != dev_priv->relative_constants_mode) { | |
1098 | if (INTEL_INFO(dev)->gen < 4) | |
1099 | return -EINVAL; | |
1100 | ||
1101 | if (INTEL_INFO(dev)->gen > 5 && | |
1102 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
1103 | return -EINVAL; | |
84f9f938 BW |
1104 | |
1105 | /* The HW changed the meaning on this bit on gen6 */ | |
1106 | if (INTEL_INFO(dev)->gen >= 6) | |
1107 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1108 | } |
1109 | break; | |
1110 | default: | |
1111 | DRM_ERROR("execbuf with unknown constants: %d\n", mode); | |
1112 | return -EINVAL; | |
1113 | } | |
1114 | ||
54cf91dc CW |
1115 | if (args->buffer_count < 1) { |
1116 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
1117 | return -EINVAL; | |
1118 | } | |
54cf91dc CW |
1119 | |
1120 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1121 | if (ring != &dev_priv->ring[RCS]) { |
c4e7a414 CW |
1122 | DRM_ERROR("clip rectangles are only valid with the render ring\n"); |
1123 | return -EINVAL; | |
1124 | } | |
1125 | ||
432e58ed | 1126 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
1127 | GFP_KERNEL); |
1128 | if (cliprects == NULL) { | |
1129 | ret = -ENOMEM; | |
1130 | goto pre_mutex_err; | |
1131 | } | |
1132 | ||
432e58ed CW |
1133 | if (copy_from_user(cliprects, |
1134 | (struct drm_clip_rect __user *)(uintptr_t) | |
1135 | args->cliprects_ptr, | |
1136 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1137 | ret = -EFAULT; |
1138 | goto pre_mutex_err; | |
1139 | } | |
1140 | } | |
1141 | ||
54cf91dc CW |
1142 | ret = i915_mutex_lock_interruptible(dev); |
1143 | if (ret) | |
1144 | goto pre_mutex_err; | |
1145 | ||
1146 | if (dev_priv->mm.suspended) { | |
1147 | mutex_unlock(&dev->struct_mutex); | |
1148 | ret = -EBUSY; | |
1149 | goto pre_mutex_err; | |
1150 | } | |
1151 | ||
67731b87 CW |
1152 | eb = eb_create(args->buffer_count); |
1153 | if (eb == NULL) { | |
1154 | mutex_unlock(&dev->struct_mutex); | |
1155 | ret = -ENOMEM; | |
1156 | goto pre_mutex_err; | |
1157 | } | |
1158 | ||
54cf91dc | 1159 | /* Look up object handles */ |
432e58ed | 1160 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
1161 | for (i = 0; i < args->buffer_count; i++) { |
1162 | struct drm_i915_gem_object *obj; | |
1163 | ||
432e58ed CW |
1164 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
1165 | exec[i].handle)); | |
c8725226 | 1166 | if (&obj->base == NULL) { |
54cf91dc | 1167 | DRM_ERROR("Invalid object handle %d at index %d\n", |
432e58ed | 1168 | exec[i].handle, i); |
54cf91dc | 1169 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
1170 | ret = -ENOENT; |
1171 | goto err; | |
1172 | } | |
54cf91dc | 1173 | |
432e58ed CW |
1174 | if (!list_empty(&obj->exec_list)) { |
1175 | DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n", | |
1176 | obj, exec[i].handle, i); | |
54cf91dc CW |
1177 | ret = -EINVAL; |
1178 | goto err; | |
1179 | } | |
432e58ed CW |
1180 | |
1181 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 1182 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 1183 | obj->exec_entry = &exec[i]; |
67731b87 | 1184 | eb_add_object(eb, obj); |
54cf91dc CW |
1185 | } |
1186 | ||
6fe4f140 CW |
1187 | /* take note of the batch buffer before we might reorder the lists */ |
1188 | batch_obj = list_entry(objects.prev, | |
1189 | struct drm_i915_gem_object, | |
1190 | exec_list); | |
1191 | ||
54cf91dc | 1192 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 1193 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
1194 | if (ret) |
1195 | goto err; | |
1196 | ||
1197 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 1198 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
1199 | if (ret) { |
1200 | if (ret == -EFAULT) { | |
d9e86c0e | 1201 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
1202 | &objects, eb, |
1203 | exec, | |
54cf91dc CW |
1204 | args->buffer_count); |
1205 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1206 | } | |
1207 | if (ret) | |
1208 | goto err; | |
1209 | } | |
1210 | ||
1211 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc CW |
1212 | if (batch_obj->base.pending_write_domain) { |
1213 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
1214 | ret = -EINVAL; | |
1215 | goto err; | |
1216 | } | |
1217 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1218 | ||
432e58ed CW |
1219 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1220 | if (ret) | |
54cf91dc | 1221 | goto err; |
54cf91dc | 1222 | |
db53a302 | 1223 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 1224 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
1225 | if (seqno < ring->sync_seqno[i]) { |
1226 | /* The GPU can not handle its semaphore value wrapping, | |
1227 | * so every billion or so execbuffers, we need to stall | |
1228 | * the GPU in order to reset the counters. | |
1229 | */ | |
b93f9cf1 | 1230 | ret = i915_gpu_idle(dev, true); |
1ec14ad3 CW |
1231 | if (ret) |
1232 | goto err; | |
1233 | ||
1234 | BUG_ON(ring->sync_seqno[i]); | |
1235 | } | |
1236 | } | |
1237 | ||
e2971bda BW |
1238 | if (ring == &dev_priv->ring[RCS] && |
1239 | mode != dev_priv->relative_constants_mode) { | |
1240 | ret = intel_ring_begin(ring, 4); | |
1241 | if (ret) | |
1242 | goto err; | |
1243 | ||
1244 | intel_ring_emit(ring, MI_NOOP); | |
1245 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1246 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1247 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1248 | intel_ring_advance(ring); |
1249 | ||
1250 | dev_priv->relative_constants_mode = mode; | |
1251 | } | |
1252 | ||
ae662d31 EA |
1253 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1254 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1255 | if (ret) | |
1256 | goto err; | |
1257 | } | |
1258 | ||
db53a302 CW |
1259 | trace_i915_gem_ring_dispatch(ring, seqno); |
1260 | ||
c4e7a414 CW |
1261 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1262 | exec_len = args->batch_len; | |
1263 | if (cliprects) { | |
1264 | for (i = 0; i < args->num_cliprects; i++) { | |
1265 | ret = i915_emit_box(dev, &cliprects[i], | |
1266 | args->DR1, args->DR4); | |
1267 | if (ret) | |
1268 | goto err; | |
1269 | ||
1270 | ret = ring->dispatch_execbuffer(ring, | |
1271 | exec_start, exec_len); | |
1272 | if (ret) | |
1273 | goto err; | |
1274 | } | |
1275 | } else { | |
1276 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); | |
1277 | if (ret) | |
1278 | goto err; | |
1279 | } | |
54cf91dc | 1280 | |
1ec14ad3 | 1281 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1282 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1283 | |
1284 | err: | |
67731b87 | 1285 | eb_destroy(eb); |
432e58ed CW |
1286 | while (!list_empty(&objects)) { |
1287 | struct drm_i915_gem_object *obj; | |
1288 | ||
1289 | obj = list_first_entry(&objects, | |
1290 | struct drm_i915_gem_object, | |
1291 | exec_list); | |
1292 | list_del_init(&obj->exec_list); | |
1293 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1294 | } |
1295 | ||
1296 | mutex_unlock(&dev->struct_mutex); | |
1297 | ||
1298 | pre_mutex_err: | |
54cf91dc | 1299 | kfree(cliprects); |
54cf91dc CW |
1300 | return ret; |
1301 | } | |
1302 | ||
1303 | /* | |
1304 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1305 | * list array and passes it to the real function. | |
1306 | */ | |
1307 | int | |
1308 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1309 | struct drm_file *file) | |
1310 | { | |
1311 | struct drm_i915_gem_execbuffer *args = data; | |
1312 | struct drm_i915_gem_execbuffer2 exec2; | |
1313 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1314 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1315 | int ret, i; | |
1316 | ||
54cf91dc CW |
1317 | if (args->buffer_count < 1) { |
1318 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
1319 | return -EINVAL; | |
1320 | } | |
1321 | ||
1322 | /* Copy in the exec list from userland */ | |
1323 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1324 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1325 | if (exec_list == NULL || exec2_list == NULL) { | |
1326 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
1327 | args->buffer_count); | |
1328 | drm_free_large(exec_list); | |
1329 | drm_free_large(exec2_list); | |
1330 | return -ENOMEM; | |
1331 | } | |
1332 | ret = copy_from_user(exec_list, | |
1333 | (struct drm_i915_relocation_entry __user *) | |
1334 | (uintptr_t) args->buffers_ptr, | |
1335 | sizeof(*exec_list) * args->buffer_count); | |
1336 | if (ret != 0) { | |
1337 | DRM_ERROR("copy %d exec entries failed %d\n", | |
1338 | args->buffer_count, ret); | |
1339 | drm_free_large(exec_list); | |
1340 | drm_free_large(exec2_list); | |
1341 | return -EFAULT; | |
1342 | } | |
1343 | ||
1344 | for (i = 0; i < args->buffer_count; i++) { | |
1345 | exec2_list[i].handle = exec_list[i].handle; | |
1346 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1347 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1348 | exec2_list[i].alignment = exec_list[i].alignment; | |
1349 | exec2_list[i].offset = exec_list[i].offset; | |
1350 | if (INTEL_INFO(dev)->gen < 4) | |
1351 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1352 | else | |
1353 | exec2_list[i].flags = 0; | |
1354 | } | |
1355 | ||
1356 | exec2.buffers_ptr = args->buffers_ptr; | |
1357 | exec2.buffer_count = args->buffer_count; | |
1358 | exec2.batch_start_offset = args->batch_start_offset; | |
1359 | exec2.batch_len = args->batch_len; | |
1360 | exec2.DR1 = args->DR1; | |
1361 | exec2.DR4 = args->DR4; | |
1362 | exec2.num_cliprects = args->num_cliprects; | |
1363 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1364 | exec2.flags = I915_EXEC_RENDER; | |
1365 | ||
1366 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1367 | if (!ret) { | |
1368 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1369 | for (i = 0; i < args->buffer_count; i++) | |
1370 | exec_list[i].offset = exec2_list[i].offset; | |
1371 | /* ... and back out to userspace */ | |
1372 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1373 | (uintptr_t) args->buffers_ptr, | |
1374 | exec_list, | |
1375 | sizeof(*exec_list) * args->buffer_count); | |
1376 | if (ret) { | |
1377 | ret = -EFAULT; | |
1378 | DRM_ERROR("failed to copy %d exec entries " | |
1379 | "back to user (%d)\n", | |
1380 | args->buffer_count, ret); | |
1381 | } | |
1382 | } | |
1383 | ||
1384 | drm_free_large(exec_list); | |
1385 | drm_free_large(exec2_list); | |
1386 | return ret; | |
1387 | } | |
1388 | ||
1389 | int | |
1390 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1391 | struct drm_file *file) | |
1392 | { | |
1393 | struct drm_i915_gem_execbuffer2 *args = data; | |
1394 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1395 | int ret; | |
1396 | ||
54cf91dc CW |
1397 | if (args->buffer_count < 1) { |
1398 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
1399 | return -EINVAL; | |
1400 | } | |
1401 | ||
8408c282 CW |
1402 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1403 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1404 | if (exec2_list == NULL) | |
1405 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1406 | args->buffer_count); | |
54cf91dc CW |
1407 | if (exec2_list == NULL) { |
1408 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
1409 | args->buffer_count); | |
1410 | return -ENOMEM; | |
1411 | } | |
1412 | ret = copy_from_user(exec2_list, | |
1413 | (struct drm_i915_relocation_entry __user *) | |
1414 | (uintptr_t) args->buffers_ptr, | |
1415 | sizeof(*exec2_list) * args->buffer_count); | |
1416 | if (ret != 0) { | |
1417 | DRM_ERROR("copy %d exec entries failed %d\n", | |
1418 | args->buffer_count, ret); | |
1419 | drm_free_large(exec2_list); | |
1420 | return -EFAULT; | |
1421 | } | |
1422 | ||
1423 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1424 | if (!ret) { | |
1425 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1426 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1427 | (uintptr_t) args->buffers_ptr, | |
1428 | exec2_list, | |
1429 | sizeof(*exec2_list) * args->buffer_count); | |
1430 | if (ret) { | |
1431 | ret = -EFAULT; | |
1432 | DRM_ERROR("failed to copy %d exec entries " | |
1433 | "back to user (%d)\n", | |
1434 | args->buffer_count, ret); | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | drm_free_large(exec2_list); | |
1439 | return ret; | |
1440 | } |