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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
26b1ff35 BW |
31 | /* PPGTT stuff */ |
32 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
33 | ||
34 | #define GEN6_PDE_VALID (1 << 0) | |
35 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
36 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
37 | ||
38 | #define GEN6_PTE_VALID (1 << 0) | |
39 | #define GEN6_PTE_UNCACHED (1 << 1) | |
40 | #define HSW_PTE_UNCACHED (0) | |
41 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
42 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
43 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
44 | ||
2d04befb KG |
45 | static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
46 | dma_addr_t addr, | |
47 | enum i915_cache_level level) | |
54d12527 | 48 | { |
e7c2b58b | 49 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 50 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
51 | |
52 | switch (level) { | |
53 | case I915_CACHE_LLC_MLC: | |
9119708c | 54 | pte |= GEN6_PTE_CACHE_LLC_MLC; |
e7210c3c BW |
55 | break; |
56 | case I915_CACHE_LLC: | |
57 | pte |= GEN6_PTE_CACHE_LLC; | |
58 | break; | |
59 | case I915_CACHE_NONE: | |
9119708c | 60 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
61 | break; |
62 | default: | |
63 | BUG(); | |
64 | } | |
65 | ||
54d12527 BW |
66 | return pte; |
67 | } | |
68 | ||
93c34e70 KG |
69 | #define BYT_PTE_WRITEABLE (1 << 1) |
70 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
71 | ||
72 | static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev, | |
73 | dma_addr_t addr, | |
74 | enum i915_cache_level level) | |
75 | { | |
76 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
77 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
78 | ||
79 | /* Mark the page as writeable. Other platforms don't have a | |
80 | * setting for read-only/writable, so this matches that behavior. | |
81 | */ | |
82 | pte |= BYT_PTE_WRITEABLE; | |
83 | ||
84 | if (level != I915_CACHE_NONE) | |
85 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
86 | ||
87 | return pte; | |
88 | } | |
89 | ||
9119708c KG |
90 | static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev, |
91 | dma_addr_t addr, | |
92 | enum i915_cache_level level) | |
93 | { | |
94 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
95 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
96 | ||
97 | if (level != I915_CACHE_NONE) | |
98 | pte |= GEN6_PTE_CACHE_LLC; | |
99 | ||
100 | return pte; | |
101 | } | |
102 | ||
b7c36d25 | 103 | static int gen6_ppgtt_enable(struct drm_device *dev) |
6197349b BW |
104 | { |
105 | drm_i915_private_t *dev_priv = dev->dev_private; | |
106 | uint32_t pd_offset; | |
107 | struct intel_ring_buffer *ring; | |
108 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
109 | gen6_gtt_pte_t __iomem *pd_addr; | |
110 | uint32_t pd_entry; | |
111 | int i; | |
112 | ||
0a732870 BW |
113 | WARN_ON(ppgtt->pd_offset & 0x3f); |
114 | ||
6197349b BW |
115 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
116 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
117 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
118 | dma_addr_t pt_addr; | |
119 | ||
120 | pt_addr = ppgtt->pt_dma_addr[i]; | |
121 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
122 | pd_entry |= GEN6_PDE_VALID; | |
123 | ||
124 | writel(pd_entry, pd_addr + i); | |
125 | } | |
126 | readl(pd_addr); | |
127 | ||
128 | pd_offset = ppgtt->pd_offset; | |
129 | pd_offset /= 64; /* in cachelines, */ | |
130 | pd_offset <<= 16; | |
131 | ||
132 | if (INTEL_INFO(dev)->gen == 6) { | |
133 | uint32_t ecochk, gab_ctl, ecobits; | |
134 | ||
135 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
136 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
137 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
138 | |
139 | gab_ctl = I915_READ(GAB_CTL); | |
140 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
141 | ||
142 | ecochk = I915_READ(GAM_ECOCHK); | |
143 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
144 | ECOCHK_PPGTT_CACHE64B); | |
145 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
146 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 147 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
148 | |
149 | ecobits = I915_READ(GAC_ECO_BITS); | |
150 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
151 | ||
a6f429a5 VS |
152 | ecochk = I915_READ(GAM_ECOCHK); |
153 | if (IS_HASWELL(dev)) { | |
154 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
155 | } else { | |
156 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
157 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
158 | } | |
159 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
160 | /* GFX_MODE is per-ring on gen7+ */ |
161 | } | |
162 | ||
163 | for_each_ring(ring, dev_priv, i) { | |
164 | if (INTEL_INFO(dev)->gen >= 7) | |
165 | I915_WRITE(RING_MODE_GEN7(ring), | |
166 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
167 | ||
168 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
169 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
170 | } | |
b7c36d25 | 171 | return 0; |
6197349b BW |
172 | } |
173 | ||
1d2a314c | 174 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 175 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
176 | unsigned first_entry, |
177 | unsigned num_entries) | |
178 | { | |
e7c2b58b | 179 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 180 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
181 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
182 | unsigned last_pte, i; | |
1d2a314c | 183 | |
2d04befb KG |
184 | scratch_pte = ppgtt->pte_encode(ppgtt->dev, |
185 | ppgtt->scratch_page_dma_addr, | |
186 | I915_CACHE_LLC); | |
1d2a314c | 187 | |
7bddb01f DV |
188 | while (num_entries) { |
189 | last_pte = first_pte + num_entries; | |
190 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
191 | last_pte = I915_PPGTT_PT_ENTRIES; | |
192 | ||
a15326a5 | 193 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 194 | |
7bddb01f DV |
195 | for (i = first_pte; i < last_pte; i++) |
196 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
197 | |
198 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 199 | |
7bddb01f DV |
200 | num_entries -= last_pte - first_pte; |
201 | first_pte = 0; | |
a15326a5 | 202 | act_pt++; |
7bddb01f | 203 | } |
1d2a314c DV |
204 | } |
205 | ||
def886c3 DV |
206 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
207 | struct sg_table *pages, | |
208 | unsigned first_entry, | |
209 | enum i915_cache_level cache_level) | |
210 | { | |
e7c2b58b | 211 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 212 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
213 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
214 | struct sg_page_iter sg_iter; | |
215 | ||
a15326a5 | 216 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
217 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
218 | dma_addr_t page_addr; | |
219 | ||
2db76d7c | 220 | page_addr = sg_page_iter_dma_address(&sg_iter); |
2d04befb KG |
221 | pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr, |
222 | cache_level); | |
6e995e23 ID |
223 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
224 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
225 | act_pt++; |
226 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 227 | act_pte = 0; |
def886c3 | 228 | |
def886c3 | 229 | } |
def886c3 | 230 | } |
6e995e23 | 231 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
232 | } |
233 | ||
3440d265 | 234 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 235 | { |
3440d265 DV |
236 | int i; |
237 | ||
238 | if (ppgtt->pt_dma_addr) { | |
239 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
240 | pci_unmap_page(ppgtt->dev->pdev, | |
241 | ppgtt->pt_dma_addr[i], | |
242 | 4096, PCI_DMA_BIDIRECTIONAL); | |
243 | } | |
244 | ||
245 | kfree(ppgtt->pt_dma_addr); | |
246 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
247 | __free_page(ppgtt->pt_pages[i]); | |
248 | kfree(ppgtt->pt_pages); | |
249 | kfree(ppgtt); | |
250 | } | |
251 | ||
252 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
253 | { | |
254 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 255 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 256 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
257 | int i; |
258 | int ret = -ENOMEM; | |
259 | ||
260 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
261 | * entries. For aliasing ppgtt support we just steal them at the end for | |
262 | * now. */ | |
a54c0c27 BW |
263 | first_pd_entry_in_global_pt = |
264 | gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES; | |
1d2a314c | 265 | |
9119708c KG |
266 | if (IS_HASWELL(dev)) { |
267 | ppgtt->pte_encode = hsw_pte_encode; | |
268 | } else if (IS_VALLEYVIEW(dev)) { | |
93c34e70 KG |
269 | ppgtt->pte_encode = byt_pte_encode; |
270 | } else { | |
271 | ppgtt->pte_encode = gen6_pte_encode; | |
272 | } | |
1d2a314c | 273 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
6197349b | 274 | ppgtt->enable = gen6_ppgtt_enable; |
def886c3 DV |
275 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
276 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 277 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
278 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
279 | GFP_KERNEL); | |
280 | if (!ppgtt->pt_pages) | |
3440d265 | 281 | return -ENOMEM; |
1d2a314c DV |
282 | |
283 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
284 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
285 | if (!ppgtt->pt_pages[i]) | |
286 | goto err_pt_alloc; | |
287 | } | |
288 | ||
8d2e6308 BW |
289 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
290 | GFP_KERNEL); | |
291 | if (!ppgtt->pt_dma_addr) | |
292 | goto err_pt_alloc; | |
1d2a314c | 293 | |
8d2e6308 BW |
294 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
295 | dma_addr_t pt_addr; | |
211c568b | 296 | |
8d2e6308 BW |
297 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
298 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 299 | |
8d2e6308 BW |
300 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
301 | ret = -EIO; | |
302 | goto err_pd_pin; | |
1d2a314c | 303 | |
211c568b | 304 | } |
8d2e6308 | 305 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 306 | } |
1d2a314c | 307 | |
def886c3 DV |
308 | ppgtt->clear_range(ppgtt, 0, |
309 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 310 | |
e7c2b58b | 311 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 312 | |
1d2a314c DV |
313 | return 0; |
314 | ||
315 | err_pd_pin: | |
316 | if (ppgtt->pt_dma_addr) { | |
317 | for (i--; i >= 0; i--) | |
318 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
319 | 4096, PCI_DMA_BIDIRECTIONAL); | |
320 | } | |
321 | err_pt_alloc: | |
322 | kfree(ppgtt->pt_dma_addr); | |
323 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
324 | if (ppgtt->pt_pages[i]) | |
325 | __free_page(ppgtt->pt_pages[i]); | |
326 | } | |
327 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
328 | |
329 | return ret; | |
330 | } | |
331 | ||
332 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
333 | { | |
334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
335 | struct i915_hw_ppgtt *ppgtt; | |
336 | int ret; | |
337 | ||
338 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
339 | if (!ppgtt) | |
340 | return -ENOMEM; | |
341 | ||
342 | ppgtt->dev = dev; | |
1e7d12d4 | 343 | ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; |
3440d265 | 344 | |
3ed124b2 BW |
345 | if (INTEL_INFO(dev)->gen < 8) |
346 | ret = gen6_ppgtt_init(ppgtt); | |
347 | else | |
348 | BUG(); | |
349 | ||
3440d265 DV |
350 | if (ret) |
351 | kfree(ppgtt); | |
352 | else | |
353 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
354 | |
355 | return ret; | |
356 | } | |
357 | ||
358 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
359 | { | |
360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
361 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
362 | |
363 | if (!ppgtt) | |
364 | return; | |
365 | ||
3440d265 | 366 | ppgtt->cleanup(ppgtt); |
5963cf04 | 367 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
368 | } |
369 | ||
7bddb01f DV |
370 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
371 | struct drm_i915_gem_object *obj, | |
372 | enum i915_cache_level cache_level) | |
373 | { | |
def886c3 DV |
374 | ppgtt->insert_entries(ppgtt, obj->pages, |
375 | obj->gtt_space->start >> PAGE_SHIFT, | |
376 | cache_level); | |
7bddb01f DV |
377 | } |
378 | ||
379 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
380 | struct drm_i915_gem_object *obj) | |
381 | { | |
def886c3 DV |
382 | ppgtt->clear_range(ppgtt, |
383 | obj->gtt_space->start >> PAGE_SHIFT, | |
384 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
385 | } |
386 | ||
a81cc00c BW |
387 | extern int intel_iommu_gfx_mapped; |
388 | /* Certain Gen5 chipsets require require idling the GPU before | |
389 | * unmapping anything from the GTT when VT-d is enabled. | |
390 | */ | |
391 | static inline bool needs_idle_maps(struct drm_device *dev) | |
392 | { | |
393 | #ifdef CONFIG_INTEL_IOMMU | |
394 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
395 | * was loaded first. | |
396 | */ | |
397 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
398 | return true; | |
399 | #endif | |
400 | return false; | |
401 | } | |
402 | ||
5c042287 BW |
403 | static bool do_idling(struct drm_i915_private *dev_priv) |
404 | { | |
405 | bool ret = dev_priv->mm.interruptible; | |
406 | ||
a81cc00c | 407 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 408 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 409 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
410 | DRM_ERROR("Couldn't idle GPU\n"); |
411 | /* Wait a bit, in hopes it avoids the hang */ | |
412 | udelay(10); | |
413 | } | |
414 | } | |
415 | ||
416 | return ret; | |
417 | } | |
418 | ||
419 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
420 | { | |
a81cc00c | 421 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
422 | dev_priv->mm.interruptible = interruptible; |
423 | } | |
424 | ||
76aaf220 DV |
425 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
426 | { | |
427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 428 | struct drm_i915_gem_object *obj; |
76aaf220 | 429 | |
bee4a186 | 430 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
431 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
432 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 433 | |
6c085a72 | 434 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
a8e93126 | 435 | i915_gem_clflush_object(obj); |
74163907 | 436 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
437 | } |
438 | ||
e76e9aeb | 439 | i915_gem_chipset_flush(dev); |
76aaf220 | 440 | } |
7c2e6fdf | 441 | |
74163907 | 442 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 443 | { |
9da3da66 | 444 | if (obj->has_dma_mapping) |
74163907 | 445 | return 0; |
9da3da66 CW |
446 | |
447 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
448 | obj->pages->sgl, obj->pages->nents, | |
449 | PCI_DMA_BIDIRECTIONAL)) | |
450 | return -ENOSPC; | |
451 | ||
452 | return 0; | |
7c2e6fdf DV |
453 | } |
454 | ||
e76e9aeb BW |
455 | /* |
456 | * Binds an object into the global gtt with the specified cache level. The object | |
457 | * will be accessible to the GPU via commands whose operands reference offsets | |
458 | * within the global GTT as well as accessible by the GPU through the GMADR | |
459 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
460 | */ | |
7faf1ab2 DV |
461 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
462 | struct sg_table *st, | |
463 | unsigned int first_entry, | |
464 | enum i915_cache_level level) | |
e76e9aeb | 465 | { |
e76e9aeb | 466 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7c2b58b BW |
467 | gen6_gtt_pte_t __iomem *gtt_entries = |
468 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
469 | int i = 0; |
470 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
471 | dma_addr_t addr; |
472 | ||
6e995e23 | 473 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 474 | addr = sg_page_iter_dma_address(&sg_iter); |
2d04befb KG |
475 | iowrite32(dev_priv->gtt.pte_encode(dev, addr, level), |
476 | >t_entries[i]); | |
6e995e23 | 477 | i++; |
e76e9aeb BW |
478 | } |
479 | ||
e76e9aeb BW |
480 | /* XXX: This serves as a posting read to make sure that the PTE has |
481 | * actually been updated. There is some concern that even though | |
482 | * registers and PTEs are within the same BAR that they are potentially | |
483 | * of NUMA access patterns. Therefore, even with the way we assume | |
484 | * hardware should work, we must keep this posting read for paranoia. | |
485 | */ | |
486 | if (i != 0) | |
960e3e42 | 487 | WARN_ON(readl(>t_entries[i-1]) |
2d04befb | 488 | != dev_priv->gtt.pte_encode(dev, addr, level)); |
0f9b91c7 BW |
489 | |
490 | /* This next bit makes the above posting read even more important. We | |
491 | * want to flush the TLBs only after we're certain all the PTE updates | |
492 | * have finished. | |
493 | */ | |
494 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
495 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
496 | } |
497 | ||
7faf1ab2 DV |
498 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
499 | unsigned int first_entry, | |
500 | unsigned int num_entries) | |
501 | { | |
502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e7c2b58b BW |
503 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
504 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 505 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
506 | int i; |
507 | ||
508 | if (WARN(num_entries > max_entries, | |
509 | "First entry = %d; Num entries = %d (max=%d)\n", | |
510 | first_entry, num_entries, max_entries)) | |
511 | num_entries = max_entries; | |
512 | ||
2d04befb KG |
513 | scratch_pte = dev_priv->gtt.pte_encode(dev, |
514 | dev_priv->gtt.scratch_page_dma, | |
515 | I915_CACHE_LLC); | |
7faf1ab2 DV |
516 | for (i = 0; i < num_entries; i++) |
517 | iowrite32(scratch_pte, >t_base[i]); | |
518 | readl(gtt_base); | |
519 | } | |
520 | ||
521 | ||
522 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
523 | struct sg_table *st, | |
524 | unsigned int pg_start, | |
525 | enum i915_cache_level cache_level) | |
526 | { | |
527 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
528 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
529 | ||
530 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
531 | ||
532 | } | |
533 | ||
534 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
535 | unsigned int first_entry, | |
536 | unsigned int num_entries) | |
537 | { | |
538 | intel_gtt_clear_range(first_entry, num_entries); | |
539 | } | |
540 | ||
541 | ||
74163907 DV |
542 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
543 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
544 | { |
545 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
546 | struct drm_i915_private *dev_priv = dev->dev_private; |
547 | ||
548 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
549 | obj->gtt_space->start >> PAGE_SHIFT, | |
550 | cache_level); | |
d5bd1449 | 551 | |
74898d7e | 552 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
553 | } |
554 | ||
05394f39 | 555 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 556 | { |
7faf1ab2 DV |
557 | struct drm_device *dev = obj->base.dev; |
558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
559 | ||
560 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
561 | obj->gtt_space->start >> PAGE_SHIFT, | |
562 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
563 | |
564 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
565 | } |
566 | ||
567 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 568 | { |
5c042287 BW |
569 | struct drm_device *dev = obj->base.dev; |
570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
571 | bool interruptible; | |
572 | ||
573 | interruptible = do_idling(dev_priv); | |
574 | ||
9da3da66 CW |
575 | if (!obj->has_dma_mapping) |
576 | dma_unmap_sg(&dev->pdev->dev, | |
577 | obj->pages->sgl, obj->pages->nents, | |
578 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
579 | |
580 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 581 | } |
644ec02b | 582 | |
42d6ab48 CW |
583 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
584 | unsigned long color, | |
585 | unsigned long *start, | |
586 | unsigned long *end) | |
587 | { | |
588 | if (node->color != color) | |
589 | *start += 4096; | |
590 | ||
591 | if (!list_empty(&node->node_list)) { | |
592 | node = list_entry(node->node_list.next, | |
593 | struct drm_mm_node, | |
594 | node_list); | |
595 | if (node->allocated && node->color != color) | |
596 | *end -= 4096; | |
597 | } | |
598 | } | |
d7e5008f BW |
599 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
600 | unsigned long start, | |
601 | unsigned long mappable_end, | |
602 | unsigned long end) | |
644ec02b | 603 | { |
e78891ca BW |
604 | /* Let GEM Manage all of the aperture. |
605 | * | |
606 | * However, leave one page at the end still bound to the scratch page. | |
607 | * There are a number of places where the hardware apparently prefetches | |
608 | * past the end of the object, and we've seen multiple hangs with the | |
609 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
610 | * aperture. One page should be enough to keep any prefetching inside | |
611 | * of the aperture. | |
612 | */ | |
644ec02b | 613 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
614 | struct drm_mm_node *entry; |
615 | struct drm_i915_gem_object *obj; | |
616 | unsigned long hole_start, hole_end; | |
644ec02b | 617 | |
35451cb6 BW |
618 | BUG_ON(mappable_end > end); |
619 | ||
ed2f3452 | 620 | /* Subtract the guard page ... */ |
d1dd20a9 | 621 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
622 | if (!HAS_LLC(dev)) |
623 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 624 | |
ed2f3452 CW |
625 | /* Mark any preallocated objects as occupied */ |
626 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
627 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", | |
628 | obj->gtt_offset, obj->base.size); | |
629 | ||
630 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
631 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
632 | obj->gtt_offset, | |
633 | obj->base.size, | |
634 | false); | |
635 | obj->has_global_gtt_mapping = 1; | |
636 | } | |
637 | ||
5d4545ae | 638 | dev_priv->gtt.start = start; |
5d4545ae | 639 | dev_priv->gtt.total = end - start; |
644ec02b | 640 | |
ed2f3452 CW |
641 | /* Clear any non-preallocated blocks */ |
642 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
643 | hole_start, hole_end) { | |
644 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
645 | hole_start, hole_end); | |
7faf1ab2 DV |
646 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
647 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
648 | } |
649 | ||
650 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 651 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
652 | } |
653 | ||
d7e5008f BW |
654 | static bool |
655 | intel_enable_ppgtt(struct drm_device *dev) | |
656 | { | |
657 | if (i915_enable_ppgtt >= 0) | |
658 | return i915_enable_ppgtt; | |
659 | ||
660 | #ifdef CONFIG_INTEL_IOMMU | |
661 | /* Disable ppgtt on SNB if VT-d is on. */ | |
662 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
663 | return false; | |
664 | #endif | |
665 | ||
666 | return true; | |
667 | } | |
668 | ||
669 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
670 | { | |
671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
672 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 673 | |
a54c0c27 | 674 | gtt_size = dev_priv->gtt.total; |
93d18799 | 675 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
676 | |
677 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 678 | int ret; |
3eb1c005 BW |
679 | |
680 | if (INTEL_INFO(dev)->gen <= 7) { | |
681 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
682 | * aperture accordingly when using aliasing ppgtt. */ | |
683 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
684 | } | |
d7e5008f BW |
685 | |
686 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
687 | ||
688 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 689 | if (!ret) |
d7e5008f | 690 | return; |
e78891ca BW |
691 | |
692 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
693 | drm_mm_takedown(&dev_priv->mm.gtt_space); | |
694 | gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
d7e5008f | 695 | } |
e78891ca | 696 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
697 | } |
698 | ||
699 | static int setup_scratch_page(struct drm_device *dev) | |
700 | { | |
701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702 | struct page *page; | |
703 | dma_addr_t dma_addr; | |
704 | ||
705 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
706 | if (page == NULL) | |
707 | return -ENOMEM; | |
708 | get_page(page); | |
709 | set_pages_uc(page, 1); | |
710 | ||
711 | #ifdef CONFIG_INTEL_IOMMU | |
712 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
713 | PCI_DMA_BIDIRECTIONAL); | |
714 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
715 | return -EINVAL; | |
716 | #else | |
717 | dma_addr = page_to_phys(page); | |
718 | #endif | |
9c61a32d BW |
719 | dev_priv->gtt.scratch_page = page; |
720 | dev_priv->gtt.scratch_page_dma = dma_addr; | |
e76e9aeb BW |
721 | |
722 | return 0; | |
723 | } | |
724 | ||
725 | static void teardown_scratch_page(struct drm_device *dev) | |
726 | { | |
727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9c61a32d BW |
728 | set_pages_wb(dev_priv->gtt.scratch_page, 1); |
729 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, | |
e76e9aeb | 730 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
9c61a32d BW |
731 | put_page(dev_priv->gtt.scratch_page); |
732 | __free_page(dev_priv->gtt.scratch_page); | |
e76e9aeb BW |
733 | } |
734 | ||
735 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
736 | { | |
737 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
738 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
739 | return snb_gmch_ctl << 20; | |
740 | } | |
741 | ||
baa09f5f | 742 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
743 | { |
744 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
745 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
746 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
747 | } | |
748 | ||
baa09f5f | 749 | static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl) |
03752f5b BW |
750 | { |
751 | static const int stolen_decoder[] = { | |
752 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352}; | |
753 | snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT; | |
754 | snb_gmch_ctl &= IVB_GMCH_GMS_MASK; | |
755 | return stolen_decoder[snb_gmch_ctl] << 20; | |
756 | } | |
757 | ||
baa09f5f BW |
758 | static int gen6_gmch_probe(struct drm_device *dev, |
759 | size_t *gtt_total, | |
41907ddc BW |
760 | size_t *stolen, |
761 | phys_addr_t *mappable_base, | |
762 | unsigned long *mappable_end) | |
e76e9aeb BW |
763 | { |
764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
765 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 766 | unsigned int gtt_size; |
e76e9aeb | 767 | u16 snb_gmch_ctl; |
e76e9aeb BW |
768 | int ret; |
769 | ||
41907ddc BW |
770 | *mappable_base = pci_resource_start(dev->pdev, 2); |
771 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
772 | ||
baa09f5f BW |
773 | /* 64/512MB is the current min/max we actually know of, but this is just |
774 | * a coarse sanity check. | |
e76e9aeb | 775 | */ |
41907ddc | 776 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
777 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
778 | dev_priv->gtt.mappable_end); | |
779 | return -ENXIO; | |
e76e9aeb BW |
780 | } |
781 | ||
e76e9aeb BW |
782 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
783 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 784 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 785 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 786 | |
086ddcce | 787 | if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) |
baa09f5f BW |
788 | *stolen = gen7_get_stolen_size(snb_gmch_ctl); |
789 | else | |
790 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); | |
e76e9aeb | 791 | |
e7c2b58b | 792 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 793 | |
a93e4161 BW |
794 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
795 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
796 | (pci_resource_len(dev->pdev, 0) / 2); | |
797 | ||
baa09f5f | 798 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 799 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 800 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 801 | return -ENOMEM; |
e76e9aeb BW |
802 | } |
803 | ||
baa09f5f BW |
804 | ret = setup_scratch_page(dev); |
805 | if (ret) | |
806 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 807 | |
7faf1ab2 DV |
808 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
809 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
810 | ||
e76e9aeb BW |
811 | return ret; |
812 | } | |
813 | ||
d93c6233 | 814 | static void gen6_gmch_remove(struct drm_device *dev) |
e76e9aeb BW |
815 | { |
816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 817 | iounmap(dev_priv->gtt.gsm); |
baa09f5f | 818 | teardown_scratch_page(dev_priv->dev); |
644ec02b | 819 | } |
baa09f5f BW |
820 | |
821 | static int i915_gmch_probe(struct drm_device *dev, | |
822 | size_t *gtt_total, | |
41907ddc BW |
823 | size_t *stolen, |
824 | phys_addr_t *mappable_base, | |
825 | unsigned long *mappable_end) | |
baa09f5f BW |
826 | { |
827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
828 | int ret; | |
829 | ||
baa09f5f BW |
830 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
831 | if (!ret) { | |
832 | DRM_ERROR("failed to set up gmch\n"); | |
833 | return -EIO; | |
834 | } | |
835 | ||
41907ddc | 836 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
837 | |
838 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
839 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | |
840 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static void i915_gmch_remove(struct drm_device *dev) | |
846 | { | |
847 | intel_gmch_remove(); | |
848 | } | |
849 | ||
850 | int i915_gem_gtt_init(struct drm_device *dev) | |
851 | { | |
852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
854 | int ret; |
855 | ||
baa09f5f BW |
856 | if (INTEL_INFO(dev)->gen <= 5) { |
857 | dev_priv->gtt.gtt_probe = i915_gmch_probe; | |
858 | dev_priv->gtt.gtt_remove = i915_gmch_remove; | |
859 | } else { | |
860 | dev_priv->gtt.gtt_probe = gen6_gmch_probe; | |
861 | dev_priv->gtt.gtt_remove = gen6_gmch_remove; | |
9119708c KG |
862 | if (IS_HASWELL(dev)) { |
863 | dev_priv->gtt.pte_encode = hsw_pte_encode; | |
864 | } else if (IS_VALLEYVIEW(dev)) { | |
93c34e70 KG |
865 | dev_priv->gtt.pte_encode = byt_pte_encode; |
866 | } else { | |
867 | dev_priv->gtt.pte_encode = gen6_pte_encode; | |
868 | } | |
baa09f5f BW |
869 | } |
870 | ||
871 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, | |
41907ddc BW |
872 | &dev_priv->gtt.stolen_size, |
873 | >t->mappable_base, | |
874 | >t->mappable_end); | |
a54c0c27 | 875 | if (ret) |
baa09f5f | 876 | return ret; |
baa09f5f | 877 | |
baa09f5f BW |
878 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
879 | DRM_INFO("Memory usable by graphics device = %zdM\n", | |
880 | dev_priv->gtt.total >> 20); | |
881 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", | |
882 | dev_priv->gtt.mappable_end >> 20); | |
883 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", | |
884 | dev_priv->gtt.stolen_size >> 20); | |
885 | ||
886 | return 0; | |
887 | } |