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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
e7c2b58b | 31 | typedef uint32_t gen6_gtt_pte_t; |
f61c0609 | 32 | |
26b1ff35 BW |
33 | /* PPGTT stuff */ |
34 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
35 | ||
36 | #define GEN6_PDE_VALID (1 << 0) | |
37 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
38 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
39 | ||
40 | #define GEN6_PTE_VALID (1 << 0) | |
41 | #define GEN6_PTE_UNCACHED (1 << 1) | |
42 | #define HSW_PTE_UNCACHED (0) | |
43 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
44 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
45 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
46 | ||
e7c2b58b | 47 | static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
c81dbe05 BW |
48 | dma_addr_t addr, |
49 | enum i915_cache_level level) | |
54d12527 | 50 | { |
e7c2b58b | 51 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 52 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
53 | |
54 | switch (level) { | |
55 | case I915_CACHE_LLC_MLC: | |
56 | /* Haswell doesn't set L3 this way */ | |
57 | if (IS_HASWELL(dev)) | |
58 | pte |= GEN6_PTE_CACHE_LLC; | |
59 | else | |
60 | pte |= GEN6_PTE_CACHE_LLC_MLC; | |
61 | break; | |
62 | case I915_CACHE_LLC: | |
63 | pte |= GEN6_PTE_CACHE_LLC; | |
64 | break; | |
65 | case I915_CACHE_NONE: | |
66 | if (IS_HASWELL(dev)) | |
67 | pte |= HSW_PTE_UNCACHED; | |
68 | else | |
69 | pte |= GEN6_PTE_UNCACHED; | |
70 | break; | |
71 | default: | |
72 | BUG(); | |
73 | } | |
74 | ||
54d12527 BW |
75 | return pte; |
76 | } | |
77 | ||
1d2a314c | 78 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 79 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
80 | unsigned first_entry, |
81 | unsigned num_entries) | |
82 | { | |
e7c2b58b | 83 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 84 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
85 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
86 | unsigned last_pte, i; | |
1d2a314c | 87 | |
960e3e42 DV |
88 | scratch_pte = gen6_pte_encode(ppgtt->dev, |
89 | ppgtt->scratch_page_dma_addr, | |
90 | I915_CACHE_LLC); | |
1d2a314c | 91 | |
7bddb01f DV |
92 | while (num_entries) { |
93 | last_pte = first_pte + num_entries; | |
94 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
95 | last_pte = I915_PPGTT_PT_ENTRIES; | |
96 | ||
a15326a5 | 97 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 98 | |
7bddb01f DV |
99 | for (i = first_pte; i < last_pte; i++) |
100 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
101 | |
102 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 103 | |
7bddb01f DV |
104 | num_entries -= last_pte - first_pte; |
105 | first_pte = 0; | |
a15326a5 | 106 | act_pt++; |
7bddb01f | 107 | } |
1d2a314c DV |
108 | } |
109 | ||
def886c3 DV |
110 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
111 | struct sg_table *pages, | |
112 | unsigned first_entry, | |
113 | enum i915_cache_level cache_level) | |
114 | { | |
e7c2b58b | 115 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 116 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
117 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
118 | struct sg_page_iter sg_iter; | |
119 | ||
a15326a5 | 120 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
121 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
122 | dma_addr_t page_addr; | |
123 | ||
2db76d7c | 124 | page_addr = sg_page_iter_dma_address(&sg_iter); |
6e995e23 | 125 | pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr, |
6ddc4fc7 | 126 | cache_level); |
6e995e23 ID |
127 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
128 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
129 | act_pt++; |
130 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 131 | act_pte = 0; |
def886c3 | 132 | |
def886c3 | 133 | } |
def886c3 | 134 | } |
6e995e23 | 135 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
136 | } |
137 | ||
3440d265 | 138 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 139 | { |
3440d265 DV |
140 | int i; |
141 | ||
142 | if (ppgtt->pt_dma_addr) { | |
143 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
144 | pci_unmap_page(ppgtt->dev->pdev, | |
145 | ppgtt->pt_dma_addr[i], | |
146 | 4096, PCI_DMA_BIDIRECTIONAL); | |
147 | } | |
148 | ||
149 | kfree(ppgtt->pt_dma_addr); | |
150 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
151 | __free_page(ppgtt->pt_pages[i]); | |
152 | kfree(ppgtt->pt_pages); | |
153 | kfree(ppgtt); | |
154 | } | |
155 | ||
156 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
157 | { | |
158 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 159 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 160 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
161 | int i; |
162 | int ret = -ENOMEM; | |
163 | ||
164 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
165 | * entries. For aliasing ppgtt support we just steal them at the end for | |
166 | * now. */ | |
a54c0c27 BW |
167 | first_pd_entry_in_global_pt = |
168 | gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES; | |
1d2a314c | 169 | |
1d2a314c | 170 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
def886c3 DV |
171 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
172 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 173 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
174 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
175 | GFP_KERNEL); | |
176 | if (!ppgtt->pt_pages) | |
3440d265 | 177 | return -ENOMEM; |
1d2a314c DV |
178 | |
179 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
180 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
181 | if (!ppgtt->pt_pages[i]) | |
182 | goto err_pt_alloc; | |
183 | } | |
184 | ||
8d2e6308 BW |
185 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
186 | GFP_KERNEL); | |
187 | if (!ppgtt->pt_dma_addr) | |
188 | goto err_pt_alloc; | |
1d2a314c | 189 | |
8d2e6308 BW |
190 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
191 | dma_addr_t pt_addr; | |
211c568b | 192 | |
8d2e6308 BW |
193 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
194 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 195 | |
8d2e6308 BW |
196 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
197 | ret = -EIO; | |
198 | goto err_pd_pin; | |
1d2a314c | 199 | |
211c568b | 200 | } |
8d2e6308 | 201 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 202 | } |
1d2a314c | 203 | |
def886c3 DV |
204 | ppgtt->clear_range(ppgtt, 0, |
205 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 206 | |
e7c2b58b | 207 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 208 | |
1d2a314c DV |
209 | return 0; |
210 | ||
211 | err_pd_pin: | |
212 | if (ppgtt->pt_dma_addr) { | |
213 | for (i--; i >= 0; i--) | |
214 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
215 | 4096, PCI_DMA_BIDIRECTIONAL); | |
216 | } | |
217 | err_pt_alloc: | |
218 | kfree(ppgtt->pt_dma_addr); | |
219 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
220 | if (ppgtt->pt_pages[i]) | |
221 | __free_page(ppgtt->pt_pages[i]); | |
222 | } | |
223 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
224 | |
225 | return ret; | |
226 | } | |
227 | ||
228 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
229 | { | |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | struct i915_hw_ppgtt *ppgtt; | |
232 | int ret; | |
233 | ||
234 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
235 | if (!ppgtt) | |
236 | return -ENOMEM; | |
237 | ||
238 | ppgtt->dev = dev; | |
1e7d12d4 | 239 | ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; |
3440d265 DV |
240 | |
241 | ret = gen6_ppgtt_init(ppgtt); | |
242 | if (ret) | |
243 | kfree(ppgtt); | |
244 | else | |
245 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
246 | |
247 | return ret; | |
248 | } | |
249 | ||
250 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
251 | { | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
254 | |
255 | if (!ppgtt) | |
256 | return; | |
257 | ||
3440d265 | 258 | ppgtt->cleanup(ppgtt); |
1d2a314c DV |
259 | } |
260 | ||
7bddb01f DV |
261 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
262 | struct drm_i915_gem_object *obj, | |
263 | enum i915_cache_level cache_level) | |
264 | { | |
def886c3 DV |
265 | ppgtt->insert_entries(ppgtt, obj->pages, |
266 | obj->gtt_space->start >> PAGE_SHIFT, | |
267 | cache_level); | |
7bddb01f DV |
268 | } |
269 | ||
270 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
271 | struct drm_i915_gem_object *obj) | |
272 | { | |
def886c3 DV |
273 | ppgtt->clear_range(ppgtt, |
274 | obj->gtt_space->start >> PAGE_SHIFT, | |
275 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
276 | } |
277 | ||
26b1ff35 BW |
278 | void i915_gem_init_ppgtt(struct drm_device *dev) |
279 | { | |
280 | drm_i915_private_t *dev_priv = dev->dev_private; | |
281 | uint32_t pd_offset; | |
282 | struct intel_ring_buffer *ring; | |
283 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
e7c2b58b | 284 | gen6_gtt_pte_t __iomem *pd_addr; |
26b1ff35 BW |
285 | uint32_t pd_entry; |
286 | int i; | |
287 | ||
288 | if (!dev_priv->mm.aliasing_ppgtt) | |
289 | return; | |
290 | ||
e7c2b58b BW |
291 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + |
292 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
26b1ff35 BW |
293 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
294 | dma_addr_t pt_addr; | |
295 | ||
8d2e6308 | 296 | pt_addr = ppgtt->pt_dma_addr[i]; |
26b1ff35 BW |
297 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
298 | pd_entry |= GEN6_PDE_VALID; | |
299 | ||
300 | writel(pd_entry, pd_addr + i); | |
301 | } | |
302 | readl(pd_addr); | |
303 | ||
304 | pd_offset = ppgtt->pd_offset; | |
305 | pd_offset /= 64; /* in cachelines, */ | |
306 | pd_offset <<= 16; | |
307 | ||
308 | if (INTEL_INFO(dev)->gen == 6) { | |
309 | uint32_t ecochk, gab_ctl, ecobits; | |
310 | ||
311 | ecobits = I915_READ(GAC_ECO_BITS); | |
312 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
313 | ||
314 | gab_ctl = I915_READ(GAB_CTL); | |
315 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
316 | ||
317 | ecochk = I915_READ(GAM_ECOCHK); | |
318 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
319 | ECOCHK_PPGTT_CACHE64B); | |
320 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
321 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
322 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
323 | /* GFX_MODE is per-ring on gen7+ */ | |
324 | } | |
325 | ||
326 | for_each_ring(ring, dev_priv, i) { | |
327 | if (INTEL_INFO(dev)->gen >= 7) | |
328 | I915_WRITE(RING_MODE_GEN7(ring), | |
329 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
330 | ||
331 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
332 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
333 | } | |
334 | } | |
335 | ||
a81cc00c BW |
336 | extern int intel_iommu_gfx_mapped; |
337 | /* Certain Gen5 chipsets require require idling the GPU before | |
338 | * unmapping anything from the GTT when VT-d is enabled. | |
339 | */ | |
340 | static inline bool needs_idle_maps(struct drm_device *dev) | |
341 | { | |
342 | #ifdef CONFIG_INTEL_IOMMU | |
343 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
344 | * was loaded first. | |
345 | */ | |
346 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
347 | return true; | |
348 | #endif | |
349 | return false; | |
350 | } | |
351 | ||
5c042287 BW |
352 | static bool do_idling(struct drm_i915_private *dev_priv) |
353 | { | |
354 | bool ret = dev_priv->mm.interruptible; | |
355 | ||
a81cc00c | 356 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 357 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 358 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
359 | DRM_ERROR("Couldn't idle GPU\n"); |
360 | /* Wait a bit, in hopes it avoids the hang */ | |
361 | udelay(10); | |
362 | } | |
363 | } | |
364 | ||
365 | return ret; | |
366 | } | |
367 | ||
368 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
369 | { | |
a81cc00c | 370 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
371 | dev_priv->mm.interruptible = interruptible; |
372 | } | |
373 | ||
76aaf220 DV |
374 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
375 | { | |
376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 377 | struct drm_i915_gem_object *obj; |
76aaf220 | 378 | |
bee4a186 | 379 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
380 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
381 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 382 | |
6c085a72 | 383 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
a8e93126 | 384 | i915_gem_clflush_object(obj); |
74163907 | 385 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
386 | } |
387 | ||
e76e9aeb | 388 | i915_gem_chipset_flush(dev); |
76aaf220 | 389 | } |
7c2e6fdf | 390 | |
74163907 | 391 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 392 | { |
9da3da66 | 393 | if (obj->has_dma_mapping) |
74163907 | 394 | return 0; |
9da3da66 CW |
395 | |
396 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
397 | obj->pages->sgl, obj->pages->nents, | |
398 | PCI_DMA_BIDIRECTIONAL)) | |
399 | return -ENOSPC; | |
400 | ||
401 | return 0; | |
7c2e6fdf DV |
402 | } |
403 | ||
e76e9aeb BW |
404 | /* |
405 | * Binds an object into the global gtt with the specified cache level. The object | |
406 | * will be accessible to the GPU via commands whose operands reference offsets | |
407 | * within the global GTT as well as accessible by the GPU through the GMADR | |
408 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
409 | */ | |
7faf1ab2 DV |
410 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
411 | struct sg_table *st, | |
412 | unsigned int first_entry, | |
413 | enum i915_cache_level level) | |
e76e9aeb | 414 | { |
e76e9aeb | 415 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7c2b58b BW |
416 | gen6_gtt_pte_t __iomem *gtt_entries = |
417 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
418 | int i = 0; |
419 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
420 | dma_addr_t addr; |
421 | ||
6e995e23 | 422 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 423 | addr = sg_page_iter_dma_address(&sg_iter); |
6e995e23 ID |
424 | iowrite32(gen6_pte_encode(dev, addr, level), >t_entries[i]); |
425 | i++; | |
e76e9aeb BW |
426 | } |
427 | ||
e76e9aeb BW |
428 | /* XXX: This serves as a posting read to make sure that the PTE has |
429 | * actually been updated. There is some concern that even though | |
430 | * registers and PTEs are within the same BAR that they are potentially | |
431 | * of NUMA access patterns. Therefore, even with the way we assume | |
432 | * hardware should work, we must keep this posting read for paranoia. | |
433 | */ | |
434 | if (i != 0) | |
960e3e42 DV |
435 | WARN_ON(readl(>t_entries[i-1]) |
436 | != gen6_pte_encode(dev, addr, level)); | |
0f9b91c7 BW |
437 | |
438 | /* This next bit makes the above posting read even more important. We | |
439 | * want to flush the TLBs only after we're certain all the PTE updates | |
440 | * have finished. | |
441 | */ | |
442 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
443 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
444 | } |
445 | ||
7faf1ab2 DV |
446 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
447 | unsigned int first_entry, | |
448 | unsigned int num_entries) | |
449 | { | |
450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e7c2b58b BW |
451 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
452 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 453 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
454 | int i; |
455 | ||
456 | if (WARN(num_entries > max_entries, | |
457 | "First entry = %d; Num entries = %d (max=%d)\n", | |
458 | first_entry, num_entries, max_entries)) | |
459 | num_entries = max_entries; | |
460 | ||
960e3e42 DV |
461 | scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma, |
462 | I915_CACHE_LLC); | |
7faf1ab2 DV |
463 | for (i = 0; i < num_entries; i++) |
464 | iowrite32(scratch_pte, >t_base[i]); | |
465 | readl(gtt_base); | |
466 | } | |
467 | ||
468 | ||
469 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
470 | struct sg_table *st, | |
471 | unsigned int pg_start, | |
472 | enum i915_cache_level cache_level) | |
473 | { | |
474 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
475 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
476 | ||
477 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
478 | ||
479 | } | |
480 | ||
481 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
482 | unsigned int first_entry, | |
483 | unsigned int num_entries) | |
484 | { | |
485 | intel_gtt_clear_range(first_entry, num_entries); | |
486 | } | |
487 | ||
488 | ||
74163907 DV |
489 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
490 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
491 | { |
492 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
493 | struct drm_i915_private *dev_priv = dev->dev_private; |
494 | ||
495 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
496 | obj->gtt_space->start >> PAGE_SHIFT, | |
497 | cache_level); | |
d5bd1449 | 498 | |
74898d7e | 499 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
500 | } |
501 | ||
05394f39 | 502 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 503 | { |
7faf1ab2 DV |
504 | struct drm_device *dev = obj->base.dev; |
505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
506 | ||
507 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
508 | obj->gtt_space->start >> PAGE_SHIFT, | |
509 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
510 | |
511 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
512 | } |
513 | ||
514 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 515 | { |
5c042287 BW |
516 | struct drm_device *dev = obj->base.dev; |
517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
518 | bool interruptible; | |
519 | ||
520 | interruptible = do_idling(dev_priv); | |
521 | ||
9da3da66 CW |
522 | if (!obj->has_dma_mapping) |
523 | dma_unmap_sg(&dev->pdev->dev, | |
524 | obj->pages->sgl, obj->pages->nents, | |
525 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
526 | |
527 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 528 | } |
644ec02b | 529 | |
42d6ab48 CW |
530 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
531 | unsigned long color, | |
532 | unsigned long *start, | |
533 | unsigned long *end) | |
534 | { | |
535 | if (node->color != color) | |
536 | *start += 4096; | |
537 | ||
538 | if (!list_empty(&node->node_list)) { | |
539 | node = list_entry(node->node_list.next, | |
540 | struct drm_mm_node, | |
541 | node_list); | |
542 | if (node->allocated && node->color != color) | |
543 | *end -= 4096; | |
544 | } | |
545 | } | |
d7e5008f BW |
546 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
547 | unsigned long start, | |
548 | unsigned long mappable_end, | |
549 | unsigned long end) | |
644ec02b | 550 | { |
e78891ca BW |
551 | /* Let GEM Manage all of the aperture. |
552 | * | |
553 | * However, leave one page at the end still bound to the scratch page. | |
554 | * There are a number of places where the hardware apparently prefetches | |
555 | * past the end of the object, and we've seen multiple hangs with the | |
556 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
557 | * aperture. One page should be enough to keep any prefetching inside | |
558 | * of the aperture. | |
559 | */ | |
644ec02b | 560 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
561 | struct drm_mm_node *entry; |
562 | struct drm_i915_gem_object *obj; | |
563 | unsigned long hole_start, hole_end; | |
644ec02b | 564 | |
35451cb6 BW |
565 | BUG_ON(mappable_end > end); |
566 | ||
ed2f3452 | 567 | /* Subtract the guard page ... */ |
d1dd20a9 | 568 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
569 | if (!HAS_LLC(dev)) |
570 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 571 | |
ed2f3452 CW |
572 | /* Mark any preallocated objects as occupied */ |
573 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
574 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", | |
575 | obj->gtt_offset, obj->base.size); | |
576 | ||
577 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
578 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
579 | obj->gtt_offset, | |
580 | obj->base.size, | |
581 | false); | |
582 | obj->has_global_gtt_mapping = 1; | |
583 | } | |
584 | ||
5d4545ae | 585 | dev_priv->gtt.start = start; |
5d4545ae | 586 | dev_priv->gtt.total = end - start; |
644ec02b | 587 | |
ed2f3452 CW |
588 | /* Clear any non-preallocated blocks */ |
589 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
590 | hole_start, hole_end) { | |
591 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
592 | hole_start, hole_end); | |
7faf1ab2 DV |
593 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
594 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
595 | } |
596 | ||
597 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 598 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
599 | } |
600 | ||
d7e5008f BW |
601 | static bool |
602 | intel_enable_ppgtt(struct drm_device *dev) | |
603 | { | |
604 | if (i915_enable_ppgtt >= 0) | |
605 | return i915_enable_ppgtt; | |
606 | ||
607 | #ifdef CONFIG_INTEL_IOMMU | |
608 | /* Disable ppgtt on SNB if VT-d is on. */ | |
609 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
610 | return false; | |
611 | #endif | |
612 | ||
613 | return true; | |
614 | } | |
615 | ||
616 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
617 | { | |
618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
619 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 620 | |
a54c0c27 | 621 | gtt_size = dev_priv->gtt.total; |
93d18799 | 622 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
623 | |
624 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 625 | int ret; |
d7e5008f BW |
626 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the |
627 | * aperture accordingly when using aliasing ppgtt. */ | |
628 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
629 | ||
630 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
631 | ||
632 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 633 | if (!ret) |
d7e5008f | 634 | return; |
e78891ca BW |
635 | |
636 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
637 | drm_mm_takedown(&dev_priv->mm.gtt_space); | |
638 | gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
d7e5008f | 639 | } |
e78891ca | 640 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
641 | } |
642 | ||
643 | static int setup_scratch_page(struct drm_device *dev) | |
644 | { | |
645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
646 | struct page *page; | |
647 | dma_addr_t dma_addr; | |
648 | ||
649 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
650 | if (page == NULL) | |
651 | return -ENOMEM; | |
652 | get_page(page); | |
653 | set_pages_uc(page, 1); | |
654 | ||
655 | #ifdef CONFIG_INTEL_IOMMU | |
656 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
657 | PCI_DMA_BIDIRECTIONAL); | |
658 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
659 | return -EINVAL; | |
660 | #else | |
661 | dma_addr = page_to_phys(page); | |
662 | #endif | |
9c61a32d BW |
663 | dev_priv->gtt.scratch_page = page; |
664 | dev_priv->gtt.scratch_page_dma = dma_addr; | |
e76e9aeb BW |
665 | |
666 | return 0; | |
667 | } | |
668 | ||
669 | static void teardown_scratch_page(struct drm_device *dev) | |
670 | { | |
671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9c61a32d BW |
672 | set_pages_wb(dev_priv->gtt.scratch_page, 1); |
673 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, | |
e76e9aeb | 674 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
9c61a32d BW |
675 | put_page(dev_priv->gtt.scratch_page); |
676 | __free_page(dev_priv->gtt.scratch_page); | |
e76e9aeb BW |
677 | } |
678 | ||
679 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
680 | { | |
681 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
682 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
683 | return snb_gmch_ctl << 20; | |
684 | } | |
685 | ||
baa09f5f | 686 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
687 | { |
688 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
689 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
690 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
691 | } | |
692 | ||
baa09f5f | 693 | static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl) |
03752f5b BW |
694 | { |
695 | static const int stolen_decoder[] = { | |
696 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352}; | |
697 | snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT; | |
698 | snb_gmch_ctl &= IVB_GMCH_GMS_MASK; | |
699 | return stolen_decoder[snb_gmch_ctl] << 20; | |
700 | } | |
701 | ||
baa09f5f BW |
702 | static int gen6_gmch_probe(struct drm_device *dev, |
703 | size_t *gtt_total, | |
41907ddc BW |
704 | size_t *stolen, |
705 | phys_addr_t *mappable_base, | |
706 | unsigned long *mappable_end) | |
e76e9aeb BW |
707 | { |
708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
709 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 710 | unsigned int gtt_size; |
e76e9aeb | 711 | u16 snb_gmch_ctl; |
e76e9aeb BW |
712 | int ret; |
713 | ||
41907ddc BW |
714 | *mappable_base = pci_resource_start(dev->pdev, 2); |
715 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
716 | ||
baa09f5f BW |
717 | /* 64/512MB is the current min/max we actually know of, but this is just |
718 | * a coarse sanity check. | |
e76e9aeb | 719 | */ |
41907ddc | 720 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
721 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
722 | dev_priv->gtt.mappable_end); | |
723 | return -ENXIO; | |
e76e9aeb BW |
724 | } |
725 | ||
e76e9aeb BW |
726 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
727 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 728 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 729 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 730 | |
086ddcce | 731 | if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) |
baa09f5f BW |
732 | *stolen = gen7_get_stolen_size(snb_gmch_ctl); |
733 | else | |
734 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); | |
e76e9aeb | 735 | |
e7c2b58b | 736 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 737 | |
a93e4161 BW |
738 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
739 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
740 | (pci_resource_len(dev->pdev, 0) / 2); | |
741 | ||
baa09f5f | 742 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 743 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 744 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 745 | return -ENOMEM; |
e76e9aeb BW |
746 | } |
747 | ||
baa09f5f BW |
748 | ret = setup_scratch_page(dev); |
749 | if (ret) | |
750 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 751 | |
7faf1ab2 DV |
752 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
753 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
754 | ||
e76e9aeb BW |
755 | return ret; |
756 | } | |
757 | ||
d93c6233 | 758 | static void gen6_gmch_remove(struct drm_device *dev) |
e76e9aeb BW |
759 | { |
760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 761 | iounmap(dev_priv->gtt.gsm); |
baa09f5f | 762 | teardown_scratch_page(dev_priv->dev); |
644ec02b | 763 | } |
baa09f5f BW |
764 | |
765 | static int i915_gmch_probe(struct drm_device *dev, | |
766 | size_t *gtt_total, | |
41907ddc BW |
767 | size_t *stolen, |
768 | phys_addr_t *mappable_base, | |
769 | unsigned long *mappable_end) | |
baa09f5f BW |
770 | { |
771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
772 | int ret; | |
773 | ||
baa09f5f BW |
774 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
775 | if (!ret) { | |
776 | DRM_ERROR("failed to set up gmch\n"); | |
777 | return -EIO; | |
778 | } | |
779 | ||
41907ddc | 780 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
781 | |
782 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
783 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | |
784 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static void i915_gmch_remove(struct drm_device *dev) | |
790 | { | |
791 | intel_gmch_remove(); | |
792 | } | |
793 | ||
794 | int i915_gem_gtt_init(struct drm_device *dev) | |
795 | { | |
796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
797 | struct i915_gtt *gtt = &dev_priv->gtt; | |
798 | unsigned long gtt_size; | |
799 | int ret; | |
800 | ||
baa09f5f BW |
801 | if (INTEL_INFO(dev)->gen <= 5) { |
802 | dev_priv->gtt.gtt_probe = i915_gmch_probe; | |
803 | dev_priv->gtt.gtt_remove = i915_gmch_remove; | |
804 | } else { | |
805 | dev_priv->gtt.gtt_probe = gen6_gmch_probe; | |
806 | dev_priv->gtt.gtt_remove = gen6_gmch_remove; | |
807 | } | |
808 | ||
809 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, | |
41907ddc BW |
810 | &dev_priv->gtt.stolen_size, |
811 | >t->mappable_base, | |
812 | >t->mappable_end); | |
a54c0c27 | 813 | if (ret) |
baa09f5f | 814 | return ret; |
baa09f5f | 815 | |
e7c2b58b | 816 | gtt_size = (dev_priv->gtt.total >> PAGE_SHIFT) * sizeof(gen6_gtt_pte_t); |
baa09f5f BW |
817 | |
818 | /* GMADR is the PCI mmio aperture into the global GTT. */ | |
819 | DRM_INFO("Memory usable by graphics device = %zdM\n", | |
820 | dev_priv->gtt.total >> 20); | |
821 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", | |
822 | dev_priv->gtt.mappable_end >> 20); | |
823 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", | |
824 | dev_priv->gtt.stolen_size >> 20); | |
825 | ||
826 | return 0; | |
827 | } |