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Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
33 | ||
26b1ff35 BW |
34 | /* PPGTT stuff */ |
35 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 36 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
37 | |
38 | #define GEN6_PDE_VALID (1 << 0) | |
39 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
40 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
41 | ||
42 | #define GEN6_PTE_VALID (1 << 0) | |
43 | #define GEN6_PTE_UNCACHED (1 << 1) | |
44 | #define HSW_PTE_UNCACHED (0) | |
45 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
46 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
47 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
0d8ff15e BW |
48 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
49 | ||
50 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
51 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
52 | */ | |
53 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
54 | (((bits) & 0x8) << (11 - 3))) | |
55 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
4d15c145 | 56 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
26b1ff35 | 57 | |
80a74f7f | 58 | static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr, |
2d04befb | 59 | enum i915_cache_level level) |
54d12527 | 60 | { |
e7c2b58b | 61 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 62 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
63 | |
64 | switch (level) { | |
65 | case I915_CACHE_LLC_MLC: | |
9119708c | 66 | pte |= GEN6_PTE_CACHE_LLC_MLC; |
e7210c3c BW |
67 | break; |
68 | case I915_CACHE_LLC: | |
69 | pte |= GEN6_PTE_CACHE_LLC; | |
70 | break; | |
71 | case I915_CACHE_NONE: | |
9119708c | 72 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
73 | break; |
74 | default: | |
75 | BUG(); | |
76 | } | |
77 | ||
54d12527 BW |
78 | return pte; |
79 | } | |
80 | ||
93c34e70 KG |
81 | #define BYT_PTE_WRITEABLE (1 << 1) |
82 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
83 | ||
80a74f7f | 84 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
93c34e70 KG |
85 | enum i915_cache_level level) |
86 | { | |
87 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
88 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
89 | ||
90 | /* Mark the page as writeable. Other platforms don't have a | |
91 | * setting for read-only/writable, so this matches that behavior. | |
92 | */ | |
93 | pte |= BYT_PTE_WRITEABLE; | |
94 | ||
95 | if (level != I915_CACHE_NONE) | |
96 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
97 | ||
98 | return pte; | |
99 | } | |
100 | ||
80a74f7f | 101 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
9119708c KG |
102 | enum i915_cache_level level) |
103 | { | |
104 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
0d8ff15e | 105 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
106 | |
107 | if (level != I915_CACHE_NONE) | |
0d8ff15e | 108 | pte |= HSW_WB_LLC_AGE0; |
9119708c KG |
109 | |
110 | return pte; | |
111 | } | |
112 | ||
4d15c145 BW |
113 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
114 | enum i915_cache_level level) | |
115 | { | |
116 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
117 | pte |= HSW_PTE_ADDR_ENCODE(addr); | |
118 | ||
119 | if (level != I915_CACHE_NONE) | |
120 | pte |= HSW_WB_ELLC_LLC_AGE0; | |
121 | ||
122 | return pte; | |
123 | } | |
124 | ||
3e302542 | 125 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 126 | { |
853ba5d2 | 127 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
128 | gen6_gtt_pte_t __iomem *pd_addr; |
129 | uint32_t pd_entry; | |
130 | int i; | |
131 | ||
0a732870 | 132 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
133 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
134 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
135 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
136 | dma_addr_t pt_addr; | |
137 | ||
138 | pt_addr = ppgtt->pt_dma_addr[i]; | |
139 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
140 | pd_entry |= GEN6_PDE_VALID; | |
141 | ||
142 | writel(pd_entry, pd_addr + i); | |
143 | } | |
144 | readl(pd_addr); | |
3e302542 BW |
145 | } |
146 | ||
147 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
148 | { | |
149 | drm_i915_private_t *dev_priv = dev->dev_private; | |
150 | uint32_t pd_offset; | |
151 | struct intel_ring_buffer *ring; | |
152 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
153 | int i; | |
154 | ||
155 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
156 | ||
157 | gen6_write_pdes(ppgtt); | |
6197349b BW |
158 | |
159 | pd_offset = ppgtt->pd_offset; | |
160 | pd_offset /= 64; /* in cachelines, */ | |
161 | pd_offset <<= 16; | |
162 | ||
163 | if (INTEL_INFO(dev)->gen == 6) { | |
164 | uint32_t ecochk, gab_ctl, ecobits; | |
165 | ||
166 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
167 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
168 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
169 | |
170 | gab_ctl = I915_READ(GAB_CTL); | |
171 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
172 | ||
173 | ecochk = I915_READ(GAM_ECOCHK); | |
174 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
175 | ECOCHK_PPGTT_CACHE64B); | |
176 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
177 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 178 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
179 | |
180 | ecobits = I915_READ(GAC_ECO_BITS); | |
181 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
182 | ||
a6f429a5 VS |
183 | ecochk = I915_READ(GAM_ECOCHK); |
184 | if (IS_HASWELL(dev)) { | |
185 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
186 | } else { | |
187 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
188 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
189 | } | |
190 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
191 | /* GFX_MODE is per-ring on gen7+ */ |
192 | } | |
193 | ||
194 | for_each_ring(ring, dev_priv, i) { | |
195 | if (INTEL_INFO(dev)->gen >= 7) | |
196 | I915_WRITE(RING_MODE_GEN7(ring), | |
197 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
198 | ||
199 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
200 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
201 | } | |
b7c36d25 | 202 | return 0; |
6197349b BW |
203 | } |
204 | ||
1d2a314c | 205 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 206 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c DV |
207 | unsigned first_entry, |
208 | unsigned num_entries) | |
209 | { | |
853ba5d2 BW |
210 | struct i915_hw_ppgtt *ppgtt = |
211 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 212 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 213 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
214 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
215 | unsigned last_pte, i; | |
1d2a314c | 216 | |
853ba5d2 | 217 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); |
1d2a314c | 218 | |
7bddb01f DV |
219 | while (num_entries) { |
220 | last_pte = first_pte + num_entries; | |
221 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
222 | last_pte = I915_PPGTT_PT_ENTRIES; | |
223 | ||
a15326a5 | 224 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 225 | |
7bddb01f DV |
226 | for (i = first_pte; i < last_pte; i++) |
227 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
228 | |
229 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 230 | |
7bddb01f DV |
231 | num_entries -= last_pte - first_pte; |
232 | first_pte = 0; | |
a15326a5 | 233 | act_pt++; |
7bddb01f | 234 | } |
1d2a314c DV |
235 | } |
236 | ||
853ba5d2 | 237 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
238 | struct sg_table *pages, |
239 | unsigned first_entry, | |
240 | enum i915_cache_level cache_level) | |
241 | { | |
853ba5d2 BW |
242 | struct i915_hw_ppgtt *ppgtt = |
243 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 244 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 245 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
246 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
247 | struct sg_page_iter sg_iter; | |
248 | ||
a15326a5 | 249 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
250 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
251 | dma_addr_t page_addr; | |
252 | ||
2db76d7c | 253 | page_addr = sg_page_iter_dma_address(&sg_iter); |
853ba5d2 | 254 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level); |
6e995e23 ID |
255 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
256 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
257 | act_pt++; |
258 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 259 | act_pte = 0; |
def886c3 | 260 | |
def886c3 | 261 | } |
def886c3 | 262 | } |
6e995e23 | 263 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
264 | } |
265 | ||
853ba5d2 | 266 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 267 | { |
853ba5d2 BW |
268 | struct i915_hw_ppgtt *ppgtt = |
269 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
270 | int i; |
271 | ||
93bd8649 BW |
272 | drm_mm_takedown(&ppgtt->base.mm); |
273 | ||
3440d265 DV |
274 | if (ppgtt->pt_dma_addr) { |
275 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 276 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
277 | ppgtt->pt_dma_addr[i], |
278 | 4096, PCI_DMA_BIDIRECTIONAL); | |
279 | } | |
280 | ||
281 | kfree(ppgtt->pt_dma_addr); | |
282 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
283 | __free_page(ppgtt->pt_pages[i]); | |
284 | kfree(ppgtt->pt_pages); | |
285 | kfree(ppgtt); | |
286 | } | |
287 | ||
288 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
289 | { | |
853ba5d2 | 290 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 291 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 292 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
293 | int i; |
294 | int ret = -ENOMEM; | |
295 | ||
296 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
297 | * entries. For aliasing ppgtt support we just steal them at the end for | |
298 | * now. */ | |
e1b73cba | 299 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 300 | |
9119708c | 301 | if (IS_HASWELL(dev)) { |
853ba5d2 | 302 | ppgtt->base.pte_encode = hsw_pte_encode; |
9119708c | 303 | } else if (IS_VALLEYVIEW(dev)) { |
853ba5d2 | 304 | ppgtt->base.pte_encode = byt_pte_encode; |
93c34e70 | 305 | } else { |
853ba5d2 | 306 | ppgtt->base.pte_encode = gen6_pte_encode; |
93c34e70 | 307 | } |
6670a5a5 | 308 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 309 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
310 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
311 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
312 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
313 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
1d2a314c DV |
314 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
315 | GFP_KERNEL); | |
316 | if (!ppgtt->pt_pages) | |
3440d265 | 317 | return -ENOMEM; |
1d2a314c DV |
318 | |
319 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
320 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
321 | if (!ppgtt->pt_pages[i]) | |
322 | goto err_pt_alloc; | |
323 | } | |
324 | ||
8d2e6308 BW |
325 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
326 | GFP_KERNEL); | |
327 | if (!ppgtt->pt_dma_addr) | |
328 | goto err_pt_alloc; | |
1d2a314c | 329 | |
8d2e6308 BW |
330 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
331 | dma_addr_t pt_addr; | |
211c568b | 332 | |
8d2e6308 BW |
333 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
334 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 335 | |
8d2e6308 BW |
336 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
337 | ret = -EIO; | |
338 | goto err_pd_pin; | |
1d2a314c | 339 | |
211c568b | 340 | } |
8d2e6308 | 341 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 342 | } |
1d2a314c | 343 | |
853ba5d2 BW |
344 | ppgtt->base.clear_range(&ppgtt->base, 0, |
345 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 346 | |
e7c2b58b | 347 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 348 | |
1d2a314c DV |
349 | return 0; |
350 | ||
351 | err_pd_pin: | |
352 | if (ppgtt->pt_dma_addr) { | |
353 | for (i--; i >= 0; i--) | |
354 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
355 | 4096, PCI_DMA_BIDIRECTIONAL); | |
356 | } | |
357 | err_pt_alloc: | |
358 | kfree(ppgtt->pt_dma_addr); | |
359 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
360 | if (ppgtt->pt_pages[i]) | |
361 | __free_page(ppgtt->pt_pages[i]); | |
362 | } | |
363 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
364 | |
365 | return ret; | |
366 | } | |
367 | ||
368 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
369 | { | |
370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
371 | struct i915_hw_ppgtt *ppgtt; | |
372 | int ret; | |
373 | ||
374 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
375 | if (!ppgtt) | |
376 | return -ENOMEM; | |
377 | ||
853ba5d2 | 378 | ppgtt->base.dev = dev; |
3440d265 | 379 | |
3ed124b2 BW |
380 | if (INTEL_INFO(dev)->gen < 8) |
381 | ret = gen6_ppgtt_init(ppgtt); | |
382 | else | |
383 | BUG(); | |
384 | ||
3440d265 DV |
385 | if (ret) |
386 | kfree(ppgtt); | |
93bd8649 | 387 | else { |
3440d265 | 388 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
389 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
390 | ppgtt->base.total); | |
391 | } | |
1d2a314c DV |
392 | |
393 | return ret; | |
394 | } | |
395 | ||
396 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
397 | { | |
398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
399 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
400 | |
401 | if (!ppgtt) | |
402 | return; | |
403 | ||
853ba5d2 | 404 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 405 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
406 | } |
407 | ||
7bddb01f DV |
408 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
409 | struct drm_i915_gem_object *obj, | |
410 | enum i915_cache_level cache_level) | |
411 | { | |
853ba5d2 BW |
412 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
413 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
414 | cache_level); | |
7bddb01f DV |
415 | } |
416 | ||
417 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
418 | struct drm_i915_gem_object *obj) | |
419 | { | |
853ba5d2 BW |
420 | ppgtt->base.clear_range(&ppgtt->base, |
421 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
422 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
423 | } |
424 | ||
a81cc00c BW |
425 | extern int intel_iommu_gfx_mapped; |
426 | /* Certain Gen5 chipsets require require idling the GPU before | |
427 | * unmapping anything from the GTT when VT-d is enabled. | |
428 | */ | |
429 | static inline bool needs_idle_maps(struct drm_device *dev) | |
430 | { | |
431 | #ifdef CONFIG_INTEL_IOMMU | |
432 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
433 | * was loaded first. | |
434 | */ | |
435 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
436 | return true; | |
437 | #endif | |
438 | return false; | |
439 | } | |
440 | ||
5c042287 BW |
441 | static bool do_idling(struct drm_i915_private *dev_priv) |
442 | { | |
443 | bool ret = dev_priv->mm.interruptible; | |
444 | ||
a81cc00c | 445 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 446 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 447 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
448 | DRM_ERROR("Couldn't idle GPU\n"); |
449 | /* Wait a bit, in hopes it avoids the hang */ | |
450 | udelay(10); | |
451 | } | |
452 | } | |
453 | ||
454 | return ret; | |
455 | } | |
456 | ||
457 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
458 | { | |
a81cc00c | 459 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
460 | dev_priv->mm.interruptible = interruptible; |
461 | } | |
462 | ||
76aaf220 DV |
463 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
464 | { | |
465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 466 | struct drm_i915_gem_object *obj; |
76aaf220 | 467 | |
bee4a186 | 468 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
469 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
470 | dev_priv->gtt.base.start / PAGE_SIZE, | |
471 | dev_priv->gtt.base.total / PAGE_SIZE); | |
bee4a186 | 472 | |
35c20a60 | 473 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
a8e93126 | 474 | i915_gem_clflush_object(obj); |
74163907 | 475 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
476 | } |
477 | ||
e76e9aeb | 478 | i915_gem_chipset_flush(dev); |
76aaf220 | 479 | } |
7c2e6fdf | 480 | |
74163907 | 481 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 482 | { |
9da3da66 | 483 | if (obj->has_dma_mapping) |
74163907 | 484 | return 0; |
9da3da66 CW |
485 | |
486 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
487 | obj->pages->sgl, obj->pages->nents, | |
488 | PCI_DMA_BIDIRECTIONAL)) | |
489 | return -ENOSPC; | |
490 | ||
491 | return 0; | |
7c2e6fdf DV |
492 | } |
493 | ||
e76e9aeb BW |
494 | /* |
495 | * Binds an object into the global gtt with the specified cache level. The object | |
496 | * will be accessible to the GPU via commands whose operands reference offsets | |
497 | * within the global GTT as well as accessible by the GPU through the GMADR | |
498 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
499 | */ | |
853ba5d2 | 500 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
501 | struct sg_table *st, |
502 | unsigned int first_entry, | |
503 | enum i915_cache_level level) | |
e76e9aeb | 504 | { |
853ba5d2 | 505 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
506 | gen6_gtt_pte_t __iomem *gtt_entries = |
507 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
508 | int i = 0; |
509 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
510 | dma_addr_t addr; |
511 | ||
6e995e23 | 512 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 513 | addr = sg_page_iter_dma_address(&sg_iter); |
853ba5d2 | 514 | iowrite32(vm->pte_encode(addr, level), >t_entries[i]); |
6e995e23 | 515 | i++; |
e76e9aeb BW |
516 | } |
517 | ||
e76e9aeb BW |
518 | /* XXX: This serves as a posting read to make sure that the PTE has |
519 | * actually been updated. There is some concern that even though | |
520 | * registers and PTEs are within the same BAR that they are potentially | |
521 | * of NUMA access patterns. Therefore, even with the way we assume | |
522 | * hardware should work, we must keep this posting read for paranoia. | |
523 | */ | |
524 | if (i != 0) | |
853ba5d2 BW |
525 | WARN_ON(readl(>t_entries[i-1]) != |
526 | vm->pte_encode(addr, level)); | |
0f9b91c7 BW |
527 | |
528 | /* This next bit makes the above posting read even more important. We | |
529 | * want to flush the TLBs only after we're certain all the PTE updates | |
530 | * have finished. | |
531 | */ | |
532 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
533 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
534 | } |
535 | ||
853ba5d2 | 536 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 DV |
537 | unsigned int first_entry, |
538 | unsigned int num_entries) | |
539 | { | |
853ba5d2 | 540 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
541 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
542 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 543 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
544 | int i; |
545 | ||
546 | if (WARN(num_entries > max_entries, | |
547 | "First entry = %d; Num entries = %d (max=%d)\n", | |
548 | first_entry, num_entries, max_entries)) | |
549 | num_entries = max_entries; | |
550 | ||
853ba5d2 | 551 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); |
7faf1ab2 DV |
552 | for (i = 0; i < num_entries; i++) |
553 | iowrite32(scratch_pte, >t_base[i]); | |
554 | readl(gtt_base); | |
555 | } | |
556 | ||
557 | ||
853ba5d2 | 558 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
559 | struct sg_table *st, |
560 | unsigned int pg_start, | |
561 | enum i915_cache_level cache_level) | |
562 | { | |
563 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
564 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
565 | ||
566 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
567 | ||
568 | } | |
569 | ||
853ba5d2 | 570 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 DV |
571 | unsigned int first_entry, |
572 | unsigned int num_entries) | |
573 | { | |
574 | intel_gtt_clear_range(first_entry, num_entries); | |
575 | } | |
576 | ||
577 | ||
74163907 DV |
578 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
579 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
580 | { |
581 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 582 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 583 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 584 | |
853ba5d2 BW |
585 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
586 | entry, | |
587 | cache_level); | |
d5bd1449 | 588 | |
74898d7e | 589 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
590 | } |
591 | ||
05394f39 | 592 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 593 | { |
7faf1ab2 DV |
594 | struct drm_device *dev = obj->base.dev; |
595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 596 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 597 | |
853ba5d2 BW |
598 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
599 | entry, | |
600 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
601 | |
602 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
603 | } |
604 | ||
605 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 606 | { |
5c042287 BW |
607 | struct drm_device *dev = obj->base.dev; |
608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
609 | bool interruptible; | |
610 | ||
611 | interruptible = do_idling(dev_priv); | |
612 | ||
9da3da66 CW |
613 | if (!obj->has_dma_mapping) |
614 | dma_unmap_sg(&dev->pdev->dev, | |
615 | obj->pages->sgl, obj->pages->nents, | |
616 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
617 | |
618 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 619 | } |
644ec02b | 620 | |
42d6ab48 CW |
621 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
622 | unsigned long color, | |
623 | unsigned long *start, | |
624 | unsigned long *end) | |
625 | { | |
626 | if (node->color != color) | |
627 | *start += 4096; | |
628 | ||
629 | if (!list_empty(&node->node_list)) { | |
630 | node = list_entry(node->node_list.next, | |
631 | struct drm_mm_node, | |
632 | node_list); | |
633 | if (node->allocated && node->color != color) | |
634 | *end -= 4096; | |
635 | } | |
636 | } | |
d7e5008f BW |
637 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
638 | unsigned long start, | |
639 | unsigned long mappable_end, | |
640 | unsigned long end) | |
644ec02b | 641 | { |
e78891ca BW |
642 | /* Let GEM Manage all of the aperture. |
643 | * | |
644 | * However, leave one page at the end still bound to the scratch page. | |
645 | * There are a number of places where the hardware apparently prefetches | |
646 | * past the end of the object, and we've seen multiple hangs with the | |
647 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
648 | * aperture. One page should be enough to keep any prefetching inside | |
649 | * of the aperture. | |
650 | */ | |
644ec02b | 651 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
652 | struct drm_mm_node *entry; |
653 | struct drm_i915_gem_object *obj; | |
654 | unsigned long hole_start, hole_end; | |
644ec02b | 655 | |
35451cb6 BW |
656 | BUG_ON(mappable_end > end); |
657 | ||
ed2f3452 | 658 | /* Subtract the guard page ... */ |
93bd8649 | 659 | drm_mm_init(&dev_priv->gtt.base.mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 660 | if (!HAS_LLC(dev)) |
93bd8649 | 661 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 662 | |
ed2f3452 | 663 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 664 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2f633156 | 665 | struct i915_vma *vma = __i915_gem_obj_to_vma(obj); |
b3a070cc | 666 | int ret; |
edd41a87 | 667 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
668 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
669 | ||
670 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
2f633156 | 671 | ret = drm_mm_reserve_node(&dev_priv->gtt.base.mm, &vma->node); |
c6cfb325 | 672 | if (ret) |
b3a070cc | 673 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 | 674 | obj->has_global_gtt_mapping = 1; |
2f633156 | 675 | list_add(&vma->vma_link, &obj->vma_list); |
ed2f3452 CW |
676 | } |
677 | ||
853ba5d2 BW |
678 | dev_priv->gtt.base.start = start; |
679 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 680 | |
ed2f3452 | 681 | /* Clear any non-preallocated blocks */ |
93bd8649 | 682 | drm_mm_for_each_hole(entry, &dev_priv->gtt.base.mm, |
ed2f3452 | 683 | hole_start, hole_end) { |
853ba5d2 | 684 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
685 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
686 | hole_start, hole_end); | |
853ba5d2 BW |
687 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
688 | hole_start / PAGE_SIZE, | |
689 | count); | |
ed2f3452 CW |
690 | } |
691 | ||
692 | /* And finally clear the reserved guard page */ | |
853ba5d2 BW |
693 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
694 | end / PAGE_SIZE - 1, 1); | |
e76e9aeb BW |
695 | } |
696 | ||
d7e5008f BW |
697 | static bool |
698 | intel_enable_ppgtt(struct drm_device *dev) | |
699 | { | |
700 | if (i915_enable_ppgtt >= 0) | |
701 | return i915_enable_ppgtt; | |
702 | ||
703 | #ifdef CONFIG_INTEL_IOMMU | |
704 | /* Disable ppgtt on SNB if VT-d is on. */ | |
705 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
706 | return false; | |
707 | #endif | |
708 | ||
709 | return true; | |
710 | } | |
711 | ||
712 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
713 | { | |
714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
715 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 716 | |
853ba5d2 | 717 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 718 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
719 | |
720 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 721 | int ret; |
3eb1c005 BW |
722 | |
723 | if (INTEL_INFO(dev)->gen <= 7) { | |
724 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
725 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 726 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 727 | } |
d7e5008f BW |
728 | |
729 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
730 | ||
731 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 732 | if (!ret) |
d7e5008f | 733 | return; |
e78891ca BW |
734 | |
735 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 736 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
6670a5a5 | 737 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 738 | } |
e78891ca | 739 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
740 | } |
741 | ||
742 | static int setup_scratch_page(struct drm_device *dev) | |
743 | { | |
744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
745 | struct page *page; | |
746 | dma_addr_t dma_addr; | |
747 | ||
748 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
749 | if (page == NULL) | |
750 | return -ENOMEM; | |
751 | get_page(page); | |
752 | set_pages_uc(page, 1); | |
753 | ||
754 | #ifdef CONFIG_INTEL_IOMMU | |
755 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
756 | PCI_DMA_BIDIRECTIONAL); | |
757 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
758 | return -EINVAL; | |
759 | #else | |
760 | dma_addr = page_to_phys(page); | |
761 | #endif | |
853ba5d2 BW |
762 | dev_priv->gtt.base.scratch.page = page; |
763 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
764 | |
765 | return 0; | |
766 | } | |
767 | ||
768 | static void teardown_scratch_page(struct drm_device *dev) | |
769 | { | |
770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
771 | struct page *page = dev_priv->gtt.base.scratch.page; |
772 | ||
773 | set_pages_wb(page, 1); | |
774 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 775 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
776 | put_page(page); |
777 | __free_page(page); | |
e76e9aeb BW |
778 | } |
779 | ||
780 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
781 | { | |
782 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
783 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
784 | return snb_gmch_ctl << 20; | |
785 | } | |
786 | ||
baa09f5f | 787 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
788 | { |
789 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
790 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
791 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
792 | } | |
793 | ||
baa09f5f BW |
794 | static int gen6_gmch_probe(struct drm_device *dev, |
795 | size_t *gtt_total, | |
41907ddc BW |
796 | size_t *stolen, |
797 | phys_addr_t *mappable_base, | |
798 | unsigned long *mappable_end) | |
e76e9aeb BW |
799 | { |
800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
801 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 802 | unsigned int gtt_size; |
e76e9aeb | 803 | u16 snb_gmch_ctl; |
e76e9aeb BW |
804 | int ret; |
805 | ||
41907ddc BW |
806 | *mappable_base = pci_resource_start(dev->pdev, 2); |
807 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
808 | ||
baa09f5f BW |
809 | /* 64/512MB is the current min/max we actually know of, but this is just |
810 | * a coarse sanity check. | |
e76e9aeb | 811 | */ |
41907ddc | 812 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
813 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
814 | dev_priv->gtt.mappable_end); | |
815 | return -ENXIO; | |
e76e9aeb BW |
816 | } |
817 | ||
e76e9aeb BW |
818 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
819 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 820 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 821 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 822 | |
c4ae25ec | 823 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e7c2b58b | 824 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 825 | |
a93e4161 BW |
826 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
827 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
828 | (pci_resource_len(dev->pdev, 0) / 2); | |
829 | ||
baa09f5f | 830 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 831 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 832 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 833 | return -ENOMEM; |
e76e9aeb BW |
834 | } |
835 | ||
baa09f5f BW |
836 | ret = setup_scratch_page(dev); |
837 | if (ret) | |
838 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 839 | |
853ba5d2 BW |
840 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
841 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 842 | |
e76e9aeb BW |
843 | return ret; |
844 | } | |
845 | ||
853ba5d2 | 846 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 847 | { |
853ba5d2 BW |
848 | |
849 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
850 | iounmap(gtt->gsm); | |
851 | teardown_scratch_page(vm->dev); | |
644ec02b | 852 | } |
baa09f5f BW |
853 | |
854 | static int i915_gmch_probe(struct drm_device *dev, | |
855 | size_t *gtt_total, | |
41907ddc BW |
856 | size_t *stolen, |
857 | phys_addr_t *mappable_base, | |
858 | unsigned long *mappable_end) | |
baa09f5f BW |
859 | { |
860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
861 | int ret; | |
862 | ||
baa09f5f BW |
863 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
864 | if (!ret) { | |
865 | DRM_ERROR("failed to set up gmch\n"); | |
866 | return -EIO; | |
867 | } | |
868 | ||
41907ddc | 869 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
870 | |
871 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
872 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
873 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
874 | |
875 | return 0; | |
876 | } | |
877 | ||
853ba5d2 | 878 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
879 | { |
880 | intel_gmch_remove(); | |
881 | } | |
882 | ||
883 | int i915_gem_gtt_init(struct drm_device *dev) | |
884 | { | |
885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
886 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
887 | int ret; |
888 | ||
baa09f5f | 889 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 890 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 891 | gtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 892 | } else { |
b2f21b4d | 893 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 894 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 895 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 896 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 897 | else if (IS_HASWELL(dev)) |
853ba5d2 | 898 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 899 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 900 | gtt->base.pte_encode = byt_pte_encode; |
b2f21b4d | 901 | else |
853ba5d2 | 902 | gtt->base.pte_encode = gen6_pte_encode; |
baa09f5f BW |
903 | } |
904 | ||
853ba5d2 | 905 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 906 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 907 | if (ret) |
baa09f5f | 908 | return ret; |
baa09f5f | 909 | |
853ba5d2 BW |
910 | gtt->base.dev = dev; |
911 | ||
baa09f5f | 912 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
913 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
914 | gtt->base.total >> 20); | |
b2f21b4d BW |
915 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
916 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
917 | |
918 | return 0; | |
919 | } |