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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
f61c0609 BW |
31 | typedef uint32_t gtt_pte_t; |
32 | ||
26b1ff35 BW |
33 | /* PPGTT stuff */ |
34 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
35 | ||
36 | #define GEN6_PDE_VALID (1 << 0) | |
37 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
38 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
39 | ||
40 | #define GEN6_PTE_VALID (1 << 0) | |
41 | #define GEN6_PTE_UNCACHED (1 << 1) | |
42 | #define HSW_PTE_UNCACHED (0) | |
43 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
44 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
45 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
46 | ||
960e3e42 DV |
47 | static inline gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
48 | dma_addr_t addr, | |
49 | enum i915_cache_level level) | |
54d12527 BW |
50 | { |
51 | gtt_pte_t pte = GEN6_PTE_VALID; | |
52 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
e7210c3c BW |
53 | |
54 | switch (level) { | |
55 | case I915_CACHE_LLC_MLC: | |
56 | /* Haswell doesn't set L3 this way */ | |
57 | if (IS_HASWELL(dev)) | |
58 | pte |= GEN6_PTE_CACHE_LLC; | |
59 | else | |
60 | pte |= GEN6_PTE_CACHE_LLC_MLC; | |
61 | break; | |
62 | case I915_CACHE_LLC: | |
63 | pte |= GEN6_PTE_CACHE_LLC; | |
64 | break; | |
65 | case I915_CACHE_NONE: | |
66 | if (IS_HASWELL(dev)) | |
67 | pte |= HSW_PTE_UNCACHED; | |
68 | else | |
69 | pte |= GEN6_PTE_UNCACHED; | |
70 | break; | |
71 | default: | |
72 | BUG(); | |
73 | } | |
74 | ||
54d12527 BW |
75 | |
76 | return pte; | |
77 | } | |
78 | ||
1d2a314c | 79 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 80 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
81 | unsigned first_entry, |
82 | unsigned num_entries) | |
83 | { | |
f61c0609 BW |
84 | gtt_pte_t *pt_vaddr; |
85 | gtt_pte_t scratch_pte; | |
7bddb01f DV |
86 | unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; |
87 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; | |
88 | unsigned last_pte, i; | |
1d2a314c | 89 | |
960e3e42 DV |
90 | scratch_pte = gen6_pte_encode(ppgtt->dev, |
91 | ppgtt->scratch_page_dma_addr, | |
92 | I915_CACHE_LLC); | |
1d2a314c | 93 | |
7bddb01f DV |
94 | while (num_entries) { |
95 | last_pte = first_pte + num_entries; | |
96 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
97 | last_pte = I915_PPGTT_PT_ENTRIES; | |
98 | ||
99 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]); | |
1d2a314c | 100 | |
7bddb01f DV |
101 | for (i = first_pte; i < last_pte; i++) |
102 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
103 | |
104 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 105 | |
7bddb01f DV |
106 | num_entries -= last_pte - first_pte; |
107 | first_pte = 0; | |
108 | act_pd++; | |
109 | } | |
1d2a314c DV |
110 | } |
111 | ||
def886c3 DV |
112 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
113 | struct sg_table *pages, | |
114 | unsigned first_entry, | |
115 | enum i915_cache_level cache_level) | |
116 | { | |
117 | gtt_pte_t *pt_vaddr; | |
118 | unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; | |
119 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; | |
120 | unsigned i, j, m, segment_len; | |
121 | dma_addr_t page_addr; | |
122 | struct scatterlist *sg; | |
123 | ||
124 | /* init sg walking */ | |
125 | sg = pages->sgl; | |
126 | i = 0; | |
127 | segment_len = sg_dma_len(sg) >> PAGE_SHIFT; | |
128 | m = 0; | |
129 | ||
130 | while (i < pages->nents) { | |
131 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]); | |
132 | ||
133 | for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) { | |
134 | page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
960e3e42 DV |
135 | pt_vaddr[j] = gen6_pte_encode(ppgtt->dev, page_addr, |
136 | cache_level); | |
def886c3 DV |
137 | |
138 | /* grab the next page */ | |
139 | if (++m == segment_len) { | |
140 | if (++i == pages->nents) | |
141 | break; | |
142 | ||
143 | sg = sg_next(sg); | |
144 | segment_len = sg_dma_len(sg) >> PAGE_SHIFT; | |
145 | m = 0; | |
146 | } | |
147 | } | |
148 | ||
149 | kunmap_atomic(pt_vaddr); | |
150 | ||
151 | first_pte = 0; | |
152 | act_pd++; | |
153 | } | |
154 | } | |
155 | ||
3440d265 | 156 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 157 | { |
3440d265 DV |
158 | int i; |
159 | ||
160 | if (ppgtt->pt_dma_addr) { | |
161 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
162 | pci_unmap_page(ppgtt->dev->pdev, | |
163 | ppgtt->pt_dma_addr[i], | |
164 | 4096, PCI_DMA_BIDIRECTIONAL); | |
165 | } | |
166 | ||
167 | kfree(ppgtt->pt_dma_addr); | |
168 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
169 | __free_page(ppgtt->pt_pages[i]); | |
170 | kfree(ppgtt->pt_pages); | |
171 | kfree(ppgtt); | |
172 | } | |
173 | ||
174 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
175 | { | |
176 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 177 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 178 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
179 | int i; |
180 | int ret = -ENOMEM; | |
181 | ||
182 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
183 | * entries. For aliasing ppgtt support we just steal them at the end for | |
184 | * now. */ | |
9a0f938b | 185 | first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES; |
1d2a314c | 186 | |
1d2a314c | 187 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
def886c3 DV |
188 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
189 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 190 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
191 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
192 | GFP_KERNEL); | |
193 | if (!ppgtt->pt_pages) | |
3440d265 | 194 | return -ENOMEM; |
1d2a314c DV |
195 | |
196 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
197 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
198 | if (!ppgtt->pt_pages[i]) | |
199 | goto err_pt_alloc; | |
200 | } | |
201 | ||
8d2e6308 BW |
202 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
203 | GFP_KERNEL); | |
204 | if (!ppgtt->pt_dma_addr) | |
205 | goto err_pt_alloc; | |
1d2a314c | 206 | |
8d2e6308 BW |
207 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
208 | dma_addr_t pt_addr; | |
211c568b | 209 | |
8d2e6308 BW |
210 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
211 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 212 | |
8d2e6308 BW |
213 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
214 | ret = -EIO; | |
215 | goto err_pd_pin; | |
1d2a314c | 216 | |
211c568b | 217 | } |
8d2e6308 | 218 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 219 | } |
1d2a314c | 220 | |
9c61a32d | 221 | ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; |
1d2a314c | 222 | |
def886c3 DV |
223 | ppgtt->clear_range(ppgtt, 0, |
224 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 225 | |
f61c0609 | 226 | ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t); |
1d2a314c | 227 | |
1d2a314c DV |
228 | return 0; |
229 | ||
230 | err_pd_pin: | |
231 | if (ppgtt->pt_dma_addr) { | |
232 | for (i--; i >= 0; i--) | |
233 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
234 | 4096, PCI_DMA_BIDIRECTIONAL); | |
235 | } | |
236 | err_pt_alloc: | |
237 | kfree(ppgtt->pt_dma_addr); | |
238 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
239 | if (ppgtt->pt_pages[i]) | |
240 | __free_page(ppgtt->pt_pages[i]); | |
241 | } | |
242 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
243 | |
244 | return ret; | |
245 | } | |
246 | ||
247 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
248 | { | |
249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
250 | struct i915_hw_ppgtt *ppgtt; | |
251 | int ret; | |
252 | ||
253 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
254 | if (!ppgtt) | |
255 | return -ENOMEM; | |
256 | ||
257 | ppgtt->dev = dev; | |
258 | ||
259 | ret = gen6_ppgtt_init(ppgtt); | |
260 | if (ret) | |
261 | kfree(ppgtt); | |
262 | else | |
263 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
264 | |
265 | return ret; | |
266 | } | |
267 | ||
268 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
269 | { | |
270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
271 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
272 | |
273 | if (!ppgtt) | |
274 | return; | |
275 | ||
3440d265 | 276 | ppgtt->cleanup(ppgtt); |
1d2a314c DV |
277 | } |
278 | ||
7bddb01f DV |
279 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
280 | struct drm_i915_gem_object *obj, | |
281 | enum i915_cache_level cache_level) | |
282 | { | |
def886c3 DV |
283 | ppgtt->insert_entries(ppgtt, obj->pages, |
284 | obj->gtt_space->start >> PAGE_SHIFT, | |
285 | cache_level); | |
7bddb01f DV |
286 | } |
287 | ||
288 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
289 | struct drm_i915_gem_object *obj) | |
290 | { | |
def886c3 DV |
291 | ppgtt->clear_range(ppgtt, |
292 | obj->gtt_space->start >> PAGE_SHIFT, | |
293 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
294 | } |
295 | ||
26b1ff35 BW |
296 | void i915_gem_init_ppgtt(struct drm_device *dev) |
297 | { | |
298 | drm_i915_private_t *dev_priv = dev->dev_private; | |
299 | uint32_t pd_offset; | |
300 | struct intel_ring_buffer *ring; | |
301 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
079a43f6 | 302 | gtt_pte_t __iomem *pd_addr; |
26b1ff35 BW |
303 | uint32_t pd_entry; |
304 | int i; | |
305 | ||
306 | if (!dev_priv->mm.aliasing_ppgtt) | |
307 | return; | |
308 | ||
309 | ||
5d4545ae | 310 | pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t); |
26b1ff35 BW |
311 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
312 | dma_addr_t pt_addr; | |
313 | ||
8d2e6308 | 314 | pt_addr = ppgtt->pt_dma_addr[i]; |
26b1ff35 BW |
315 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
316 | pd_entry |= GEN6_PDE_VALID; | |
317 | ||
318 | writel(pd_entry, pd_addr + i); | |
319 | } | |
320 | readl(pd_addr); | |
321 | ||
322 | pd_offset = ppgtt->pd_offset; | |
323 | pd_offset /= 64; /* in cachelines, */ | |
324 | pd_offset <<= 16; | |
325 | ||
326 | if (INTEL_INFO(dev)->gen == 6) { | |
327 | uint32_t ecochk, gab_ctl, ecobits; | |
328 | ||
329 | ecobits = I915_READ(GAC_ECO_BITS); | |
330 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
331 | ||
332 | gab_ctl = I915_READ(GAB_CTL); | |
333 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
334 | ||
335 | ecochk = I915_READ(GAM_ECOCHK); | |
336 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
337 | ECOCHK_PPGTT_CACHE64B); | |
338 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
339 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
340 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
341 | /* GFX_MODE is per-ring on gen7+ */ | |
342 | } | |
343 | ||
344 | for_each_ring(ring, dev_priv, i) { | |
345 | if (INTEL_INFO(dev)->gen >= 7) | |
346 | I915_WRITE(RING_MODE_GEN7(ring), | |
347 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
348 | ||
349 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
350 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
351 | } | |
352 | } | |
353 | ||
a81cc00c BW |
354 | extern int intel_iommu_gfx_mapped; |
355 | /* Certain Gen5 chipsets require require idling the GPU before | |
356 | * unmapping anything from the GTT when VT-d is enabled. | |
357 | */ | |
358 | static inline bool needs_idle_maps(struct drm_device *dev) | |
359 | { | |
360 | #ifdef CONFIG_INTEL_IOMMU | |
361 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
362 | * was loaded first. | |
363 | */ | |
364 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
365 | return true; | |
366 | #endif | |
367 | return false; | |
368 | } | |
369 | ||
5c042287 BW |
370 | static bool do_idling(struct drm_i915_private *dev_priv) |
371 | { | |
372 | bool ret = dev_priv->mm.interruptible; | |
373 | ||
a81cc00c | 374 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 375 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 376 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
377 | DRM_ERROR("Couldn't idle GPU\n"); |
378 | /* Wait a bit, in hopes it avoids the hang */ | |
379 | udelay(10); | |
380 | } | |
381 | } | |
382 | ||
383 | return ret; | |
384 | } | |
385 | ||
386 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
387 | { | |
a81cc00c | 388 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
389 | dev_priv->mm.interruptible = interruptible; |
390 | } | |
391 | ||
76aaf220 DV |
392 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
393 | { | |
394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 395 | struct drm_i915_gem_object *obj; |
76aaf220 | 396 | |
bee4a186 | 397 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
398 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
399 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 400 | |
6c085a72 | 401 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
a8e93126 | 402 | i915_gem_clflush_object(obj); |
74163907 | 403 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
404 | } |
405 | ||
e76e9aeb | 406 | i915_gem_chipset_flush(dev); |
76aaf220 | 407 | } |
7c2e6fdf | 408 | |
74163907 | 409 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 410 | { |
9da3da66 | 411 | if (obj->has_dma_mapping) |
74163907 | 412 | return 0; |
9da3da66 CW |
413 | |
414 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
415 | obj->pages->sgl, obj->pages->nents, | |
416 | PCI_DMA_BIDIRECTIONAL)) | |
417 | return -ENOSPC; | |
418 | ||
419 | return 0; | |
7c2e6fdf DV |
420 | } |
421 | ||
e76e9aeb BW |
422 | /* |
423 | * Binds an object into the global gtt with the specified cache level. The object | |
424 | * will be accessible to the GPU via commands whose operands reference offsets | |
425 | * within the global GTT as well as accessible by the GPU through the GMADR | |
426 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
427 | */ | |
7faf1ab2 DV |
428 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
429 | struct sg_table *st, | |
430 | unsigned int first_entry, | |
431 | enum i915_cache_level level) | |
e76e9aeb | 432 | { |
e76e9aeb | 433 | struct drm_i915_private *dev_priv = dev->dev_private; |
e76e9aeb | 434 | struct scatterlist *sg = st->sgl; |
1c45140d | 435 | gtt_pte_t __iomem *gtt_entries = |
5d4545ae | 436 | (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
e76e9aeb BW |
437 | int unused, i = 0; |
438 | unsigned int len, m = 0; | |
439 | dma_addr_t addr; | |
440 | ||
441 | for_each_sg(st->sgl, sg, st->nents, unused) { | |
442 | len = sg_dma_len(sg) >> PAGE_SHIFT; | |
443 | for (m = 0; m < len; m++) { | |
444 | addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
960e3e42 DV |
445 | iowrite32(gen6_pte_encode(dev, addr, level), |
446 | >t_entries[i]); | |
e76e9aeb BW |
447 | i++; |
448 | } | |
449 | } | |
450 | ||
e76e9aeb BW |
451 | /* XXX: This serves as a posting read to make sure that the PTE has |
452 | * actually been updated. There is some concern that even though | |
453 | * registers and PTEs are within the same BAR that they are potentially | |
454 | * of NUMA access patterns. Therefore, even with the way we assume | |
455 | * hardware should work, we must keep this posting read for paranoia. | |
456 | */ | |
457 | if (i != 0) | |
960e3e42 DV |
458 | WARN_ON(readl(>t_entries[i-1]) |
459 | != gen6_pte_encode(dev, addr, level)); | |
0f9b91c7 BW |
460 | |
461 | /* This next bit makes the above posting read even more important. We | |
462 | * want to flush the TLBs only after we're certain all the PTE updates | |
463 | * have finished. | |
464 | */ | |
465 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
466 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
467 | } |
468 | ||
7faf1ab2 DV |
469 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
470 | unsigned int first_entry, | |
471 | unsigned int num_entries) | |
472 | { | |
473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
474 | gtt_pte_t scratch_pte; | |
475 | gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
476 | const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry; | |
477 | int i; | |
478 | ||
479 | if (WARN(num_entries > max_entries, | |
480 | "First entry = %d; Num entries = %d (max=%d)\n", | |
481 | first_entry, num_entries, max_entries)) | |
482 | num_entries = max_entries; | |
483 | ||
960e3e42 DV |
484 | scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma, |
485 | I915_CACHE_LLC); | |
7faf1ab2 DV |
486 | for (i = 0; i < num_entries; i++) |
487 | iowrite32(scratch_pte, >t_base[i]); | |
488 | readl(gtt_base); | |
489 | } | |
490 | ||
491 | ||
492 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
493 | struct sg_table *st, | |
494 | unsigned int pg_start, | |
495 | enum i915_cache_level cache_level) | |
496 | { | |
497 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
498 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
499 | ||
500 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
501 | ||
502 | } | |
503 | ||
504 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
505 | unsigned int first_entry, | |
506 | unsigned int num_entries) | |
507 | { | |
508 | intel_gtt_clear_range(first_entry, num_entries); | |
509 | } | |
510 | ||
511 | ||
74163907 DV |
512 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
513 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
514 | { |
515 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
516 | struct drm_i915_private *dev_priv = dev->dev_private; |
517 | ||
518 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
519 | obj->gtt_space->start >> PAGE_SHIFT, | |
520 | cache_level); | |
d5bd1449 | 521 | |
74898d7e | 522 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
523 | } |
524 | ||
05394f39 | 525 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 526 | { |
7faf1ab2 DV |
527 | struct drm_device *dev = obj->base.dev; |
528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
529 | ||
530 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
531 | obj->gtt_space->start >> PAGE_SHIFT, | |
532 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
533 | |
534 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
535 | } |
536 | ||
537 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 538 | { |
5c042287 BW |
539 | struct drm_device *dev = obj->base.dev; |
540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541 | bool interruptible; | |
542 | ||
543 | interruptible = do_idling(dev_priv); | |
544 | ||
9da3da66 CW |
545 | if (!obj->has_dma_mapping) |
546 | dma_unmap_sg(&dev->pdev->dev, | |
547 | obj->pages->sgl, obj->pages->nents, | |
548 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
549 | |
550 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 551 | } |
644ec02b | 552 | |
42d6ab48 CW |
553 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
554 | unsigned long color, | |
555 | unsigned long *start, | |
556 | unsigned long *end) | |
557 | { | |
558 | if (node->color != color) | |
559 | *start += 4096; | |
560 | ||
561 | if (!list_empty(&node->node_list)) { | |
562 | node = list_entry(node->node_list.next, | |
563 | struct drm_mm_node, | |
564 | node_list); | |
565 | if (node->allocated && node->color != color) | |
566 | *end -= 4096; | |
567 | } | |
568 | } | |
569 | ||
d7e5008f BW |
570 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
571 | unsigned long start, | |
572 | unsigned long mappable_end, | |
573 | unsigned long end) | |
644ec02b DV |
574 | { |
575 | drm_i915_private_t *dev_priv = dev->dev_private; | |
ed2f3452 CW |
576 | struct drm_mm_node *entry; |
577 | struct drm_i915_gem_object *obj; | |
578 | unsigned long hole_start, hole_end; | |
644ec02b | 579 | |
35451cb6 BW |
580 | BUG_ON(mappable_end > end); |
581 | ||
ed2f3452 | 582 | /* Subtract the guard page ... */ |
d1dd20a9 | 583 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
584 | if (!HAS_LLC(dev)) |
585 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 586 | |
ed2f3452 CW |
587 | /* Mark any preallocated objects as occupied */ |
588 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
589 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", | |
590 | obj->gtt_offset, obj->base.size); | |
591 | ||
592 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
593 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
594 | obj->gtt_offset, | |
595 | obj->base.size, | |
596 | false); | |
597 | obj->has_global_gtt_mapping = 1; | |
598 | } | |
599 | ||
5d4545ae | 600 | dev_priv->gtt.start = start; |
5d4545ae | 601 | dev_priv->gtt.total = end - start; |
644ec02b | 602 | |
ed2f3452 CW |
603 | /* Clear any non-preallocated blocks */ |
604 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
605 | hole_start, hole_end) { | |
606 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
607 | hole_start, hole_end); | |
7faf1ab2 DV |
608 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
609 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
610 | } |
611 | ||
612 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 613 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
614 | } |
615 | ||
d7e5008f BW |
616 | static bool |
617 | intel_enable_ppgtt(struct drm_device *dev) | |
618 | { | |
619 | if (i915_enable_ppgtt >= 0) | |
620 | return i915_enable_ppgtt; | |
621 | ||
622 | #ifdef CONFIG_INTEL_IOMMU | |
623 | /* Disable ppgtt on SNB if VT-d is on. */ | |
624 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
625 | return false; | |
626 | #endif | |
627 | ||
628 | return true; | |
629 | } | |
630 | ||
631 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
632 | { | |
633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
634 | unsigned long gtt_size, mappable_size; | |
635 | int ret; | |
636 | ||
637 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
93d18799 | 638 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
639 | |
640 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
641 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
642 | * aperture accordingly when using aliasing ppgtt. */ | |
643 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
644 | ||
645 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
646 | ||
647 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
648 | if (ret) { | |
649 | mutex_unlock(&dev->struct_mutex); | |
650 | return; | |
651 | } | |
652 | } else { | |
653 | /* Let GEM Manage all of the aperture. | |
654 | * | |
655 | * However, leave one page at the end still bound to the scratch | |
656 | * page. There are a number of places where the hardware | |
657 | * apparently prefetches past the end of the object, and we've | |
658 | * seen multiple hangs with the GPU head pointer stuck in a | |
659 | * batchbuffer bound at the last page of the aperture. One page | |
660 | * should be enough to keep any prefetching inside of the | |
661 | * aperture. | |
662 | */ | |
663 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
664 | } | |
e76e9aeb BW |
665 | } |
666 | ||
667 | static int setup_scratch_page(struct drm_device *dev) | |
668 | { | |
669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
670 | struct page *page; | |
671 | dma_addr_t dma_addr; | |
672 | ||
673 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
674 | if (page == NULL) | |
675 | return -ENOMEM; | |
676 | get_page(page); | |
677 | set_pages_uc(page, 1); | |
678 | ||
679 | #ifdef CONFIG_INTEL_IOMMU | |
680 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
681 | PCI_DMA_BIDIRECTIONAL); | |
682 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
683 | return -EINVAL; | |
684 | #else | |
685 | dma_addr = page_to_phys(page); | |
686 | #endif | |
9c61a32d BW |
687 | dev_priv->gtt.scratch_page = page; |
688 | dev_priv->gtt.scratch_page_dma = dma_addr; | |
e76e9aeb BW |
689 | |
690 | return 0; | |
691 | } | |
692 | ||
693 | static void teardown_scratch_page(struct drm_device *dev) | |
694 | { | |
695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9c61a32d BW |
696 | set_pages_wb(dev_priv->gtt.scratch_page, 1); |
697 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, | |
e76e9aeb | 698 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
9c61a32d BW |
699 | put_page(dev_priv->gtt.scratch_page); |
700 | __free_page(dev_priv->gtt.scratch_page); | |
e76e9aeb BW |
701 | } |
702 | ||
703 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
704 | { | |
705 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
706 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
707 | return snb_gmch_ctl << 20; | |
708 | } | |
709 | ||
710 | static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl) | |
711 | { | |
712 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
713 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
714 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
715 | } | |
716 | ||
03752f5b BW |
717 | static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl) |
718 | { | |
719 | static const int stolen_decoder[] = { | |
720 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352}; | |
721 | snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT; | |
722 | snb_gmch_ctl &= IVB_GMCH_GMS_MASK; | |
723 | return stolen_decoder[snb_gmch_ctl] << 20; | |
724 | } | |
725 | ||
e76e9aeb BW |
726 | int i915_gem_gtt_init(struct drm_device *dev) |
727 | { | |
728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
729 | phys_addr_t gtt_bus_addr; | |
730 | u16 snb_gmch_ctl; | |
e76e9aeb BW |
731 | int ret; |
732 | ||
dabb7a91 | 733 | dev_priv->gtt.mappable_base = pci_resource_start(dev->pdev, 2); |
93d18799 | 734 | dev_priv->gtt.mappable_end = pci_resource_len(dev->pdev, 2); |
dabb7a91 | 735 | |
e76e9aeb BW |
736 | /* On modern platforms we need not worry ourself with the legacy |
737 | * hostbridge query stuff. Skip it entirely | |
738 | */ | |
739 | if (INTEL_INFO(dev)->gen < 6) { | |
740 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL); | |
741 | if (!ret) { | |
742 | DRM_ERROR("failed to set up gmch\n"); | |
743 | return -EIO; | |
744 | } | |
745 | ||
746 | dev_priv->mm.gtt = intel_gtt_get(); | |
747 | if (!dev_priv->mm.gtt) { | |
748 | DRM_ERROR("Failed to initialize GTT\n"); | |
749 | intel_gmch_remove(); | |
750 | return -ENODEV; | |
751 | } | |
a81cc00c BW |
752 | |
753 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev); | |
754 | ||
7faf1ab2 DV |
755 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; |
756 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
757 | ||
e76e9aeb BW |
758 | return 0; |
759 | } | |
760 | ||
e76e9aeb BW |
761 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
762 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
763 | ||
8d2e6308 BW |
764 | dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL); |
765 | if (!dev_priv->mm.gtt) | |
766 | return -ENOMEM; | |
20652097 | 767 | |
e76e9aeb | 768 | /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */ |
b5c62158 | 769 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20); |
e76e9aeb BW |
770 | |
771 | /* i9xx_setup */ | |
772 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
773 | dev_priv->mm.gtt->gtt_total_entries = | |
774 | gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t); | |
03752f5b BW |
775 | if (INTEL_INFO(dev)->gen < 7) |
776 | dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); | |
777 | else | |
778 | dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl); | |
e76e9aeb | 779 | |
e76e9aeb BW |
780 | /* 64/512MB is the current min/max we actually know of, but this is just a |
781 | * coarse sanity check. | |
782 | */ | |
93d18799 BW |
783 | if ((dev_priv->gtt.mappable_end < (64<<20) || |
784 | (dev_priv->gtt.mappable_end > (512<<20)))) { | |
785 | DRM_ERROR("Unknown GMADR size (%lx)\n", | |
786 | dev_priv->gtt.mappable_end); | |
e76e9aeb BW |
787 | ret = -ENXIO; |
788 | goto err_out; | |
789 | } | |
790 | ||
791 | ret = setup_scratch_page(dev); | |
792 | if (ret) { | |
793 | DRM_ERROR("Scratch setup failed\n"); | |
794 | goto err_out; | |
795 | } | |
796 | ||
5d4545ae BW |
797 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, |
798 | dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t)); | |
799 | if (!dev_priv->gtt.gsm) { | |
e76e9aeb BW |
800 | DRM_ERROR("Failed to map the gtt page table\n"); |
801 | teardown_scratch_page(dev); | |
802 | ret = -ENOMEM; | |
803 | goto err_out; | |
804 | } | |
805 | ||
806 | /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */ | |
d640c4b0 | 807 | DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8); |
93d18799 | 808 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", dev_priv->gtt.mappable_end >> 20); |
e76e9aeb BW |
809 | DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20); |
810 | ||
7faf1ab2 DV |
811 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
812 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
813 | ||
e76e9aeb BW |
814 | return 0; |
815 | ||
816 | err_out: | |
817 | kfree(dev_priv->mm.gtt); | |
818 | if (INTEL_INFO(dev)->gen < 6) | |
819 | intel_gmch_remove(); | |
820 | return ret; | |
821 | } | |
822 | ||
823 | void i915_gem_gtt_fini(struct drm_device *dev) | |
824 | { | |
825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 826 | iounmap(dev_priv->gtt.gsm); |
e76e9aeb BW |
827 | teardown_scratch_page(dev); |
828 | if (INTEL_INFO(dev)->gen < 6) | |
829 | intel_gmch_remove(); | |
830 | kfree(dev_priv->mm.gtt); | |
644ec02b | 831 | } |