[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c

/*
 * Copyright © 2010 Daniel Vetter
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"

/* PPGTT support for Sandybdrige/Gen6 and later */
static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
				   unsigned first_entry,
				   unsigned num_entries)
{
	uint32_t *pt_vaddr;
	uint32_t scratch_pte;
	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	unsigned last_pte, i;

	scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr);
	scratch_pte |= GEN6_PTE_VALID | GEN6_PTE_CACHE_LLC;

	while (num_entries) {
		last_pte = first_pte + num_entries;
		if (last_pte > I915_PPGTT_PT_ENTRIES)
			last_pte = I915_PPGTT_PT_ENTRIES;

		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);

		for (i = first_pte; i < last_pte; i++)
			pt_vaddr[i] = scratch_pte;

		kunmap_atomic(pt_vaddr);

		num_entries -= last_pte - first_pte;
		first_pte = 0;
		act_pd++;
	}
}

int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_hw_ppgtt *ppgtt;
	uint32_t pd_entry;
	unsigned first_pd_entry_in_global_pt;
	uint32_t __iomem *pd_addr;
	int i;
	int ret = -ENOMEM;

	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
	 * entries. For aliasing ppgtt support we just steal them at the end for
	 * now. */
	first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;

	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
	if (!ppgtt)
		return ret;

	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
	ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
				  GFP_KERNEL);
	if (!ppgtt->pt_pages)
		goto err_ppgtt;

	for (i = 0; i < ppgtt->num_pd_entries; i++) {
		ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
		if (!ppgtt->pt_pages[i])
			goto err_pt_alloc;
	}

	if (dev_priv->mm.gtt->needs_dmar) {
		ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
						*ppgtt->num_pd_entries,
					     GFP_KERNEL);
		if (!ppgtt->pt_dma_addr)
			goto err_pt_alloc;
	}

	pd_addr = dev_priv->mm.gtt->gtt + first_pd_entry_in_global_pt;
	for (i = 0; i < ppgtt->num_pd_entries; i++) {
		dma_addr_t pt_addr;
		if (dev_priv->mm.gtt->needs_dmar) {
			pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
					       0, 4096,
					       PCI_DMA_BIDIRECTIONAL);

			if (pci_dma_mapping_error(dev->pdev,
						  pt_addr)) {
				ret = -EIO;
				goto err_pd_pin;

			}
			ppgtt->pt_dma_addr[i] = pt_addr;
		} else
			pt_addr = page_to_phys(ppgtt->pt_pages[i]);

		pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
		pd_entry |= GEN6_PDE_VALID;

		writel(pd_entry, pd_addr + i);
	}
	readl(pd_addr);

	ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;

	i915_ppgtt_clear_range(ppgtt, 0,
			       ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);

	ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(uint32_t);

	dev_priv->mm.aliasing_ppgtt = ppgtt;

	return 0;

err_pd_pin:
	if (ppgtt->pt_dma_addr) {
		for (i--; i >= 0; i--)
			pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
				       4096, PCI_DMA_BIDIRECTIONAL);
	}
err_pt_alloc:
	kfree(ppgtt->pt_dma_addr);
	for (i = 0; i < ppgtt->num_pd_entries; i++) {
		if (ppgtt->pt_pages[i])
			__free_page(ppgtt->pt_pages[i]);
	}
	kfree(ppgtt->pt_pages);
err_ppgtt:
	kfree(ppgtt);

	return ret;
}

void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
	int i;

	if (!ppgtt)
		return;

	if (ppgtt->pt_dma_addr) {
		for (i = 0; i < ppgtt->num_pd_entries; i++)
			pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
				       4096, PCI_DMA_BIDIRECTIONAL);
	}

	kfree(ppgtt->pt_dma_addr);
	for (i = 0; i < ppgtt->num_pd_entries; i++)
		__free_page(ppgtt->pt_pages[i]);
	kfree(ppgtt->pt_pages);
	kfree(ppgtt);
}

static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
					 struct scatterlist *sg_list,
					 unsigned sg_len,
					 unsigned first_entry,
					 uint32_t pte_flags)
{
	uint32_t *pt_vaddr, pte;
	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	unsigned i, j, m, segment_len;
	dma_addr_t page_addr;
	struct scatterlist *sg;

	/* init sg walking */
	sg = sg_list;
	i = 0;
	segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
	m = 0;

	while (i < sg_len) {
		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);

		for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
			page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
			pte = GEN6_PTE_ADDR_ENCODE(page_addr);
			pt_vaddr[j] = pte | pte_flags;

			/* grab the next page */
			m++;
			if (m == segment_len) {
				sg = sg_next(sg);
				i++;
				if (i == sg_len)
					break;

				segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
				m = 0;
			}
		}

		kunmap_atomic(pt_vaddr);

		first_pte = 0;
		act_pd++;
	}
}

static void i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt,
				    unsigned first_entry, unsigned num_entries,
				    struct page **pages, uint32_t pte_flags)
{
	uint32_t *pt_vaddr, pte;
	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	unsigned last_pte, i;
	dma_addr_t page_addr;

	while (num_entries) {
		last_pte = first_pte + num_entries;
		last_pte = min_t(unsigned, last_pte, I915_PPGTT_PT_ENTRIES);

		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);

		for (i = first_pte; i < last_pte; i++) {
			page_addr = page_to_phys(*pages);
			pte = GEN6_PTE_ADDR_ENCODE(page_addr);
			pt_vaddr[i] = pte | pte_flags;

			pages++;
		}

		kunmap_atomic(pt_vaddr);

		num_entries -= last_pte - first_pte;
		first_pte = 0;
		act_pd++;
	}
}

void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
			    struct drm_i915_gem_object *obj,
			    enum i915_cache_level cache_level)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t pte_flags = GEN6_PTE_VALID;

	switch (cache_level) {
	case I915_CACHE_LLC_MLC:
		pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
		break;
	case I915_CACHE_LLC:
		pte_flags |= GEN6_PTE_CACHE_LLC;
		break;
	case I915_CACHE_NONE:
		pte_flags |= GEN6_PTE_UNCACHED;
		break;
	default:
		BUG();
	}

	if (dev_priv->mm.gtt->needs_dmar) {
		BUG_ON(!obj->sg_list);

		i915_ppgtt_insert_sg_entries(ppgtt,
					     obj->sg_list,
					     obj->num_sg,
					     obj->gtt_space->start >> PAGE_SHIFT,
					     pte_flags);
	} else
		i915_ppgtt_insert_pages(ppgtt,
					obj->gtt_space->start >> PAGE_SHIFT,
					obj->base.size >> PAGE_SHIFT,
					obj->pages,
					pte_flags);
}

void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
			      struct drm_i915_gem_object *obj)
{
	i915_ppgtt_clear_range(ppgtt,
			       obj->gtt_space->start >> PAGE_SHIFT,
			       obj->base.size >> PAGE_SHIFT);
}

/* XXX kill agp_type! */
static unsigned int cache_level_to_agp_type(struct drm_device *dev,
					    enum i915_cache_level cache_level)
{
	switch (cache_level) {
	case I915_CACHE_LLC_MLC:
		if (INTEL_INFO(dev)->gen >= 6)
			return AGP_USER_CACHED_MEMORY_LLC_MLC;
		/* Older chipsets do not have this extra level of CPU
		 * cacheing, so fallthrough and request the PTE simply
		 * as cached.
		 */
	case I915_CACHE_LLC:
		return AGP_USER_CACHED_MEMORY;
	default:
	case I915_CACHE_NONE:
		return AGP_USER_MEMORY;
	}
}

static bool do_idling(struct drm_i915_private *dev_priv)
{
	bool ret = dev_priv->mm.interruptible;

	if (unlikely(dev_priv->mm.gtt->do_idle_maps)) {
		dev_priv->mm.interruptible = false;
		if (i915_gpu_idle(dev_priv->dev, false)) {
			DRM_ERROR("Couldn't idle GPU\n");
			/* Wait a bit, in hopes it avoids the hang */
			udelay(10);
		}
	}

	return ret;
}

static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
{
	if (unlikely(dev_priv->mm.gtt->do_idle_maps))
		dev_priv->mm.interruptible = interruptible;
}

void i915_gem_restore_gtt_mappings(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;

	/* First fill our portion of the GTT with scratch pages */
	intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
			      (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);

	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
		i915_gem_clflush_object(obj);
		i915_gem_gtt_bind_object(obj, obj->cache_level);
	}

	intel_gtt_chipset_flush();
}

int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->mm.gtt->needs_dmar)
		return intel_gtt_map_memory(obj->pages,
					    obj->base.size >> PAGE_SHIFT,
					    &obj->sg_list,
					    &obj->num_sg);
	else
		return 0;
}

void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
			      enum i915_cache_level cache_level)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);

	if (dev_priv->mm.gtt->needs_dmar) {
		BUG_ON(!obj->sg_list);

		intel_gtt_insert_sg_entries(obj->sg_list,
					    obj->num_sg,
					    obj->gtt_space->start >> PAGE_SHIFT,
					    agp_type);
	} else
		intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
				       obj->base.size >> PAGE_SHIFT,
				       obj->pages,
				       agp_type);

	obj->has_global_gtt_mapping = 1;
}

void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
{
	intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
			      obj->base.size >> PAGE_SHIFT);

	obj->has_global_gtt_mapping = 0;
}

void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool interruptible;

	interruptible = do_idling(dev_priv);

	if (obj->sg_list) {
		intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
		obj->sg_list = NULL;
	}

	undo_idling(dev_priv, interruptible);
}

void i915_gem_init_global_gtt(struct drm_device *dev,
			      unsigned long start,
			      unsigned long mappable_end,
			      unsigned long end)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

	drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);

	dev_priv->mm.gtt_start = start;
	dev_priv->mm.gtt_mappable_end = mappable_end;
	dev_priv->mm.gtt_end = end;
	dev_priv->mm.gtt_total = end - start;
	dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;

	/* Take over this portion of the GTT */
	intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
}
Commit	Line	Data
76aaf220 DV	1	/*
	2	* Copyright © 2010 Daniel Vetter
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#include "drmP.h"
	26	#include "drm.h"
	27	#include "i915_drm.h"
	28	#include "i915_drv.h"
	29	#include "i915_trace.h"
	30	#include "intel_drv.h"
	31
1d2a314c DV	32	/* PPGTT support for Sandybdrige/Gen6 and later */
	33	static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
	34	unsigned first_entry,
	35	unsigned num_entries)
	36	{
1d2a314c DV	37	uint32_t *pt_vaddr;
1d2a314c DV	38	uint32_t scratch_pte;
7bddb01f DV	39	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
	40	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	41	unsigned last_pte, i;
1d2a314c DV	42
	43	scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr);
	44	scratch_pte \|= GEN6_PTE_VALID \| GEN6_PTE_CACHE_LLC;
	45
7bddb01f DV	46	while (num_entries) {
	47	last_pte = first_pte + num_entries;
	48	if (last_pte > I915_PPGTT_PT_ENTRIES)
	49	last_pte = I915_PPGTT_PT_ENTRIES;
	50
	51	pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
1d2a314c	52
7bddb01f DV	53	for (i = first_pte; i < last_pte; i++)
7bddb01f DV	54	pt_vaddr[i] = scratch_pte;
1d2a314c DV	55
1d2a314c DV	56	kunmap_atomic(pt_vaddr);
1d2a314c	57
7bddb01f DV	58	num_entries -= last_pte - first_pte;
	59	first_pte = 0;
	60	act_pd++;
	61	}
1d2a314c DV	62	}
	63
	64	int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
	65	{
	66	struct drm_i915_private *dev_priv = dev->dev_private;
	67	struct i915_hw_ppgtt *ppgtt;
	68	uint32_t pd_entry;
	69	unsigned first_pd_entry_in_global_pt;
	70	uint32_t __iomem *pd_addr;
	71	int i;
	72	int ret = -ENOMEM;
	73
	74	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
	75	* entries. For aliasing ppgtt support we just steal them at the end for
	76	* now. */
	77	first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;
	78
	79	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
	80	if (!ppgtt)
	81	return ret;
	82
	83	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
	84	ppgtt->pt_pages = kzalloc(sizeof(struct page )ppgtt->num_pd_entries,
	85	GFP_KERNEL);
	86	if (!ppgtt->pt_pages)
	87	goto err_ppgtt;
	88
	89	for (i = 0; i < ppgtt->num_pd_entries; i++) {
	90	ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
	91	if (!ppgtt->pt_pages[i])
	92	goto err_pt_alloc;
	93	}
	94
	95	if (dev_priv->mm.gtt->needs_dmar) {
	96	ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
	97	*ppgtt->num_pd_entries,
	98	GFP_KERNEL);
	99	if (!ppgtt->pt_dma_addr)
	100	goto err_pt_alloc;
	101	}
	102
	103	pd_addr = dev_priv->mm.gtt->gtt + first_pd_entry_in_global_pt;
	104	for (i = 0; i < ppgtt->num_pd_entries; i++) {
	105	dma_addr_t pt_addr;
	106	if (dev_priv->mm.gtt->needs_dmar) {
	107	pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
	108	0, 4096,
	109	PCI_DMA_BIDIRECTIONAL);
	110
	111	if (pci_dma_mapping_error(dev->pdev,
	112	pt_addr)) {
	113	ret = -EIO;
	114	goto err_pd_pin;
	115
	116	}
	117	ppgtt->pt_dma_addr[i] = pt_addr;
	118	} else
	119	pt_addr = page_to_phys(ppgtt->pt_pages[i]);
	120
	121	pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
	122	pd_entry \|= GEN6_PDE_VALID;
	123
	124	writel(pd_entry, pd_addr + i);
	125	}
126	readl(pd_addr);
127
128	ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
129
130	i915_ppgtt_clear_range(ppgtt, 0,
131	ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
132
133	ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(uint32_t);
134
135	dev_priv->mm.aliasing_ppgtt = ppgtt;
136
137	return 0;
138
139	err_pd_pin:
140	if (ppgtt->pt_dma_addr) {
141	for (i--; i >= 0; i--)
142	pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
143	4096, PCI_DMA_BIDIRECTIONAL);
144	}
145	err_pt_alloc:
146	kfree(ppgtt->pt_dma_addr);
147	for (i = 0; i < ppgtt->num_pd_entries; i++) {
148	if (ppgtt->pt_pages[i])
149	__free_page(ppgtt->pt_pages[i]);
150	}
151	kfree(ppgtt->pt_pages);
152	err_ppgtt:
153	kfree(ppgtt);
154
155	return ret;
156	}
157
158	void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
159	{
160	struct drm_i915_private *dev_priv = dev->dev_private;
161	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
162	int i;
163
164	if (!ppgtt)
165	return;
166
167	if (ppgtt->pt_dma_addr) {
168	for (i = 0; i < ppgtt->num_pd_entries; i++)
169	pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
170	4096, PCI_DMA_BIDIRECTIONAL);
171	}
172
173	kfree(ppgtt->pt_dma_addr);
174	for (i = 0; i < ppgtt->num_pd_entries; i++)
175	__free_page(ppgtt->pt_pages[i]);
176	kfree(ppgtt->pt_pages);
177	kfree(ppgtt);
178	}
179
7bddb01f DV	180	static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
	181	struct scatterlist *sg_list,
	182	unsigned sg_len,
	183	unsigned first_entry,
	184	uint32_t pte_flags)
	185	{
	186	uint32_t *pt_vaddr, pte;
	187	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
	188	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	189	unsigned i, j, m, segment_len;
	190	dma_addr_t page_addr;
	191	struct scatterlist *sg;
	192
	193	/* init sg walking */
	194	sg = sg_list;
	195	i = 0;
	196	segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
	197	m = 0;
	198
	199	while (i < sg_len) {
	200	pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
	201
	202	for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
	203	page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
	204	pte = GEN6_PTE_ADDR_ENCODE(page_addr);
	205	pt_vaddr[j] = pte \| pte_flags;
	206
	207	/* grab the next page */
	208	m++;
	209	if (m == segment_len) {
	210	sg = sg_next(sg);
	211	i++;
	212	if (i == sg_len)
	213	break;
	214
	215	segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
	216	m = 0;
	217	}
	218	}
	219
	220	kunmap_atomic(pt_vaddr);
	221
	222	first_pte = 0;
	223	act_pd++;
	224	}
	225	}
	226
	227	static void i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt,
	228	unsigned first_entry, unsigned num_entries,
	229	struct page **pages, uint32_t pte_flags)
	230	{
	231	uint32_t *pt_vaddr, pte;
	232	unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
	233	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
	234	unsigned last_pte, i;
	235	dma_addr_t page_addr;
	236
	237	while (num_entries) {
	238	last_pte = first_pte + num_entries;
	239	last_pte = min_t(unsigned, last_pte, I915_PPGTT_PT_ENTRIES);
	240
	241	pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
	242
	243	for (i = first_pte; i < last_pte; i++) {
244	page_addr = page_to_phys(*pages);
245	pte = GEN6_PTE_ADDR_ENCODE(page_addr);
246	pt_vaddr[i] = pte \| pte_flags;
247
248	pages++;
249	}
250
251	kunmap_atomic(pt_vaddr);
252
253	num_entries -= last_pte - first_pte;
254	first_pte = 0;
255	act_pd++;
256	}
257	}
258
259	void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
260	struct drm_i915_gem_object *obj,
261	enum i915_cache_level cache_level)
262	{
263	struct drm_device *dev = obj->base.dev;
264	struct drm_i915_private *dev_priv = dev->dev_private;
265	uint32_t pte_flags = GEN6_PTE_VALID;
266
267	switch (cache_level) {
268	case I915_CACHE_LLC_MLC:
269	pte_flags \|= GEN6_PTE_CACHE_LLC_MLC;
270	break;
271	case I915_CACHE_LLC:
272	pte_flags \|= GEN6_PTE_CACHE_LLC;
273	break;
274	case I915_CACHE_NONE:
275	pte_flags \|= GEN6_PTE_UNCACHED;
276	break;
277	default:
278	BUG();
279	}
280
281	if (dev_priv->mm.gtt->needs_dmar) {
282	BUG_ON(!obj->sg_list);
283
284	i915_ppgtt_insert_sg_entries(ppgtt,
285	obj->sg_list,
286	obj->num_sg,
287	obj->gtt_space->start >> PAGE_SHIFT,
288	pte_flags);
289	} else
290	i915_ppgtt_insert_pages(ppgtt,
291	obj->gtt_space->start >> PAGE_SHIFT,
292	obj->base.size >> PAGE_SHIFT,
293	obj->pages,
294	pte_flags);
295	}
296
297	void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
298	struct drm_i915_gem_object *obj)
299	{
300	i915_ppgtt_clear_range(ppgtt,
301	obj->gtt_space->start >> PAGE_SHIFT,
302	obj->base.size >> PAGE_SHIFT);
303	}
304
93dfb40c CW	305	/* XXX kill agp_type! */
	306	static unsigned int cache_level_to_agp_type(struct drm_device *dev,
	307	enum i915_cache_level cache_level)
	308	{
	309	switch (cache_level) {
	310	case I915_CACHE_LLC_MLC:
	311	if (INTEL_INFO(dev)->gen >= 6)
	312	return AGP_USER_CACHED_MEMORY_LLC_MLC;
	313	/* Older chipsets do not have this extra level of CPU
	314	* cacheing, so fallthrough and request the PTE simply
	315	* as cached.
	316	*/
	317	case I915_CACHE_LLC:
	318	return AGP_USER_CACHED_MEMORY;
	319	default:
	320	case I915_CACHE_NONE:
	321	return AGP_USER_MEMORY;
	322	}
	323	}
	324
5c042287 BW	325	static bool do_idling(struct drm_i915_private *dev_priv)
	326	{
	327	bool ret = dev_priv->mm.interruptible;
	328
	329	if (unlikely(dev_priv->mm.gtt->do_idle_maps)) {
	330	dev_priv->mm.interruptible = false;
8436473a	331	if (i915_gpu_idle(dev_priv->dev, false)) {
5c042287 BW	332	DRM_ERROR("Couldn't idle GPU\n");
	333	/* Wait a bit, in hopes it avoids the hang */
	334	udelay(10);
	335	}
	336	}
	337
	338	return ret;
	339	}
	340
	341	static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
	342	{
	343	if (unlikely(dev_priv->mm.gtt->do_idle_maps))
	344	dev_priv->mm.interruptible = interruptible;
	345	}
	346
76aaf220 DV	347	void i915_gem_restore_gtt_mappings(struct drm_device *dev)
	348	{
	349	struct drm_i915_private *dev_priv = dev->dev_private;
05394f39	350	struct drm_i915_gem_object *obj;
76aaf220	351
bee4a186 CW	352	/* First fill our portion of the GTT with scratch pages */
	353	intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
	354	(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
	355
05394f39	356	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
a8e93126	357	i915_gem_clflush_object(obj);
74163907	358	i915_gem_gtt_bind_object(obj, obj->cache_level);
76aaf220 DV	359	}
76aaf220 DV	360
76aaf220 DV	361	intel_gtt_chipset_flush();
76aaf220 DV	362	}
7c2e6fdf	363
74163907	364	int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf	365	{
05394f39	366	struct drm_device *dev = obj->base.dev;
185cbcb3	367	struct drm_i915_private *dev_priv = dev->dev_private;
7c2e6fdf	368
74163907 DV	369	if (dev_priv->mm.gtt->needs_dmar)
	370	return intel_gtt_map_memory(obj->pages,
	371	obj->base.size >> PAGE_SHIFT,
	372	&obj->sg_list,
	373	&obj->num_sg);
	374	else
	375	return 0;
7c2e6fdf DV	376	}
7c2e6fdf DV	377
74163907 DV	378	void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
74163907 DV	379	enum i915_cache_level cache_level)
d5bd1449 CW	380	{
	381	struct drm_device *dev = obj->base.dev;
	382	struct drm_i915_private *dev_priv = dev->dev_private;
	383	unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
	384
	385	if (dev_priv->mm.gtt->needs_dmar) {
	386	BUG_ON(!obj->sg_list);
	387
	388	intel_gtt_insert_sg_entries(obj->sg_list,
	389	obj->num_sg,
	390	obj->gtt_space->start >> PAGE_SHIFT,
	391	agp_type);
	392	} else
	393	intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
	394	obj->base.size >> PAGE_SHIFT,
	395	obj->pages,
	396	agp_type);
74898d7e DV	397
74898d7e DV	398	obj->has_global_gtt_mapping = 1;
d5bd1449 CW	399	}
d5bd1449 CW	400
05394f39	401	void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
74163907 DV	402	{
	403	intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
	404	obj->base.size >> PAGE_SHIFT);
74898d7e DV	405
74898d7e DV	406	obj->has_global_gtt_mapping = 0;
74163907 DV	407	}
	408
	409	void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf	410	{
5c042287 BW	411	struct drm_device *dev = obj->base.dev;
	412	struct drm_i915_private *dev_priv = dev->dev_private;
	413	bool interruptible;
	414
	415	interruptible = do_idling(dev_priv);
	416
d9126400	417	if (obj->sg_list) {
05394f39 CW	418	intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
05394f39 CW	419	obj->sg_list = NULL;
185cbcb3	420	}
5c042287 BW	421
5c042287 BW	422	undo_idling(dev_priv, interruptible);
7c2e6fdf	423	}
644ec02b DV	424
	425	void i915_gem_init_global_gtt(struct drm_device *dev,
	426	unsigned long start,
	427	unsigned long mappable_end,
	428	unsigned long end)
	429	{
	430	drm_i915_private_t *dev_priv = dev->dev_private;
	431
	432	drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
	433
	434	dev_priv->mm.gtt_start = start;
	435	dev_priv->mm.gtt_mappable_end = mappable_end;
	436	dev_priv->mm.gtt_end = end;
	437	dev_priv->mm.gtt_total = end - start;
	438	dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
	439
	440	/* Take over this portion of the GTT */
	441	intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
	442	}