[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c

/*
 * Copyright © 2010 Daniel Vetter
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"

/* XXX kill agp_type! */
static unsigned int cache_level_to_agp_type(struct drm_device *dev,
					    enum i915_cache_level cache_level)
{
	switch (cache_level) {
	case I915_CACHE_LLC_MLC:
		if (INTEL_INFO(dev)->gen >= 6)
			return AGP_USER_CACHED_MEMORY_LLC_MLC;
		/* Older chipsets do not have this extra level of CPU
		 * cacheing, so fallthrough and request the PTE simply
		 * as cached.
		 */
	case I915_CACHE_LLC:
		return AGP_USER_CACHED_MEMORY;
	default:
	case I915_CACHE_NONE:
		return AGP_USER_MEMORY;
	}
}

void i915_gem_restore_gtt_mappings(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;

	/* First fill our portion of the GTT with scratch pages */
	intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
			      (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);

	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
		i915_gem_clflush_object(obj);
		i915_gem_gtt_rebind_object(obj, obj->cache_level);
	}

	intel_gtt_chipset_flush();
}

int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
	int ret;

	if (dev_priv->mm.gtt->needs_dmar) {
		ret = intel_gtt_map_memory(obj->pages,
					   obj->base.size >> PAGE_SHIFT,
					   &obj->sg_list,
					   &obj->num_sg);
		if (ret != 0)
			return ret;

		intel_gtt_insert_sg_entries(obj->sg_list,
					    obj->num_sg,
					    obj->gtt_space->start >> PAGE_SHIFT,
					    agp_type);
	} else
		intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
				       obj->base.size >> PAGE_SHIFT,
				       obj->pages,
				       agp_type);

	return 0;
}

void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
				enum i915_cache_level cache_level)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);

	if (dev_priv->mm.gtt->needs_dmar) {
		BUG_ON(!obj->sg_list);

		intel_gtt_insert_sg_entries(obj->sg_list,
					    obj->num_sg,
					    obj->gtt_space->start >> PAGE_SHIFT,
					    agp_type);
	} else
		intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
				       obj->base.size >> PAGE_SHIFT,
				       obj->pages,
				       agp_type);
}

void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
{
	intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
			      obj->base.size >> PAGE_SHIFT);

	if (obj->sg_list) {
		intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
		obj->sg_list = NULL;
	}
}
Commit	Line	Data
76aaf220 DV	1	/*
	2	* Copyright © 2010 Daniel Vetter
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#include "drmP.h"
	26	#include "drm.h"
	27	#include "i915_drm.h"
	28	#include "i915_drv.h"
	29	#include "i915_trace.h"
	30	#include "intel_drv.h"
	31
93dfb40c CW	32	/* XXX kill agp_type! */
	33	static unsigned int cache_level_to_agp_type(struct drm_device *dev,
	34	enum i915_cache_level cache_level)
	35	{
	36	switch (cache_level) {
	37	case I915_CACHE_LLC_MLC:
	38	if (INTEL_INFO(dev)->gen >= 6)
	39	return AGP_USER_CACHED_MEMORY_LLC_MLC;
	40	/* Older chipsets do not have this extra level of CPU
	41	* cacheing, so fallthrough and request the PTE simply
	42	* as cached.
	43	*/
	44	case I915_CACHE_LLC:
	45	return AGP_USER_CACHED_MEMORY;
	46	default:
	47	case I915_CACHE_NONE:
	48	return AGP_USER_MEMORY;
	49	}
	50	}
	51
76aaf220 DV	52	void i915_gem_restore_gtt_mappings(struct drm_device *dev)
	53	{
	54	struct drm_i915_private *dev_priv = dev->dev_private;
05394f39	55	struct drm_i915_gem_object *obj;
76aaf220	56
bee4a186 CW	57	/* First fill our portion of the GTT with scratch pages */
	58	intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
	59	(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
	60
05394f39	61	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
a8e93126	62	i915_gem_clflush_object(obj);
d5bd1449	63	i915_gem_gtt_rebind_object(obj, obj->cache_level);
76aaf220 DV	64	}
76aaf220 DV	65
76aaf220 DV	66	intel_gtt_chipset_flush();
76aaf220 DV	67	}
7c2e6fdf	68
05394f39	69	int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
7c2e6fdf	70	{
05394f39	71	struct drm_device *dev = obj->base.dev;
185cbcb3	72	struct drm_i915_private *dev_priv = dev->dev_private;
93dfb40c	73	unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
185cbcb3	74	int ret;
7c2e6fdf	75
185cbcb3	76	if (dev_priv->mm.gtt->needs_dmar) {
05394f39 CW	77	ret = intel_gtt_map_memory(obj->pages,
	78	obj->base.size >> PAGE_SHIFT,
	79	&obj->sg_list,
	80	&obj->num_sg);
185cbcb3 DV	81	if (ret != 0)
	82	return ret;
	83
05394f39 CW	84	intel_gtt_insert_sg_entries(obj->sg_list,
	85	obj->num_sg,
	86	obj->gtt_space->start >> PAGE_SHIFT,
93dfb40c	87	agp_type);
185cbcb3	88	} else
05394f39 CW	89	intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
	90	obj->base.size >> PAGE_SHIFT,
	91	obj->pages,
93dfb40c	92	agp_type);
7c2e6fdf	93
185cbcb3	94	return 0;
7c2e6fdf DV	95	}
7c2e6fdf DV	96
e4ffd173 CW	97	void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
e4ffd173 CW	98	enum i915_cache_level cache_level)
d5bd1449 CW	99	{
	100	struct drm_device *dev = obj->base.dev;
	101	struct drm_i915_private *dev_priv = dev->dev_private;
	102	unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
	103
	104	if (dev_priv->mm.gtt->needs_dmar) {
	105	BUG_ON(!obj->sg_list);
	106
	107	intel_gtt_insert_sg_entries(obj->sg_list,
	108	obj->num_sg,
	109	obj->gtt_space->start >> PAGE_SHIFT,
	110	agp_type);
	111	} else
	112	intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
	113	obj->base.size >> PAGE_SHIFT,
	114	obj->pages,
	115	agp_type);
	116	}
	117
05394f39	118	void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
7c2e6fdf	119	{
d9126400 CW	120	intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
d9126400 CW	121	obj->base.size >> PAGE_SHIFT);
7c2e6fdf	122
d9126400	123	if (obj->sg_list) {
05394f39 CW	124	intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
05394f39 CW	125	obj->sg_list = NULL;
185cbcb3	126	}
7c2e6fdf	127	}