]>
Commit | Line | Data |
---|---|---|
0260c420 BW |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Please try to maintain the following order within this file unless it makes | |
24 | * sense to do otherwise. From top to bottom: | |
25 | * 1. typedefs | |
26 | * 2. #defines, and macros | |
27 | * 3. structure definitions | |
28 | * 4. function prototypes | |
29 | * | |
30 | * Within each section, please try to order by generation in ascending order, | |
31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). | |
32 | */ | |
33 | ||
34 | #ifndef __I915_GEM_GTT_H__ | |
35 | #define __I915_GEM_GTT_H__ | |
36 | ||
8ef8561f | 37 | #include <linux/io-mapping.h> |
b42fe9ca | 38 | #include <linux/mm.h> |
8448661d | 39 | #include <linux/pagevec.h> |
8ef8561f | 40 | |
b42fe9ca | 41 | #include "i915_gem_timeline.h" |
b0decaf7 | 42 | #include "i915_gem_request.h" |
8448661d | 43 | #include "i915_selftest.h" |
b0decaf7 | 44 | |
2a9654b2 MA |
45 | #define I915_GTT_PAGE_SIZE_4K BIT(12) |
46 | #define I915_GTT_PAGE_SIZE_64K BIT(16) | |
47 | #define I915_GTT_PAGE_SIZE_2M BIT(21) | |
48 | ||
49 | #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K | |
50 | #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M | |
51 | ||
f51455d4 CW |
52 | #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE |
53 | ||
49ef5294 CW |
54 | #define I915_FENCE_REG_NONE -1 |
55 | #define I915_MAX_NUM_FENCES 32 | |
56 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
57 | #define I915_MAX_NUM_FENCE_BITS 6 | |
58 | ||
4d884705 | 59 | struct drm_i915_file_private; |
49ef5294 | 60 | struct drm_i915_fence_reg; |
4d884705 | 61 | |
75c7b0b8 CW |
62 | typedef u32 gen6_pte_t; |
63 | typedef u64 gen8_pte_t; | |
64 | typedef u64 gen8_pde_t; | |
65 | typedef u64 gen8_ppgtt_pdpe_t; | |
66 | typedef u64 gen8_ppgtt_pml4e_t; | |
0260c420 | 67 | |
72e96d64 | 68 | #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) |
0260c420 | 69 | |
0260c420 BW |
70 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
71 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
72 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
73 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
74 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
75 | #define GEN6_PTE_UNCACHED (1 << 1) | |
76 | #define GEN6_PTE_VALID (1 << 0) | |
77 | ||
dd19674b | 78 | #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) |
07749ef3 MT |
79 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) |
80 | #define I915_PDES 512 | |
81 | #define I915_PDE_MASK (I915_PDES - 1) | |
678d96fb | 82 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
07749ef3 MT |
83 | |
84 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) | |
85 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) | |
0260c420 | 86 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
678d96fb | 87 | #define GEN6_PDE_SHIFT 22 |
0260c420 BW |
88 | #define GEN6_PDE_VALID (1 << 0) |
89 | ||
90 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) | |
91 | ||
92 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
93 | #define BYT_PTE_WRITEABLE (1 << 1) | |
94 | ||
95 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits | |
96 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
97 | */ | |
98 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
99 | (((bits) & 0x8) << (11 - 3))) | |
100 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | |
101 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
102 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | |
103 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | |
104 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | |
105 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | |
106 | #define HSW_PTE_UNCACHED (0) | |
107 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) | |
108 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) | |
109 | ||
e7167769 | 110 | /* GEN8 32b style address is defined as a 3 level page table: |
0260c420 BW |
111 | * 31:30 | 29:21 | 20:12 | 11:0 |
112 | * PDPE | PDE | PTE | offset | |
113 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
114 | * programmed via register. | |
e7167769 MK |
115 | */ |
116 | #define GEN8_3LVL_PDPES 4 | |
117 | #define GEN8_PDE_SHIFT 21 | |
118 | #define GEN8_PDE_MASK 0x1ff | |
119 | #define GEN8_PTE_SHIFT 12 | |
120 | #define GEN8_PTE_MASK 0x1ff | |
121 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) | |
122 | ||
123 | /* GEN8 48b style address is defined as a 4 level page table: | |
81ba8aef MT |
124 | * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 |
125 | * PML4E | PDPE | PDE | PTE | offset | |
0260c420 | 126 | */ |
81ba8aef MT |
127 | #define GEN8_PML4ES_PER_PML4 512 |
128 | #define GEN8_PML4E_SHIFT 39 | |
762d9936 | 129 | #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) |
0260c420 | 130 | #define GEN8_PDPE_SHIFT 30 |
81ba8aef MT |
131 | /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page |
132 | * tables */ | |
133 | #define GEN8_PDPE_MASK 0x1ff | |
0260c420 | 134 | |
c095b97c ZW |
135 | #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) |
136 | #define PPAT_CACHED_PDE 0 /* WB LLC */ | |
137 | #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ | |
138 | #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ | |
0260c420 | 139 | |
ee0ce478 | 140 | #define CHV_PPAT_SNOOP (1<<6) |
1790625b | 141 | #define GEN8_PPAT_AGE(x) ((x)<<4) |
0260c420 BW |
142 | #define GEN8_PPAT_LLCeLLC (3<<2) |
143 | #define GEN8_PPAT_LLCELLC (2<<2) | |
144 | #define GEN8_PPAT_LLC (1<<2) | |
145 | #define GEN8_PPAT_WB (3<<0) | |
146 | #define GEN8_PPAT_WT (2<<0) | |
147 | #define GEN8_PPAT_WC (1<<0) | |
148 | #define GEN8_PPAT_UC (0<<0) | |
149 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
75c7b0b8 | 150 | #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) |
0260c420 | 151 | |
4395890a ZW |
152 | #define GEN8_PPAT_GET_CA(x) ((x) & 3) |
153 | #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) | |
154 | #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) | |
155 | #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) | |
156 | ||
0a03852e MA |
157 | #define GEN8_PDE_PS_2M BIT(7) |
158 | ||
b42fe9ca JL |
159 | struct sg_table; |
160 | ||
50470bb0 | 161 | struct intel_rotation_info { |
7ff19c56 | 162 | struct intel_rotation_plane_info { |
1663b9d6 | 163 | /* tiles */ |
6687c906 | 164 | unsigned int width, height, stride, offset; |
1663b9d6 | 165 | } plane[2]; |
8d9046ad CW |
166 | } __packed; |
167 | ||
168 | static inline void assert_intel_rotation_info_is_packed(void) | |
169 | { | |
170 | BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); | |
171 | } | |
fe14d5f4 | 172 | |
7ff19c56 CW |
173 | struct intel_partial_info { |
174 | u64 offset; | |
175 | unsigned int size; | |
8d9046ad CW |
176 | } __packed; |
177 | ||
178 | static inline void assert_intel_partial_info_is_packed(void) | |
179 | { | |
180 | BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); | |
181 | } | |
7ff19c56 | 182 | |
992e418d CW |
183 | enum i915_ggtt_view_type { |
184 | I915_GGTT_VIEW_NORMAL = 0, | |
185 | I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), | |
186 | I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), | |
187 | }; | |
188 | ||
189 | static inline void assert_i915_ggtt_view_type_is_unique(void) | |
190 | { | |
191 | /* As we encode the size of each branch inside the union into its type, | |
192 | * we have to be careful that each branch has a unique size. | |
193 | */ | |
194 | switch ((enum i915_ggtt_view_type)0) { | |
195 | case I915_GGTT_VIEW_NORMAL: | |
196 | case I915_GGTT_VIEW_PARTIAL: | |
197 | case I915_GGTT_VIEW_ROTATED: | |
198 | /* gcc complains if these are identical cases */ | |
199 | break; | |
200 | } | |
201 | } | |
202 | ||
fe14d5f4 TU |
203 | struct i915_ggtt_view { |
204 | enum i915_ggtt_view_type type; | |
8bd7ef16 | 205 | union { |
992e418d | 206 | /* Members need to contain no holes/padding */ |
7ff19c56 | 207 | struct intel_partial_info partial; |
7723f47d | 208 | struct intel_rotation_info rotated; |
8bab1193 | 209 | }; |
fe14d5f4 TU |
210 | }; |
211 | ||
0260c420 | 212 | enum i915_cache_level; |
fe14d5f4 | 213 | |
b42fe9ca | 214 | struct i915_vma; |
bde13ebd | 215 | |
44159ddb | 216 | struct i915_page_dma { |
d7b3de91 | 217 | struct page *page; |
44159ddb MK |
218 | union { |
219 | dma_addr_t daddr; | |
220 | ||
221 | /* For gen6/gen7 only. This is the offset in the GGTT | |
222 | * where the page directory entries for PPGTT begin | |
223 | */ | |
75c7b0b8 | 224 | u32 ggtt_offset; |
44159ddb MK |
225 | }; |
226 | }; | |
227 | ||
567047be MK |
228 | #define px_base(px) (&(px)->base) |
229 | #define px_page(px) (px_base(px)->page) | |
230 | #define px_dma(px) (px_base(px)->daddr) | |
231 | ||
44159ddb MK |
232 | struct i915_page_table { |
233 | struct i915_page_dma base; | |
dd19674b | 234 | unsigned int used_ptes; |
d7b3de91 BW |
235 | }; |
236 | ||
ec565b3c | 237 | struct i915_page_directory { |
44159ddb | 238 | struct i915_page_dma base; |
7324cc04 | 239 | |
ec565b3c | 240 | struct i915_page_table *page_table[I915_PDES]; /* PDEs */ |
fe52e37f | 241 | unsigned int used_pdes; |
d7b3de91 BW |
242 | }; |
243 | ||
ec565b3c | 244 | struct i915_page_directory_pointer { |
6ac18502 | 245 | struct i915_page_dma base; |
6ac18502 | 246 | struct i915_page_directory **page_directory; |
e2b763ca | 247 | unsigned int used_pdpes; |
d7b3de91 BW |
248 | }; |
249 | ||
81ba8aef MT |
250 | struct i915_pml4 { |
251 | struct i915_page_dma base; | |
81ba8aef MT |
252 | struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; |
253 | }; | |
254 | ||
0260c420 BW |
255 | struct i915_address_space { |
256 | struct drm_mm mm; | |
80b204bc | 257 | struct i915_gem_timeline timeline; |
49d73912 | 258 | struct drm_i915_private *i915; |
8448661d | 259 | struct device *dma; |
2bfa996e CW |
260 | /* Every address space belongs to a struct file - except for the global |
261 | * GTT that is owned by the driver (and so @file is set to NULL). In | |
262 | * principle, no information should leak from one context to another | |
263 | * (or between files/processes etc) unless explicitly shared by the | |
264 | * owner. Tracking the owner is important in order to free up per-file | |
265 | * objects along with the file, to aide resource tracking, and to | |
266 | * assign blame. | |
267 | */ | |
268 | struct drm_i915_file_private *file; | |
0260c420 | 269 | struct list_head global_link; |
c44ef60e | 270 | u64 total; /* size addr space maps (ex. 2GB for ggtt) */ |
ff8f7975 | 271 | u64 reserved; /* size addr space reserved */ |
0260c420 | 272 | |
50e046b6 CW |
273 | bool closed; |
274 | ||
8bcdd0f7 | 275 | struct i915_page_dma scratch_page; |
79ab9370 MK |
276 | struct i915_page_table *scratch_pt; |
277 | struct i915_page_directory *scratch_pd; | |
69ab76fd | 278 | struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ |
0260c420 BW |
279 | |
280 | /** | |
281 | * List of objects currently involved in rendering. | |
282 | * | |
283 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 284 | * flushed, not necessarily primitives. last_read_req |
0260c420 BW |
285 | * represents when the rendering involved will be completed. |
286 | * | |
287 | * A reference is held on the buffer while on this list. | |
288 | */ | |
289 | struct list_head active_list; | |
290 | ||
291 | /** | |
292 | * LRU list of objects which are not in the ringbuffer and | |
293 | * are ready to unbind, but are still in the GTT. | |
294 | * | |
97b2a6a1 | 295 | * last_read_req is NULL while an object is in this list. |
0260c420 BW |
296 | * |
297 | * A reference is not held on the buffer while on this list, | |
298 | * as merely being GTT-bound shouldn't prevent its being | |
299 | * freed, and we'll pull it off the list in the free path. | |
300 | */ | |
301 | struct list_head inactive_list; | |
302 | ||
50e046b6 CW |
303 | /** |
304 | * List of vma that have been unbound. | |
305 | * | |
306 | * A reference is not held on the buffer while on this list. | |
307 | */ | |
308 | struct list_head unbound_list; | |
309 | ||
8448661d CW |
310 | struct pagevec free_pages; |
311 | bool pt_kmap_wc; | |
312 | ||
0260c420 | 313 | /* FIXME: Need a more generic return type */ |
07749ef3 MT |
314 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
315 | enum i915_cache_level level, | |
4fb84d99 | 316 | u32 flags); /* Create a valid PTE */ |
f329f5f6 DV |
317 | /* flags for pte_encode */ |
318 | #define PTE_READ_ONLY (1<<0) | |
678d96fb | 319 | int (*allocate_va_range)(struct i915_address_space *vm, |
75c7b0b8 | 320 | u64 start, u64 length); |
0260c420 | 321 | void (*clear_range)(struct i915_address_space *vm, |
75c7b0b8 | 322 | u64 start, u64 length); |
d6473f56 CW |
323 | void (*insert_page)(struct i915_address_space *vm, |
324 | dma_addr_t addr, | |
75c7b0b8 | 325 | u64 offset, |
d6473f56 CW |
326 | enum i915_cache_level cache_level, |
327 | u32 flags); | |
0260c420 | 328 | void (*insert_entries)(struct i915_address_space *vm, |
4a234c5f | 329 | struct i915_vma *vma, |
75c7b0b8 CW |
330 | enum i915_cache_level cache_level, |
331 | u32 flags); | |
0260c420 | 332 | void (*cleanup)(struct i915_address_space *vm); |
777dc5bb DV |
333 | /** Unmap an object from an address space. This usually consists of |
334 | * setting the valid PTE entries to a reserved scratch page. */ | |
335 | void (*unbind_vma)(struct i915_vma *vma); | |
336 | /* Map an object into an address space with the given cache flags. */ | |
70b9f6f8 DV |
337 | int (*bind_vma)(struct i915_vma *vma, |
338 | enum i915_cache_level cache_level, | |
339 | u32 flags); | |
fa3f46af MA |
340 | int (*set_pages)(struct i915_vma *vma); |
341 | void (*clear_pages)(struct i915_vma *vma); | |
8448661d CW |
342 | |
343 | I915_SELFTEST_DECLARE(struct fault_attr fault_attr); | |
0260c420 BW |
344 | }; |
345 | ||
2bfa996e | 346 | #define i915_is_ggtt(V) (!(V)->file) |
596c5923 | 347 | |
3e490042 MK |
348 | static inline bool |
349 | i915_vm_is_48bit(const struct i915_address_space *vm) | |
350 | { | |
351 | return (vm->total - 1) >> 32; | |
352 | } | |
353 | ||
0260c420 BW |
354 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
355 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
356 | * collateral associated with any va->pa translations GEN hardware also has a | |
357 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
358 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
359 | * the spec. | |
360 | */ | |
62106b4f | 361 | struct i915_ggtt { |
0260c420 | 362 | struct i915_address_space base; |
f7bbe788 | 363 | struct io_mapping mappable; /* Mapping to our CPU mappable region */ |
0260c420 | 364 | |
edd1f2fe CW |
365 | phys_addr_t mappable_base; /* PA of our GMADR */ |
366 | u64 mappable_end; /* End offset that we can CPU map */ | |
367 | ||
3c6b29b2 PZ |
368 | /* Stolen memory is segmented in hardware with different portions |
369 | * offlimits to certain functions. | |
370 | * | |
371 | * The drm_mm is initialised to the total accessible range, as found | |
372 | * from the PCI config. On Broadwell+, this is further restricted to | |
373 | * avoid the first page! The upper end of stolen memory is reserved for | |
374 | * hardware functions and similarly removed from the accessible range. | |
375 | */ | |
edd1f2fe CW |
376 | u32 stolen_size; /* Total size of stolen memory */ |
377 | u32 stolen_usable_size; /* Total size minus reserved ranges */ | |
378 | u32 stolen_reserved_base; | |
379 | u32 stolen_reserved_size; | |
0260c420 BW |
380 | |
381 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
382 | void __iomem *gsm; | |
7c3f86b6 | 383 | void (*invalidate)(struct drm_i915_private *dev_priv); |
0260c420 BW |
384 | |
385 | bool do_idle_maps; | |
386 | ||
387 | int mtrr; | |
95374d75 CW |
388 | |
389 | struct drm_mm_node error_capture; | |
0260c420 BW |
390 | }; |
391 | ||
392 | struct i915_hw_ppgtt { | |
393 | struct i915_address_space base; | |
394 | struct kref ref; | |
395 | struct drm_mm_node node; | |
563222a7 | 396 | unsigned long pd_dirty_rings; |
d7b3de91 | 397 | union { |
81ba8aef MT |
398 | struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ |
399 | struct i915_page_directory_pointer pdp; /* GEN8+ */ | |
400 | struct i915_page_directory pd; /* GEN6-7 */ | |
d7b3de91 | 401 | }; |
0260c420 | 402 | |
678d96fb BW |
403 | gen6_pte_t __iomem *pd_addr; |
404 | ||
0260c420 | 405 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 406 | struct drm_i915_gem_request *req); |
0260c420 BW |
407 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
408 | }; | |
409 | ||
731f74c5 DG |
410 | /* |
411 | * gen6_for_each_pde() iterates over every pde from start until start+length. | |
412 | * If start and start+length are not perfectly divisible, the macro will round | |
413 | * down and up as needed. Start=0 and length=2G effectively iterates over | |
414 | * every PDE in the system. The macro modifies ALL its parameters except 'pd', | |
415 | * so each of the other parameters should preferably be a simple variable, or | |
416 | * at most an lvalue with no side-effects! | |
678d96fb | 417 | */ |
731f74c5 DG |
418 | #define gen6_for_each_pde(pt, pd, start, length, iter) \ |
419 | for (iter = gen6_pde_index(start); \ | |
420 | length > 0 && iter < I915_PDES && \ | |
421 | (pt = (pd)->page_table[iter], true); \ | |
422 | ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ | |
423 | temp = min(temp - start, length); \ | |
424 | start += temp, length -= temp; }), ++iter) | |
425 | ||
426 | #define gen6_for_all_pdes(pt, pd, iter) \ | |
427 | for (iter = 0; \ | |
428 | iter < I915_PDES && \ | |
429 | (pt = (pd)->page_table[iter], true); \ | |
430 | ++iter) | |
09942c65 | 431 | |
75c7b0b8 | 432 | static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) |
678d96fb | 433 | { |
75c7b0b8 | 434 | const u32 mask = NUM_PTE(pde_shift) - 1; |
678d96fb BW |
435 | |
436 | return (address >> PAGE_SHIFT) & mask; | |
437 | } | |
438 | ||
439 | /* Helper to counts the number of PTEs within the given length. This count | |
440 | * does not cross a page table boundary, so the max value would be | |
441 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. | |
442 | */ | |
75c7b0b8 | 443 | static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) |
678d96fb | 444 | { |
75c7b0b8 CW |
445 | const u64 mask = ~((1ULL << pde_shift) - 1); |
446 | u64 end; | |
678d96fb BW |
447 | |
448 | WARN_ON(length == 0); | |
449 | WARN_ON(offset_in_page(addr|length)); | |
450 | ||
451 | end = addr + length; | |
452 | ||
453 | if ((addr & mask) != (end & mask)) | |
454 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); | |
455 | ||
456 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); | |
457 | } | |
458 | ||
75c7b0b8 | 459 | static inline u32 i915_pde_index(u64 addr, u32 shift) |
678d96fb BW |
460 | { |
461 | return (addr >> shift) & I915_PDE_MASK; | |
462 | } | |
463 | ||
75c7b0b8 | 464 | static inline u32 gen6_pte_index(u32 addr) |
678d96fb BW |
465 | { |
466 | return i915_pte_index(addr, GEN6_PDE_SHIFT); | |
467 | } | |
468 | ||
75c7b0b8 | 469 | static inline u32 gen6_pte_count(u32 addr, u32 length) |
678d96fb BW |
470 | { |
471 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); | |
472 | } | |
473 | ||
75c7b0b8 | 474 | static inline u32 gen6_pde_index(u32 addr) |
678d96fb BW |
475 | { |
476 | return i915_pde_index(addr, GEN6_PDE_SHIFT); | |
477 | } | |
478 | ||
3e490042 MK |
479 | static inline unsigned int |
480 | i915_pdpes_per_pdp(const struct i915_address_space *vm) | |
481 | { | |
482 | if (i915_vm_is_48bit(vm)) | |
483 | return GEN8_PML4ES_PER_PML4; | |
484 | ||
e7167769 | 485 | return GEN8_3LVL_PDPES; |
3e490042 MK |
486 | } |
487 | ||
9271d959 MT |
488 | /* Equivalent to the gen6 version, For each pde iterates over every pde |
489 | * between from start until start + length. On gen8+ it simply iterates | |
490 | * over every page directory entry in a page directory. | |
491 | */ | |
e8ebd8e2 DG |
492 | #define gen8_for_each_pde(pt, pd, start, length, iter) \ |
493 | for (iter = gen8_pde_index(start); \ | |
494 | length > 0 && iter < I915_PDES && \ | |
495 | (pt = (pd)->page_table[iter], true); \ | |
496 | ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ | |
497 | temp = min(temp - start, length); \ | |
498 | start += temp, length -= temp; }), ++iter) | |
499 | ||
500 | #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ | |
501 | for (iter = gen8_pdpe_index(start); \ | |
3e490042 | 502 | length > 0 && iter < i915_pdpes_per_pdp(vm) && \ |
e8ebd8e2 DG |
503 | (pd = (pdp)->page_directory[iter], true); \ |
504 | ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ | |
505 | temp = min(temp - start, length); \ | |
506 | start += temp, length -= temp; }), ++iter) | |
507 | ||
508 | #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ | |
509 | for (iter = gen8_pml4e_index(start); \ | |
510 | length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ | |
511 | (pdp = (pml4)->pdps[iter], true); \ | |
512 | ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ | |
513 | temp = min(temp - start, length); \ | |
514 | start += temp, length -= temp; }), ++iter) | |
762d9936 | 515 | |
75c7b0b8 | 516 | static inline u32 gen8_pte_index(u64 address) |
9271d959 MT |
517 | { |
518 | return i915_pte_index(address, GEN8_PDE_SHIFT); | |
519 | } | |
520 | ||
75c7b0b8 | 521 | static inline u32 gen8_pde_index(u64 address) |
9271d959 MT |
522 | { |
523 | return i915_pde_index(address, GEN8_PDE_SHIFT); | |
524 | } | |
525 | ||
75c7b0b8 | 526 | static inline u32 gen8_pdpe_index(u64 address) |
9271d959 MT |
527 | { |
528 | return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; | |
529 | } | |
530 | ||
75c7b0b8 | 531 | static inline u32 gen8_pml4e_index(u64 address) |
9271d959 | 532 | { |
762d9936 | 533 | return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; |
9271d959 MT |
534 | } |
535 | ||
75c7b0b8 | 536 | static inline u64 gen8_pte_count(u64 address, u64 length) |
33c8819f MT |
537 | { |
538 | return i915_pte_count(address, length, GEN8_PDE_SHIFT); | |
539 | } | |
540 | ||
d852c7bf MK |
541 | static inline dma_addr_t |
542 | i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) | |
543 | { | |
fe52e37f | 544 | return px_dma(ppgtt->pdp.page_directory[n]); |
d852c7bf MK |
545 | } |
546 | ||
b42fe9ca JL |
547 | static inline struct i915_ggtt * |
548 | i915_vm_to_ggtt(struct i915_address_space *vm) | |
549 | { | |
550 | GEM_BUG_ON(!i915_is_ggtt(vm)); | |
551 | return container_of(vm, struct i915_ggtt, base); | |
552 | } | |
553 | ||
4395890a ZW |
554 | #define INTEL_MAX_PPAT_ENTRIES 8 |
555 | #define INTEL_PPAT_PERFECT_MATCH (~0U) | |
556 | ||
557 | struct intel_ppat; | |
558 | ||
559 | struct intel_ppat_entry { | |
560 | struct intel_ppat *ppat; | |
561 | struct kref ref; | |
562 | u8 value; | |
563 | }; | |
564 | ||
565 | struct intel_ppat { | |
566 | struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; | |
567 | DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); | |
568 | DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); | |
569 | unsigned int max_entries; | |
570 | u8 clear_value; | |
571 | /* | |
572 | * Return a score to show how two PPAT values match, | |
573 | * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match | |
574 | */ | |
575 | unsigned int (*match)(u8 src, u8 dst); | |
576 | void (*update_hw)(struct drm_i915_private *i915); | |
577 | ||
578 | struct drm_i915_private *i915; | |
579 | }; | |
580 | ||
581 | const struct intel_ppat_entry * | |
582 | intel_ppat_get(struct drm_i915_private *i915, u8 value); | |
583 | void intel_ppat_put(const struct intel_ppat_entry *entry); | |
584 | ||
6cde9a02 CW |
585 | int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); |
586 | void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); | |
587 | ||
97d6d7ab CW |
588 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); |
589 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); | |
590 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); | |
7c3f86b6 CW |
591 | void i915_ggtt_enable_guc(struct drm_i915_private *i915); |
592 | void i915_ggtt_disable_guc(struct drm_i915_private *i915); | |
f6b9d5ca | 593 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); |
97d6d7ab | 594 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); |
ee960be7 | 595 | |
c6be607a | 596 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); |
ee960be7 | 597 | void i915_ppgtt_release(struct kref *kref); |
2bfa996e | 598 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
599 | struct drm_i915_file_private *fpriv, |
600 | const char *name); | |
0c7eeda1 | 601 | void i915_ppgtt_close(struct i915_address_space *vm); |
ee960be7 DV |
602 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
603 | { | |
604 | if (ppgtt) | |
605 | kref_get(&ppgtt->ref); | |
606 | } | |
607 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) | |
608 | { | |
609 | if (ppgtt) | |
610 | kref_put(&ppgtt->ref, i915_ppgtt_release); | |
611 | } | |
0260c420 | 612 | |
dc97997a | 613 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); |
275a991c TU |
614 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); |
615 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); | |
0260c420 | 616 | |
03ac84f1 CW |
617 | int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
618 | struct sg_table *pages); | |
619 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, | |
620 | struct sg_table *pages); | |
0260c420 | 621 | |
625d988a CW |
622 | int i915_gem_gtt_reserve(struct i915_address_space *vm, |
623 | struct drm_mm_node *node, | |
624 | u64 size, u64 offset, unsigned long color, | |
625 | unsigned int flags); | |
626 | ||
e007b19d CW |
627 | int i915_gem_gtt_insert(struct i915_address_space *vm, |
628 | struct drm_mm_node *node, | |
629 | u64 size, u64 alignment, unsigned long color, | |
630 | u64 start, u64 end, unsigned int flags); | |
631 | ||
59bfa124 | 632 | /* Flags used by pin/bind&friends. */ |
305bc234 CW |
633 | #define PIN_NONBLOCK BIT(0) |
634 | #define PIN_MAPPABLE BIT(1) | |
635 | #define PIN_ZONE_4G BIT(2) | |
82118877 | 636 | #define PIN_NONFAULT BIT(3) |
616d9cee | 637 | #define PIN_NOEVICT BIT(4) |
305bc234 CW |
638 | |
639 | #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ | |
640 | #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ | |
641 | #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ | |
642 | #define PIN_UPDATE BIT(8) | |
643 | ||
644 | #define PIN_HIGH BIT(9) | |
645 | #define PIN_OFFSET_BIAS BIT(10) | |
646 | #define PIN_OFFSET_FIXED BIT(11) | |
f51455d4 | 647 | #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) |
59bfa124 | 648 | |
0260c420 | 649 | #endif |