]>
Commit | Line | Data |
---|---|---|
0260c420 BW |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Please try to maintain the following order within this file unless it makes | |
24 | * sense to do otherwise. From top to bottom: | |
25 | * 1. typedefs | |
26 | * 2. #defines, and macros | |
27 | * 3. structure definitions | |
28 | * 4. function prototypes | |
29 | * | |
30 | * Within each section, please try to order by generation in ascending order, | |
31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). | |
32 | */ | |
33 | ||
34 | #ifndef __I915_GEM_GTT_H__ | |
35 | #define __I915_GEM_GTT_H__ | |
36 | ||
8ef8561f | 37 | #include <linux/io-mapping.h> |
b42fe9ca | 38 | #include <linux/mm.h> |
8ef8561f | 39 | |
b42fe9ca | 40 | #include "i915_gem_timeline.h" |
b0decaf7 CW |
41 | #include "i915_gem_request.h" |
42 | ||
f51455d4 CW |
43 | #define I915_GTT_PAGE_SIZE 4096UL |
44 | #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE | |
45 | ||
49ef5294 CW |
46 | #define I915_FENCE_REG_NONE -1 |
47 | #define I915_MAX_NUM_FENCES 32 | |
48 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
49 | #define I915_MAX_NUM_FENCE_BITS 6 | |
50 | ||
4d884705 | 51 | struct drm_i915_file_private; |
49ef5294 | 52 | struct drm_i915_fence_reg; |
4d884705 | 53 | |
07749ef3 MT |
54 | typedef uint32_t gen6_pte_t; |
55 | typedef uint64_t gen8_pte_t; | |
56 | typedef uint64_t gen8_pde_t; | |
762d9936 MT |
57 | typedef uint64_t gen8_ppgtt_pdpe_t; |
58 | typedef uint64_t gen8_ppgtt_pml4e_t; | |
0260c420 | 59 | |
72e96d64 | 60 | #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) |
0260c420 | 61 | |
0260c420 BW |
62 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
63 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
64 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
65 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
66 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
67 | #define GEN6_PTE_UNCACHED (1 << 1) | |
68 | #define GEN6_PTE_VALID (1 << 0) | |
69 | ||
07749ef3 MT |
70 | #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) |
71 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) | |
72 | #define I915_PDES 512 | |
73 | #define I915_PDE_MASK (I915_PDES - 1) | |
678d96fb | 74 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
07749ef3 MT |
75 | |
76 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) | |
77 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) | |
0260c420 | 78 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
678d96fb | 79 | #define GEN6_PDE_SHIFT 22 |
0260c420 BW |
80 | #define GEN6_PDE_VALID (1 << 0) |
81 | ||
82 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) | |
83 | ||
84 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
85 | #define BYT_PTE_WRITEABLE (1 << 1) | |
86 | ||
87 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits | |
88 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
89 | */ | |
90 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
91 | (((bits) & 0x8) << (11 - 3))) | |
92 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | |
93 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
94 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | |
95 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | |
96 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | |
97 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | |
98 | #define HSW_PTE_UNCACHED (0) | |
99 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) | |
100 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) | |
101 | ||
102 | /* GEN8 legacy style address is defined as a 3 level page table: | |
103 | * 31:30 | 29:21 | 20:12 | 11:0 | |
104 | * PDPE | PDE | PTE | offset | |
105 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
106 | * programmed via register. | |
81ba8aef MT |
107 | * |
108 | * GEN8 48b legacy style address is defined as a 4 level page table: | |
109 | * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 | |
110 | * PML4E | PDPE | PDE | PTE | offset | |
0260c420 | 111 | */ |
81ba8aef MT |
112 | #define GEN8_PML4ES_PER_PML4 512 |
113 | #define GEN8_PML4E_SHIFT 39 | |
762d9936 | 114 | #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) |
0260c420 | 115 | #define GEN8_PDPE_SHIFT 30 |
81ba8aef MT |
116 | /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page |
117 | * tables */ | |
118 | #define GEN8_PDPE_MASK 0x1ff | |
0260c420 BW |
119 | #define GEN8_PDE_SHIFT 21 |
120 | #define GEN8_PDE_MASK 0x1ff | |
121 | #define GEN8_PTE_SHIFT 12 | |
122 | #define GEN8_PTE_MASK 0x1ff | |
76643600 | 123 | #define GEN8_LEGACY_PDPES 4 |
07749ef3 | 124 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) |
0260c420 | 125 | |
275a991c TU |
126 | #define I915_PDPES_PER_PDP(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\ |
127 | GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) | |
6ac18502 | 128 | |
0260c420 BW |
129 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
130 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
131 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
132 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
133 | ||
ee0ce478 | 134 | #define CHV_PPAT_SNOOP (1<<6) |
0260c420 BW |
135 | #define GEN8_PPAT_AGE(x) (x<<4) |
136 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
137 | #define GEN8_PPAT_LLCELLC (2<<2) | |
138 | #define GEN8_PPAT_LLC (1<<2) | |
139 | #define GEN8_PPAT_WB (3<<0) | |
140 | #define GEN8_PPAT_WT (2<<0) | |
141 | #define GEN8_PPAT_WC (1<<0) | |
142 | #define GEN8_PPAT_UC (0<<0) | |
143 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
144 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
145 | ||
b42fe9ca JL |
146 | struct sg_table; |
147 | ||
fe14d5f4 TU |
148 | enum i915_ggtt_view_type { |
149 | I915_GGTT_VIEW_NORMAL = 0, | |
8bd7ef16 JL |
150 | I915_GGTT_VIEW_ROTATED, |
151 | I915_GGTT_VIEW_PARTIAL, | |
50470bb0 TU |
152 | }; |
153 | ||
154 | struct intel_rotation_info { | |
7ff19c56 | 155 | struct intel_rotation_plane_info { |
1663b9d6 | 156 | /* tiles */ |
6687c906 | 157 | unsigned int width, height, stride, offset; |
1663b9d6 | 158 | } plane[2]; |
fe14d5f4 TU |
159 | }; |
160 | ||
7ff19c56 CW |
161 | struct intel_partial_info { |
162 | u64 offset; | |
163 | unsigned int size; | |
164 | }; | |
165 | ||
fe14d5f4 TU |
166 | struct i915_ggtt_view { |
167 | enum i915_ggtt_view_type type; | |
168 | ||
8bd7ef16 | 169 | union { |
7ff19c56 | 170 | struct intel_partial_info partial; |
7723f47d | 171 | struct intel_rotation_info rotated; |
8bd7ef16 | 172 | } params; |
fe14d5f4 TU |
173 | }; |
174 | ||
175 | extern const struct i915_ggtt_view i915_ggtt_view_normal; | |
9abc4648 | 176 | extern const struct i915_ggtt_view i915_ggtt_view_rotated; |
fe14d5f4 | 177 | |
0260c420 | 178 | enum i915_cache_level; |
fe14d5f4 | 179 | |
b42fe9ca | 180 | struct i915_vma; |
bde13ebd | 181 | |
44159ddb | 182 | struct i915_page_dma { |
d7b3de91 | 183 | struct page *page; |
44159ddb MK |
184 | union { |
185 | dma_addr_t daddr; | |
186 | ||
187 | /* For gen6/gen7 only. This is the offset in the GGTT | |
188 | * where the page directory entries for PPGTT begin | |
189 | */ | |
190 | uint32_t ggtt_offset; | |
191 | }; | |
192 | }; | |
193 | ||
567047be MK |
194 | #define px_base(px) (&(px)->base) |
195 | #define px_page(px) (px_base(px)->page) | |
196 | #define px_dma(px) (px_base(px)->daddr) | |
197 | ||
44159ddb MK |
198 | struct i915_page_table { |
199 | struct i915_page_dma base; | |
678d96fb BW |
200 | |
201 | unsigned long *used_ptes; | |
d7b3de91 BW |
202 | }; |
203 | ||
ec565b3c | 204 | struct i915_page_directory { |
44159ddb | 205 | struct i915_page_dma base; |
7324cc04 | 206 | |
33c8819f | 207 | unsigned long *used_pdes; |
ec565b3c | 208 | struct i915_page_table *page_table[I915_PDES]; /* PDEs */ |
d7b3de91 BW |
209 | }; |
210 | ||
ec565b3c | 211 | struct i915_page_directory_pointer { |
6ac18502 MT |
212 | struct i915_page_dma base; |
213 | ||
214 | unsigned long *used_pdpes; | |
215 | struct i915_page_directory **page_directory; | |
d7b3de91 BW |
216 | }; |
217 | ||
81ba8aef MT |
218 | struct i915_pml4 { |
219 | struct i915_page_dma base; | |
220 | ||
221 | DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); | |
222 | struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; | |
223 | }; | |
224 | ||
0260c420 BW |
225 | struct i915_address_space { |
226 | struct drm_mm mm; | |
80b204bc | 227 | struct i915_gem_timeline timeline; |
49d73912 | 228 | struct drm_i915_private *i915; |
2bfa996e CW |
229 | /* Every address space belongs to a struct file - except for the global |
230 | * GTT that is owned by the driver (and so @file is set to NULL). In | |
231 | * principle, no information should leak from one context to another | |
232 | * (or between files/processes etc) unless explicitly shared by the | |
233 | * owner. Tracking the owner is important in order to free up per-file | |
234 | * objects along with the file, to aide resource tracking, and to | |
235 | * assign blame. | |
236 | */ | |
237 | struct drm_i915_file_private *file; | |
0260c420 | 238 | struct list_head global_link; |
c44ef60e MK |
239 | u64 start; /* Start offset always 0 for dri2 */ |
240 | u64 total; /* size addr space maps (ex. 2GB for ggtt) */ | |
0260c420 | 241 | |
50e046b6 CW |
242 | bool closed; |
243 | ||
8bcdd0f7 | 244 | struct i915_page_dma scratch_page; |
79ab9370 MK |
245 | struct i915_page_table *scratch_pt; |
246 | struct i915_page_directory *scratch_pd; | |
69ab76fd | 247 | struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ |
0260c420 BW |
248 | |
249 | /** | |
250 | * List of objects currently involved in rendering. | |
251 | * | |
252 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 253 | * flushed, not necessarily primitives. last_read_req |
0260c420 BW |
254 | * represents when the rendering involved will be completed. |
255 | * | |
256 | * A reference is held on the buffer while on this list. | |
257 | */ | |
258 | struct list_head active_list; | |
259 | ||
260 | /** | |
261 | * LRU list of objects which are not in the ringbuffer and | |
262 | * are ready to unbind, but are still in the GTT. | |
263 | * | |
97b2a6a1 | 264 | * last_read_req is NULL while an object is in this list. |
0260c420 BW |
265 | * |
266 | * A reference is not held on the buffer while on this list, | |
267 | * as merely being GTT-bound shouldn't prevent its being | |
268 | * freed, and we'll pull it off the list in the free path. | |
269 | */ | |
270 | struct list_head inactive_list; | |
271 | ||
50e046b6 CW |
272 | /** |
273 | * List of vma that have been unbound. | |
274 | * | |
275 | * A reference is not held on the buffer while on this list. | |
276 | */ | |
277 | struct list_head unbound_list; | |
278 | ||
0260c420 | 279 | /* FIXME: Need a more generic return type */ |
07749ef3 MT |
280 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
281 | enum i915_cache_level level, | |
4fb84d99 | 282 | u32 flags); /* Create a valid PTE */ |
f329f5f6 DV |
283 | /* flags for pte_encode */ |
284 | #define PTE_READ_ONLY (1<<0) | |
678d96fb BW |
285 | int (*allocate_va_range)(struct i915_address_space *vm, |
286 | uint64_t start, | |
287 | uint64_t length); | |
0260c420 BW |
288 | void (*clear_range)(struct i915_address_space *vm, |
289 | uint64_t start, | |
4fb84d99 | 290 | uint64_t length); |
d6473f56 CW |
291 | void (*insert_page)(struct i915_address_space *vm, |
292 | dma_addr_t addr, | |
293 | uint64_t offset, | |
294 | enum i915_cache_level cache_level, | |
295 | u32 flags); | |
0260c420 BW |
296 | void (*insert_entries)(struct i915_address_space *vm, |
297 | struct sg_table *st, | |
298 | uint64_t start, | |
24f3a8cf | 299 | enum i915_cache_level cache_level, u32 flags); |
0260c420 | 300 | void (*cleanup)(struct i915_address_space *vm); |
777dc5bb DV |
301 | /** Unmap an object from an address space. This usually consists of |
302 | * setting the valid PTE entries to a reserved scratch page. */ | |
303 | void (*unbind_vma)(struct i915_vma *vma); | |
304 | /* Map an object into an address space with the given cache flags. */ | |
70b9f6f8 DV |
305 | int (*bind_vma)(struct i915_vma *vma, |
306 | enum i915_cache_level cache_level, | |
307 | u32 flags); | |
0260c420 BW |
308 | }; |
309 | ||
2bfa996e | 310 | #define i915_is_ggtt(V) (!(V)->file) |
596c5923 | 311 | |
0260c420 BW |
312 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
313 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
314 | * collateral associated with any va->pa translations GEN hardware also has a | |
315 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
316 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
317 | * the spec. | |
318 | */ | |
62106b4f | 319 | struct i915_ggtt { |
0260c420 | 320 | struct i915_address_space base; |
f7bbe788 | 321 | struct io_mapping mappable; /* Mapping to our CPU mappable region */ |
0260c420 | 322 | |
edd1f2fe CW |
323 | phys_addr_t mappable_base; /* PA of our GMADR */ |
324 | u64 mappable_end; /* End offset that we can CPU map */ | |
325 | ||
3c6b29b2 PZ |
326 | /* Stolen memory is segmented in hardware with different portions |
327 | * offlimits to certain functions. | |
328 | * | |
329 | * The drm_mm is initialised to the total accessible range, as found | |
330 | * from the PCI config. On Broadwell+, this is further restricted to | |
331 | * avoid the first page! The upper end of stolen memory is reserved for | |
332 | * hardware functions and similarly removed from the accessible range. | |
333 | */ | |
edd1f2fe CW |
334 | u32 stolen_size; /* Total size of stolen memory */ |
335 | u32 stolen_usable_size; /* Total size minus reserved ranges */ | |
336 | u32 stolen_reserved_base; | |
337 | u32 stolen_reserved_size; | |
0260c420 BW |
338 | |
339 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
340 | void __iomem *gsm; | |
7c3f86b6 | 341 | void (*invalidate)(struct drm_i915_private *dev_priv); |
0260c420 BW |
342 | |
343 | bool do_idle_maps; | |
344 | ||
345 | int mtrr; | |
95374d75 CW |
346 | |
347 | struct drm_mm_node error_capture; | |
0260c420 BW |
348 | }; |
349 | ||
350 | struct i915_hw_ppgtt { | |
351 | struct i915_address_space base; | |
352 | struct kref ref; | |
353 | struct drm_mm_node node; | |
563222a7 | 354 | unsigned long pd_dirty_rings; |
d7b3de91 | 355 | union { |
81ba8aef MT |
356 | struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ |
357 | struct i915_page_directory_pointer pdp; /* GEN8+ */ | |
358 | struct i915_page_directory pd; /* GEN6-7 */ | |
d7b3de91 | 359 | }; |
0260c420 | 360 | |
678d96fb BW |
361 | gen6_pte_t __iomem *pd_addr; |
362 | ||
0260c420 BW |
363 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
364 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, | |
e85b26dc | 365 | struct drm_i915_gem_request *req); |
0260c420 BW |
366 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
367 | }; | |
368 | ||
731f74c5 DG |
369 | /* |
370 | * gen6_for_each_pde() iterates over every pde from start until start+length. | |
371 | * If start and start+length are not perfectly divisible, the macro will round | |
372 | * down and up as needed. Start=0 and length=2G effectively iterates over | |
373 | * every PDE in the system. The macro modifies ALL its parameters except 'pd', | |
374 | * so each of the other parameters should preferably be a simple variable, or | |
375 | * at most an lvalue with no side-effects! | |
678d96fb | 376 | */ |
731f74c5 DG |
377 | #define gen6_for_each_pde(pt, pd, start, length, iter) \ |
378 | for (iter = gen6_pde_index(start); \ | |
379 | length > 0 && iter < I915_PDES && \ | |
380 | (pt = (pd)->page_table[iter], true); \ | |
381 | ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ | |
382 | temp = min(temp - start, length); \ | |
383 | start += temp, length -= temp; }), ++iter) | |
384 | ||
385 | #define gen6_for_all_pdes(pt, pd, iter) \ | |
386 | for (iter = 0; \ | |
387 | iter < I915_PDES && \ | |
388 | (pt = (pd)->page_table[iter], true); \ | |
389 | ++iter) | |
09942c65 | 390 | |
678d96fb BW |
391 | static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) |
392 | { | |
393 | const uint32_t mask = NUM_PTE(pde_shift) - 1; | |
394 | ||
395 | return (address >> PAGE_SHIFT) & mask; | |
396 | } | |
397 | ||
398 | /* Helper to counts the number of PTEs within the given length. This count | |
399 | * does not cross a page table boundary, so the max value would be | |
400 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. | |
401 | */ | |
402 | static inline uint32_t i915_pte_count(uint64_t addr, size_t length, | |
403 | uint32_t pde_shift) | |
404 | { | |
69603dbb | 405 | const uint64_t mask = ~((1ULL << pde_shift) - 1); |
678d96fb BW |
406 | uint64_t end; |
407 | ||
408 | WARN_ON(length == 0); | |
409 | WARN_ON(offset_in_page(addr|length)); | |
410 | ||
411 | end = addr + length; | |
412 | ||
413 | if ((addr & mask) != (end & mask)) | |
414 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); | |
415 | ||
416 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); | |
417 | } | |
418 | ||
419 | static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) | |
420 | { | |
421 | return (addr >> shift) & I915_PDE_MASK; | |
422 | } | |
423 | ||
424 | static inline uint32_t gen6_pte_index(uint32_t addr) | |
425 | { | |
426 | return i915_pte_index(addr, GEN6_PDE_SHIFT); | |
427 | } | |
428 | ||
429 | static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) | |
430 | { | |
431 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); | |
432 | } | |
433 | ||
434 | static inline uint32_t gen6_pde_index(uint32_t addr) | |
435 | { | |
436 | return i915_pde_index(addr, GEN6_PDE_SHIFT); | |
437 | } | |
438 | ||
9271d959 MT |
439 | /* Equivalent to the gen6 version, For each pde iterates over every pde |
440 | * between from start until start + length. On gen8+ it simply iterates | |
441 | * over every page directory entry in a page directory. | |
442 | */ | |
e8ebd8e2 DG |
443 | #define gen8_for_each_pde(pt, pd, start, length, iter) \ |
444 | for (iter = gen8_pde_index(start); \ | |
445 | length > 0 && iter < I915_PDES && \ | |
446 | (pt = (pd)->page_table[iter], true); \ | |
447 | ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ | |
448 | temp = min(temp - start, length); \ | |
449 | start += temp, length -= temp; }), ++iter) | |
450 | ||
451 | #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ | |
452 | for (iter = gen8_pdpe_index(start); \ | |
453 | length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ | |
454 | (pd = (pdp)->page_directory[iter], true); \ | |
455 | ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ | |
456 | temp = min(temp - start, length); \ | |
457 | start += temp, length -= temp; }), ++iter) | |
458 | ||
459 | #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ | |
460 | for (iter = gen8_pml4e_index(start); \ | |
461 | length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ | |
462 | (pdp = (pml4)->pdps[iter], true); \ | |
463 | ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ | |
464 | temp = min(temp - start, length); \ | |
465 | start += temp, length -= temp; }), ++iter) | |
762d9936 | 466 | |
9271d959 MT |
467 | static inline uint32_t gen8_pte_index(uint64_t address) |
468 | { | |
469 | return i915_pte_index(address, GEN8_PDE_SHIFT); | |
470 | } | |
471 | ||
472 | static inline uint32_t gen8_pde_index(uint64_t address) | |
473 | { | |
474 | return i915_pde_index(address, GEN8_PDE_SHIFT); | |
475 | } | |
476 | ||
477 | static inline uint32_t gen8_pdpe_index(uint64_t address) | |
478 | { | |
479 | return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; | |
480 | } | |
481 | ||
482 | static inline uint32_t gen8_pml4e_index(uint64_t address) | |
483 | { | |
762d9936 | 484 | return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; |
9271d959 MT |
485 | } |
486 | ||
33c8819f MT |
487 | static inline size_t gen8_pte_count(uint64_t address, uint64_t length) |
488 | { | |
489 | return i915_pte_count(address, length, GEN8_PDE_SHIFT); | |
490 | } | |
491 | ||
d852c7bf MK |
492 | static inline dma_addr_t |
493 | i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) | |
494 | { | |
495 | return test_bit(n, ppgtt->pdp.used_pdpes) ? | |
567047be | 496 | px_dma(ppgtt->pdp.page_directory[n]) : |
79ab9370 | 497 | px_dma(ppgtt->base.scratch_pd); |
d852c7bf MK |
498 | } |
499 | ||
b42fe9ca JL |
500 | static inline struct i915_ggtt * |
501 | i915_vm_to_ggtt(struct i915_address_space *vm) | |
502 | { | |
503 | GEM_BUG_ON(!i915_is_ggtt(vm)); | |
504 | return container_of(vm, struct i915_ggtt, base); | |
505 | } | |
506 | ||
97d6d7ab CW |
507 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); |
508 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); | |
509 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); | |
7c3f86b6 CW |
510 | void i915_ggtt_enable_guc(struct drm_i915_private *i915); |
511 | void i915_ggtt_disable_guc(struct drm_i915_private *i915); | |
f6b9d5ca | 512 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); |
97d6d7ab | 513 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); |
ee960be7 | 514 | |
c6be607a | 515 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); |
ee960be7 | 516 | void i915_ppgtt_release(struct kref *kref); |
2bfa996e | 517 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
518 | struct drm_i915_file_private *fpriv, |
519 | const char *name); | |
0c7eeda1 | 520 | void i915_ppgtt_close(struct i915_address_space *vm); |
ee960be7 DV |
521 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
522 | { | |
523 | if (ppgtt) | |
524 | kref_get(&ppgtt->ref); | |
525 | } | |
526 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) | |
527 | { | |
528 | if (ppgtt) | |
529 | kref_put(&ppgtt->ref, i915_ppgtt_release); | |
530 | } | |
0260c420 | 531 | |
dc97997a | 532 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); |
275a991c TU |
533 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); |
534 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); | |
0260c420 | 535 | |
03ac84f1 CW |
536 | int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
537 | struct sg_table *pages); | |
538 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, | |
539 | struct sg_table *pages); | |
0260c420 | 540 | |
625d988a CW |
541 | int i915_gem_gtt_reserve(struct i915_address_space *vm, |
542 | struct drm_mm_node *node, | |
543 | u64 size, u64 offset, unsigned long color, | |
544 | unsigned int flags); | |
545 | ||
e007b19d CW |
546 | int i915_gem_gtt_insert(struct i915_address_space *vm, |
547 | struct drm_mm_node *node, | |
548 | u64 size, u64 alignment, unsigned long color, | |
549 | u64 start, u64 end, unsigned int flags); | |
550 | ||
59bfa124 | 551 | /* Flags used by pin/bind&friends. */ |
305bc234 CW |
552 | #define PIN_NONBLOCK BIT(0) |
553 | #define PIN_MAPPABLE BIT(1) | |
554 | #define PIN_ZONE_4G BIT(2) | |
82118877 | 555 | #define PIN_NONFAULT BIT(3) |
305bc234 CW |
556 | |
557 | #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ | |
558 | #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ | |
559 | #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ | |
560 | #define PIN_UPDATE BIT(8) | |
561 | ||
562 | #define PIN_HIGH BIT(9) | |
563 | #define PIN_OFFSET_BIAS BIT(10) | |
564 | #define PIN_OFFSET_FIXED BIT(11) | |
f51455d4 | 565 | #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) |
59bfa124 | 566 | |
0260c420 | 567 | #endif |