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0260c420 BW |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Please try to maintain the following order within this file unless it makes | |
24 | * sense to do otherwise. From top to bottom: | |
25 | * 1. typedefs | |
26 | * 2. #defines, and macros | |
27 | * 3. structure definitions | |
28 | * 4. function prototypes | |
29 | * | |
30 | * Within each section, please try to order by generation in ascending order, | |
31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). | |
32 | */ | |
33 | ||
34 | #ifndef __I915_GEM_GTT_H__ | |
35 | #define __I915_GEM_GTT_H__ | |
36 | ||
4d884705 DV |
37 | struct drm_i915_file_private; |
38 | ||
07749ef3 MT |
39 | typedef uint32_t gen6_pte_t; |
40 | typedef uint64_t gen8_pte_t; | |
41 | typedef uint64_t gen8_pde_t; | |
0260c420 BW |
42 | |
43 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) | |
44 | ||
07749ef3 | 45 | |
0260c420 BW |
46 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
47 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
48 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
49 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
50 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
51 | #define GEN6_PTE_UNCACHED (1 << 1) | |
52 | #define GEN6_PTE_VALID (1 << 0) | |
53 | ||
07749ef3 MT |
54 | #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) |
55 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) | |
56 | #define I915_PDES 512 | |
57 | #define I915_PDE_MASK (I915_PDES - 1) | |
678d96fb | 58 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
07749ef3 MT |
59 | |
60 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) | |
61 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) | |
0260c420 | 62 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
678d96fb | 63 | #define GEN6_PDE_SHIFT 22 |
0260c420 BW |
64 | #define GEN6_PDE_VALID (1 << 0) |
65 | ||
66 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) | |
67 | ||
68 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
69 | #define BYT_PTE_WRITEABLE (1 << 1) | |
70 | ||
71 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits | |
72 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
73 | */ | |
74 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
75 | (((bits) & 0x8) << (11 - 3))) | |
76 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | |
77 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
78 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | |
79 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | |
80 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | |
81 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | |
82 | #define HSW_PTE_UNCACHED (0) | |
83 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) | |
84 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) | |
85 | ||
86 | /* GEN8 legacy style address is defined as a 3 level page table: | |
87 | * 31:30 | 29:21 | 20:12 | 11:0 | |
88 | * PDPE | PDE | PTE | offset | |
89 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
90 | * programmed via register. | |
91 | */ | |
92 | #define GEN8_PDPE_SHIFT 30 | |
93 | #define GEN8_PDPE_MASK 0x3 | |
94 | #define GEN8_PDE_SHIFT 21 | |
95 | #define GEN8_PDE_MASK 0x1ff | |
96 | #define GEN8_PTE_SHIFT 12 | |
97 | #define GEN8_PTE_MASK 0x1ff | |
76643600 | 98 | #define GEN8_LEGACY_PDPES 4 |
07749ef3 | 99 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) |
0260c420 BW |
100 | |
101 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) | |
102 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
103 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
104 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
105 | ||
ee0ce478 | 106 | #define CHV_PPAT_SNOOP (1<<6) |
0260c420 BW |
107 | #define GEN8_PPAT_AGE(x) (x<<4) |
108 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
109 | #define GEN8_PPAT_LLCELLC (2<<2) | |
110 | #define GEN8_PPAT_LLC (1<<2) | |
111 | #define GEN8_PPAT_WB (3<<0) | |
112 | #define GEN8_PPAT_WT (2<<0) | |
113 | #define GEN8_PPAT_WC (1<<0) | |
114 | #define GEN8_PPAT_UC (0<<0) | |
115 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
116 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
117 | ||
fe14d5f4 TU |
118 | enum i915_ggtt_view_type { |
119 | I915_GGTT_VIEW_NORMAL = 0, | |
8bd7ef16 JL |
120 | I915_GGTT_VIEW_ROTATED, |
121 | I915_GGTT_VIEW_PARTIAL, | |
50470bb0 TU |
122 | }; |
123 | ||
124 | struct intel_rotation_info { | |
125 | unsigned int height; | |
126 | unsigned int pitch; | |
127 | uint32_t pixel_format; | |
128 | uint64_t fb_modifier; | |
fe14d5f4 TU |
129 | }; |
130 | ||
131 | struct i915_ggtt_view { | |
132 | enum i915_ggtt_view_type type; | |
133 | ||
8bd7ef16 JL |
134 | union { |
135 | struct { | |
136 | unsigned long offset; | |
137 | unsigned int size; | |
138 | } partial; | |
139 | } params; | |
140 | ||
fe14d5f4 | 141 | struct sg_table *pages; |
50470bb0 TU |
142 | |
143 | union { | |
144 | struct intel_rotation_info rotation_info; | |
145 | }; | |
fe14d5f4 TU |
146 | }; |
147 | ||
148 | extern const struct i915_ggtt_view i915_ggtt_view_normal; | |
9abc4648 | 149 | extern const struct i915_ggtt_view i915_ggtt_view_rotated; |
fe14d5f4 | 150 | |
0260c420 | 151 | enum i915_cache_level; |
fe14d5f4 | 152 | |
0260c420 BW |
153 | /** |
154 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
155 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
156 | * object into/from the address space. | |
157 | * | |
158 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
159 | * will always be <= an objects lifetime. So object refcounting should cover us. | |
160 | */ | |
161 | struct i915_vma { | |
162 | struct drm_mm_node node; | |
163 | struct drm_i915_gem_object *obj; | |
164 | struct i915_address_space *vm; | |
165 | ||
aff43766 TU |
166 | /** Flags and address space this VMA is bound to */ |
167 | #define GLOBAL_BIND (1<<0) | |
168 | #define LOCAL_BIND (1<<1) | |
aff43766 TU |
169 | unsigned int bound : 4; |
170 | ||
fe14d5f4 TU |
171 | /** |
172 | * Support different GGTT views into the same object. | |
173 | * This means there can be multiple VMA mappings per object and per VM. | |
174 | * i915_ggtt_view_type is used to distinguish between those entries. | |
175 | * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also | |
176 | * assumed in GEM functions which take no ggtt view parameter. | |
177 | */ | |
178 | struct i915_ggtt_view ggtt_view; | |
179 | ||
0260c420 BW |
180 | /** This object's place on the active/inactive lists */ |
181 | struct list_head mm_list; | |
182 | ||
183 | struct list_head vma_link; /* Link in the object's VMA list */ | |
184 | ||
185 | /** This vma's place in the batchbuffer or on the eviction list */ | |
186 | struct list_head exec_list; | |
187 | ||
188 | /** | |
189 | * Used for performing relocations during execbuffer insertion. | |
190 | */ | |
191 | struct hlist_node exec_node; | |
192 | unsigned long exec_handle; | |
193 | struct drm_i915_gem_exec_object2 *exec_entry; | |
194 | ||
195 | /** | |
196 | * How many users have pinned this object in GTT space. The following | |
4feb7659 DV |
197 | * users can each hold at most one reference: pwrite/pread, execbuffer |
198 | * (objects are not allowed multiple times for the same batchbuffer), | |
199 | * and the framebuffer code. When switching/pageflipping, the | |
200 | * framebuffer code has at most two buffers pinned per crtc. | |
0260c420 BW |
201 | * |
202 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
203 | * bits with absolutely no headroom. So use 4 bits. */ | |
204 | unsigned int pin_count:4; | |
205 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf | |
0260c420 BW |
206 | }; |
207 | ||
ec565b3c | 208 | struct i915_page_table { |
d7b3de91 | 209 | struct page *page; |
7324cc04 | 210 | dma_addr_t daddr; |
678d96fb BW |
211 | |
212 | unsigned long *used_ptes; | |
d7b3de91 BW |
213 | }; |
214 | ||
ec565b3c | 215 | struct i915_page_directory { |
d7b3de91 | 216 | struct page *page; /* NULL for GEN6-GEN7 */ |
7324cc04 BW |
217 | union { |
218 | uint32_t pd_offset; | |
219 | dma_addr_t daddr; | |
220 | }; | |
221 | ||
33c8819f | 222 | unsigned long *used_pdes; |
ec565b3c | 223 | struct i915_page_table *page_table[I915_PDES]; /* PDEs */ |
d7b3de91 BW |
224 | }; |
225 | ||
ec565b3c | 226 | struct i915_page_directory_pointer { |
d7b3de91 | 227 | /* struct page *page; */ |
33c8819f | 228 | DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES); |
ec565b3c | 229 | struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES]; |
d7b3de91 BW |
230 | }; |
231 | ||
0260c420 BW |
232 | struct i915_address_space { |
233 | struct drm_mm mm; | |
234 | struct drm_device *dev; | |
235 | struct list_head global_link; | |
236 | unsigned long start; /* Start offset always 0 for dri2 */ | |
237 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ | |
238 | ||
239 | struct { | |
240 | dma_addr_t addr; | |
241 | struct page *page; | |
242 | } scratch; | |
243 | ||
244 | /** | |
245 | * List of objects currently involved in rendering. | |
246 | * | |
247 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 248 | * flushed, not necessarily primitives. last_read_req |
0260c420 BW |
249 | * represents when the rendering involved will be completed. |
250 | * | |
251 | * A reference is held on the buffer while on this list. | |
252 | */ | |
253 | struct list_head active_list; | |
254 | ||
255 | /** | |
256 | * LRU list of objects which are not in the ringbuffer and | |
257 | * are ready to unbind, but are still in the GTT. | |
258 | * | |
97b2a6a1 | 259 | * last_read_req is NULL while an object is in this list. |
0260c420 BW |
260 | * |
261 | * A reference is not held on the buffer while on this list, | |
262 | * as merely being GTT-bound shouldn't prevent its being | |
263 | * freed, and we'll pull it off the list in the free path. | |
264 | */ | |
265 | struct list_head inactive_list; | |
266 | ||
267 | /* FIXME: Need a more generic return type */ | |
07749ef3 MT |
268 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
269 | enum i915_cache_level level, | |
270 | bool valid, u32 flags); /* Create a valid PTE */ | |
f329f5f6 DV |
271 | /* flags for pte_encode */ |
272 | #define PTE_READ_ONLY (1<<0) | |
678d96fb BW |
273 | int (*allocate_va_range)(struct i915_address_space *vm, |
274 | uint64_t start, | |
275 | uint64_t length); | |
0260c420 BW |
276 | void (*clear_range)(struct i915_address_space *vm, |
277 | uint64_t start, | |
278 | uint64_t length, | |
279 | bool use_scratch); | |
280 | void (*insert_entries)(struct i915_address_space *vm, | |
281 | struct sg_table *st, | |
282 | uint64_t start, | |
24f3a8cf | 283 | enum i915_cache_level cache_level, u32 flags); |
0260c420 | 284 | void (*cleanup)(struct i915_address_space *vm); |
777dc5bb DV |
285 | /** Unmap an object from an address space. This usually consists of |
286 | * setting the valid PTE entries to a reserved scratch page. */ | |
287 | void (*unbind_vma)(struct i915_vma *vma); | |
288 | /* Map an object into an address space with the given cache flags. */ | |
70b9f6f8 DV |
289 | int (*bind_vma)(struct i915_vma *vma, |
290 | enum i915_cache_level cache_level, | |
291 | u32 flags); | |
0260c420 BW |
292 | }; |
293 | ||
294 | /* The Graphics Translation Table is the way in which GEN hardware translates a | |
295 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
296 | * collateral associated with any va->pa translations GEN hardware also has a | |
297 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
298 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
299 | * the spec. | |
300 | */ | |
301 | struct i915_gtt { | |
302 | struct i915_address_space base; | |
303 | size_t stolen_size; /* Total size of stolen memory */ | |
304 | ||
305 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
306 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
307 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
308 | ||
309 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
310 | void __iomem *gsm; | |
311 | ||
312 | bool do_idle_maps; | |
313 | ||
314 | int mtrr; | |
315 | ||
316 | /* global gtt ops */ | |
317 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, | |
318 | size_t *stolen, phys_addr_t *mappable_base, | |
319 | unsigned long *mappable_end); | |
320 | }; | |
321 | ||
322 | struct i915_hw_ppgtt { | |
323 | struct i915_address_space base; | |
324 | struct kref ref; | |
325 | struct drm_mm_node node; | |
563222a7 | 326 | unsigned long pd_dirty_rings; |
d7b3de91 | 327 | union { |
ec565b3c MT |
328 | struct i915_page_directory_pointer pdp; |
329 | struct i915_page_directory pd; | |
d7b3de91 | 330 | }; |
0260c420 | 331 | |
ec565b3c | 332 | struct i915_page_table *scratch_pt; |
7cb6d7ac | 333 | struct i915_page_directory *scratch_pd; |
4933d519 | 334 | |
4d884705 | 335 | struct drm_i915_file_private *file_priv; |
0260c420 | 336 | |
678d96fb BW |
337 | gen6_pte_t __iomem *pd_addr; |
338 | ||
0260c420 BW |
339 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
340 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, | |
6689c167 | 341 | struct intel_engine_cs *ring); |
0260c420 BW |
342 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
343 | }; | |
344 | ||
678d96fb BW |
345 | /* For each pde iterates over every pde between from start until start + length. |
346 | * If start, and start+length are not perfectly divisible, the macro will round | |
347 | * down, and up as needed. The macro modifies pde, start, and length. Dev is | |
348 | * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, | |
349 | * and length = 2G effectively iterates over every PDE in the system. | |
350 | * | |
351 | * XXX: temp is not actually needed, but it saves doing the ALIGN operation. | |
352 | */ | |
353 | #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ | |
fdc454c1 MT |
354 | for (iter = gen6_pde_index(start); \ |
355 | pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ | |
356 | iter++, \ | |
678d96fb BW |
357 | temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ |
358 | temp = min_t(unsigned, temp, length), \ | |
359 | start += temp, length -= temp) | |
360 | ||
09942c65 MT |
361 | #define gen6_for_all_pdes(pt, ppgtt, iter) \ |
362 | for (iter = 0; \ | |
363 | pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ | |
364 | iter++) | |
365 | ||
678d96fb BW |
366 | static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) |
367 | { | |
368 | const uint32_t mask = NUM_PTE(pde_shift) - 1; | |
369 | ||
370 | return (address >> PAGE_SHIFT) & mask; | |
371 | } | |
372 | ||
373 | /* Helper to counts the number of PTEs within the given length. This count | |
374 | * does not cross a page table boundary, so the max value would be | |
375 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. | |
376 | */ | |
377 | static inline uint32_t i915_pte_count(uint64_t addr, size_t length, | |
378 | uint32_t pde_shift) | |
379 | { | |
380 | const uint64_t mask = ~((1 << pde_shift) - 1); | |
381 | uint64_t end; | |
382 | ||
383 | WARN_ON(length == 0); | |
384 | WARN_ON(offset_in_page(addr|length)); | |
385 | ||
386 | end = addr + length; | |
387 | ||
388 | if ((addr & mask) != (end & mask)) | |
389 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); | |
390 | ||
391 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); | |
392 | } | |
393 | ||
394 | static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) | |
395 | { | |
396 | return (addr >> shift) & I915_PDE_MASK; | |
397 | } | |
398 | ||
399 | static inline uint32_t gen6_pte_index(uint32_t addr) | |
400 | { | |
401 | return i915_pte_index(addr, GEN6_PDE_SHIFT); | |
402 | } | |
403 | ||
404 | static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) | |
405 | { | |
406 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); | |
407 | } | |
408 | ||
409 | static inline uint32_t gen6_pde_index(uint32_t addr) | |
410 | { | |
411 | return i915_pde_index(addr, GEN6_PDE_SHIFT); | |
412 | } | |
413 | ||
9271d959 MT |
414 | /* Equivalent to the gen6 version, For each pde iterates over every pde |
415 | * between from start until start + length. On gen8+ it simply iterates | |
416 | * over every page directory entry in a page directory. | |
417 | */ | |
418 | #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ | |
419 | for (iter = gen8_pde_index(start); \ | |
420 | pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ | |
421 | iter++, \ | |
422 | temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ | |
423 | temp = min(temp, length), \ | |
424 | start += temp, length -= temp) | |
425 | ||
426 | #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ | |
427 | for (iter = gen8_pdpe_index(start); \ | |
428 | pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES; \ | |
429 | iter++, \ | |
430 | temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ | |
431 | temp = min(temp, length), \ | |
432 | start += temp, length -= temp) | |
433 | ||
434 | /* Clamp length to the next page_directory boundary */ | |
435 | static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length) | |
436 | { | |
437 | uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT); | |
438 | ||
439 | if (next_pd > (start + length)) | |
440 | return length; | |
441 | ||
442 | return next_pd - start; | |
443 | } | |
444 | ||
445 | static inline uint32_t gen8_pte_index(uint64_t address) | |
446 | { | |
447 | return i915_pte_index(address, GEN8_PDE_SHIFT); | |
448 | } | |
449 | ||
450 | static inline uint32_t gen8_pde_index(uint64_t address) | |
451 | { | |
452 | return i915_pde_index(address, GEN8_PDE_SHIFT); | |
453 | } | |
454 | ||
455 | static inline uint32_t gen8_pdpe_index(uint64_t address) | |
456 | { | |
457 | return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; | |
458 | } | |
459 | ||
460 | static inline uint32_t gen8_pml4e_index(uint64_t address) | |
461 | { | |
462 | WARN_ON(1); /* For 64B */ | |
463 | return 0; | |
464 | } | |
465 | ||
33c8819f MT |
466 | static inline size_t gen8_pte_count(uint64_t address, uint64_t length) |
467 | { | |
468 | return i915_pte_count(address, length, GEN8_PDE_SHIFT); | |
469 | } | |
470 | ||
0260c420 BW |
471 | int i915_gem_gtt_init(struct drm_device *dev); |
472 | void i915_gem_init_global_gtt(struct drm_device *dev); | |
90d0a0e8 | 473 | void i915_global_gtt_cleanup(struct drm_device *dev); |
0260c420 | 474 | |
ee960be7 DV |
475 | |
476 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); | |
82460d97 | 477 | int i915_ppgtt_init_hw(struct drm_device *dev); |
4ad2fd88 | 478 | int i915_ppgtt_init_ring(struct intel_engine_cs *ring); |
ee960be7 | 479 | void i915_ppgtt_release(struct kref *kref); |
4d884705 DV |
480 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, |
481 | struct drm_i915_file_private *fpriv); | |
ee960be7 DV |
482 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
483 | { | |
484 | if (ppgtt) | |
485 | kref_get(&ppgtt->ref); | |
486 | } | |
487 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) | |
488 | { | |
489 | if (ppgtt) | |
490 | kref_put(&ppgtt->ref, i915_ppgtt_release); | |
491 | } | |
0260c420 BW |
492 | |
493 | void i915_check_and_clear_faults(struct drm_device *dev); | |
494 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); | |
495 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
496 | ||
497 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); | |
498 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); | |
499 | ||
9abc4648 JL |
500 | static inline bool |
501 | i915_ggtt_view_equal(const struct i915_ggtt_view *a, | |
502 | const struct i915_ggtt_view *b) | |
503 | { | |
504 | if (WARN_ON(!a || !b)) | |
505 | return false; | |
506 | ||
8bd7ef16 JL |
507 | if (a->type != b->type) |
508 | return false; | |
509 | if (a->type == I915_GGTT_VIEW_PARTIAL) | |
510 | return !memcmp(&a->params, &b->params, sizeof(a->params)); | |
511 | return true; | |
9abc4648 JL |
512 | } |
513 | ||
91e6711e JL |
514 | size_t |
515 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
516 | const struct i915_ggtt_view *view); | |
517 | ||
0260c420 | 518 | #endif |