]>
Commit | Line | Data |
---|---|---|
05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
fa545cbf CW |
25 | #include <linux/prefetch.h> |
26 | ||
05235c53 CW |
27 | #include "i915_drv.h" |
28 | ||
04769652 CW |
29 | static const char *i915_fence_get_driver_name(struct fence *fence) |
30 | { | |
31 | return "i915"; | |
32 | } | |
33 | ||
34 | static const char *i915_fence_get_timeline_name(struct fence *fence) | |
35 | { | |
36 | /* Timelines are bound by eviction to a VM. However, since | |
37 | * we only have a global seqno at the moment, we only have | |
38 | * a single timeline. Note that each timeline will have | |
39 | * multiple execution contexts (fence contexts) as we allow | |
40 | * engines within a single timeline to execute in parallel. | |
41 | */ | |
42 | return "global"; | |
43 | } | |
44 | ||
45 | static bool i915_fence_signaled(struct fence *fence) | |
46 | { | |
47 | return i915_gem_request_completed(to_request(fence)); | |
48 | } | |
49 | ||
50 | static bool i915_fence_enable_signaling(struct fence *fence) | |
51 | { | |
52 | if (i915_fence_signaled(fence)) | |
53 | return false; | |
54 | ||
55 | intel_engine_enable_signaling(to_request(fence)); | |
56 | return true; | |
57 | } | |
58 | ||
59 | static signed long i915_fence_wait(struct fence *fence, | |
60 | bool interruptible, | |
61 | signed long timeout_jiffies) | |
62 | { | |
63 | s64 timeout_ns, *timeout; | |
64 | int ret; | |
65 | ||
66 | if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT) { | |
67 | timeout_ns = jiffies_to_nsecs(timeout_jiffies); | |
68 | timeout = &timeout_ns; | |
69 | } else { | |
70 | timeout = NULL; | |
71 | } | |
72 | ||
776f3236 CW |
73 | ret = i915_wait_request(to_request(fence), |
74 | interruptible, timeout, | |
75 | NO_WAITBOOST); | |
04769652 CW |
76 | if (ret == -ETIME) |
77 | return 0; | |
78 | ||
79 | if (ret < 0) | |
80 | return ret; | |
81 | ||
82 | if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT) | |
83 | timeout_jiffies = nsecs_to_jiffies(timeout_ns); | |
84 | ||
85 | return timeout_jiffies; | |
86 | } | |
87 | ||
88 | static void i915_fence_value_str(struct fence *fence, char *str, int size) | |
89 | { | |
90 | snprintf(str, size, "%u", fence->seqno); | |
91 | } | |
92 | ||
93 | static void i915_fence_timeline_value_str(struct fence *fence, char *str, | |
94 | int size) | |
95 | { | |
96 | snprintf(str, size, "%u", | |
97 | intel_engine_get_seqno(to_request(fence)->engine)); | |
98 | } | |
99 | ||
100 | static void i915_fence_release(struct fence *fence) | |
101 | { | |
102 | struct drm_i915_gem_request *req = to_request(fence); | |
103 | ||
104 | kmem_cache_free(req->i915->requests, req); | |
105 | } | |
106 | ||
107 | const struct fence_ops i915_fence_ops = { | |
108 | .get_driver_name = i915_fence_get_driver_name, | |
109 | .get_timeline_name = i915_fence_get_timeline_name, | |
110 | .enable_signaling = i915_fence_enable_signaling, | |
111 | .signaled = i915_fence_signaled, | |
112 | .wait = i915_fence_wait, | |
113 | .release = i915_fence_release, | |
114 | .fence_value_str = i915_fence_value_str, | |
115 | .timeline_value_str = i915_fence_timeline_value_str, | |
116 | }; | |
117 | ||
05235c53 CW |
118 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
119 | struct drm_file *file) | |
120 | { | |
121 | struct drm_i915_private *dev_private; | |
122 | struct drm_i915_file_private *file_priv; | |
123 | ||
124 | WARN_ON(!req || !file || req->file_priv); | |
125 | ||
126 | if (!req || !file) | |
127 | return -EINVAL; | |
128 | ||
129 | if (req->file_priv) | |
130 | return -EINVAL; | |
131 | ||
132 | dev_private = req->i915; | |
133 | file_priv = file->driver_priv; | |
134 | ||
135 | spin_lock(&file_priv->mm.lock); | |
136 | req->file_priv = file_priv; | |
137 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
138 | spin_unlock(&file_priv->mm.lock); | |
139 | ||
05235c53 CW |
140 | return 0; |
141 | } | |
142 | ||
143 | static inline void | |
144 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
145 | { | |
146 | struct drm_i915_file_private *file_priv = request->file_priv; | |
147 | ||
148 | if (!file_priv) | |
149 | return; | |
150 | ||
151 | spin_lock(&file_priv->mm.lock); | |
152 | list_del(&request->client_list); | |
153 | request->file_priv = NULL; | |
154 | spin_unlock(&file_priv->mm.lock); | |
05235c53 CW |
155 | } |
156 | ||
fa545cbf CW |
157 | void i915_gem_retire_noop(struct i915_gem_active *active, |
158 | struct drm_i915_gem_request *request) | |
159 | { | |
160 | /* Space left intentionally blank */ | |
161 | } | |
162 | ||
05235c53 CW |
163 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
164 | { | |
fa545cbf CW |
165 | struct i915_gem_active *active, *next; |
166 | ||
05235c53 | 167 | trace_i915_gem_request_retire(request); |
209b3f7e | 168 | list_del(&request->link); |
05235c53 CW |
169 | |
170 | /* We know the GPU must have read the request to have | |
171 | * sent us the seqno + interrupt, so use the position | |
172 | * of tail of the request to update the last known position | |
173 | * of the GPU head. | |
174 | * | |
175 | * Note this requires that we are always called in request | |
176 | * completion order. | |
177 | */ | |
675d9ad7 | 178 | list_del(&request->ring_link); |
1dae2dfb | 179 | request->ring->last_retired_head = request->postfix; |
05235c53 | 180 | |
fa545cbf CW |
181 | /* Walk through the active list, calling retire on each. This allows |
182 | * objects to track their GPU activity and mark themselves as idle | |
183 | * when their *last* active request is completed (updating state | |
184 | * tracking lists for eviction, active references for GEM, etc). | |
185 | * | |
186 | * As the ->retire() may free the node, we decouple it first and | |
187 | * pass along the auxiliary information (to avoid dereferencing | |
188 | * the node after the callback). | |
189 | */ | |
190 | list_for_each_entry_safe(active, next, &request->active_list, link) { | |
191 | /* In microbenchmarks or focusing upon time inside the kernel, | |
192 | * we may spend an inordinate amount of time simply handling | |
193 | * the retirement of requests and processing their callbacks. | |
194 | * Of which, this loop itself is particularly hot due to the | |
195 | * cache misses when jumping around the list of i915_gem_active. | |
196 | * So we try to keep this loop as streamlined as possible and | |
197 | * also prefetch the next i915_gem_active to try and hide | |
198 | * the likely cache miss. | |
199 | */ | |
200 | prefetchw(next); | |
201 | ||
202 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 203 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf CW |
204 | |
205 | active->retire(active, request); | |
206 | } | |
207 | ||
05235c53 CW |
208 | i915_gem_request_remove_from_client(request); |
209 | ||
210 | if (request->previous_context) { | |
211 | if (i915.enable_execlists) | |
212 | intel_lr_context_unpin(request->previous_context, | |
213 | request->engine); | |
214 | } | |
215 | ||
9a6feaf0 | 216 | i915_gem_context_put(request->ctx); |
e8a261ea | 217 | i915_gem_request_put(request); |
05235c53 CW |
218 | } |
219 | ||
220 | void i915_gem_request_retire_upto(struct drm_i915_gem_request *req) | |
221 | { | |
222 | struct intel_engine_cs *engine = req->engine; | |
223 | struct drm_i915_gem_request *tmp; | |
224 | ||
225 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
209b3f7e | 226 | GEM_BUG_ON(list_empty(&req->link)); |
05235c53 CW |
227 | |
228 | do { | |
229 | tmp = list_first_entry(&engine->request_list, | |
efdf7c06 | 230 | typeof(*tmp), link); |
05235c53 CW |
231 | |
232 | i915_gem_request_retire(tmp); | |
233 | } while (tmp != req); | |
05235c53 CW |
234 | } |
235 | ||
236 | static int i915_gem_check_wedge(unsigned int reset_counter, bool interruptible) | |
237 | { | |
238 | if (__i915_terminally_wedged(reset_counter)) | |
239 | return -EIO; | |
240 | ||
241 | if (__i915_reset_in_progress(reset_counter)) { | |
242 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
243 | * -EIO unconditionally for these. | |
244 | */ | |
245 | if (!interruptible) | |
246 | return -EIO; | |
247 | ||
248 | return -EAGAIN; | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static int i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno) | |
255 | { | |
256 | struct intel_engine_cs *engine; | |
257 | int ret; | |
258 | ||
259 | /* Carefully retire all requests without writing to the rings */ | |
260 | for_each_engine(engine, dev_priv) { | |
dcff85c8 | 261 | ret = intel_engine_idle(engine, true); |
05235c53 CW |
262 | if (ret) |
263 | return ret; | |
264 | } | |
265 | i915_gem_retire_requests(dev_priv); | |
266 | ||
267 | /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ | |
268 | if (!i915_seqno_passed(seqno, dev_priv->next_seqno)) { | |
269 | while (intel_kick_waiters(dev_priv) || | |
270 | intel_kick_signalers(dev_priv)) | |
271 | yield(); | |
272 | } | |
273 | ||
274 | /* Finally reset hw state */ | |
275 | for_each_engine(engine, dev_priv) | |
7e37f889 | 276 | intel_engine_init_seqno(engine, seqno); |
05235c53 CW |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
281 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) | |
282 | { | |
283 | struct drm_i915_private *dev_priv = to_i915(dev); | |
284 | int ret; | |
285 | ||
286 | if (seqno == 0) | |
287 | return -EINVAL; | |
288 | ||
289 | /* HWS page needs to be set less than what we | |
290 | * will inject to ring | |
291 | */ | |
292 | ret = i915_gem_init_seqno(dev_priv, seqno - 1); | |
293 | if (ret) | |
294 | return ret; | |
295 | ||
05235c53 | 296 | dev_priv->next_seqno = seqno; |
05235c53 CW |
297 | return 0; |
298 | } | |
299 | ||
300 | static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno) | |
301 | { | |
302 | /* reserve 0 for non-seqno */ | |
303 | if (unlikely(dev_priv->next_seqno == 0)) { | |
304 | int ret; | |
305 | ||
306 | ret = i915_gem_init_seqno(dev_priv, 0); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | dev_priv->next_seqno = 1; | |
311 | } | |
312 | ||
ddf07be7 | 313 | *seqno = dev_priv->next_seqno++; |
05235c53 CW |
314 | return 0; |
315 | } | |
316 | ||
8e637178 CW |
317 | /** |
318 | * i915_gem_request_alloc - allocate a request structure | |
319 | * | |
320 | * @engine: engine that we wish to issue the request on. | |
321 | * @ctx: context that the request will be associated with. | |
322 | * This can be NULL if the request is not directly related to | |
323 | * any specific user context, in which case this function will | |
324 | * choose an appropriate context to use. | |
325 | * | |
326 | * Returns a pointer to the allocated request if successful, | |
327 | * or an error code if not. | |
328 | */ | |
329 | struct drm_i915_gem_request * | |
330 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
331 | struct i915_gem_context *ctx) | |
05235c53 CW |
332 | { |
333 | struct drm_i915_private *dev_priv = engine->i915; | |
334 | unsigned int reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
335 | struct drm_i915_gem_request *req; | |
04769652 | 336 | u32 seqno; |
05235c53 CW |
337 | int ret; |
338 | ||
05235c53 CW |
339 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
340 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex | |
341 | * and restart. | |
342 | */ | |
343 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); | |
344 | if (ret) | |
8e637178 | 345 | return ERR_PTR(ret); |
05235c53 | 346 | |
9b5f4e5e | 347 | /* Move the oldest request to the slab-cache (if not in use!) */ |
2a1d7752 | 348 | req = list_first_entry_or_null(&engine->request_list, |
efdf7c06 | 349 | typeof(*req), link); |
2a1d7752 CW |
350 | if (req && i915_gem_request_completed(req)) |
351 | i915_gem_request_retire(req); | |
9b5f4e5e | 352 | |
5a198b8c CW |
353 | /* Beware: Dragons be flying overhead. |
354 | * | |
355 | * We use RCU to look up requests in flight. The lookups may | |
356 | * race with the request being allocated from the slab freelist. | |
357 | * That is the request we are writing to here, may be in the process | |
1426f715 | 358 | * of being read by __i915_gem_active_get_rcu(). As such, |
5a198b8c CW |
359 | * we have to be very careful when overwriting the contents. During |
360 | * the RCU lookup, we change chase the request->engine pointer, | |
361 | * read the request->fence.seqno and increment the reference count. | |
362 | * | |
363 | * The reference count is incremented atomically. If it is zero, | |
364 | * the lookup knows the request is unallocated and complete. Otherwise, | |
365 | * it is either still in use, or has been reallocated and reset | |
366 | * with fence_init(). This increment is safe for release as we check | |
367 | * that the request we have a reference to and matches the active | |
368 | * request. | |
369 | * | |
370 | * Before we increment the refcount, we chase the request->engine | |
371 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
372 | * that pointer to NULL and cause a crash during the lookup. If | |
373 | * we see the request is completed (based on the value of the | |
374 | * old engine and seqno), the lookup is complete and reports NULL. | |
375 | * If we decide the request is not completed (new engine or seqno), | |
376 | * then we grab a reference and double check that it is still the | |
377 | * active request - which it won't be and restart the lookup. | |
378 | * | |
379 | * Do not use kmem_cache_zalloc() here! | |
380 | */ | |
381 | req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL); | |
05235c53 | 382 | if (!req) |
8e637178 | 383 | return ERR_PTR(-ENOMEM); |
05235c53 | 384 | |
04769652 | 385 | ret = i915_gem_get_seqno(dev_priv, &seqno); |
05235c53 CW |
386 | if (ret) |
387 | goto err; | |
388 | ||
04769652 CW |
389 | spin_lock_init(&req->lock); |
390 | fence_init(&req->fence, | |
391 | &i915_fence_ops, | |
392 | &req->lock, | |
393 | engine->fence_context, | |
394 | seqno); | |
395 | ||
fa545cbf | 396 | INIT_LIST_HEAD(&req->active_list); |
05235c53 CW |
397 | req->i915 = dev_priv; |
398 | req->engine = engine; | |
9a6feaf0 | 399 | req->ctx = i915_gem_context_get(ctx); |
05235c53 | 400 | |
5a198b8c CW |
401 | /* No zalloc, must clear what we need by hand */ |
402 | req->previous_context = NULL; | |
403 | req->file_priv = NULL; | |
058d88c4 | 404 | req->batch = NULL; |
5a198b8c CW |
405 | req->elsp_submitted = 0; |
406 | ||
05235c53 CW |
407 | /* |
408 | * Reserve space in the ring buffer for all the commands required to | |
409 | * eventually emit this request. This is to guarantee that the | |
410 | * i915_add_request() call can't fail. Note that the reserve may need | |
411 | * to be redone if the request is not actually submitted straight | |
412 | * away, e.g. because a GPU scheduler has deferred it. | |
413 | */ | |
414 | req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; | |
415 | ||
416 | if (i915.enable_execlists) | |
417 | ret = intel_logical_ring_alloc_request_extras(req); | |
418 | else | |
419 | ret = intel_ring_alloc_request_extras(req); | |
420 | if (ret) | |
421 | goto err_ctx; | |
422 | ||
d045446d CW |
423 | /* Record the position of the start of the request so that |
424 | * should we detect the updated seqno part-way through the | |
425 | * GPU processing the request, we never over-estimate the | |
426 | * position of the head. | |
427 | */ | |
428 | req->head = req->ring->tail; | |
429 | ||
8e637178 | 430 | return req; |
05235c53 CW |
431 | |
432 | err_ctx: | |
9a6feaf0 | 433 | i915_gem_context_put(ctx); |
05235c53 CW |
434 | err: |
435 | kmem_cache_free(dev_priv->requests, req); | |
8e637178 | 436 | return ERR_PTR(ret); |
05235c53 CW |
437 | } |
438 | ||
439 | static void i915_gem_mark_busy(const struct intel_engine_cs *engine) | |
440 | { | |
441 | struct drm_i915_private *dev_priv = engine->i915; | |
442 | ||
443 | dev_priv->gt.active_engines |= intel_engine_flag(engine); | |
444 | if (dev_priv->gt.awake) | |
445 | return; | |
446 | ||
447 | intel_runtime_pm_get_noresume(dev_priv); | |
448 | dev_priv->gt.awake = true; | |
449 | ||
54b4f68f | 450 | intel_enable_gt_powersave(dev_priv); |
05235c53 CW |
451 | i915_update_gfx_val(dev_priv); |
452 | if (INTEL_GEN(dev_priv) >= 6) | |
453 | gen6_rps_busy(dev_priv); | |
454 | ||
455 | queue_delayed_work(dev_priv->wq, | |
456 | &dev_priv->gt.retire_work, | |
457 | round_jiffies_up_relative(HZ)); | |
458 | } | |
459 | ||
460 | /* | |
461 | * NB: This function is not allowed to fail. Doing so would mean the the | |
462 | * request is not being tracked for completion but the work itself is | |
463 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
464 | */ | |
17f298cf | 465 | void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) |
05235c53 | 466 | { |
95b2ab56 CW |
467 | struct intel_engine_cs *engine = request->engine; |
468 | struct intel_ring *ring = request->ring; | |
05235c53 CW |
469 | u32 request_start; |
470 | u32 reserved_tail; | |
471 | int ret; | |
472 | ||
05235c53 CW |
473 | /* |
474 | * To ensure that this call will not fail, space for its emissions | |
475 | * should already have been reserved in the ring buffer. Let the ring | |
476 | * know that it is time to use that space up. | |
477 | */ | |
ba76d91b | 478 | request_start = ring->tail; |
05235c53 CW |
479 | reserved_tail = request->reserved_space; |
480 | request->reserved_space = 0; | |
481 | ||
482 | /* | |
483 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
484 | * after having emitted the batchbuffer command. Hence we need to fix | |
485 | * things up similar to emitting the lazy request. The difference here | |
486 | * is that the flush _must_ happen before the next request, no matter | |
487 | * what. | |
488 | */ | |
489 | if (flush_caches) { | |
7c9cf4e3 | 490 | ret = engine->emit_flush(request, EMIT_FLUSH); |
c7fe7d25 | 491 | |
05235c53 | 492 | /* Not allowed to fail! */ |
c7fe7d25 | 493 | WARN(ret, "engine->emit_flush() failed: %d!\n", ret); |
05235c53 CW |
494 | } |
495 | ||
496 | trace_i915_gem_request_add(request); | |
497 | ||
05235c53 CW |
498 | /* Seal the request and mark it as pending execution. Note that |
499 | * we may inspect this state, without holding any locks, during | |
500 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
501 | * see a more recent value in the hws than we are tracking. | |
502 | */ | |
503 | request->emitted_jiffies = jiffies; | |
504 | request->previous_seqno = engine->last_submitted_seqno; | |
dcff85c8 CW |
505 | engine->last_submitted_seqno = request->fence.seqno; |
506 | i915_gem_active_set(&engine->last_request, request); | |
efdf7c06 | 507 | list_add_tail(&request->link, &engine->request_list); |
675d9ad7 | 508 | list_add_tail(&request->ring_link, &ring->request_list); |
05235c53 | 509 | |
d045446d | 510 | /* Record the position of the start of the breadcrumb so that |
05235c53 CW |
511 | * should we detect the updated seqno part-way through the |
512 | * GPU processing the request, we never over-estimate the | |
d045446d | 513 | * position of the ring's HEAD. |
05235c53 | 514 | */ |
ba76d91b | 515 | request->postfix = ring->tail; |
05235c53 | 516 | |
05235c53 | 517 | /* Not allowed to fail! */ |
ddd66c51 CW |
518 | ret = engine->emit_request(request); |
519 | WARN(ret, "(%s)->emit_request failed: %d!\n", engine->name, ret); | |
c5efa1ad | 520 | |
05235c53 | 521 | /* Sanity check that the reserved size was large enough. */ |
ba76d91b | 522 | ret = ring->tail - request_start; |
05235c53 | 523 | if (ret < 0) |
1dae2dfb | 524 | ret += ring->size; |
05235c53 CW |
525 | WARN_ONCE(ret > reserved_tail, |
526 | "Not enough space reserved (%d bytes) " | |
527 | "for adding the request (%d bytes)\n", | |
528 | reserved_tail, ret); | |
529 | ||
530 | i915_gem_mark_busy(engine); | |
ddd66c51 | 531 | engine->submit_request(request); |
05235c53 CW |
532 | } |
533 | ||
534 | static unsigned long local_clock_us(unsigned int *cpu) | |
535 | { | |
536 | unsigned long t; | |
537 | ||
538 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
539 | * The result and subsequent calculations are also defined in the same | |
540 | * approximate microseconds units. The principal source of timing | |
541 | * error here is from the simple truncation. | |
542 | * | |
543 | * Note that local_clock() is only defined wrt to the current CPU; | |
544 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
545 | * blocking preemption for the entire busywait, we can detect the CPU | |
546 | * switch and use that as indicator of system load and a reason to | |
547 | * stop busywaiting, see busywait_stop(). | |
548 | */ | |
549 | *cpu = get_cpu(); | |
550 | t = local_clock() >> 10; | |
551 | put_cpu(); | |
552 | ||
553 | return t; | |
554 | } | |
555 | ||
556 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
557 | { | |
558 | unsigned int this_cpu; | |
559 | ||
560 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
561 | return true; | |
562 | ||
563 | return this_cpu != cpu; | |
564 | } | |
565 | ||
566 | bool __i915_spin_request(const struct drm_i915_gem_request *req, | |
567 | int state, unsigned long timeout_us) | |
568 | { | |
569 | unsigned int cpu; | |
570 | ||
571 | /* When waiting for high frequency requests, e.g. during synchronous | |
572 | * rendering split between the CPU and GPU, the finite amount of time | |
573 | * required to set up the irq and wait upon it limits the response | |
574 | * rate. By busywaiting on the request completion for a short while we | |
575 | * can service the high frequency waits as quick as possible. However, | |
576 | * if it is a slow request, we want to sleep as quickly as possible. | |
577 | * The tradeoff between waiting and sleeping is roughly the time it | |
578 | * takes to sleep on a request, on the order of a microsecond. | |
579 | */ | |
580 | ||
581 | timeout_us += local_clock_us(&cpu); | |
582 | do { | |
583 | if (i915_gem_request_completed(req)) | |
584 | return true; | |
585 | ||
586 | if (signal_pending_state(state, current)) | |
587 | break; | |
588 | ||
589 | if (busywait_stop(timeout_us, cpu)) | |
590 | break; | |
591 | ||
592 | cpu_relax_lowlatency(); | |
593 | } while (!need_resched()); | |
594 | ||
595 | return false; | |
596 | } | |
597 | ||
598 | /** | |
776f3236 | 599 | * i915_wait_request - wait until execution of request has finished |
05235c53 CW |
600 | * @req: duh! |
601 | * @interruptible: do an interruptible wait (normally yes) | |
602 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
603 | * @rps: client to charge for RPS boosting | |
604 | * | |
605 | * Note: It is of utmost importance that the passed in seqno and reset_counter | |
606 | * values have been read by the caller in an smp safe manner. Where read-side | |
607 | * locks are involved, it is sufficient to read the reset_counter before | |
608 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
609 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
610 | * inserted. | |
611 | * | |
612 | * Returns 0 if the request was found within the alloted time. Else returns the | |
613 | * errno with remaining time filled in timeout argument. | |
614 | */ | |
776f3236 CW |
615 | int i915_wait_request(struct drm_i915_gem_request *req, |
616 | bool interruptible, | |
617 | s64 *timeout, | |
618 | struct intel_rps_client *rps) | |
05235c53 CW |
619 | { |
620 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
621 | DEFINE_WAIT(reset); | |
622 | struct intel_wait wait; | |
623 | unsigned long timeout_remain; | |
624 | int ret = 0; | |
625 | ||
626 | might_sleep(); | |
627 | ||
05235c53 CW |
628 | if (i915_gem_request_completed(req)) |
629 | return 0; | |
630 | ||
631 | timeout_remain = MAX_SCHEDULE_TIMEOUT; | |
632 | if (timeout) { | |
633 | if (WARN_ON(*timeout < 0)) | |
634 | return -EINVAL; | |
635 | ||
636 | if (*timeout == 0) | |
637 | return -ETIME; | |
638 | ||
639 | /* Record current time in case interrupted, or wedged */ | |
640 | timeout_remain = nsecs_to_jiffies_timeout(*timeout); | |
641 | *timeout += ktime_get_raw_ns(); | |
642 | } | |
643 | ||
644 | trace_i915_gem_request_wait_begin(req); | |
645 | ||
646 | /* This client is about to stall waiting for the GPU. In many cases | |
647 | * this is undesirable and limits the throughput of the system, as | |
648 | * many clients cannot continue processing user input/output whilst | |
649 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
650 | * to the GPU load and thus incurs additional latency for the client. | |
651 | * We can circumvent that by promoting the GPU frequency to maximum | |
652 | * before we wait. This makes the GPU throttle up much more quickly | |
653 | * (good for benchmarks and user experience, e.g. window animations), | |
654 | * but at a cost of spending more power processing the workload | |
655 | * (bad for battery). Not all clients even want their results | |
656 | * immediately and for them we should just let the GPU select its own | |
657 | * frequency to maximise efficiency. To prevent a single client from | |
658 | * forcing the clocks too high for the whole system, we only allow | |
659 | * each client to waitboost once in a busy period. | |
660 | */ | |
42df2714 | 661 | if (IS_RPS_CLIENT(rps) && INTEL_GEN(req->i915) >= 6) |
05235c53 CW |
662 | gen6_rps_boost(req->i915, rps, req->emitted_jiffies); |
663 | ||
437c3087 | 664 | /* Optimistic short spin before touching IRQs */ |
05235c53 CW |
665 | if (i915_spin_request(req, state, 5)) |
666 | goto complete; | |
667 | ||
668 | set_current_state(state); | |
669 | add_wait_queue(&req->i915->gpu_error.wait_queue, &reset); | |
670 | ||
04769652 | 671 | intel_wait_init(&wait, req->fence.seqno); |
05235c53 CW |
672 | if (intel_engine_add_wait(req->engine, &wait)) |
673 | /* In order to check that we haven't missed the interrupt | |
674 | * as we enabled it, we need to kick ourselves to do a | |
675 | * coherent check on the seqno before we sleep. | |
676 | */ | |
677 | goto wakeup; | |
678 | ||
679 | for (;;) { | |
680 | if (signal_pending_state(state, current)) { | |
681 | ret = -ERESTARTSYS; | |
682 | break; | |
683 | } | |
684 | ||
685 | timeout_remain = io_schedule_timeout(timeout_remain); | |
686 | if (timeout_remain == 0) { | |
687 | ret = -ETIME; | |
688 | break; | |
689 | } | |
690 | ||
691 | if (intel_wait_complete(&wait)) | |
692 | break; | |
693 | ||
694 | set_current_state(state); | |
695 | ||
696 | wakeup: | |
697 | /* Carefully check if the request is complete, giving time | |
698 | * for the seqno to be visible following the interrupt. | |
699 | * We also have to check in case we are kicked by the GPU | |
700 | * reset in order to drop the struct_mutex. | |
701 | */ | |
702 | if (__i915_request_irq_complete(req)) | |
703 | break; | |
704 | ||
705 | /* Only spin if we know the GPU is processing this request */ | |
706 | if (i915_spin_request(req, state, 2)) | |
707 | break; | |
708 | } | |
709 | remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset); | |
710 | ||
711 | intel_engine_remove_wait(req->engine, &wait); | |
712 | __set_current_state(TASK_RUNNING); | |
713 | complete: | |
714 | trace_i915_gem_request_wait_end(req); | |
715 | ||
716 | if (timeout) { | |
717 | *timeout -= ktime_get_raw_ns(); | |
718 | if (*timeout < 0) | |
719 | *timeout = 0; | |
720 | ||
721 | /* | |
722 | * Apparently ktime isn't accurate enough and occasionally has a | |
723 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
724 | * things up to make the test happy. We allow up to 1 jiffy. | |
725 | * | |
726 | * This is a regrssion from the timespec->ktime conversion. | |
727 | */ | |
728 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
729 | *timeout = 0; | |
730 | } | |
731 | ||
42df2714 CW |
732 | if (IS_RPS_USER(rps) && |
733 | req->fence.seqno == req->engine->last_submitted_seqno) { | |
05235c53 CW |
734 | /* The GPU is now idle and this client has stalled. |
735 | * Since no other client has submitted a request in the | |
736 | * meantime, assume that this client is the only one | |
737 | * supplying work to the GPU but is unable to keep that | |
738 | * work supplied because it is waiting. Since the GPU is | |
739 | * then never kept fully busy, RPS autoclocking will | |
740 | * keep the clocks relatively low, causing further delays. | |
741 | * Compensate by giving the synchronous client credit for | |
742 | * a waitboost next time. | |
743 | */ | |
744 | spin_lock(&req->i915->rps.client_lock); | |
745 | list_del_init(&rps->link); | |
746 | spin_unlock(&req->i915->rps.client_lock); | |
747 | } | |
748 | ||
749 | return ret; | |
750 | } | |
4b8de8e6 | 751 | |
0340d9fd | 752 | static void engine_retire_requests(struct intel_engine_cs *engine) |
4b8de8e6 CW |
753 | { |
754 | struct drm_i915_gem_request *request, *next; | |
755 | ||
756 | list_for_each_entry_safe(request, next, &engine->request_list, link) { | |
757 | if (!i915_gem_request_completed(request)) | |
758 | break; | |
759 | ||
760 | i915_gem_request_retire(request); | |
761 | } | |
762 | } | |
763 | ||
764 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv) | |
765 | { | |
766 | struct intel_engine_cs *engine; | |
767 | ||
768 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
769 | ||
770 | if (dev_priv->gt.active_engines == 0) | |
771 | return; | |
772 | ||
773 | GEM_BUG_ON(!dev_priv->gt.awake); | |
774 | ||
775 | for_each_engine(engine, dev_priv) { | |
0340d9fd | 776 | engine_retire_requests(engine); |
dcff85c8 | 777 | if (!intel_engine_is_active(engine)) |
4b8de8e6 CW |
778 | dev_priv->gt.active_engines &= ~intel_engine_flag(engine); |
779 | } | |
780 | ||
781 | if (dev_priv->gt.active_engines == 0) | |
782 | queue_delayed_work(dev_priv->wq, | |
783 | &dev_priv->gt.idle_work, | |
784 | msecs_to_jiffies(100)); | |
785 | } |