[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_tiling.c

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include <linux/string.h>
#include <linux/bitops.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"

/**
 * DOC: buffer object tiling
 *
 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
 * declare fence register requirements.
 *
 * In principle GEM doesn't care at all about the internal data layout of an
 * object, and hence it also doesn't care about tiling or swizzling. There's two
 * exceptions:
 *
 * - For X and Y tiling the hardware provides detilers for CPU access, so called
 *   fences. Since there's only a limited amount of them the kernel must manage
 *   these, and therefore userspace must tell the kernel the object tiling if it
 *   wants to use fences for detiling.
 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
 *   depends upon the physical page frame number. When swapping such objects the
 *   page frame number might change and the kernel must be able to fix this up
 *   and hence now the tiling. Note that on a subset of platforms with
 *   asymmetric memory channel population the swizzling pattern changes in an
 *   unknown way, and for those the kernel simply forbids swapping completely.
 *
 * Since neither of this applies for new tiling layouts on modern platforms like
 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
 * Anything else can be handled in userspace entirely without the kernel's
 * invovlement.
 */

/**
 * i915_gem_fence_size - required global GTT size for a fence
 * @i915: i915 device
 * @size: object size
 * @tiling: tiling mode
 * @stride: tiling stride
 *
 * Return the required global GTT size for a fence (view of a tiled object),
 * taking into account potential fence register mapping.
 */
u32 i915_gem_fence_size(struct drm_i915_private *i915,
			u32 size, unsigned int tiling, unsigned int stride)
{
	u32 ggtt_size;

	GEM_BUG_ON(!size);

	if (tiling == I915_TILING_NONE)
		return size;

	GEM_BUG_ON(!stride);

	if (INTEL_GEN(i915) >= 4) {
		stride *= i915_gem_tile_height(tiling);
		GEM_BUG_ON(stride & 4095);
		return roundup(size, stride);
	}

	/* Previous chips need a power-of-two fence region when tiling */
	if (IS_GEN3(i915))
		ggtt_size = 1024*1024;
	else
		ggtt_size = 512*1024;

	while (ggtt_size < size)
		ggtt_size <<= 1;

	return ggtt_size;
}

/**
 * i915_gem_fence_alignment - required global GTT alignment for a fence
 * @i915: i915 device
 * @size: object size
 * @tiling: tiling mode
 * @stride: tiling stride
 *
 * Return the required global GTT alignment for a fence (a view of a tiled
 * object), taking into account potential fence register mapping.
 */
u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
			     unsigned int tiling, unsigned int stride)
{
	GEM_BUG_ON(!size);

	/*
	 * Minimum alignment is 4k (GTT page size), but might be greater
	 * if a fence register is needed for the object.
	 */
	if (INTEL_GEN(i915) >= 4 || tiling == I915_TILING_NONE)
		return 4096;

	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
	return i915_gem_fence_size(i915, size, tiling, stride);
}

/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_i915_private *dev_priv,
	       int stride, int size, int tiling_mode)
{
	int tile_width;

	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (tiling_mode > I915_TILING_LAST)
		return false;

	if (IS_GEN2(dev_priv) ||
	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
		tile_width = 128;
	else
		tile_width = 512;

	/* check maximum stride & object size */
	/* i965+ stores the end address of the gtt mapping in the fence
	 * reg, so dont bother to check the size */
	if (INTEL_GEN(dev_priv) >= 7) {
		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
			return false;
	} else if (INTEL_GEN(dev_priv) >= 4) {
		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
			return false;
	} else {
		if (stride > 8192)
			return false;

		if (IS_GEN3(dev_priv)) {
			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
				return false;
		} else {
			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
				return false;
		}
	}

	if (stride < tile_width)
		return false;

	/* 965+ just needs multiples of tile width */
	if (INTEL_GEN(dev_priv) >= 4) {
		if (stride & (tile_width - 1))
			return false;
		return true;
	}

	/* Pre-965 needs power of two tile widths */
	if (stride & (stride - 1))
		return false;

	return true;
}

static bool i915_vma_fence_prepare(struct i915_vma *vma,
				   int tiling_mode, unsigned int stride)
{
	struct drm_i915_private *i915 = vma->vm->i915;
	u32 size, alignment;

	if (!i915_vma_is_map_and_fenceable(vma))
		return true;

	size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
	if (vma->node.size < size)
		return false;

	alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
	if (vma->node.start & (alignment - 1))
		return false;

	return true;
}

/* Make the current GTT allocation valid for the change in tiling. */
static int
i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
			      int tiling_mode, unsigned int stride)
{
	struct i915_vma *vma;
	int ret;

	if (tiling_mode == I915_TILING_NONE)
		return 0;

	list_for_each_entry(vma, &obj->vma_list, obj_link) {
		if (!i915_vma_is_ggtt(vma))
			break;

		if (i915_vma_fence_prepare(vma, tiling_mode, stride))
			continue;

		ret = i915_vma_unbind(vma);
		if (ret)
			return ret;
	}

	return 0;
}

/**
 * i915_gem_set_tiling - IOCTL handler to set tiling mode
 * @dev: DRM device
 * @data: data pointer for the ioctl
 * @file: DRM file for the ioctl call
 *
 * Sets the tiling mode of an object, returning the required swizzling of
 * bit 6 of addresses in the object.
 *
 * Called by the user via ioctl.
 *
 * Returns:
 * Zero on success, negative errno on failure.
 */
int
i915_gem_set_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_set_tiling *args = data;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct drm_i915_gem_object *obj;
	int err = 0;

	/* Make sure we don't cross-contaminate obj->tiling_and_stride */
	BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);

	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj)
		return -ENOENT;

	if (!i915_tiling_ok(dev_priv,
			    args->stride, obj->base.size, args->tiling_mode)) {
		i915_gem_object_put(obj);
		return -EINVAL;
	}

	mutex_lock(&dev->struct_mutex);
	if (obj->pin_display || obj->framebuffer_references) {
		err = -EBUSY;
		goto err;
	}

	if (args->tiling_mode == I915_TILING_NONE) {
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		args->stride = 0;
	} else {
		if (args->tiling_mode == I915_TILING_X)
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		else
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;

		/* Hide bit 17 swizzling from the user.  This prevents old Mesa
		 * from aborting the application on sw fallbacks to bit 17,
		 * and we use the pread/pwrite bit17 paths to swizzle for it.
		 * If there was a user that was relying on the swizzle
		 * information for drm_intel_bo_map()ed reads/writes this would
		 * break it, but we don't have any of those.
		 */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

		/* If we can't handle the swizzling, make it untiled. */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
			args->tiling_mode = I915_TILING_NONE;
			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
			args->stride = 0;
		}
	}

	if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
	    args->stride != i915_gem_object_get_stride(obj)) {
		/* We need to rebind the object if its current allocation
		 * no longer meets the alignment restrictions for its new
		 * tiling mode. Otherwise we can just leave it alone, but
		 * need to ensure that any fence register is updated before
		 * the next fenced (either through the GTT or by the BLT unit
		 * on older GPUs) access.
		 *
		 * After updating the tiling parameters, we then flag whether
		 * we need to update an associated fence register. Note this
		 * has to also include the unfenced register the GPU uses
		 * whilst executing a fenced command for an untiled object.
		 */

		err = i915_gem_object_fence_prepare(obj,
						    args->tiling_mode,
						    args->stride);
		if (!err) {
			struct i915_vma *vma;

			mutex_lock(&obj->mm.lock);
			if (obj->mm.pages &&
			    obj->mm.madv == I915_MADV_WILLNEED &&
			    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
				if (args->tiling_mode == I915_TILING_NONE) {
					GEM_BUG_ON(!obj->mm.quirked);
					__i915_gem_object_unpin_pages(obj);
					obj->mm.quirked = false;
				}
				if (!i915_gem_object_is_tiled(obj)) {
					GEM_BUG_ON(!obj->mm.quirked);
					__i915_gem_object_pin_pages(obj);
					obj->mm.quirked = true;
				}
			}
			mutex_unlock(&obj->mm.lock);

			list_for_each_entry(vma, &obj->vma_list, obj_link) {
				if (!i915_vma_is_ggtt(vma))
					break;

				vma->fence_size = i915_gem_fence_size(dev_priv, vma->size,
								      args->tiling_mode,
								      args->stride);
				vma->fence_alignment = i915_gem_fence_alignment(dev_priv, vma->size,
										args->tiling_mode,
										args->stride);

				if (vma->fence)
					vma->fence->dirty = true;
			}
			obj->tiling_and_stride =
				args->stride | args->tiling_mode;

			/* Force the fence to be reacquired for GTT access */
			i915_gem_release_mmap(obj);
		}
	}
	/* we have to maintain this existing ABI... */
	args->stride = i915_gem_object_get_stride(obj);
	args->tiling_mode = i915_gem_object_get_tiling(obj);

	/* Try to preallocate memory required to save swizzling on put-pages */
	if (i915_gem_object_needs_bit17_swizzle(obj)) {
		if (obj->bit_17 == NULL) {
			obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
					      sizeof(long), GFP_KERNEL);
		}
	} else {
		kfree(obj->bit_17);
		obj->bit_17 = NULL;
	}

err:
	i915_gem_object_put(obj);
	mutex_unlock(&dev->struct_mutex);

	return err;
}

/**
 * i915_gem_get_tiling - IOCTL handler to get tiling mode
 * @dev: DRM device
 * @data: data pointer for the ioctl
 * @file: DRM file for the ioctl call
 *
 * Returns the current tiling mode and required bit 6 swizzling for the object.
 *
 * Called by the user via ioctl.
 *
 * Returns:
 * Zero on success, negative errno on failure.
 */
int
i915_gem_get_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_get_tiling *args = data;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct drm_i915_gem_object *obj;
	int err = -ENOENT;

	rcu_read_lock();
	obj = i915_gem_object_lookup_rcu(file, args->handle);
	if (obj) {
		args->tiling_mode =
			READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
		err = 0;
	}
	rcu_read_unlock();
	if (unlikely(err))
		return err;

	switch (args->tiling_mode) {
	case I915_TILING_X:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		break;
	case I915_TILING_Y:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
		break;
	default:
	case I915_TILING_NONE:
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		break;
	}

	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
	else
		args->phys_swizzle_mode = args->swizzle_mode;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

	return 0;
}
Commit	Line	Data
673a394b EA	1	/*
	2	* Copyright © 2008 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*
	26	*/
	27
760285e7 DH	28	#include <linux/string.h>
	29	#include <linux/bitops.h>
	30	#include <drm/drmP.h>
	31	#include <drm/i915_drm.h>
673a394b EA	32	#include "i915_drv.h"
673a394b EA	33
3271dca4 DV	34	/**
3271dca4 DV	35	* DOC: buffer object tiling
673a394b	36	*
3271dca4 DV	37	* i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
3271dca4 DV	38	* declare fence register requirements.
673a394b	39	*
3271dca4 DV	40	* In principle GEM doesn't care at all about the internal data layout of an
	41	* object, and hence it also doesn't care about tiling or swizzling. There's two
	42	* exceptions:
673a394b	43	*
3271dca4 DV	44	* - For X and Y tiling the hardware provides detilers for CPU access, so called
	45	* fences. Since there's only a limited amount of them the kernel must manage
	46	* these, and therefore userspace must tell the kernel the object tiling if it
	47	* wants to use fences for detiling.
	48	* - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
	49	* depends upon the physical page frame number. When swapping such objects the
	50	* page frame number might change and the kernel must be able to fix this up
	51	* and hence now the tiling. Note that on a subset of platforms with
	52	* asymmetric memory channel population the swizzling pattern changes in an
	53	* unknown way, and for those the kernel simply forbids swapping completely.
673a394b	54	*
3271dca4 DV	55	* Since neither of this applies for new tiling layouts on modern platforms like
	56	* W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
	57	* Anything else can be handled in userspace entirely without the kernel's
	58	* invovlement.
673a394b EA	59	*/
673a394b EA	60
91d4e0aa CW	61	/**
	62	* i915_gem_fence_size - required global GTT size for a fence
	63	* @i915: i915 device
	64	* @size: object size
	65	* @tiling: tiling mode
	66	* @stride: tiling stride
	67	*
	68	* Return the required global GTT size for a fence (view of a tiled object),
	69	* taking into account potential fence register mapping.
	70	*/
	71	u32 i915_gem_fence_size(struct drm_i915_private *i915,
	72	u32 size, unsigned int tiling, unsigned int stride)
	73	{
	74	u32 ggtt_size;
	75
	76	GEM_BUG_ON(!size);
	77
	78	if (tiling == I915_TILING_NONE)
	79	return size;
	80
	81	GEM_BUG_ON(!stride);
	82
	83	if (INTEL_GEN(i915) >= 4) {
	84	stride *= i915_gem_tile_height(tiling);
	85	GEM_BUG_ON(stride & 4095);
	86	return roundup(size, stride);
	87	}
	88
	89	/* Previous chips need a power-of-two fence region when tiling */
	90	if (IS_GEN3(i915))
	91	ggtt_size = 1024*1024;
	92	else
	93	ggtt_size = 512*1024;
	94
	95	while (ggtt_size < size)
	96	ggtt_size <<= 1;
	97
	98	return ggtt_size;
	99	}
	100
	101	/**
	102	* i915_gem_fence_alignment - required global GTT alignment for a fence
	103	* @i915: i915 device
	104	* @size: object size
	105	* @tiling: tiling mode
	106	* @stride: tiling stride
	107	*
	108	* Return the required global GTT alignment for a fence (a view of a tiled
	109	* object), taking into account potential fence register mapping.
	110	*/
	111	u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
	112	unsigned int tiling, unsigned int stride)
	113	{
	114	GEM_BUG_ON(!size);
	115
	116	/*
	117	* Minimum alignment is 4k (GTT page size), but might be greater
	118	* if a fence register is needed for the object.
	119	*/
	120	if (INTEL_GEN(i915) >= 4 \|\| tiling == I915_TILING_NONE)
	121	return 4096;
	122
	123	/*
	124	* Previous chips need to be aligned to the size of the smallest
125	* fence register that can contain the object.
126	*/
127	return i915_gem_fence_size(i915, size, tiling, stride);
128	}
129
0f973f27	130	/* Check pitch constriants for all chips & tiling formats */
a00b10c3	131	static bool
118bb9fb TU	132	i915_tiling_ok(struct drm_i915_private *dev_priv,
118bb9fb TU	133	int stride, int size, int tiling_mode)
0f973f27	134	{
0ee537ab	135	int tile_width;
0f973f27 JB	136
	137	/* Linear is always fine */
	138	if (tiling_mode == I915_TILING_NONE)
	139	return true;
	140
deeb1519 CW	141	if (tiling_mode > I915_TILING_LAST)
	142	return false;
	143
5db94019	144	if (IS_GEN2(dev_priv) \|\|
50a0bc90	145	(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
0f973f27 JB	146	tile_width = 128;
	147	else
	148	tile_width = 512;
	149
8d7773a3	150	/* check maximum stride & object size */
3a062478 VS	151	/* i965+ stores the end address of the gtt mapping in the fence
3a062478 VS	152	* reg, so dont bother to check the size */
118bb9fb	153	if (INTEL_GEN(dev_priv) >= 7) {
3a062478 VS	154	if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
3a062478 VS	155	return false;
118bb9fb	156	} else if (INTEL_GEN(dev_priv) >= 4) {
8d7773a3 DV	157	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
8d7773a3 DV	158	return false;
a6c45cf0	159	} else {
c36a2a6d	160	if (stride > 8192)
8d7773a3	161	return false;
e76a16de	162
5db94019	163	if (IS_GEN3(dev_priv)) {
c36a2a6d DV	164	if (size > I830_FENCE_MAX_SIZE_VAL << 20)
	165	return false;
	166	} else {
	167	if (size > I830_FENCE_MAX_SIZE_VAL << 19)
	168	return false;
	169	}
8d7773a3 DV	170	}
8d7773a3 DV	171
fe48d8de VS	172	if (stride < tile_width)
	173	return false;
	174
0f973f27	175	/* 965+ just needs multiples of tile width */
118bb9fb	176	if (INTEL_GEN(dev_priv) >= 4) {
0f973f27 JB	177	if (stride & (tile_width - 1))
	178	return false;
	179	return true;
	180	}
	181
	182	/* Pre-965 needs power of two tile widths */
0f973f27 JB	183	if (stride & (stride - 1))
	184	return false;
	185
0f973f27 JB	186	return true;
	187	}
	188
5b30694b CW	189	static bool i915_vma_fence_prepare(struct i915_vma *vma,
5b30694b CW	190	int tiling_mode, unsigned int stride)
49ef5294	191	{
944397f0 CW	192	struct drm_i915_private *i915 = vma->vm->i915;
944397f0 CW	193	u32 size, alignment;
49ef5294 CW	194
	195	if (!i915_vma_is_map_and_fenceable(vma))
	196	return true;
	197
91d4e0aa	198	size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
49ef5294 CW	199	if (vma->node.size < size)
	200	return false;
	201
91d4e0aa	202	alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
944397f0	203	if (vma->node.start & (alignment - 1))
49ef5294 CW	204	return false;
	205
	206	return true;
	207	}
	208
f23eda8c CW	209	/* Make the current GTT allocation valid for the change in tiling. */
f23eda8c CW	210	static int
5b30694b CW	211	i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
5b30694b CW	212	int tiling_mode, unsigned int stride)
52dc7d32	213	{
f23eda8c	214	struct i915_vma *vma;
49ef5294	215	int ret;
52dc7d32 CW	216
52dc7d32 CW	217	if (tiling_mode == I915_TILING_NONE)
f23eda8c	218	return 0;
52dc7d32	219
49ef5294	220	list_for_each_entry(vma, &obj->vma_list, obj_link) {
944397f0 CW	221	if (!i915_vma_is_ggtt(vma))
	222	break;
	223
5b30694b	224	if (i915_vma_fence_prepare(vma, tiling_mode, stride))
49ef5294	225	continue;
a6c45cf0	226
49ef5294 CW	227	ret = i915_vma_unbind(vma);
	228	if (ret)
	229	return ret;
df153158 CW	230	}
df153158 CW	231
f23eda8c	232	return 0;
52dc7d32 CW	233	}
52dc7d32 CW	234
673a394b	235	/**
3271dca4 DV	236	* i915_gem_set_tiling - IOCTL handler to set tiling mode
	237	* @dev: DRM device
	238	* @data: data pointer for the ioctl
	239	* @file: DRM file for the ioctl call
	240	*
673a394b EA	241	* Sets the tiling mode of an object, returning the required swizzling of
673a394b EA	242	* bit 6 of addresses in the object.
3271dca4 DV	243	*
	244	* Called by the user via ioctl.
	245	*
	246	* Returns:
	247	* Zero on success, negative errno on failure.
673a394b EA	248	*/
	249	int
	250	i915_gem_set_tiling(struct drm_device dev, void data,
05394f39	251	struct drm_file *file)
673a394b EA	252	{
673a394b EA	253	struct drm_i915_gem_set_tiling *args = data;
fac5e23e	254	struct drm_i915_private *dev_priv = to_i915(dev);
05394f39	255	struct drm_i915_gem_object *obj;
f23eda8c	256	int err = 0;
673a394b	257
3e510a8e CW	258	/* Make sure we don't cross-contaminate obj->tiling_and_stride */
	259	BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
	260
03ac0642 CW	261	obj = i915_gem_object_lookup(file, args->handle);
03ac0642 CW	262	if (!obj)
bf79cb91	263	return -ENOENT;
673a394b	264
118bb9fb	265	if (!i915_tiling_ok(dev_priv,
05394f39	266	args->stride, obj->base.size, args->tiling_mode)) {
f0cd5182	267	i915_gem_object_put(obj);
0f973f27	268	return -EINVAL;
72daad40	269	}
0f973f27	270
6c31a614	271	mutex_lock(&dev->struct_mutex);
1f30a614	272	if (obj->pin_display \|\| obj->framebuffer_references) {
f23eda8c	273	err = -EBUSY;
6c31a614	274	goto err;
31770bd4 DV	275	}
31770bd4 DV	276
673a394b	277	if (args->tiling_mode == I915_TILING_NONE) {
673a394b	278	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	279	args->stride = 0;
673a394b EA	280	} else {
	281	if (args->tiling_mode == I915_TILING_X)
	282	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	283	else
	284	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
280b713b EA	285
	286	/* Hide bit 17 swizzling from the user. This prevents old Mesa
	287	* from aborting the application on sw fallbacks to bit 17,
	288	* and we use the pread/pwrite bit17 paths to swizzle for it.
	289	* If there was a user that was relying on the swizzle
	290	* information for drm_intel_bo_map()ed reads/writes this would
	291	* break it, but we don't have any of those.
	292	*/
	293	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	294	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	295	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	296	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	297
673a394b EA	298	/* If we can't handle the swizzling, make it untiled. */
	299	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
	300	args->tiling_mode = I915_TILING_NONE;
	301	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	302	args->stride = 0;
673a394b EA	303	}
673a394b EA	304	}
0f973f27	305
3e510a8e CW	306	if (args->tiling_mode != i915_gem_object_get_tiling(obj) \|\|
3e510a8e CW	307	args->stride != i915_gem_object_get_stride(obj)) {
52dc7d32 CW	308	/* We need to rebind the object if its current allocation
	309	* no longer meets the alignment restrictions for its new
	310	* tiling mode. Otherwise we can just leave it alone, but
1869b620 CW	311	* need to ensure that any fence register is updated before
	312	* the next fenced (either through the GTT or by the BLT unit
	313	* on older GPUs) access.
5d82e3e6 CW	314	*
	315	* After updating the tiling parameters, we then flag whether
	316	* we need to update an associated fence register. Note this
	317	* has to also include the unfenced register the GPU uses
	318	* whilst executing a fenced command for an untiled object.
0f973f27	319	*/
467cffba	320
5b30694b CW	321	err = i915_gem_object_fence_prepare(obj,
	322	args->tiling_mode,
	323	args->stride);
f23eda8c	324	if (!err) {
49ef5294 CW	325	struct i915_vma *vma;
49ef5294 CW	326
1233e2db	327	mutex_lock(&obj->mm.lock);
a4f5ea64 CW	328	if (obj->mm.pages &&
a4f5ea64 CW	329	obj->mm.madv == I915_MADV_WILLNEED &&
656bfa3a	330	dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
bc0629a7 CW	331	if (args->tiling_mode == I915_TILING_NONE) {
bc0629a7 CW	332	GEM_BUG_ON(!obj->mm.quirked);
a4f5ea64	333	__i915_gem_object_unpin_pages(obj);
bc0629a7 CW	334	obj->mm.quirked = false;
	335	}
	336	if (!i915_gem_object_is_tiled(obj)) {
2c3a3f44	337	GEM_BUG_ON(!obj->mm.quirked);
a4f5ea64	338	__i915_gem_object_pin_pages(obj);
bc0629a7 CW	339	obj->mm.quirked = true;
bc0629a7 CW	340	}
656bfa3a	341	}
1233e2db	342	mutex_unlock(&obj->mm.lock);
656bfa3a	343
49ef5294	344	list_for_each_entry(vma, &obj->vma_list, obj_link) {
944397f0 CW	345	if (!i915_vma_is_ggtt(vma))
	346	break;
	347
91d4e0aa CW	348	vma->fence_size = i915_gem_fence_size(dev_priv, vma->size,
	349	args->tiling_mode,
	350	args->stride);
	351	vma->fence_alignment = i915_gem_fence_alignment(dev_priv, vma->size,
	352	args->tiling_mode,
	353	args->stride);
944397f0 CW	354
	355	if (vma->fence)
	356	vma->fence->dirty = true;
49ef5294	357	}
3e510a8e CW	358	obj->tiling_and_stride =
3e510a8e CW	359	args->stride \| args->tiling_mode;
1869b620 CW	360
	361	/* Force the fence to be reacquired for GTT access */
	362	i915_gem_release_mmap(obj);
467cffba	363	}
0f973f27	364	}
467cffba	365	/* we have to maintain this existing ABI... */
3e510a8e CW	366	args->stride = i915_gem_object_get_stride(obj);
3e510a8e CW	367	args->tiling_mode = i915_gem_object_get_tiling(obj);
e9b73c67 CW	368
	369	/* Try to preallocate memory required to save swizzling on put-pages */
	370	if (i915_gem_object_needs_bit17_swizzle(obj)) {
	371	if (obj->bit_17 == NULL) {
a1e22653	372	obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
e9b73c67 CW	373	sizeof(long), GFP_KERNEL);
	374	}
	375	} else {
	376	kfree(obj->bit_17);
	377	obj->bit_17 = NULL;
	378	}
	379
6c31a614	380	err:
f8c417cd	381	i915_gem_object_put(obj);
d6873102	382	mutex_unlock(&dev->struct_mutex);
673a394b	383
f23eda8c	384	return err;
673a394b EA	385	}
	386
	387	/**
3271dca4 DV	388	* i915_gem_get_tiling - IOCTL handler to get tiling mode
	389	* @dev: DRM device
	390	* @data: data pointer for the ioctl
	391	* @file: DRM file for the ioctl call
	392	*
673a394b	393	* Returns the current tiling mode and required bit 6 swizzling for the object.
3271dca4 DV	394	*
	395	* Called by the user via ioctl.
	396	*
	397	* Returns:
	398	* Zero on success, negative errno on failure.
673a394b EA	399	*/
	400	int
	401	i915_gem_get_tiling(struct drm_device dev, void data,
05394f39	402	struct drm_file *file)
673a394b EA	403	{
673a394b EA	404	struct drm_i915_gem_get_tiling *args = data;
fac5e23e	405	struct drm_i915_private *dev_priv = to_i915(dev);
05394f39	406	struct drm_i915_gem_object *obj;
fbbd37b3 CW	407	int err = -ENOENT;
	408
	409	rcu_read_lock();
	410	obj = i915_gem_object_lookup_rcu(file, args->handle);
	411	if (obj) {
	412	args->tiling_mode =
	413	READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
	414	err = 0;
	415	}
	416	rcu_read_unlock();
	417	if (unlikely(err))
	418	return err;
673a394b	419
9ad36761	420	switch (args->tiling_mode) {
673a394b EA	421	case I915_TILING_X:
	422	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	423	break;
	424	case I915_TILING_Y:
	425	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
	426	break;
fbbd37b3	427	default:
673a394b EA	428	case I915_TILING_NONE:
	429	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	430	break;
673a394b EA	431	}
673a394b EA	432
280b713b	433	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
5eb3e5a5 CW	434	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
	435	args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
	436	else
	437	args->phys_swizzle_mode = args->swizzle_mode;
280b713b EA	438	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	439	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	440	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	441	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	442
673a394b EA	443	return 0;
673a394b EA	444	}