[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / i915_gem_tiling.c

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include "linux/string.h"
#include "linux/bitops.h"
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"

/** @file i915_gem_tiling.c
 *
 * Support for managing tiling state of buffer objects.
 *
 * The idea behind tiling is to increase cache hit rates by rearranging
 * pixel data so that a group of pixel accesses are in the same cacheline.
 * Performance improvement from doing this on the back/depth buffer are on
 * the order of 30%.
 *
 * Intel architectures make this somewhat more complicated, though, by
 * adjustments made to addressing of data when the memory is in interleaved
 * mode (matched pairs of DIMMS) to improve memory bandwidth.
 * For interleaved memory, the CPU sends every sequential 64 bytes
 * to an alternate memory channel so it can get the bandwidth from both.
 *
 * The GPU also rearranges its accesses for increased bandwidth to interleaved
 * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 * it does it a little differently, since one walks addresses not just in the
 * X direction but also Y.  So, along with alternating channels when bit
 * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 * are common to both the 915 and 965-class hardware.
 *
 * The CPU also sometimes XORs in higher bits as well, to improve
 * bandwidth doing strided access like we do so frequently in graphics.  This
 * is called "Channel XOR Randomization" in the MCH documentation.  The result
 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 * decode.
 *
 * All of this bit 6 XORing has an effect on our memory management,
 * as we need to make sure that the 3d driver can correctly address object
 * contents.
 *
 * If we don't have interleaved memory, all tiling is safe and no swizzling is
 * required.
 *
 * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 * 17 is not just a page offset, so as we page an objet out and back in,
 * individual pages in it will have different bit 17 addresses, resulting in
 * each 64 bytes being swapped with its neighbor!
 *
 * Otherwise, if interleaved, we have to tell the 3d driver what the address
 * swizzling it needs to do is, since it's writing with the CPU to the pages
 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 * to match what the GPU expects.
 */

/**
 * Detects bit 6 swizzling of address lookup between IGD access and CPU
 * access through main memory.
 */
void
i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

	if (INTEL_INFO(dev)->gen >= 6) {
		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	} else if (IS_GEN5(dev)) {
		/* On Ironlake whatever DRAM config, GPU always do
		 * same swizzling setup.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_9_10;
		swizzle_y = I915_BIT_6_SWIZZLE_9;
	} else if (IS_GEN2(dev)) {
		/* As far as we know, the 865 doesn't have these bit 6
		 * swizzling issues.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	} else if (IS_MOBILE(dev)) {
		uint32_t dcc;

		/* On mobile 9xx chipsets, channel interleave by the CPU is
		 * determined by DCC.  For single-channel, neither the CPU
		 * nor the GPU do swizzling.  For dual channel interleaved,
		 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
		 * 9 for Y tiled.  The CPU's interleave is independent, and
		 * can be based on either bit 11 (haven't seen this yet) or
		 * bit 17 (common).
		 */
		dcc = I915_READ(DCC);
		switch (dcc & DCC_ADDRESSING_MODE_MASK) {
		case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
			break;
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
			if (dcc & DCC_CHANNEL_XOR_DISABLE) {
				/* This is the base swizzling by the GPU for
				 * tiled buffers.
				 */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
				swizzle_y = I915_BIT_6_SWIZZLE_9;
			} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
				/* Bit 11 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
				swizzle_y = I915_BIT_6_SWIZZLE_9_11;
			} else {
				/* Bit 17 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
			}
			break;
		}
		if (dcc == 0xffffffff) {
			DRM_ERROR("Couldn't read from MCHBAR.  "
				  "Disabling tiling.\n");
			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
		}
	} else {
		/* The 965, G33, and newer, have a very flexible memory
		 * configuration.  It will enable dual-channel mode
		 * (interleaving) on as much memory as it can, and the GPU
		 * will additionally sometimes enable different bit 6
		 * swizzling for tiled objects from the CPU.
		 *
		 * Here's what I found on the G965:
		 *    slot fill         memory size  swizzling
		 * 0A   0B   1A   1B    1-ch   2-ch
		 * 512  0    0    0     512    0     O
		 * 512  0    512  0     16     1008  X
		 * 512  0    0    512   16     1008  X
		 * 0    512  0    512   16     1008  X
		 * 1024 1024 1024 0     2048   1024  O
		 *
		 * We could probably detect this based on either the DRB
		 * matching, which was the case for the swizzling required in
		 * the table above, or from the 1-ch value being less than
		 * the minimum size of a rank.
		 */
		if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
		} else {
			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
			swizzle_y = I915_BIT_6_SWIZZLE_9;
		}
	}

	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
}

/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
	int tile_width;

	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (IS_GEN2(dev) ||
	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
		tile_width = 128;
	else
		tile_width = 512;

	/* check maximum stride & object size */
	if (INTEL_INFO(dev)->gen >= 4) {
		/* i965 stores the end address of the gtt mapping in the fence
		 * reg, so dont bother to check the size */
		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
			return false;
	} else {
		if (stride > 8192)
			return false;

		if (IS_GEN3(dev)) {
			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
				return false;
		} else {
			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
				return false;
		}
	}

	/* 965+ just needs multiples of tile width */
	if (INTEL_INFO(dev)->gen >= 4) {
		if (stride & (tile_width - 1))
			return false;
		return true;
	}

	/* Pre-965 needs power of two tile widths */
	if (stride < tile_width)
		return false;

	if (stride & (stride - 1))
		return false;

	return true;
}

/* Is the current GTT allocation valid for the change in tiling? */
static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
{
	u32 size;

	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (INTEL_INFO(obj->base.dev)->gen >= 4)
		return true;

	if (INTEL_INFO(obj->base.dev)->gen == 3) {
		if (obj->gtt_offset & ~I915_FENCE_START_MASK)
			return false;
	} else {
		if (obj->gtt_offset & ~I830_FENCE_START_MASK)
			return false;
	}

	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
	if (INTEL_INFO(obj->base.dev)->gen == 3)
		size = 1024*1024;
	else
		size = 512*1024;

	while (size < obj->base.size)
		size <<= 1;

	if (obj->gtt_space->size != size)
		return false;

	if (obj->gtt_offset & (size - 1))
		return false;

	return true;
}

/**
 * Sets the tiling mode of an object, returning the required swizzling of
 * bit 6 of addresses in the object.
 */
int
i915_gem_set_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_set_tiling *args = data;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int ret = 0;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;

	if (!i915_tiling_ok(dev,
			    args->stride, obj->base.size, args->tiling_mode)) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return -EINVAL;
	}

	if (obj->pin_count) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return -EBUSY;
	}

	if (args->tiling_mode == I915_TILING_NONE) {
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		args->stride = 0;
	} else {
		if (args->tiling_mode == I915_TILING_X)
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		else
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;

		/* Hide bit 17 swizzling from the user.  This prevents old Mesa
		 * from aborting the application on sw fallbacks to bit 17,
		 * and we use the pread/pwrite bit17 paths to swizzle for it.
		 * If there was a user that was relying on the swizzle
		 * information for drm_intel_bo_map()ed reads/writes this would
		 * break it, but we don't have any of those.
		 */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

		/* If we can't handle the swizzling, make it untiled. */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
			args->tiling_mode = I915_TILING_NONE;
			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
			args->stride = 0;
		}
	}

	mutex_lock(&dev->struct_mutex);
	if (args->tiling_mode != obj->tiling_mode ||
	    args->stride != obj->stride) {
		/* We need to rebind the object if its current allocation
		 * no longer meets the alignment restrictions for its new
		 * tiling mode. Otherwise we can just leave it alone, but
		 * need to ensure that any fence register is cleared.
		 */
		i915_gem_release_mmap(obj);

		obj->map_and_fenceable =
			obj->gtt_space == NULL ||
			(obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
			 i915_gem_object_fence_ok(obj, args->tiling_mode));

		/* Rebind if we need a change of alignment */
		if (!obj->map_and_fenceable) {
			u32 unfenced_alignment =
				i915_gem_get_unfenced_gtt_alignment(dev,
								    obj->base.size,
								    args->tiling_mode);
			if (obj->gtt_offset & (unfenced_alignment - 1))
				ret = i915_gem_object_unbind(obj);
		}

		if (ret == 0) {
			obj->tiling_changed = true;
			obj->tiling_mode = args->tiling_mode;
			obj->stride = args->stride;
		}
	}
	/* we have to maintain this existing ABI... */
	args->stride = obj->stride;
	args->tiling_mode = obj->tiling_mode;
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);

	return ret;
}

/**
 * Returns the current tiling mode and required bit 6 swizzling for the object.
 */
int
i915_gem_get_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_get_tiling *args = data;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;

	mutex_lock(&dev->struct_mutex);

	args->tiling_mode = obj->tiling_mode;
	switch (obj->tiling_mode) {
	case I915_TILING_X:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		break;
	case I915_TILING_Y:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
		break;
	case I915_TILING_NONE:
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		break;
	default:
		DRM_ERROR("unknown tiling mode\n");
	}

	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

/**
 * Swap every 64 bytes of this page around, to account for it having a new
 * bit 17 of its physical address and therefore being interpreted differently
 * by the GPU.
 */
static void
i915_gem_swizzle_page(struct page *page)
{
	char temp[64];
	char *vaddr;
	int i;

	vaddr = kmap(page);

	for (i = 0; i < PAGE_SIZE; i += 128) {
		memcpy(temp, &vaddr[i], 64);
		memcpy(&vaddr[i], &vaddr[i + 64], 64);
		memcpy(&vaddr[i + 64], temp, 64);
	}

	kunmap(page);
}

void
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	int page_count = obj->base.size >> PAGE_SHIFT;
	int i;

	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
		return;

	if (obj->bit_17 == NULL)
		return;

	for (i = 0; i < page_count; i++) {
		char new_bit_17 = page_to_phys(obj->pages[i]) >> 17;
		if ((new_bit_17 & 0x1) !=
		    (test_bit(i, obj->bit_17) != 0)) {
			i915_gem_swizzle_page(obj->pages[i]);
			set_page_dirty(obj->pages[i]);
		}
	}
}

void
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	int page_count = obj->base.size >> PAGE_SHIFT;
	int i;

	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
		return;

	if (obj->bit_17 == NULL) {
		obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
					   sizeof(long), GFP_KERNEL);
		if (obj->bit_17 == NULL) {
			DRM_ERROR("Failed to allocate memory for bit 17 "
				  "record\n");
			return;
		}
	}

	for (i = 0; i < page_count; i++) {
		if (page_to_phys(obj->pages[i]) & (1 << 17))
			__set_bit(i, obj->bit_17);
		else
			__clear_bit(i, obj->bit_17);
	}
}
Commit	Line	Data
673a394b EA	1	/*
	2	* Copyright © 2008 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*
	26	*/
	27
280b713b EA	28	#include "linux/string.h"
280b713b EA	29	#include "linux/bitops.h"
673a394b EA	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "i915_drm.h"
	33	#include "i915_drv.h"
	34
	35	/** @file i915_gem_tiling.c
	36	*
	37	* Support for managing tiling state of buffer objects.
	38	*
	39	* The idea behind tiling is to increase cache hit rates by rearranging
	40	* pixel data so that a group of pixel accesses are in the same cacheline.
	41	* Performance improvement from doing this on the back/depth buffer are on
	42	* the order of 30%.
	43	*
	44	* Intel architectures make this somewhat more complicated, though, by
	45	* adjustments made to addressing of data when the memory is in interleaved
	46	* mode (matched pairs of DIMMS) to improve memory bandwidth.
	47	* For interleaved memory, the CPU sends every sequential 64 bytes
	48	* to an alternate memory channel so it can get the bandwidth from both.
	49	*
	50	* The GPU also rearranges its accesses for increased bandwidth to interleaved
	51	* memory, and it matches what the CPU does for non-tiled. However, when tiled
	52	* it does it a little differently, since one walks addresses not just in the
	53	* X direction but also Y. So, along with alternating channels when bit
	54	* 6 of the address flips, it also alternates when other bits flip -- Bits 9
	55	* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
	56	* are common to both the 915 and 965-class hardware.
	57	*
	58	* The CPU also sometimes XORs in higher bits as well, to improve
	59	* bandwidth doing strided access like we do so frequently in graphics. This
	60	* is called "Channel XOR Randomization" in the MCH documentation. The result
	61	* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
	62	* decode.
	63	*
	64	* All of this bit 6 XORing has an effect on our memory management,
	65	* as we need to make sure that the 3d driver can correctly address object
	66	* contents.
	67	*
	68	* If we don't have interleaved memory, all tiling is safe and no swizzling is
	69	* required.
	70	*
	71	* When bit 17 is XORed in, we simply refuse to tile at all. Bit
	72	* 17 is not just a page offset, so as we page an objet out and back in,
	73	* individual pages in it will have different bit 17 addresses, resulting in
	74	* each 64 bytes being swapped with its neighbor!
	75	*
	76	* Otherwise, if interleaved, we have to tell the 3d driver what the address
	77	* swizzling it needs to do is, since it's writing with the CPU to the pages
	78	* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
	79	* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
	80	* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
	81	* to match what the GPU expects.
	82	*/
	83
	84	/**
	85	* Detects bit 6 swizzling of address lookup between IGD access and CPU
	86	* access through main memory.
	87	*/
	88	void
	89	i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
	90	{
	91	drm_i915_private_t *dev_priv = dev->dev_private;
	92	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	93	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
94
acc83eb5 DV	95	if (INTEL_INFO(dev)->gen >= 6) {
	96	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	97	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	98	} else if (IS_GEN5(dev)) {
f2b115e6	99	/* On Ironlake whatever DRAM config, GPU always do
553bd149 ZW	100	* same swizzling setup.
	101	*/
	102	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
	103	swizzle_y = I915_BIT_6_SWIZZLE_9;
a6c45cf0	104	} else if (IS_GEN2(dev)) {
673a394b EA	105	/* As far as we know, the 865 doesn't have these bit 6
	106	* swizzling issues.
	107	*/
	108	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	109	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
568d9a8f	110	} else if (IS_MOBILE(dev)) {
673a394b EA	111	uint32_t dcc;
673a394b EA	112
568d9a8f EA	113	/* On mobile 9xx chipsets, channel interleave by the CPU is
	114	* determined by DCC. For single-channel, neither the CPU
	115	* nor the GPU do swizzling. For dual channel interleaved,
	116	* the GPU's interleave is bit 9 and 10 for X tiled, and bit
	117	* 9 for Y tiled. The CPU's interleave is independent, and
	118	* can be based on either bit 11 (haven't seen this yet) or
	119	* bit 17 (common).
673a394b EA	120	*/
	121	dcc = I915_READ(DCC);
	122	switch (dcc & DCC_ADDRESSING_MODE_MASK) {
	123	case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
	124	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
	125	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	126	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	127	break;
	128	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
568d9a8f EA	129	if (dcc & DCC_CHANNEL_XOR_DISABLE) {
	130	/* This is the base swizzling by the GPU for
	131	* tiled buffers.
	132	*/
673a394b EA	133	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
673a394b EA	134	swizzle_y = I915_BIT_6_SWIZZLE_9;
568d9a8f EA	135	} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
568d9a8f EA	136	/* Bit 11 swizzling by the CPU in addition. */
673a394b EA	137	swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
	138	swizzle_y = I915_BIT_6_SWIZZLE_9_11;
	139	} else {
568d9a8f	140	/* Bit 17 swizzling by the CPU in addition. */
280b713b EA	141	swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
280b713b EA	142	swizzle_y = I915_BIT_6_SWIZZLE_9_17;
673a394b EA	143	}
	144	break;
	145	}
	146	if (dcc == 0xffffffff) {
	147	DRM_ERROR("Couldn't read from MCHBAR. "
	148	"Disabling tiling.\n");
	149	swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	150	swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
	151	}
	152	} else {
	153	/* The 965, G33, and newer, have a very flexible memory
	154	* configuration. It will enable dual-channel mode
	155	* (interleaving) on as much memory as it can, and the GPU
	156	* will additionally sometimes enable different bit 6
	157	* swizzling for tiled objects from the CPU.
	158	*
	159	* Here's what I found on the G965:
	160	* slot fill memory size swizzling
	161	* 0A 0B 1A 1B 1-ch 2-ch
	162	* 512 0 0 0 512 0 O
	163	* 512 0 512 0 16 1008 X
	164	* 512 0 0 512 16 1008 X
	165	* 0 512 0 512 16 1008 X
	166	* 1024 1024 1024 0 2048 1024 O
	167	*
	168	* We could probably detect this based on either the DRB
	169	* matching, which was the case for the swizzling required in
	170	* the table above, or from the 1-ch value being less than
	171	* the minimum size of a rank.
	172	*/
	173	if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
	174	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	175	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	176	} else {
	177	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
	178	swizzle_y = I915_BIT_6_SWIZZLE_9;
	179	}
	180	}
	181
	182	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
	183	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
	184	}
	185
0f973f27	186	/* Check pitch constriants for all chips & tiling formats */
a00b10c3	187	static bool
0f973f27 JB	188	i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
0f973f27 JB	189	{
0ee537ab	190	int tile_width;
0f973f27 JB	191
	192	/* Linear is always fine */
	193	if (tiling_mode == I915_TILING_NONE)
	194	return true;
	195
a6c45cf0	196	if (IS_GEN2(dev) \|\|
e76a16de	197	(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
0f973f27 JB	198	tile_width = 128;
	199	else
	200	tile_width = 512;
	201
8d7773a3	202	/* check maximum stride & object size */
a6c45cf0	203	if (INTEL_INFO(dev)->gen >= 4) {
8d7773a3 DV	204	/* i965 stores the end address of the gtt mapping in the fence
	205	* reg, so dont bother to check the size */
	206	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
	207	return false;
a6c45cf0	208	} else {
c36a2a6d	209	if (stride > 8192)
8d7773a3	210	return false;
e76a16de	211
c36a2a6d DV	212	if (IS_GEN3(dev)) {
	213	if (size > I830_FENCE_MAX_SIZE_VAL << 20)
	214	return false;
	215	} else {
	216	if (size > I830_FENCE_MAX_SIZE_VAL << 19)
	217	return false;
	218	}
8d7773a3 DV	219	}
8d7773a3 DV	220
0f973f27	221	/* 965+ just needs multiples of tile width */
a6c45cf0	222	if (INTEL_INFO(dev)->gen >= 4) {
0f973f27 JB	223	if (stride & (tile_width - 1))
	224	return false;
	225	return true;
	226	}
	227
	228	/* Pre-965 needs power of two tile widths */
	229	if (stride < tile_width)
	230	return false;
	231
	232	if (stride & (stride - 1))
	233	return false;
	234
0f973f27 JB	235	return true;
	236	}
	237
a00b10c3 CW	238	/* Is the current GTT allocation valid for the change in tiling? */
a00b10c3 CW	239	static bool
05394f39	240	i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
52dc7d32	241	{
a00b10c3	242	u32 size;
52dc7d32 CW	243
	244	if (tiling_mode == I915_TILING_NONE)
	245	return true;
	246
05394f39	247	if (INTEL_INFO(obj->base.dev)->gen >= 4)
a6c45cf0 CW	248	return true;
a6c45cf0 CW	249
05394f39 CW	250	if (INTEL_INFO(obj->base.dev)->gen == 3) {
05394f39 CW	251	if (obj->gtt_offset & ~I915_FENCE_START_MASK)
df153158 CW	252	return false;
df153158 CW	253	} else {
05394f39	254	if (obj->gtt_offset & ~I830_FENCE_START_MASK)
df153158 CW	255	return false;
	256	}
	257
a00b10c3 CW	258	/*
	259	* Previous chips need to be aligned to the size of the smallest
	260	* fence register that can contain the object.
	261	*/
05394f39	262	if (INTEL_INFO(obj->base.dev)->gen == 3)
a00b10c3 CW	263	size = 1024*1024;
	264	else
	265	size = 512*1024;
	266
05394f39	267	while (size < obj->base.size)
a00b10c3 CW	268	size <<= 1;
a00b10c3 CW	269
05394f39	270	if (obj->gtt_space->size != size)
a6c45cf0 CW	271	return false;
a6c45cf0 CW	272
05394f39	273	if (obj->gtt_offset & (size - 1))
df153158	274	return false;
52dc7d32 CW	275
	276	return true;
	277	}
	278
673a394b EA	279	/**
	280	* Sets the tiling mode of an object, returning the required swizzling of
	281	* bit 6 of addresses in the object.
	282	*/
	283	int
	284	i915_gem_set_tiling(struct drm_device dev, void data,
05394f39	285	struct drm_file *file)
673a394b EA	286	{
	287	struct drm_i915_gem_set_tiling *args = data;
	288	drm_i915_private_t *dev_priv = dev->dev_private;
05394f39	289	struct drm_i915_gem_object *obj;
47ae63e0	290	int ret = 0;
673a394b	291
05394f39	292	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226	293	if (&obj->base == NULL)
bf79cb91	294	return -ENOENT;
673a394b	295
05394f39 CW	296	if (!i915_tiling_ok(dev,
	297	args->stride, obj->base.size, args->tiling_mode)) {
	298	drm_gem_object_unreference_unlocked(&obj->base);
0f973f27	299	return -EINVAL;
72daad40	300	}
0f973f27	301
05394f39 CW	302	if (obj->pin_count) {
05394f39 CW	303	drm_gem_object_unreference_unlocked(&obj->base);
31770bd4 DV	304	return -EBUSY;
	305	}
	306
673a394b	307	if (args->tiling_mode == I915_TILING_NONE) {
673a394b	308	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	309	args->stride = 0;
673a394b EA	310	} else {
	311	if (args->tiling_mode == I915_TILING_X)
	312	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	313	else
	314	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
280b713b EA	315
	316	/* Hide bit 17 swizzling from the user. This prevents old Mesa
	317	* from aborting the application on sw fallbacks to bit 17,
	318	* and we use the pread/pwrite bit17 paths to swizzle for it.
	319	* If there was a user that was relying on the swizzle
	320	* information for drm_intel_bo_map()ed reads/writes this would
	321	* break it, but we don't have any of those.
	322	*/
	323	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	324	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	325	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	326	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	327
673a394b EA	328	/* If we can't handle the swizzling, make it untiled. */
	329	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
	330	args->tiling_mode = I915_TILING_NONE;
	331	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	332	args->stride = 0;
673a394b EA	333	}
673a394b EA	334	}
0f973f27	335
52dc7d32	336	mutex_lock(&dev->struct_mutex);
05394f39 CW	337	if (args->tiling_mode != obj->tiling_mode \|\|
05394f39 CW	338	args->stride != obj->stride) {
52dc7d32 CW	339	/* We need to rebind the object if its current allocation
	340	* no longer meets the alignment restrictions for its new
	341	* tiling mode. Otherwise we can just leave it alone, but
	342	* need to ensure that any fence register is cleared.
0f973f27	343	*/
d9e86c0e	344	i915_gem_release_mmap(obj);
fe305198	345
d9e86c0e CW	346	obj->map_and_fenceable =
	347	obj->gtt_space == NULL \|\|
	348	(obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
	349	i915_gem_object_fence_ok(obj, args->tiling_mode));
52dc7d32	350
467cffba CW	351	/* Rebind if we need a change of alignment */
	352	if (!obj->map_and_fenceable) {
	353	u32 unfenced_alignment =
e28f8711 CW	354	i915_gem_get_unfenced_gtt_alignment(dev,
	355	obj->base.size,
	356	args->tiling_mode);
467cffba CW	357	if (obj->gtt_offset & (unfenced_alignment - 1))
	358	ret = i915_gem_object_unbind(obj);
	359	}
	360
	361	if (ret == 0) {
	362	obj->tiling_changed = true;
	363	obj->tiling_mode = args->tiling_mode;
	364	obj->stride = args->stride;
	365	}
0f973f27	366	}
467cffba CW	367	/* we have to maintain this existing ABI... */
	368	args->stride = obj->stride;
	369	args->tiling_mode = obj->tiling_mode;
05394f39	370	drm_gem_object_unreference(&obj->base);
d6873102	371	mutex_unlock(&dev->struct_mutex);
673a394b	372
467cffba	373	return ret;
673a394b EA	374	}
	375
	376	/**
	377	* Returns the current tiling mode and required bit 6 swizzling for the object.
	378	*/
	379	int
	380	i915_gem_get_tiling(struct drm_device dev, void data,
05394f39	381	struct drm_file *file)
673a394b EA	382	{
	383	struct drm_i915_gem_get_tiling *args = data;
	384	drm_i915_private_t *dev_priv = dev->dev_private;
05394f39	385	struct drm_i915_gem_object *obj;
673a394b	386
05394f39	387	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226	388	if (&obj->base == NULL)
bf79cb91	389	return -ENOENT;
673a394b EA	390
	391	mutex_lock(&dev->struct_mutex);
	392
05394f39 CW	393	args->tiling_mode = obj->tiling_mode;
05394f39 CW	394	switch (obj->tiling_mode) {
673a394b EA	395	case I915_TILING_X:
	396	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	397	break;
	398	case I915_TILING_Y:
	399	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
	400	break;
	401	case I915_TILING_NONE:
	402	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	403	break;
	404	default:
	405	DRM_ERROR("unknown tiling mode\n");
	406	}
	407
280b713b EA	408	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	409	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	410	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	411	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	412	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	413
05394f39	414	drm_gem_object_unreference(&obj->base);
d6873102	415	mutex_unlock(&dev->struct_mutex);
673a394b EA	416
	417	return 0;
	418	}
280b713b EA	419
	420	/**
	421	* Swap every 64 bytes of this page around, to account for it having a new
	422	* bit 17 of its physical address and therefore being interpreted differently
	423	* by the GPU.
	424	*/
dd2575ff	425	static void
280b713b EA	426	i915_gem_swizzle_page(struct page *page)
280b713b EA	427	{
dd2575ff	428	char temp[64];
280b713b EA	429	char *vaddr;
280b713b EA	430	int i;
280b713b EA	431
280b713b EA	432	vaddr = kmap(page);
280b713b EA	433
	434	for (i = 0; i < PAGE_SIZE; i += 128) {
	435	memcpy(temp, &vaddr[i], 64);
	436	memcpy(&vaddr[i], &vaddr[i + 64], 64);
	437	memcpy(&vaddr[i + 64], temp, 64);
	438	}
	439
	440	kunmap(page);
280b713b EA	441	}
	442
	443	void
05394f39	444	i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
280b713b	445	{
05394f39	446	struct drm_device *dev = obj->base.dev;
280b713b	447	drm_i915_private_t *dev_priv = dev->dev_private;
05394f39	448	int page_count = obj->base.size >> PAGE_SHIFT;
280b713b EA	449	int i;
	450
	451	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
	452	return;
	453
05394f39	454	if (obj->bit_17 == NULL)
280b713b EA	455	return;
	456
	457	for (i = 0; i < page_count; i++) {
05394f39	458	char new_bit_17 = page_to_phys(obj->pages[i]) >> 17;
280b713b	459	if ((new_bit_17 & 0x1) !=
05394f39 CW	460	(test_bit(i, obj->bit_17) != 0)) {
	461	i915_gem_swizzle_page(obj->pages[i]);
	462	set_page_dirty(obj->pages[i]);
280b713b EA	463	}
	464	}
	465	}
	466
	467	void
05394f39	468	i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
280b713b	469	{
05394f39	470	struct drm_device *dev = obj->base.dev;
280b713b	471	drm_i915_private_t *dev_priv = dev->dev_private;
05394f39	472	int page_count = obj->base.size >> PAGE_SHIFT;
280b713b EA	473	int i;
	474
	475	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
	476	return;
	477
05394f39 CW	478	if (obj->bit_17 == NULL) {
05394f39 CW	479	obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
280b713b	480	sizeof(long), GFP_KERNEL);
05394f39	481	if (obj->bit_17 == NULL) {
280b713b EA	482	DRM_ERROR("Failed to allocate memory for bit 17 "
	483	"record\n");
	484	return;
	485	}
	486	}
	487
	488	for (i = 0; i < page_count; i++) {
05394f39 CW	489	if (page_to_phys(obj->pages[i]) & (1 << 17))
05394f39 CW	490	__set_bit(i, obj->bit_17);
280b713b	491	else
05394f39	492	__clear_bit(i, obj->bit_17);
280b713b EA	493	}
280b713b EA	494	}