[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_tiling.c

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include "linux/string.h"
#include "linux/bitops.h"
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"

/** @file i915_gem_tiling.c
 *
 * Support for managing tiling state of buffer objects.
 *
 * The idea behind tiling is to increase cache hit rates by rearranging
 * pixel data so that a group of pixel accesses are in the same cacheline.
 * Performance improvement from doing this on the back/depth buffer are on
 * the order of 30%.
 *
 * Intel architectures make this somewhat more complicated, though, by
 * adjustments made to addressing of data when the memory is in interleaved
 * mode (matched pairs of DIMMS) to improve memory bandwidth.
 * For interleaved memory, the CPU sends every sequential 64 bytes
 * to an alternate memory channel so it can get the bandwidth from both.
 *
 * The GPU also rearranges its accesses for increased bandwidth to interleaved
 * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 * it does it a little differently, since one walks addresses not just in the
 * X direction but also Y.  So, along with alternating channels when bit
 * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 * are common to both the 915 and 965-class hardware.
 *
 * The CPU also sometimes XORs in higher bits as well, to improve
 * bandwidth doing strided access like we do so frequently in graphics.  This
 * is called "Channel XOR Randomization" in the MCH documentation.  The result
 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 * decode.
 *
 * All of this bit 6 XORing has an effect on our memory management,
 * as we need to make sure that the 3d driver can correctly address object
 * contents.
 *
 * If we don't have interleaved memory, all tiling is safe and no swizzling is
 * required.
 *
 * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 * 17 is not just a page offset, so as we page an objet out and back in,
 * individual pages in it will have different bit 17 addresses, resulting in
 * each 64 bytes being swapped with its neighbor!
 *
 * Otherwise, if interleaved, we have to tell the 3d driver what the address
 * swizzling it needs to do is, since it's writing with the CPU to the pages
 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 * to match what the GPU expects.
 */

/**
 * Detects bit 6 swizzling of address lookup between IGD access and CPU
 * access through main memory.
 */
void
i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

	if (!IS_I9XX(dev)) {
		/* As far as we know, the 865 doesn't have these bit 6
		 * swizzling issues.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	} else if (IS_MOBILE(dev)) {
		uint32_t dcc;

		/* On mobile 9xx chipsets, channel interleave by the CPU is
		 * determined by DCC.  For single-channel, neither the CPU
		 * nor the GPU do swizzling.  For dual channel interleaved,
		 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
		 * 9 for Y tiled.  The CPU's interleave is independent, and
		 * can be based on either bit 11 (haven't seen this yet) or
		 * bit 17 (common).
		 */
		dcc = I915_READ(DCC);
		switch (dcc & DCC_ADDRESSING_MODE_MASK) {
		case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
			break;
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
			if (dcc & DCC_CHANNEL_XOR_DISABLE) {
				/* This is the base swizzling by the GPU for
				 * tiled buffers.
				 */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
				swizzle_y = I915_BIT_6_SWIZZLE_9;
			} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
				/* Bit 11 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
				swizzle_y = I915_BIT_6_SWIZZLE_9_11;
			} else {
				/* Bit 17 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
			}
			break;
		}
		if (dcc == 0xffffffff) {
			DRM_ERROR("Couldn't read from MCHBAR.  "
				  "Disabling tiling.\n");
			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
		}
	} else {
		/* The 965, G33, and newer, have a very flexible memory
		 * configuration.  It will enable dual-channel mode
		 * (interleaving) on as much memory as it can, and the GPU
		 * will additionally sometimes enable different bit 6
		 * swizzling for tiled objects from the CPU.
		 *
		 * Here's what I found on the G965:
		 *    slot fill         memory size  swizzling
		 * 0A   0B   1A   1B    1-ch   2-ch
		 * 512  0    0    0     512    0     O
		 * 512  0    512  0     16     1008  X
		 * 512  0    0    512   16     1008  X
		 * 0    512  0    512   16     1008  X
		 * 1024 1024 1024 0     2048   1024  O
		 *
		 * We could probably detect this based on either the DRB
		 * matching, which was the case for the swizzling required in
		 * the table above, or from the 1-ch value being less than
		 * the minimum size of a rank.
		 */
		if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
		} else {
			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
			swizzle_y = I915_BIT_6_SWIZZLE_9;
		}
	}

	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
}


/**
 * Returns the size of the fence for a tiled object of the given size.
 */
static int
i915_get_fence_size(struct drm_device *dev, int size)
{
	int i;
	int start;

	if (IS_I965G(dev)) {
		/* The 965 can have fences at any page boundary. */
		return ALIGN(size, 4096);
	} else {
		/* Align the size to a power of two greater than the smallest
		 * fence size.
		 */
		if (IS_I9XX(dev))
			start = 1024 * 1024;
		else
			start = 512 * 1024;

		for (i = start; i < size; i <<= 1)
			;

		return i;
	}
}

/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
	int tile_width;

	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
		tile_width = 128;
	else
		tile_width = 512;

	/* check maximum stride & object size */
	if (IS_I965G(dev)) {
		/* i965 stores the end address of the gtt mapping in the fence
		 * reg, so dont bother to check the size */
		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
			return false;
	} else if (IS_I9XX(dev)) {
		if (stride / tile_width > I830_FENCE_MAX_PITCH_VAL ||
		    size > (I830_FENCE_MAX_SIZE_VAL << 20))
			return false;
	} else {
		if (stride / 128 > I830_FENCE_MAX_PITCH_VAL ||
		    size > (I830_FENCE_MAX_SIZE_VAL << 19))
			return false;
	}

	/* 965+ just needs multiples of tile width */
	if (IS_I965G(dev)) {
		if (stride & (tile_width - 1))
			return false;
		return true;
	}

	/* Pre-965 needs power of two tile widths */
	if (stride < tile_width)
		return false;

	if (stride & (stride - 1))
		return false;

	/* We don't handle the aperture area covered by the fence being bigger
	 * than the object size.
	 */
	if (i915_get_fence_size(dev, size) != size)
		return false;

	return true;
}

/**
 * Sets the tiling mode of an object, returning the required swizzling of
 * bit 6 of addresses in the object.
 */
int
i915_gem_set_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file_priv)
{
	struct drm_i915_gem_set_tiling *args = data;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL)
		return -EINVAL;
	obj_priv = obj->driver_private;

	if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
		drm_gem_object_unreference(obj);
		return -EINVAL;
	}

	mutex_lock(&dev->struct_mutex);

	if (args->tiling_mode == I915_TILING_NONE) {
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	} else {
		if (args->tiling_mode == I915_TILING_X)
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		else
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;

		/* Hide bit 17 swizzling from the user.  This prevents old Mesa
		 * from aborting the application on sw fallbacks to bit 17,
		 * and we use the pread/pwrite bit17 paths to swizzle for it.
		 * If there was a user that was relying on the swizzle
		 * information for drm_intel_bo_map()ed reads/writes this would
		 * break it, but we don't have any of those.
		 */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

		/* If we can't handle the swizzling, make it untiled. */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
			args->tiling_mode = I915_TILING_NONE;
			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		}
	}
	if (args->tiling_mode != obj_priv->tiling_mode) {
		int ret;

		/* Unbind the object, as switching tiling means we're
		 * switching the cache organization due to fencing, probably.
		 */
		ret = i915_gem_object_unbind(obj);
		if (ret != 0) {
			WARN(ret != -ERESTARTSYS,
			     "failed to unbind object for tiling switch");
			args->tiling_mode = obj_priv->tiling_mode;
			mutex_unlock(&dev->struct_mutex);
			drm_gem_object_unreference(obj);

			return ret;
		}
		obj_priv->tiling_mode = args->tiling_mode;
	}
	obj_priv->stride = args->stride;

	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

/**
 * Returns the current tiling mode and required bit 6 swizzling for the object.
 */
int
i915_gem_get_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file_priv)
{
	struct drm_i915_gem_get_tiling *args = data;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;

	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	if (obj == NULL)
		return -EINVAL;
	obj_priv = obj->driver_private;

	mutex_lock(&dev->struct_mutex);

	args->tiling_mode = obj_priv->tiling_mode;
	switch (obj_priv->tiling_mode) {
	case I915_TILING_X:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		break;
	case I915_TILING_Y:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
		break;
	case I915_TILING_NONE:
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		break;
	default:
		DRM_ERROR("unknown tiling mode\n");
	}

	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

	drm_gem_object_unreference(obj);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

/**
 * Swap every 64 bytes of this page around, to account for it having a new
 * bit 17 of its physical address and therefore being interpreted differently
 * by the GPU.
 */
static int
i915_gem_swizzle_page(struct page *page)
{
	char *vaddr;
	int i;
	char temp[64];

	vaddr = kmap(page);
	if (vaddr == NULL)
		return -ENOMEM;

	for (i = 0; i < PAGE_SIZE; i += 128) {
		memcpy(temp, &vaddr[i], 64);
		memcpy(&vaddr[i], &vaddr[i + 64], 64);
		memcpy(&vaddr[i + 64], temp, 64);
	}

	kunmap(page);

	return 0;
}

void
i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj_priv = obj->driver_private;
	int page_count = obj->size >> PAGE_SHIFT;
	int i;

	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
		return;

	if (obj_priv->bit_17 == NULL)
		return;

	for (i = 0; i < page_count; i++) {
		char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17;
		if ((new_bit_17 & 0x1) !=
		    (test_bit(i, obj_priv->bit_17) != 0)) {
			int ret = i915_gem_swizzle_page(obj_priv->pages[i]);
			if (ret != 0) {
				DRM_ERROR("Failed to swizzle page\n");
				return;
			}
			set_page_dirty(obj_priv->pages[i]);
		}
	}
}

void
i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj)
{
	struct drm_device *dev = obj->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj_priv = obj->driver_private;
	int page_count = obj->size >> PAGE_SHIFT;
	int i;

	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
		return;

	if (obj_priv->bit_17 == NULL) {
		obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
					   sizeof(long), GFP_KERNEL);
		if (obj_priv->bit_17 == NULL) {
			DRM_ERROR("Failed to allocate memory for bit 17 "
				  "record\n");
			return;
		}
	}

	for (i = 0; i < page_count; i++) {
		if (page_to_phys(obj_priv->pages[i]) & (1 << 17))
			__set_bit(i, obj_priv->bit_17);
		else
			__clear_bit(i, obj_priv->bit_17);
	}
}
Commit	Line	Data
673a394b EA	1	/*
	2	* Copyright © 2008 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*
	26	*/
	27
280b713b EA	28	#include "linux/string.h"
280b713b EA	29	#include "linux/bitops.h"
673a394b EA	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "i915_drm.h"
	33	#include "i915_drv.h"
	34
	35	/** @file i915_gem_tiling.c
	36	*
	37	* Support for managing tiling state of buffer objects.
	38	*
	39	* The idea behind tiling is to increase cache hit rates by rearranging
	40	* pixel data so that a group of pixel accesses are in the same cacheline.
	41	* Performance improvement from doing this on the back/depth buffer are on
	42	* the order of 30%.
	43	*
	44	* Intel architectures make this somewhat more complicated, though, by
	45	* adjustments made to addressing of data when the memory is in interleaved
	46	* mode (matched pairs of DIMMS) to improve memory bandwidth.
	47	* For interleaved memory, the CPU sends every sequential 64 bytes
	48	* to an alternate memory channel so it can get the bandwidth from both.
	49	*
	50	* The GPU also rearranges its accesses for increased bandwidth to interleaved
	51	* memory, and it matches what the CPU does for non-tiled. However, when tiled
	52	* it does it a little differently, since one walks addresses not just in the
	53	* X direction but also Y. So, along with alternating channels when bit
	54	* 6 of the address flips, it also alternates when other bits flip -- Bits 9
	55	* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
	56	* are common to both the 915 and 965-class hardware.
	57	*
	58	* The CPU also sometimes XORs in higher bits as well, to improve
	59	* bandwidth doing strided access like we do so frequently in graphics. This
	60	* is called "Channel XOR Randomization" in the MCH documentation. The result
	61	* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
	62	* decode.
	63	*
	64	* All of this bit 6 XORing has an effect on our memory management,
	65	* as we need to make sure that the 3d driver can correctly address object
	66	* contents.
	67	*
	68	* If we don't have interleaved memory, all tiling is safe and no swizzling is
	69	* required.
	70	*
	71	* When bit 17 is XORed in, we simply refuse to tile at all. Bit
	72	* 17 is not just a page offset, so as we page an objet out and back in,
	73	* individual pages in it will have different bit 17 addresses, resulting in
	74	* each 64 bytes being swapped with its neighbor!
	75	*
	76	* Otherwise, if interleaved, we have to tell the 3d driver what the address
	77	* swizzling it needs to do is, since it's writing with the CPU to the pages
	78	* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
	79	* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
	80	* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
	81	* to match what the GPU expects.
	82	*/
	83
	84	/**
	85	* Detects bit 6 swizzling of address lookup between IGD access and CPU
	86	* access through main memory.
	87	*/
	88	void
	89	i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
	90	{
	91	drm_i915_private_t *dev_priv = dev->dev_private;
	92	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	93	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
94
95	if (!IS_I9XX(dev)) {
96	/* As far as we know, the 865 doesn't have these bit 6
97	* swizzling issues.
98	*/
99	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
100	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
568d9a8f	101	} else if (IS_MOBILE(dev)) {
673a394b EA	102	uint32_t dcc;
673a394b EA	103
568d9a8f EA	104	/* On mobile 9xx chipsets, channel interleave by the CPU is
	105	* determined by DCC. For single-channel, neither the CPU
	106	* nor the GPU do swizzling. For dual channel interleaved,
	107	* the GPU's interleave is bit 9 and 10 for X tiled, and bit
	108	* 9 for Y tiled. The CPU's interleave is independent, and
	109	* can be based on either bit 11 (haven't seen this yet) or
	110	* bit 17 (common).
673a394b EA	111	*/
	112	dcc = I915_READ(DCC);
	113	switch (dcc & DCC_ADDRESSING_MODE_MASK) {
	114	case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
	115	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
	116	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	117	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	118	break;
	119	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
568d9a8f EA	120	if (dcc & DCC_CHANNEL_XOR_DISABLE) {
	121	/* This is the base swizzling by the GPU for
	122	* tiled buffers.
	123	*/
673a394b EA	124	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
673a394b EA	125	swizzle_y = I915_BIT_6_SWIZZLE_9;
568d9a8f EA	126	} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
568d9a8f EA	127	/* Bit 11 swizzling by the CPU in addition. */
673a394b EA	128	swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
	129	swizzle_y = I915_BIT_6_SWIZZLE_9_11;
	130	} else {
568d9a8f	131	/* Bit 17 swizzling by the CPU in addition. */
280b713b EA	132	swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
280b713b EA	133	swizzle_y = I915_BIT_6_SWIZZLE_9_17;
673a394b EA	134	}
	135	break;
	136	}
	137	if (dcc == 0xffffffff) {
	138	DRM_ERROR("Couldn't read from MCHBAR. "
	139	"Disabling tiling.\n");
	140	swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	141	swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
	142	}
	143	} else {
	144	/* The 965, G33, and newer, have a very flexible memory
	145	* configuration. It will enable dual-channel mode
	146	* (interleaving) on as much memory as it can, and the GPU
	147	* will additionally sometimes enable different bit 6
	148	* swizzling for tiled objects from the CPU.
	149	*
	150	* Here's what I found on the G965:
	151	* slot fill memory size swizzling
	152	* 0A 0B 1A 1B 1-ch 2-ch
	153	* 512 0 0 0 512 0 O
	154	* 512 0 512 0 16 1008 X
	155	* 512 0 0 512 16 1008 X
	156	* 0 512 0 512 16 1008 X
	157	* 1024 1024 1024 0 2048 1024 O
	158	*
	159	* We could probably detect this based on either the DRB
	160	* matching, which was the case for the swizzling required in
	161	* the table above, or from the 1-ch value being less than
	162	* the minimum size of a rank.
	163	*/
	164	if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
	165	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	166	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	167	} else {
	168	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
	169	swizzle_y = I915_BIT_6_SWIZZLE_9;
	170	}
	171	}
	172
	173	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
	174	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
	175	}
	176
0f973f27 JB	177
	178	/**
	179	* Returns the size of the fence for a tiled object of the given size.
	180	*/
	181	static int
	182	i915_get_fence_size(struct drm_device *dev, int size)
	183	{
	184	int i;
	185	int start;
	186
	187	if (IS_I965G(dev)) {
	188	/* The 965 can have fences at any page boundary. */
	189	return ALIGN(size, 4096);
	190	} else {
	191	/* Align the size to a power of two greater than the smallest
	192	* fence size.
	193	*/
	194	if (IS_I9XX(dev))
	195	start = 1024 * 1024;
	196	else
	197	start = 512 * 1024;
	198
	199	for (i = start; i < size; i <<= 1)
	200	;
	201
	202	return i;
	203	}
	204	}
	205
	206	/* Check pitch constriants for all chips & tiling formats */
	207	static bool
	208	i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
	209	{
	210	int tile_width;
	211
	212	/* Linear is always fine */
	213	if (tiling_mode == I915_TILING_NONE)
	214	return true;
	215
	216	if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
	217	tile_width = 128;
	218	else
	219	tile_width = 512;
	220
8d7773a3 DV	221	/* check maximum stride & object size */
	222	if (IS_I965G(dev)) {
	223	/* i965 stores the end address of the gtt mapping in the fence
	224	* reg, so dont bother to check the size */
	225	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
	226	return false;
	227	} else if (IS_I9XX(dev)) {
	228	if (stride / tile_width > I830_FENCE_MAX_PITCH_VAL \|\|
	229	size > (I830_FENCE_MAX_SIZE_VAL << 20))
	230	return false;
	231	} else {
	232	if (stride / 128 > I830_FENCE_MAX_PITCH_VAL \|\|
	233	size > (I830_FENCE_MAX_SIZE_VAL << 19))
	234	return false;
	235	}
	236
0f973f27 JB	237	/* 965+ just needs multiples of tile width */
	238	if (IS_I965G(dev)) {
	239	if (stride & (tile_width - 1))
	240	return false;
	241	return true;
	242	}
	243
	244	/* Pre-965 needs power of two tile widths */
	245	if (stride < tile_width)
	246	return false;
	247
	248	if (stride & (stride - 1))
	249	return false;
	250
	251	/* We don't handle the aperture area covered by the fence being bigger
	252	* than the object size.
	253	*/
	254	if (i915_get_fence_size(dev, size) != size)
	255	return false;
	256
	257	return true;
	258	}
	259
673a394b EA	260	/**
	261	* Sets the tiling mode of an object, returning the required swizzling of
	262	* bit 6 of addresses in the object.
	263	*/
	264	int
	265	i915_gem_set_tiling(struct drm_device dev, void data,
	266	struct drm_file *file_priv)
	267	{
	268	struct drm_i915_gem_set_tiling *args = data;
	269	drm_i915_private_t *dev_priv = dev->dev_private;
	270	struct drm_gem_object *obj;
	271	struct drm_i915_gem_object *obj_priv;
	272
	273	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	274	if (obj == NULL)
	275	return -EINVAL;
	276	obj_priv = obj->driver_private;
	277
72daad40 CW	278	if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
72daad40 CW	279	drm_gem_object_unreference(obj);
0f973f27	280	return -EINVAL;
72daad40	281	}
0f973f27	282
673a394b EA	283	mutex_lock(&dev->struct_mutex);
	284
	285	if (args->tiling_mode == I915_TILING_NONE) {
673a394b EA	286	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	287	} else {
	288	if (args->tiling_mode == I915_TILING_X)
	289	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	290	else
	291	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
280b713b EA	292
	293	/* Hide bit 17 swizzling from the user. This prevents old Mesa
	294	* from aborting the application on sw fallbacks to bit 17,
	295	* and we use the pread/pwrite bit17 paths to swizzle for it.
	296	* If there was a user that was relying on the swizzle
	297	* information for drm_intel_bo_map()ed reads/writes this would
	298	* break it, but we don't have any of those.
	299	*/
	300	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	301	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	302	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	303	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	304
673a394b EA	305	/* If we can't handle the swizzling, make it untiled. */
	306	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
	307	args->tiling_mode = I915_TILING_NONE;
	308	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	309	}
	310	}
0f973f27 JB	311	if (args->tiling_mode != obj_priv->tiling_mode) {
	312	int ret;
	313
	314	/* Unbind the object, as switching tiling means we're
	315	* switching the cache organization due to fencing, probably.
	316	*/
	317	ret = i915_gem_object_unbind(obj);
	318	if (ret != 0) {
	319	WARN(ret != -ERESTARTSYS,
	320	"failed to unbind object for tiling switch");
	321	args->tiling_mode = obj_priv->tiling_mode;
	322	mutex_unlock(&dev->struct_mutex);
72daad40	323	drm_gem_object_unreference(obj);
0f973f27 JB	324
	325	return ret;
	326	}
	327	obj_priv->tiling_mode = args->tiling_mode;
	328	}
de151cf6	329	obj_priv->stride = args->stride;
673a394b	330
673a394b	331	drm_gem_object_unreference(obj);
d6873102	332	mutex_unlock(&dev->struct_mutex);
673a394b EA	333
	334	return 0;
	335	}
	336
	337	/**
	338	* Returns the current tiling mode and required bit 6 swizzling for the object.
	339	*/
	340	int
	341	i915_gem_get_tiling(struct drm_device dev, void data,
	342	struct drm_file *file_priv)
	343	{
	344	struct drm_i915_gem_get_tiling *args = data;
	345	drm_i915_private_t *dev_priv = dev->dev_private;
	346	struct drm_gem_object *obj;
	347	struct drm_i915_gem_object *obj_priv;
	348
	349	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
	350	if (obj == NULL)
	351	return -EINVAL;
	352	obj_priv = obj->driver_private;
	353
	354	mutex_lock(&dev->struct_mutex);
	355
	356	args->tiling_mode = obj_priv->tiling_mode;
	357	switch (obj_priv->tiling_mode) {
	358	case I915_TILING_X:
	359	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	360	break;
	361	case I915_TILING_Y:
	362	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
	363	break;
	364	case I915_TILING_NONE:
	365	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	366	break;
	367	default:
	368	DRM_ERROR("unknown tiling mode\n");
	369	}
	370
280b713b EA	371	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	372	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	373	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	374	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	375	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	376
673a394b	377	drm_gem_object_unreference(obj);
d6873102	378	mutex_unlock(&dev->struct_mutex);
673a394b EA	379
	380	return 0;
	381	}
280b713b EA	382
	383	/**
	384	* Swap every 64 bytes of this page around, to account for it having a new
	385	* bit 17 of its physical address and therefore being interpreted differently
	386	* by the GPU.
	387	*/
	388	static int
	389	i915_gem_swizzle_page(struct page *page)
	390	{
	391	char *vaddr;
	392	int i;
	393	char temp[64];
	394
	395	vaddr = kmap(page);
	396	if (vaddr == NULL)
	397	return -ENOMEM;
	398
	399	for (i = 0; i < PAGE_SIZE; i += 128) {
	400	memcpy(temp, &vaddr[i], 64);
	401	memcpy(&vaddr[i], &vaddr[i + 64], 64);
	402	memcpy(&vaddr[i + 64], temp, 64);
	403	}
	404
	405	kunmap(page);
	406
	407	return 0;
	408	}
	409
	410	void
	411	i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj)
	412	{
	413	struct drm_device *dev = obj->dev;
	414	drm_i915_private_t *dev_priv = dev->dev_private;
	415	struct drm_i915_gem_object *obj_priv = obj->driver_private;
	416	int page_count = obj->size >> PAGE_SHIFT;
	417	int i;
	418
	419	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
	420	return;
	421
	422	if (obj_priv->bit_17 == NULL)
	423	return;
	424
	425	for (i = 0; i < page_count; i++) {
	426	char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17;
	427	if ((new_bit_17 & 0x1) !=
	428	(test_bit(i, obj_priv->bit_17) != 0)) {
	429	int ret = i915_gem_swizzle_page(obj_priv->pages[i]);
	430	if (ret != 0) {
	431	DRM_ERROR("Failed to swizzle page\n");
	432	return;
	433	}
	434	set_page_dirty(obj_priv->pages[i]);
	435	}
	436	}
	437	}
	438
	439	void
	440	i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj)
	441	{
	442	struct drm_device *dev = obj->dev;
	443	drm_i915_private_t *dev_priv = dev->dev_private;
	444	struct drm_i915_gem_object *obj_priv = obj->driver_private;
	445	int page_count = obj->size >> PAGE_SHIFT;
446	int i;
447
448	if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
449	return;
450
451	if (obj_priv->bit_17 == NULL) {
452	obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
453	sizeof(long), GFP_KERNEL);
454	if (obj_priv->bit_17 == NULL) {
455	DRM_ERROR("Failed to allocate memory for bit 17 "
456	"record\n");
457	return;
458	}
459	}
460
461	for (i = 0; i < page_count; i++) {
462	if (page_to_phys(obj_priv->pages[i]) & (1 << 17))
463	__set_bit(i, obj_priv->bit_17);
464	else
465	__clear_bit(i, obj_priv->bit_17);
466	}
467	}