]>
Commit | Line | Data |
---|---|---|
84734a04 MK |
1 | /* |
2 | * Copyright (c) 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * Mika Kuoppala <mika.kuoppala@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include <generated/utsrelease.h> | |
31 | #include "i915_drv.h" | |
32 | ||
33 | static const char *yesno(int v) | |
34 | { | |
35 | return v ? "yes" : "no"; | |
36 | } | |
37 | ||
38 | static const char *ring_str(int ring) | |
39 | { | |
40 | switch (ring) { | |
41 | case RCS: return "render"; | |
42 | case VCS: return "bsd"; | |
43 | case BCS: return "blt"; | |
44 | case VECS: return "vebox"; | |
845f74a7 | 45 | case VCS2: return "bsd2"; |
84734a04 MK |
46 | default: return ""; |
47 | } | |
48 | } | |
49 | ||
50 | static const char *pin_flag(int pinned) | |
51 | { | |
52 | if (pinned > 0) | |
53 | return " P"; | |
54 | else if (pinned < 0) | |
55 | return " p"; | |
56 | else | |
57 | return ""; | |
58 | } | |
59 | ||
60 | static const char *tiling_flag(int tiling) | |
61 | { | |
62 | switch (tiling) { | |
63 | default: | |
64 | case I915_TILING_NONE: return ""; | |
65 | case I915_TILING_X: return " X"; | |
66 | case I915_TILING_Y: return " Y"; | |
67 | } | |
68 | } | |
69 | ||
70 | static const char *dirty_flag(int dirty) | |
71 | { | |
72 | return dirty ? " dirty" : ""; | |
73 | } | |
74 | ||
75 | static const char *purgeable_flag(int purgeable) | |
76 | { | |
77 | return purgeable ? " purgeable" : ""; | |
78 | } | |
79 | ||
80 | static bool __i915_error_ok(struct drm_i915_error_state_buf *e) | |
81 | { | |
82 | ||
83 | if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { | |
84 | e->err = -ENOSPC; | |
85 | return false; | |
86 | } | |
87 | ||
88 | if (e->bytes == e->size - 1 || e->err) | |
89 | return false; | |
90 | ||
91 | return true; | |
92 | } | |
93 | ||
94 | static bool __i915_error_seek(struct drm_i915_error_state_buf *e, | |
95 | unsigned len) | |
96 | { | |
97 | if (e->pos + len <= e->start) { | |
98 | e->pos += len; | |
99 | return false; | |
100 | } | |
101 | ||
102 | /* First vsnprintf needs to fit in its entirety for memmove */ | |
103 | if (len >= e->size) { | |
104 | e->err = -EIO; | |
105 | return false; | |
106 | } | |
107 | ||
108 | return true; | |
109 | } | |
110 | ||
111 | static void __i915_error_advance(struct drm_i915_error_state_buf *e, | |
112 | unsigned len) | |
113 | { | |
114 | /* If this is first printf in this window, adjust it so that | |
115 | * start position matches start of the buffer | |
116 | */ | |
117 | ||
118 | if (e->pos < e->start) { | |
119 | const size_t off = e->start - e->pos; | |
120 | ||
121 | /* Should not happen but be paranoid */ | |
122 | if (off > len || e->bytes) { | |
123 | e->err = -EIO; | |
124 | return; | |
125 | } | |
126 | ||
127 | memmove(e->buf, e->buf + off, len - off); | |
128 | e->bytes = len - off; | |
129 | e->pos = e->start; | |
130 | return; | |
131 | } | |
132 | ||
133 | e->bytes += len; | |
134 | e->pos += len; | |
135 | } | |
136 | ||
137 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, | |
138 | const char *f, va_list args) | |
139 | { | |
140 | unsigned len; | |
141 | ||
142 | if (!__i915_error_ok(e)) | |
143 | return; | |
144 | ||
145 | /* Seek the first printf which is hits start position */ | |
146 | if (e->pos < e->start) { | |
e29bb4eb CW |
147 | va_list tmp; |
148 | ||
149 | va_copy(tmp, args); | |
1d2cb9a5 MK |
150 | len = vsnprintf(NULL, 0, f, tmp); |
151 | va_end(tmp); | |
152 | ||
153 | if (!__i915_error_seek(e, len)) | |
84734a04 MK |
154 | return; |
155 | } | |
156 | ||
157 | len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); | |
158 | if (len >= e->size - e->bytes) | |
159 | len = e->size - e->bytes - 1; | |
160 | ||
161 | __i915_error_advance(e, len); | |
162 | } | |
163 | ||
164 | static void i915_error_puts(struct drm_i915_error_state_buf *e, | |
165 | const char *str) | |
166 | { | |
167 | unsigned len; | |
168 | ||
169 | if (!__i915_error_ok(e)) | |
170 | return; | |
171 | ||
172 | len = strlen(str); | |
173 | ||
174 | /* Seek the first printf which is hits start position */ | |
175 | if (e->pos < e->start) { | |
176 | if (!__i915_error_seek(e, len)) | |
177 | return; | |
178 | } | |
179 | ||
180 | if (len >= e->size - e->bytes) | |
181 | len = e->size - e->bytes - 1; | |
182 | memcpy(e->buf + e->bytes, str, len); | |
183 | ||
184 | __i915_error_advance(e, len); | |
185 | } | |
186 | ||
187 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
188 | #define err_puts(e, s) i915_error_puts(e, s) | |
189 | ||
190 | static void print_error_buffers(struct drm_i915_error_state_buf *m, | |
191 | const char *name, | |
192 | struct drm_i915_error_buffer *err, | |
193 | int count) | |
194 | { | |
3a448734 | 195 | err_printf(m, " %s [%d]:\n", name, count); |
84734a04 MK |
196 | |
197 | while (count--) { | |
3a448734 | 198 | err_printf(m, " %08x %8u %02x %02x %x %x", |
84734a04 MK |
199 | err->gtt_offset, |
200 | err->size, | |
201 | err->read_domains, | |
202 | err->write_domain, | |
203 | err->rseqno, err->wseqno); | |
204 | err_puts(m, pin_flag(err->pinned)); | |
205 | err_puts(m, tiling_flag(err->tiling)); | |
206 | err_puts(m, dirty_flag(err->dirty)); | |
207 | err_puts(m, purgeable_flag(err->purgeable)); | |
5cc9ed4b | 208 | err_puts(m, err->userptr ? " userptr" : ""); |
84734a04 MK |
209 | err_puts(m, err->ring != -1 ? " " : ""); |
210 | err_puts(m, ring_str(err->ring)); | |
0a4cd7c8 | 211 | err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); |
84734a04 MK |
212 | |
213 | if (err->name) | |
214 | err_printf(m, " (name: %d)", err->name); | |
215 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
216 | err_printf(m, " (fence: %d)", err->fence_reg); | |
217 | ||
218 | err_puts(m, "\n"); | |
219 | err++; | |
220 | } | |
221 | } | |
222 | ||
da661464 MK |
223 | static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) |
224 | { | |
225 | switch (a) { | |
226 | case HANGCHECK_IDLE: | |
227 | return "idle"; | |
228 | case HANGCHECK_WAIT: | |
229 | return "wait"; | |
230 | case HANGCHECK_ACTIVE: | |
231 | return "active"; | |
f260fe7b MK |
232 | case HANGCHECK_ACTIVE_LOOP: |
233 | return "active (loop)"; | |
da661464 MK |
234 | case HANGCHECK_KICK: |
235 | return "kick"; | |
236 | case HANGCHECK_HUNG: | |
237 | return "hung"; | |
238 | } | |
239 | ||
240 | return "unknown"; | |
241 | } | |
242 | ||
84734a04 MK |
243 | static void i915_ring_error_state(struct drm_i915_error_state_buf *m, |
244 | struct drm_device *dev, | |
362b8af7 | 245 | struct drm_i915_error_ring *ring) |
84734a04 | 246 | { |
362b8af7 | 247 | if (!ring->valid) |
372fbb8e CW |
248 | return; |
249 | ||
362b8af7 BW |
250 | err_printf(m, " HEAD: 0x%08x\n", ring->head); |
251 | err_printf(m, " TAIL: 0x%08x\n", ring->tail); | |
252 | err_printf(m, " CTL: 0x%08x\n", ring->ctl); | |
253 | err_printf(m, " HWS: 0x%08x\n", ring->hws); | |
e3243d16 | 254 | err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); |
362b8af7 BW |
255 | err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); |
256 | err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); | |
257 | err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); | |
3dda20a9 | 258 | if (INTEL_INFO(dev)->gen >= 4) { |
e3243d16 | 259 | err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); |
362b8af7 BW |
260 | err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); |
261 | err_printf(m, " INSTPS: 0x%08x\n", ring->instps); | |
3dda20a9 | 262 | } |
362b8af7 | 263 | err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); |
13ffadd1 BW |
264 | err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), |
265 | lower_32_bits(ring->faddr)); | |
84734a04 | 266 | if (INTEL_INFO(dev)->gen >= 6) { |
362b8af7 BW |
267 | err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); |
268 | err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); | |
84734a04 | 269 | err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", |
362b8af7 BW |
270 | ring->semaphore_mboxes[0], |
271 | ring->semaphore_seqno[0]); | |
84734a04 | 272 | err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", |
362b8af7 BW |
273 | ring->semaphore_mboxes[1], |
274 | ring->semaphore_seqno[1]); | |
4e5aabfd BW |
275 | if (HAS_VEBOX(dev)) { |
276 | err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", | |
362b8af7 BW |
277 | ring->semaphore_mboxes[2], |
278 | ring->semaphore_seqno[2]); | |
4e5aabfd | 279 | } |
84734a04 | 280 | } |
6c7a01ec BW |
281 | if (USES_PPGTT(dev)) { |
282 | err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); | |
283 | ||
284 | if (INTEL_INFO(dev)->gen >= 8) { | |
285 | int i; | |
286 | for (i = 0; i < 4; i++) | |
287 | err_printf(m, " PDP%d: 0x%016llx\n", | |
288 | i, ring->vm_info.pdp[i]); | |
289 | } else { | |
290 | err_printf(m, " PP_DIR_BASE: 0x%08x\n", | |
291 | ring->vm_info.pp_dir_base); | |
292 | } | |
293 | } | |
362b8af7 BW |
294 | err_printf(m, " seqno: 0x%08x\n", ring->seqno); |
295 | err_printf(m, " waiting: %s\n", yesno(ring->waiting)); | |
296 | err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); | |
297 | err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); | |
da661464 | 298 | err_printf(m, " hangcheck: %s [%d]\n", |
362b8af7 BW |
299 | hangcheck_action_to_str(ring->hangcheck_action), |
300 | ring->hangcheck_score); | |
84734a04 MK |
301 | } |
302 | ||
303 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) | |
304 | { | |
305 | va_list args; | |
306 | ||
307 | va_start(args, f); | |
308 | i915_error_vprintf(e, f, args); | |
309 | va_end(args); | |
310 | } | |
311 | ||
ab0e7ff9 CW |
312 | static void print_error_obj(struct drm_i915_error_state_buf *m, |
313 | struct drm_i915_error_object *obj) | |
314 | { | |
315 | int page, offset, elt; | |
316 | ||
317 | for (page = offset = 0; page < obj->page_count; page++) { | |
318 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
319 | err_printf(m, "%08x : %08x\n", offset, | |
320 | obj->pages[page][elt]); | |
321 | offset += 4; | |
322 | } | |
323 | } | |
324 | } | |
325 | ||
84734a04 MK |
326 | int i915_error_state_to_str(struct drm_i915_error_state_buf *m, |
327 | const struct i915_error_state_file_priv *error_priv) | |
328 | { | |
329 | struct drm_device *dev = error_priv->dev; | |
50227e1c | 330 | struct drm_i915_private *dev_priv = dev->dev_private; |
84734a04 | 331 | struct drm_i915_error_state *error = error_priv->error; |
0ca36d78 | 332 | struct drm_i915_error_object *obj; |
ab0e7ff9 CW |
333 | int i, j, offset, elt; |
334 | int max_hangcheck_score; | |
84734a04 MK |
335 | |
336 | if (!error) { | |
337 | err_printf(m, "no error state collected\n"); | |
338 | goto out; | |
339 | } | |
340 | ||
cb383002 | 341 | err_printf(m, "%s\n", error->error_msg); |
84734a04 MK |
342 | err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
343 | error->time.tv_usec); | |
344 | err_printf(m, "Kernel: " UTS_RELEASE "\n"); | |
ab0e7ff9 CW |
345 | max_hangcheck_score = 0; |
346 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
347 | if (error->ring[i].hangcheck_score > max_hangcheck_score) | |
348 | max_hangcheck_score = error->ring[i].hangcheck_score; | |
349 | } | |
350 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
351 | if (error->ring[i].hangcheck_score == max_hangcheck_score && | |
352 | error->ring[i].pid != -1) { | |
353 | err_printf(m, "Active process (on ring %s): %s [%d]\n", | |
354 | ring_str(i), | |
355 | error->ring[i].comm, | |
356 | error->ring[i].pid); | |
357 | } | |
358 | } | |
48b031e3 | 359 | err_printf(m, "Reset count: %u\n", error->reset_count); |
62d5d69b | 360 | err_printf(m, "Suspend count: %u\n", error->suspend_count); |
ffbab09b | 361 | err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); |
84734a04 MK |
362 | err_printf(m, "EIR: 0x%08x\n", error->eir); |
363 | err_printf(m, "IER: 0x%08x\n", error->ier); | |
885ea5a8 RV |
364 | if (INTEL_INFO(dev)->gen >= 8) { |
365 | for (i = 0; i < 4; i++) | |
366 | err_printf(m, "GTIER gt %d: 0x%08x\n", i, | |
367 | error->gtier[i]); | |
368 | } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) | |
369 | err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); | |
84734a04 MK |
370 | err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
371 | err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); | |
372 | err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); | |
373 | err_printf(m, "CCID: 0x%08x\n", error->ccid); | |
094f9a54 | 374 | err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); |
84734a04 MK |
375 | |
376 | for (i = 0; i < dev_priv->num_fence_regs; i++) | |
377 | err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); | |
378 | ||
379 | for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) | |
380 | err_printf(m, " INSTDONE_%d: 0x%08x\n", i, | |
381 | error->extra_instdone[i]); | |
382 | ||
383 | if (INTEL_INFO(dev)->gen >= 6) { | |
384 | err_printf(m, "ERROR: 0x%08x\n", error->error); | |
385 | err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); | |
386 | } | |
387 | ||
388 | if (INTEL_INFO(dev)->gen == 7) | |
389 | err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); | |
390 | ||
362b8af7 BW |
391 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
392 | err_printf(m, "%s command stream:\n", ring_str(i)); | |
393 | i915_ring_error_state(m, dev, &error->ring[i]); | |
394 | } | |
84734a04 | 395 | |
3a448734 CW |
396 | for (i = 0; i < error->vm_count; i++) { |
397 | err_printf(m, "vm[%d]\n", i); | |
398 | ||
84734a04 | 399 | print_error_buffers(m, "Active", |
3a448734 CW |
400 | error->active_bo[i], |
401 | error->active_bo_count[i]); | |
84734a04 | 402 | |
84734a04 | 403 | print_error_buffers(m, "Pinned", |
3a448734 CW |
404 | error->pinned_bo[i], |
405 | error->pinned_bo_count[i]); | |
406 | } | |
84734a04 MK |
407 | |
408 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
ab0e7ff9 CW |
409 | obj = error->ring[i].batchbuffer; |
410 | if (obj) { | |
411 | err_puts(m, dev_priv->ring[i].name); | |
412 | if (error->ring[i].pid != -1) | |
413 | err_printf(m, " (submitted by %s [%d])", | |
414 | error->ring[i].comm, | |
415 | error->ring[i].pid); | |
416 | err_printf(m, " --- gtt_offset = 0x%08x\n", | |
84734a04 | 417 | obj->gtt_offset); |
ab0e7ff9 CW |
418 | print_error_obj(m, obj); |
419 | } | |
420 | ||
421 | obj = error->ring[i].wa_batchbuffer; | |
422 | if (obj) { | |
423 | err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", | |
424 | dev_priv->ring[i].name, obj->gtt_offset); | |
425 | print_error_obj(m, obj); | |
84734a04 MK |
426 | } |
427 | ||
428 | if (error->ring[i].num_requests) { | |
429 | err_printf(m, "%s --- %d requests\n", | |
430 | dev_priv->ring[i].name, | |
431 | error->ring[i].num_requests); | |
432 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
433 | err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", | |
434 | error->ring[i].requests[j].seqno, | |
435 | error->ring[i].requests[j].jiffies, | |
436 | error->ring[i].requests[j].tail); | |
437 | } | |
438 | } | |
439 | ||
440 | if ((obj = error->ring[i].ringbuffer)) { | |
441 | err_printf(m, "%s --- ringbuffer = 0x%08x\n", | |
442 | dev_priv->ring[i].name, | |
443 | obj->gtt_offset); | |
ab0e7ff9 | 444 | print_error_obj(m, obj); |
84734a04 MK |
445 | } |
446 | ||
362b8af7 | 447 | if ((obj = error->ring[i].hws_page)) { |
f3ce3821 CW |
448 | err_printf(m, "%s --- HW Status = 0x%08x\n", |
449 | dev_priv->ring[i].name, | |
450 | obj->gtt_offset); | |
451 | offset = 0; | |
452 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
453 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", | |
454 | offset, | |
455 | obj->pages[0][elt], | |
456 | obj->pages[0][elt+1], | |
457 | obj->pages[0][elt+2], | |
458 | obj->pages[0][elt+3]); | |
459 | offset += 16; | |
460 | } | |
461 | } | |
462 | ||
372fbb8e | 463 | if ((obj = error->ring[i].ctx)) { |
84734a04 MK |
464 | err_printf(m, "%s --- HW Context = 0x%08x\n", |
465 | dev_priv->ring[i].name, | |
466 | obj->gtt_offset); | |
17d36749 | 467 | print_error_obj(m, obj); |
84734a04 MK |
468 | } |
469 | } | |
470 | ||
0ca36d78 BW |
471 | if ((obj = error->semaphore_obj)) { |
472 | err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset); | |
473 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
474 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", | |
475 | elt * 4, | |
476 | obj->pages[0][elt], | |
477 | obj->pages[0][elt+1], | |
478 | obj->pages[0][elt+2], | |
479 | obj->pages[0][elt+3]); | |
480 | } | |
481 | } | |
482 | ||
84734a04 MK |
483 | if (error->overlay) |
484 | intel_overlay_print_error_state(m, error->overlay); | |
485 | ||
486 | if (error->display) | |
487 | intel_display_print_error_state(m, dev, error->display); | |
488 | ||
489 | out: | |
490 | if (m->bytes == 0 && m->err) | |
491 | return m->err; | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
496 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, | |
0a4cd7c8 | 497 | struct drm_i915_private *i915, |
84734a04 MK |
498 | size_t count, loff_t pos) |
499 | { | |
500 | memset(ebuf, 0, sizeof(*ebuf)); | |
0a4cd7c8 | 501 | ebuf->i915 = i915; |
84734a04 MK |
502 | |
503 | /* We need to have enough room to store any i915_error_state printf | |
504 | * so that we can move it to start position. | |
505 | */ | |
506 | ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; | |
507 | ebuf->buf = kmalloc(ebuf->size, | |
508 | GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); | |
509 | ||
510 | if (ebuf->buf == NULL) { | |
511 | ebuf->size = PAGE_SIZE; | |
512 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
513 | } | |
514 | ||
515 | if (ebuf->buf == NULL) { | |
516 | ebuf->size = 128; | |
517 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
518 | } | |
519 | ||
520 | if (ebuf->buf == NULL) | |
521 | return -ENOMEM; | |
522 | ||
523 | ebuf->start = pos; | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | static void i915_error_object_free(struct drm_i915_error_object *obj) | |
529 | { | |
530 | int page; | |
531 | ||
532 | if (obj == NULL) | |
533 | return; | |
534 | ||
535 | for (page = 0; page < obj->page_count; page++) | |
536 | kfree(obj->pages[page]); | |
537 | ||
538 | kfree(obj); | |
539 | } | |
540 | ||
541 | static void i915_error_state_free(struct kref *error_ref) | |
542 | { | |
543 | struct drm_i915_error_state *error = container_of(error_ref, | |
544 | typeof(*error), ref); | |
545 | int i; | |
546 | ||
547 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
548 | i915_error_object_free(error->ring[i].batchbuffer); | |
549 | i915_error_object_free(error->ring[i].ringbuffer); | |
362b8af7 | 550 | i915_error_object_free(error->ring[i].hws_page); |
84734a04 MK |
551 | i915_error_object_free(error->ring[i].ctx); |
552 | kfree(error->ring[i].requests); | |
553 | } | |
554 | ||
0ca36d78 | 555 | i915_error_object_free(error->semaphore_obj); |
84734a04 MK |
556 | kfree(error->active_bo); |
557 | kfree(error->overlay); | |
558 | kfree(error->display); | |
559 | kfree(error); | |
560 | } | |
561 | ||
562 | static struct drm_i915_error_object * | |
8ae62dc6 CW |
563 | i915_error_object_create(struct drm_i915_private *dev_priv, |
564 | struct drm_i915_gem_object *src, | |
565 | struct i915_address_space *vm) | |
84734a04 MK |
566 | { |
567 | struct drm_i915_error_object *dst; | |
aff43766 | 568 | struct i915_vma *vma = NULL; |
8ae62dc6 | 569 | int num_pages; |
b3c3f5e6 CW |
570 | bool use_ggtt; |
571 | int i = 0; | |
84734a04 MK |
572 | u32 reloc_offset; |
573 | ||
574 | if (src == NULL || src->pages == NULL) | |
575 | return NULL; | |
576 | ||
8ae62dc6 CW |
577 | num_pages = src->base.size >> PAGE_SHIFT; |
578 | ||
84734a04 MK |
579 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); |
580 | if (dst == NULL) | |
581 | return NULL; | |
582 | ||
87a01e82 CW |
583 | if (i915_gem_obj_bound(src, vm)) |
584 | dst->gtt_offset = i915_gem_obj_offset(src, vm); | |
585 | else | |
586 | dst->gtt_offset = -1; | |
b3c3f5e6 CW |
587 | |
588 | reloc_offset = dst->gtt_offset; | |
aff43766 TU |
589 | if (i915_is_ggtt(vm)) |
590 | vma = i915_gem_obj_to_ggtt(src); | |
b3c3f5e6 | 591 | use_ggtt = (src->cache_level == I915_CACHE_NONE && |
aff43766 TU |
592 | vma && (vma->bound & GLOBAL_BIND) && |
593 | reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end); | |
b3c3f5e6 CW |
594 | |
595 | /* Cannot access stolen address directly, try to use the aperture */ | |
596 | if (src->stolen) { | |
597 | use_ggtt = true; | |
598 | ||
aff43766 | 599 | if (!(vma && vma->bound & GLOBAL_BIND)) |
b3c3f5e6 CW |
600 | goto unwind; |
601 | ||
602 | reloc_offset = i915_gem_obj_ggtt_offset(src); | |
603 | if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end) | |
604 | goto unwind; | |
605 | } | |
606 | ||
607 | /* Cannot access snooped pages through the aperture */ | |
608 | if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) | |
609 | goto unwind; | |
610 | ||
611 | dst->page_count = num_pages; | |
612 | while (num_pages--) { | |
84734a04 MK |
613 | unsigned long flags; |
614 | void *d; | |
615 | ||
616 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); | |
617 | if (d == NULL) | |
618 | goto unwind; | |
619 | ||
620 | local_irq_save(flags); | |
b3c3f5e6 | 621 | if (use_ggtt) { |
84734a04 MK |
622 | void __iomem *s; |
623 | ||
624 | /* Simply ignore tiling or any overlapping fence. | |
625 | * It's part of the error state, and this hopefully | |
626 | * captures what the GPU read. | |
627 | */ | |
628 | ||
629 | s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
630 | reloc_offset); | |
631 | memcpy_fromio(d, s, PAGE_SIZE); | |
632 | io_mapping_unmap_atomic(s); | |
84734a04 MK |
633 | } else { |
634 | struct page *page; | |
635 | void *s; | |
636 | ||
637 | page = i915_gem_object_get_page(src, i); | |
638 | ||
639 | drm_clflush_pages(&page, 1); | |
640 | ||
641 | s = kmap_atomic(page); | |
642 | memcpy(d, s, PAGE_SIZE); | |
643 | kunmap_atomic(s); | |
644 | ||
645 | drm_clflush_pages(&page, 1); | |
646 | } | |
647 | local_irq_restore(flags); | |
648 | ||
b3c3f5e6 | 649 | dst->pages[i++] = d; |
84734a04 MK |
650 | reloc_offset += PAGE_SIZE; |
651 | } | |
84734a04 MK |
652 | |
653 | return dst; | |
654 | ||
655 | unwind: | |
656 | while (i--) | |
657 | kfree(dst->pages[i]); | |
658 | kfree(dst); | |
659 | return NULL; | |
660 | } | |
a7b91078 | 661 | #define i915_error_ggtt_object_create(dev_priv, src) \ |
8ae62dc6 | 662 | i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base) |
84734a04 MK |
663 | |
664 | static void capture_bo(struct drm_i915_error_buffer *err, | |
3a448734 | 665 | struct i915_vma *vma) |
84734a04 | 666 | { |
3a448734 CW |
667 | struct drm_i915_gem_object *obj = vma->obj; |
668 | ||
84734a04 MK |
669 | err->size = obj->base.size; |
670 | err->name = obj->base.name; | |
671 | err->rseqno = obj->last_read_seqno; | |
672 | err->wseqno = obj->last_write_seqno; | |
3a448734 | 673 | err->gtt_offset = vma->node.start; |
84734a04 MK |
674 | err->read_domains = obj->base.read_domains; |
675 | err->write_domain = obj->base.write_domain; | |
676 | err->fence_reg = obj->fence_reg; | |
677 | err->pinned = 0; | |
d7f46fc4 | 678 | if (i915_gem_obj_is_pinned(obj)) |
84734a04 MK |
679 | err->pinned = 1; |
680 | if (obj->user_pin_count > 0) | |
681 | err->pinned = -1; | |
682 | err->tiling = obj->tiling_mode; | |
683 | err->dirty = obj->dirty; | |
684 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
5cc9ed4b | 685 | err->userptr = obj->userptr.mm != NULL; |
84734a04 MK |
686 | err->ring = obj->ring ? obj->ring->id : -1; |
687 | err->cache_level = obj->cache_level; | |
688 | } | |
689 | ||
690 | static u32 capture_active_bo(struct drm_i915_error_buffer *err, | |
691 | int count, struct list_head *head) | |
692 | { | |
ca191b13 | 693 | struct i915_vma *vma; |
84734a04 MK |
694 | int i = 0; |
695 | ||
ca191b13 | 696 | list_for_each_entry(vma, head, mm_list) { |
3a448734 | 697 | capture_bo(err++, vma); |
84734a04 MK |
698 | if (++i == count) |
699 | break; | |
700 | } | |
701 | ||
702 | return i; | |
703 | } | |
704 | ||
705 | static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, | |
3a448734 CW |
706 | int count, struct list_head *head, |
707 | struct i915_address_space *vm) | |
84734a04 MK |
708 | { |
709 | struct drm_i915_gem_object *obj; | |
3a448734 CW |
710 | struct drm_i915_error_buffer * const first = err; |
711 | struct drm_i915_error_buffer * const last = err + count; | |
84734a04 MK |
712 | |
713 | list_for_each_entry(obj, head, global_list) { | |
3a448734 | 714 | struct i915_vma *vma; |
84734a04 | 715 | |
3a448734 | 716 | if (err == last) |
84734a04 | 717 | break; |
3a448734 CW |
718 | |
719 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
720 | if (vma->vm == vm && vma->pin_count > 0) { | |
721 | capture_bo(err++, vma); | |
722 | break; | |
723 | } | |
84734a04 MK |
724 | } |
725 | ||
3a448734 | 726 | return err - first; |
84734a04 MK |
727 | } |
728 | ||
011cf577 BW |
729 | /* Generate a semi-unique error code. The code is not meant to have meaning, The |
730 | * code's only purpose is to try to prevent false duplicated bug reports by | |
731 | * grossly estimating a GPU error state. | |
732 | * | |
733 | * TODO Ideally, hashing the batchbuffer would be a very nice way to determine | |
734 | * the hang if we could strip the GTT offset information from it. | |
735 | * | |
736 | * It's only a small step better than a random number in its current form. | |
737 | */ | |
738 | static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, | |
cb383002 MK |
739 | struct drm_i915_error_state *error, |
740 | int *ring_id) | |
011cf577 BW |
741 | { |
742 | uint32_t error_code = 0; | |
743 | int i; | |
744 | ||
745 | /* IPEHR would be an ideal way to detect errors, as it's the gross | |
746 | * measure of "the command that hung." However, has some very common | |
747 | * synchronization commands which almost always appear in the case | |
748 | * strictly a client bug. Use instdone to differentiate those some. | |
749 | */ | |
cb383002 MK |
750 | for (i = 0; i < I915_NUM_RINGS; i++) { |
751 | if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { | |
752 | if (ring_id) | |
753 | *ring_id = i; | |
754 | ||
011cf577 | 755 | return error->ring[i].ipehr ^ error->ring[i].instdone; |
cb383002 MK |
756 | } |
757 | } | |
011cf577 BW |
758 | |
759 | return error_code; | |
760 | } | |
761 | ||
84734a04 MK |
762 | static void i915_gem_record_fences(struct drm_device *dev, |
763 | struct drm_i915_error_state *error) | |
764 | { | |
765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766 | int i; | |
767 | ||
768 | /* Fences */ | |
769 | switch (INTEL_INFO(dev)->gen) { | |
01209dd5 | 770 | case 9: |
5ab31333 | 771 | case 8: |
84734a04 MK |
772 | case 7: |
773 | case 6: | |
774 | for (i = 0; i < dev_priv->num_fence_regs; i++) | |
775 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
776 | break; | |
777 | case 5: | |
778 | case 4: | |
779 | for (i = 0; i < 16; i++) | |
780 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
781 | break; | |
782 | case 3: | |
783 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
784 | for (i = 0; i < 8; i++) | |
785 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
786 | case 2: | |
787 | for (i = 0; i < 8; i++) | |
788 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
789 | break; | |
790 | ||
791 | default: | |
792 | BUG(); | |
793 | } | |
794 | } | |
795 | ||
87f85ebc | 796 | |
0ca36d78 BW |
797 | static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, |
798 | struct drm_i915_error_state *error, | |
799 | struct intel_engine_cs *ring, | |
800 | struct drm_i915_error_ring *ering) | |
801 | { | |
b4558b46 | 802 | struct intel_engine_cs *to; |
0ca36d78 BW |
803 | int i; |
804 | ||
805 | if (!i915_semaphore_is_enabled(dev_priv->dev)) | |
806 | return; | |
807 | ||
808 | if (!error->semaphore_obj) | |
809 | error->semaphore_obj = | |
810 | i915_error_object_create(dev_priv, | |
811 | dev_priv->semaphore_obj, | |
812 | &dev_priv->gtt.base); | |
813 | ||
b4558b46 RV |
814 | for_each_ring(to, dev_priv, i) { |
815 | int idx; | |
816 | u16 signal_offset; | |
817 | u32 *tmp; | |
0ca36d78 | 818 | |
b4558b46 RV |
819 | if (ring == to) |
820 | continue; | |
821 | ||
864c6181 RV |
822 | signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) |
823 | / 4; | |
b4558b46 RV |
824 | tmp = error->semaphore_obj->pages[0]; |
825 | idx = intel_ring_sync_index(ring, to); | |
826 | ||
827 | ering->semaphore_mboxes[idx] = tmp[signal_offset]; | |
828 | ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; | |
0ca36d78 BW |
829 | } |
830 | } | |
831 | ||
87f85ebc BW |
832 | static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, |
833 | struct intel_engine_cs *ring, | |
834 | struct drm_i915_error_ring *ering) | |
835 | { | |
836 | ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); | |
837 | ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); | |
838 | ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; | |
839 | ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; | |
840 | ||
841 | if (HAS_VEBOX(dev_priv->dev)) { | |
842 | ering->semaphore_mboxes[2] = | |
843 | I915_READ(RING_SYNC_2(ring->mmio_base)); | |
844 | ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; | |
845 | } | |
846 | } | |
847 | ||
84734a04 | 848 | static void i915_record_ring_state(struct drm_device *dev, |
0ca36d78 | 849 | struct drm_i915_error_state *error, |
a4872ba6 | 850 | struct intel_engine_cs *ring, |
362b8af7 | 851 | struct drm_i915_error_ring *ering) |
84734a04 MK |
852 | { |
853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
854 | ||
855 | if (INTEL_INFO(dev)->gen >= 6) { | |
362b8af7 BW |
856 | ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); |
857 | ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
0ca36d78 BW |
858 | if (INTEL_INFO(dev)->gen >= 8) |
859 | gen8_record_semaphore_state(dev_priv, error, ring, ering); | |
860 | else | |
861 | gen6_record_semaphore_state(dev_priv, ring, ering); | |
4e5aabfd BW |
862 | } |
863 | ||
84734a04 | 864 | if (INTEL_INFO(dev)->gen >= 4) { |
362b8af7 BW |
865 | ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
866 | ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); | |
867 | ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
868 | ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
869 | ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); | |
870 | ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); | |
13ffadd1 BW |
871 | if (INTEL_INFO(dev)->gen >= 8) { |
872 | ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; | |
362b8af7 | 873 | ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; |
13ffadd1 | 874 | } |
362b8af7 | 875 | ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); |
84734a04 | 876 | } else { |
362b8af7 BW |
877 | ering->faddr = I915_READ(DMA_FADD_I8XX); |
878 | ering->ipeir = I915_READ(IPEIR); | |
879 | ering->ipehr = I915_READ(IPEHR); | |
880 | ering->instdone = I915_READ(INSTDONE); | |
84734a04 MK |
881 | } |
882 | ||
362b8af7 BW |
883 | ering->waiting = waitqueue_active(&ring->irq_queue); |
884 | ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); | |
885 | ering->seqno = ring->get_seqno(ring, false); | |
886 | ering->acthd = intel_ring_get_active_head(ring); | |
887 | ering->head = I915_READ_HEAD(ring); | |
888 | ering->tail = I915_READ_TAIL(ring); | |
889 | ering->ctl = I915_READ_CTL(ring); | |
84734a04 | 890 | |
f3ce3821 CW |
891 | if (I915_NEED_GFX_HWS(dev)) { |
892 | int mmio; | |
893 | ||
894 | if (IS_GEN7(dev)) { | |
895 | switch (ring->id) { | |
896 | default: | |
897 | case RCS: | |
898 | mmio = RENDER_HWS_PGA_GEN7; | |
899 | break; | |
900 | case BCS: | |
901 | mmio = BLT_HWS_PGA_GEN7; | |
902 | break; | |
903 | case VCS: | |
904 | mmio = BSD_HWS_PGA_GEN7; | |
905 | break; | |
906 | case VECS: | |
907 | mmio = VEBOX_HWS_PGA_GEN7; | |
908 | break; | |
909 | } | |
910 | } else if (IS_GEN6(ring->dev)) { | |
911 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
912 | } else { | |
913 | /* XXX: gen8 returns to sanity */ | |
914 | mmio = RING_HWS_PGA(ring->mmio_base); | |
915 | } | |
916 | ||
362b8af7 | 917 | ering->hws = I915_READ(mmio); |
f3ce3821 CW |
918 | } |
919 | ||
362b8af7 BW |
920 | ering->hangcheck_score = ring->hangcheck.score; |
921 | ering->hangcheck_action = ring->hangcheck.action; | |
6c7a01ec BW |
922 | |
923 | if (USES_PPGTT(dev)) { | |
924 | int i; | |
925 | ||
926 | ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); | |
927 | ||
928 | switch (INTEL_INFO(dev)->gen) { | |
2a9b7539 | 929 | case 9: |
6c7a01ec BW |
930 | case 8: |
931 | for (i = 0; i < 4; i++) { | |
932 | ering->vm_info.pdp[i] = | |
933 | I915_READ(GEN8_RING_PDP_UDW(ring, i)); | |
934 | ering->vm_info.pdp[i] <<= 32; | |
935 | ering->vm_info.pdp[i] |= | |
936 | I915_READ(GEN8_RING_PDP_LDW(ring, i)); | |
937 | } | |
938 | break; | |
939 | case 7: | |
ae89f44d BW |
940 | ering->vm_info.pp_dir_base = |
941 | I915_READ(RING_PP_DIR_BASE(ring)); | |
6c7a01ec BW |
942 | break; |
943 | case 6: | |
ae89f44d BW |
944 | ering->vm_info.pp_dir_base = |
945 | I915_READ(RING_PP_DIR_BASE_READ(ring)); | |
6c7a01ec BW |
946 | break; |
947 | } | |
948 | } | |
84734a04 MK |
949 | } |
950 | ||
951 | ||
a4872ba6 | 952 | static void i915_gem_record_active_context(struct intel_engine_cs *ring, |
84734a04 MK |
953 | struct drm_i915_error_state *error, |
954 | struct drm_i915_error_ring *ering) | |
955 | { | |
956 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
957 | struct drm_i915_gem_object *obj; | |
958 | ||
959 | /* Currently render ring is the only HW context user */ | |
960 | if (ring->id != RCS || !error->ccid) | |
961 | return; | |
962 | ||
963 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
36362ad3 BW |
964 | if (!i915_gem_obj_ggtt_bound(obj)) |
965 | continue; | |
966 | ||
84734a04 | 967 | if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { |
17d36749 | 968 | ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); |
84734a04 MK |
969 | break; |
970 | } | |
971 | } | |
972 | } | |
973 | ||
974 | static void i915_gem_record_rings(struct drm_device *dev, | |
975 | struct drm_i915_error_state *error) | |
976 | { | |
977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84734a04 MK |
978 | struct drm_i915_gem_request *request; |
979 | int i, count; | |
980 | ||
372fbb8e | 981 | for (i = 0; i < I915_NUM_RINGS; i++) { |
a4872ba6 | 982 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
9075e52f | 983 | struct intel_ringbuffer *rbuf; |
372fbb8e | 984 | |
eee73b46 CW |
985 | error->ring[i].pid = -1; |
986 | ||
372fbb8e CW |
987 | if (ring->dev == NULL) |
988 | continue; | |
989 | ||
990 | error->ring[i].valid = true; | |
991 | ||
0ca36d78 | 992 | i915_record_ring_state(dev, error, ring, &error->ring[i]); |
84734a04 | 993 | |
ab0e7ff9 CW |
994 | request = i915_gem_find_active_request(ring); |
995 | if (request) { | |
ae6c4806 DV |
996 | struct i915_address_space *vm; |
997 | ||
998 | vm = request->ctx && request->ctx->ppgtt ? | |
999 | &request->ctx->ppgtt->base : | |
1000 | &dev_priv->gtt.base; | |
1001 | ||
ab0e7ff9 CW |
1002 | /* We need to copy these to an anonymous buffer |
1003 | * as the simplest method to avoid being overwritten | |
1004 | * by userspace. | |
1005 | */ | |
1006 | error->ring[i].batchbuffer = | |
1007 | i915_error_object_create(dev_priv, | |
1008 | request->batch_obj, | |
ae6c4806 | 1009 | vm); |
ab0e7ff9 | 1010 | |
8ae62dc6 | 1011 | if (HAS_BROKEN_CS_TLB(dev_priv->dev)) |
ab0e7ff9 CW |
1012 | error->ring[i].wa_batchbuffer = |
1013 | i915_error_ggtt_object_create(dev_priv, | |
1014 | ring->scratch.obj); | |
1015 | ||
1016 | if (request->file_priv) { | |
1017 | struct task_struct *task; | |
1018 | ||
1019 | rcu_read_lock(); | |
1020 | task = pid_task(request->file_priv->file->pid, | |
1021 | PIDTYPE_PID); | |
1022 | if (task) { | |
1023 | strcpy(error->ring[i].comm, task->comm); | |
1024 | error->ring[i].pid = task->pid; | |
1025 | } | |
1026 | rcu_read_unlock(); | |
1027 | } | |
1028 | } | |
84734a04 | 1029 | |
9075e52f OM |
1030 | if (i915.enable_execlists) { |
1031 | /* TODO: This is only a small fix to keep basic error | |
1032 | * capture working, but we need to add more information | |
1033 | * for it to be useful (e.g. dump the context being | |
1034 | * executed). | |
1035 | */ | |
1036 | if (request) | |
1037 | rbuf = request->ctx->engine[ring->id].ringbuf; | |
1038 | else | |
1039 | rbuf = ring->default_context->engine[ring->id].ringbuf; | |
1040 | } else | |
1041 | rbuf = ring->buffer; | |
1042 | ||
1043 | error->ring[i].cpu_ring_head = rbuf->head; | |
1044 | error->ring[i].cpu_ring_tail = rbuf->tail; | |
1045 | ||
84734a04 | 1046 | error->ring[i].ringbuffer = |
9075e52f | 1047 | i915_error_ggtt_object_create(dev_priv, rbuf->obj); |
84734a04 | 1048 | |
8ae62dc6 CW |
1049 | error->ring[i].hws_page = |
1050 | i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); | |
84734a04 MK |
1051 | |
1052 | i915_gem_record_active_context(ring, error, &error->ring[i]); | |
1053 | ||
1054 | count = 0; | |
1055 | list_for_each_entry(request, &ring->request_list, list) | |
1056 | count++; | |
1057 | ||
1058 | error->ring[i].num_requests = count; | |
1059 | error->ring[i].requests = | |
a1e22653 | 1060 | kcalloc(count, sizeof(*error->ring[i].requests), |
84734a04 MK |
1061 | GFP_ATOMIC); |
1062 | if (error->ring[i].requests == NULL) { | |
1063 | error->ring[i].num_requests = 0; | |
1064 | continue; | |
1065 | } | |
1066 | ||
1067 | count = 0; | |
1068 | list_for_each_entry(request, &ring->request_list, list) { | |
1069 | struct drm_i915_error_request *erq; | |
1070 | ||
1071 | erq = &error->ring[i].requests[count++]; | |
1072 | erq->seqno = request->seqno; | |
1073 | erq->jiffies = request->emitted_jiffies; | |
1074 | erq->tail = request->tail; | |
1075 | } | |
1076 | } | |
1077 | } | |
1078 | ||
95f5301d BW |
1079 | /* FIXME: Since pin count/bound list is global, we duplicate what we capture per |
1080 | * VM. | |
1081 | */ | |
1082 | static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, | |
1083 | struct drm_i915_error_state *error, | |
1084 | struct i915_address_space *vm, | |
1085 | const int ndx) | |
84734a04 | 1086 | { |
95f5301d | 1087 | struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; |
84734a04 | 1088 | struct drm_i915_gem_object *obj; |
95f5301d | 1089 | struct i915_vma *vma; |
84734a04 MK |
1090 | int i; |
1091 | ||
1092 | i = 0; | |
ca191b13 | 1093 | list_for_each_entry(vma, &vm->active_list, mm_list) |
84734a04 | 1094 | i++; |
95f5301d | 1095 | error->active_bo_count[ndx] = i; |
3a448734 CW |
1096 | |
1097 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
1098 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
1099 | if (vma->vm == vm && vma->pin_count > 0) { | |
1100 | i++; | |
1101 | break; | |
1102 | } | |
1103 | } | |
95f5301d | 1104 | error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; |
84734a04 MK |
1105 | |
1106 | if (i) { | |
a1e22653 | 1107 | active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); |
95f5301d BW |
1108 | if (active_bo) |
1109 | pinned_bo = active_bo + error->active_bo_count[ndx]; | |
84734a04 MK |
1110 | } |
1111 | ||
95f5301d BW |
1112 | if (active_bo) |
1113 | error->active_bo_count[ndx] = | |
1114 | capture_active_bo(active_bo, | |
1115 | error->active_bo_count[ndx], | |
5cef07e1 | 1116 | &vm->active_list); |
84734a04 | 1117 | |
95f5301d BW |
1118 | if (pinned_bo) |
1119 | error->pinned_bo_count[ndx] = | |
1120 | capture_pinned_bo(pinned_bo, | |
1121 | error->pinned_bo_count[ndx], | |
3a448734 | 1122 | &dev_priv->mm.bound_list, vm); |
95f5301d BW |
1123 | error->active_bo[ndx] = active_bo; |
1124 | error->pinned_bo[ndx] = pinned_bo; | |
1125 | } | |
1126 | ||
1127 | static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, | |
1128 | struct drm_i915_error_state *error) | |
1129 | { | |
1130 | struct i915_address_space *vm; | |
1131 | int cnt = 0, i = 0; | |
1132 | ||
1133 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
1134 | cnt++; | |
1135 | ||
95f5301d BW |
1136 | error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); |
1137 | error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); | |
1138 | error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), | |
1139 | GFP_ATOMIC); | |
1140 | error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), | |
1141 | GFP_ATOMIC); | |
1142 | ||
3a448734 CW |
1143 | if (error->active_bo == NULL || |
1144 | error->pinned_bo == NULL || | |
1145 | error->active_bo_count == NULL || | |
1146 | error->pinned_bo_count == NULL) { | |
1147 | kfree(error->active_bo); | |
1148 | kfree(error->active_bo_count); | |
1149 | kfree(error->pinned_bo); | |
1150 | kfree(error->pinned_bo_count); | |
1151 | ||
1152 | error->active_bo = NULL; | |
1153 | error->active_bo_count = NULL; | |
1154 | error->pinned_bo = NULL; | |
1155 | error->pinned_bo_count = NULL; | |
1156 | } else { | |
1157 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
1158 | i915_gem_capture_vm(dev_priv, error, vm, i++); | |
1159 | ||
1160 | error->vm_count = cnt; | |
1161 | } | |
84734a04 MK |
1162 | } |
1163 | ||
1d762aad BW |
1164 | /* Capture all registers which don't fit into another category. */ |
1165 | static void i915_capture_reg_state(struct drm_i915_private *dev_priv, | |
1166 | struct drm_i915_error_state *error) | |
84734a04 | 1167 | { |
1d762aad | 1168 | struct drm_device *dev = dev_priv->dev; |
885ea5a8 | 1169 | int i; |
84734a04 | 1170 | |
654c90c6 BW |
1171 | /* General organization |
1172 | * 1. Registers specific to a single generation | |
1173 | * 2. Registers which belong to multiple generations | |
1174 | * 3. Feature specific registers. | |
1175 | * 4. Everything else | |
1176 | * Please try to follow the order. | |
1177 | */ | |
84734a04 | 1178 | |
654c90c6 BW |
1179 | /* 1: Registers specific to a single generation */ |
1180 | if (IS_VALLEYVIEW(dev)) { | |
885ea5a8 | 1181 | error->gtier[0] = I915_READ(GTIER); |
843db716 | 1182 | error->ier = I915_READ(VLV_IER); |
654c90c6 BW |
1183 | error->forcewake = I915_READ(FORCEWAKE_VLV); |
1184 | } | |
84734a04 | 1185 | |
654c90c6 BW |
1186 | if (IS_GEN7(dev)) |
1187 | error->err_int = I915_READ(GEN7_ERR_INT); | |
84734a04 | 1188 | |
91ec5d11 | 1189 | if (IS_GEN6(dev)) { |
84734a04 | 1190 | error->forcewake = I915_READ(FORCEWAKE); |
91ec5d11 BW |
1191 | error->gab_ctl = I915_READ(GAB_CTL); |
1192 | error->gfx_mode = I915_READ(GFX_MODE); | |
1193 | } | |
84734a04 | 1194 | |
654c90c6 BW |
1195 | /* 2: Registers which belong to multiple generations */ |
1196 | if (INTEL_INFO(dev)->gen >= 7) | |
1197 | error->forcewake = I915_READ(FORCEWAKE_MT); | |
84734a04 MK |
1198 | |
1199 | if (INTEL_INFO(dev)->gen >= 6) { | |
654c90c6 | 1200 | error->derrmr = I915_READ(DERRMR); |
84734a04 MK |
1201 | error->error = I915_READ(ERROR_GEN6); |
1202 | error->done_reg = I915_READ(DONE_REG); | |
1203 | } | |
1204 | ||
654c90c6 | 1205 | /* 3: Feature specific registers */ |
91ec5d11 BW |
1206 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1207 | error->gam_ecochk = I915_READ(GAM_ECOCHK); | |
1208 | error->gac_eco = I915_READ(GAC_ECO_BITS); | |
1209 | } | |
1210 | ||
1211 | /* 4: Everything else */ | |
654c90c6 BW |
1212 | if (HAS_HW_CONTEXTS(dev)) |
1213 | error->ccid = I915_READ(CCID); | |
1214 | ||
885ea5a8 RV |
1215 | if (INTEL_INFO(dev)->gen >= 8) { |
1216 | error->ier = I915_READ(GEN8_DE_MISC_IER); | |
1217 | for (i = 0; i < 4; i++) | |
1218 | error->gtier[i] = I915_READ(GEN8_GT_IER(i)); | |
1219 | } else if (HAS_PCH_SPLIT(dev)) { | |
843db716 | 1220 | error->ier = I915_READ(DEIER); |
885ea5a8 | 1221 | error->gtier[0] = I915_READ(GTIER); |
843db716 RV |
1222 | } else if (IS_GEN2(dev)) { |
1223 | error->ier = I915_READ16(IER); | |
1224 | } else if (!IS_VALLEYVIEW(dev)) { | |
1225 | error->ier = I915_READ(IER); | |
654c90c6 | 1226 | } |
654c90c6 BW |
1227 | error->eir = I915_READ(EIR); |
1228 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
84734a04 MK |
1229 | |
1230 | i915_get_extra_instdone(dev, error->extra_instdone); | |
1d762aad BW |
1231 | } |
1232 | ||
cb383002 | 1233 | static void i915_error_capture_msg(struct drm_device *dev, |
58174462 MK |
1234 | struct drm_i915_error_state *error, |
1235 | bool wedged, | |
1236 | const char *error_msg) | |
cb383002 MK |
1237 | { |
1238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1239 | u32 ecode; | |
58174462 | 1240 | int ring_id = -1, len; |
cb383002 MK |
1241 | |
1242 | ecode = i915_error_generate_code(dev_priv, error, &ring_id); | |
1243 | ||
58174462 | 1244 | len = scnprintf(error->error_msg, sizeof(error->error_msg), |
0b5492d6 MK |
1245 | "GPU HANG: ecode %d:%d:0x%08x", |
1246 | INTEL_INFO(dev)->gen, ring_id, ecode); | |
58174462 MK |
1247 | |
1248 | if (ring_id != -1 && error->ring[ring_id].pid != -1) | |
1249 | len += scnprintf(error->error_msg + len, | |
1250 | sizeof(error->error_msg) - len, | |
1251 | ", in %s [%d]", | |
1252 | error->ring[ring_id].comm, | |
1253 | error->ring[ring_id].pid); | |
1254 | ||
1255 | scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, | |
1256 | ", reason: %s, action: %s", | |
1257 | error_msg, | |
1258 | wedged ? "reset" : "continue"); | |
cb383002 MK |
1259 | } |
1260 | ||
48b031e3 MK |
1261 | static void i915_capture_gen_state(struct drm_i915_private *dev_priv, |
1262 | struct drm_i915_error_state *error) | |
1263 | { | |
1264 | error->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
62d5d69b | 1265 | error->suspend_count = dev_priv->suspend_count; |
48b031e3 MK |
1266 | } |
1267 | ||
1d762aad BW |
1268 | /** |
1269 | * i915_capture_error_state - capture an error record for later analysis | |
1270 | * @dev: drm device | |
1271 | * | |
1272 | * Should be called when an error is detected (either a hang or an error | |
1273 | * interrupt) to capture error state from the time of the error. Fills | |
1274 | * out a structure which becomes available in debugfs for user level tools | |
1275 | * to pick up. | |
1276 | */ | |
58174462 MK |
1277 | void i915_capture_error_state(struct drm_device *dev, bool wedged, |
1278 | const char *error_msg) | |
1d762aad | 1279 | { |
53a4c6b2 | 1280 | static bool warned; |
1d762aad BW |
1281 | struct drm_i915_private *dev_priv = dev->dev_private; |
1282 | struct drm_i915_error_state *error; | |
1283 | unsigned long flags; | |
1d762aad BW |
1284 | |
1285 | /* Account for pipe specific data like PIPE*STAT */ | |
1286 | error = kzalloc(sizeof(*error), GFP_ATOMIC); | |
1287 | if (!error) { | |
1288 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); | |
1289 | return; | |
1290 | } | |
1291 | ||
011cf577 BW |
1292 | kref_init(&error->ref); |
1293 | ||
48b031e3 | 1294 | i915_capture_gen_state(dev_priv, error); |
011cf577 BW |
1295 | i915_capture_reg_state(dev_priv, error); |
1296 | i915_gem_capture_buffers(dev_priv, error); | |
1297 | i915_gem_record_fences(dev, error); | |
1298 | i915_gem_record_rings(dev, error); | |
1d762aad | 1299 | |
84734a04 MK |
1300 | do_gettimeofday(&error->time); |
1301 | ||
1302 | error->overlay = intel_overlay_capture_error_state(dev); | |
1303 | error->display = intel_display_capture_error_state(dev); | |
1304 | ||
58174462 | 1305 | i915_error_capture_msg(dev, error, wedged, error_msg); |
cb383002 MK |
1306 | DRM_INFO("%s\n", error->error_msg); |
1307 | ||
84734a04 MK |
1308 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1309 | if (dev_priv->gpu_error.first_error == NULL) { | |
1310 | dev_priv->gpu_error.first_error = error; | |
1311 | error = NULL; | |
1312 | } | |
1313 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
1314 | ||
cb383002 | 1315 | if (error) { |
84734a04 | 1316 | i915_error_state_free(&error->ref); |
cb383002 MK |
1317 | return; |
1318 | } | |
1319 | ||
1320 | if (!warned) { | |
1321 | DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); | |
1322 | DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); | |
1323 | DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); | |
1324 | DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); | |
1325 | DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); | |
1326 | warned = true; | |
1327 | } | |
84734a04 MK |
1328 | } |
1329 | ||
1330 | void i915_error_state_get(struct drm_device *dev, | |
1331 | struct i915_error_state_file_priv *error_priv) | |
1332 | { | |
1333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84734a04 | 1334 | |
5b254c59 | 1335 | spin_lock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1336 | error_priv->error = dev_priv->gpu_error.first_error; |
1337 | if (error_priv->error) | |
1338 | kref_get(&error_priv->error->ref); | |
5b254c59 | 1339 | spin_unlock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1340 | |
1341 | } | |
1342 | ||
1343 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv) | |
1344 | { | |
1345 | if (error_priv->error) | |
1346 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
1347 | } | |
1348 | ||
1349 | void i915_destroy_error_state(struct drm_device *dev) | |
1350 | { | |
1351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1352 | struct drm_i915_error_state *error; | |
84734a04 | 1353 | |
5b254c59 | 1354 | spin_lock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1355 | error = dev_priv->gpu_error.first_error; |
1356 | dev_priv->gpu_error.first_error = NULL; | |
5b254c59 | 1357 | spin_unlock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1358 | |
1359 | if (error) | |
1360 | kref_put(&error->ref, i915_error_state_free); | |
1361 | } | |
1362 | ||
0a4cd7c8 | 1363 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type) |
84734a04 MK |
1364 | { |
1365 | switch (type) { | |
1366 | case I915_CACHE_NONE: return " uncached"; | |
0a4cd7c8 | 1367 | case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; |
350ec881 | 1368 | case I915_CACHE_L3_LLC: return " L3+LLC"; |
f56383cb | 1369 | case I915_CACHE_WT: return " WT"; |
84734a04 MK |
1370 | default: return ""; |
1371 | } | |
1372 | } | |
1373 | ||
1374 | /* NB: please notice the memset */ | |
1375 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) | |
1376 | { | |
1377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1378 | memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); | |
1379 | ||
1380 | switch (INTEL_INFO(dev)->gen) { | |
1381 | case 2: | |
1382 | case 3: | |
1383 | instdone[0] = I915_READ(INSTDONE); | |
1384 | break; | |
1385 | case 4: | |
1386 | case 5: | |
1387 | case 6: | |
1388 | instdone[0] = I915_READ(INSTDONE_I965); | |
1389 | instdone[1] = I915_READ(INSTDONE1); | |
1390 | break; | |
1391 | default: | |
1392 | WARN_ONCE(1, "Unsupported platform\n"); | |
1393 | case 7: | |
d0582ed2 | 1394 | case 8: |
2fcdcd8a | 1395 | case 9: |
84734a04 MK |
1396 | instdone[0] = I915_READ(GEN7_INSTDONE_1); |
1397 | instdone[1] = I915_READ(GEN7_SC_INSTDONE); | |
1398 | instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
1399 | instdone[3] = I915_READ(GEN7_ROW_INSTDONE); | |
1400 | break; | |
1401 | } | |
1402 | } |