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drm/i915: Add reason for capture in error state
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47}
48
49static const char *pin_flag(int pinned)
50{
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57}
58
59static const char *tiling_flag(int tiling)
60{
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67}
68
69static const char *dirty_flag(int dirty)
70{
71 return dirty ? " dirty" : "";
72}
73
74static const char *purgeable_flag(int purgeable)
75{
76 return purgeable ? " purgeable" : "";
77}
78
79static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80{
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91}
92
93static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95{
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108}
109
110static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112{
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134}
135
136static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138{
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
e29bb4eb
CW		 146 va_list tmp;
147
148 va_copy(tmp, args);
149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
84734a04
MK		 150 return;
151 }
152
153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
154 if (len >= e->size - e->bytes)
155 len = e->size - e->bytes - 1;
156
157 __i915_error_advance(e, len);
158}
159
160static void i915_error_puts(struct drm_i915_error_state_buf *e,
161 const char *str)
162{
163 unsigned len;
164
165 if (!__i915_error_ok(e))
166 return;
167
168 len = strlen(str);
169
170 /* Seek the first printf which is hits start position */
171 if (e->pos < e->start) {
172 if (!__i915_error_seek(e, len))
173 return;
174 }
175
176 if (len >= e->size - e->bytes)
177 len = e->size - e->bytes - 1;
178 memcpy(e->buf + e->bytes, str, len);
179
180 __i915_error_advance(e, len);
181}
182
183#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
184#define err_puts(e, s) i915_error_puts(e, s)
185
186static void print_error_buffers(struct drm_i915_error_state_buf *m,
187 const char *name,
188 struct drm_i915_error_buffer *err,
189 int count)
190{
191 err_printf(m, "%s [%d]:\n", name, count);
192
193 while (count--) {
194 err_printf(m, " %08x %8u %02x %02x %x %x",
195 err->gtt_offset,
196 err->size,
197 err->read_domains,
198 err->write_domain,
199 err->rseqno, err->wseqno);
200 err_puts(m, pin_flag(err->pinned));
201 err_puts(m, tiling_flag(err->tiling));
202 err_puts(m, dirty_flag(err->dirty));
203 err_puts(m, purgeable_flag(err->purgeable));
204 err_puts(m, err->ring != -1 ? " " : "");
205 err_puts(m, ring_str(err->ring));
206 err_puts(m, i915_cache_level_str(err->cache_level));
207
208 if (err->name)
209 err_printf(m, " (name: %d)", err->name);
210 if (err->fence_reg != I915_FENCE_REG_NONE)
211 err_printf(m, " (fence: %d)", err->fence_reg);
212
213 err_puts(m, "\n");
214 err++;
215 }
216}
217
da661464
MK		 218static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
219{
220 switch (a) {
221 case HANGCHECK_IDLE:
222 return "idle";
223 case HANGCHECK_WAIT:
224 return "wait";
225 case HANGCHECK_ACTIVE:
226 return "active";
227 case HANGCHECK_KICK:
228 return "kick";
229 case HANGCHECK_HUNG:
230 return "hung";
231 }
232
233 return "unknown";
234}
235
84734a04
MK		 236static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
237 struct drm_device *dev,
362b8af7 238 struct drm_i915_error_ring *ring)
84734a04 239{
362b8af7 240 if (!ring->valid)
372fbb8e
CW		 241 return;
242
362b8af7
BW		 243 err_printf(m, " HEAD: 0x%08x\n", ring->head);
244 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
245 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
246 err_printf(m, " HWS: 0x%08x\n", ring->hws);
247 err_printf(m, " ACTHD: 0x%08x\n", ring->acthd);
248 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
249 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
250 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 251 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 252 err_printf(m, " BBADDR: 0x%08llx\n", ring->bbaddr);
253 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
254 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 255 }
362b8af7
BW		 256 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
257 err_printf(m, " FADDR: 0x%08x\n", ring->faddr);
84734a04 258 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 259 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
260 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 261 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 262 ring->semaphore_mboxes[0],
263 ring->semaphore_seqno[0]);
84734a04 264 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 265 ring->semaphore_mboxes[1],
266 ring->semaphore_seqno[1]);
4e5aabfd
BW		 267 if (HAS_VEBOX(dev)) {
268 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 269 ring->semaphore_mboxes[2],
270 ring->semaphore_seqno[2]);
4e5aabfd 271 }
84734a04 272 }
6c7a01ec
BW		 273 if (USES_PPGTT(dev)) {
274 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
275
276 if (INTEL_INFO(dev)->gen >= 8) {
277 int i;
278 for (i = 0; i < 4; i++)
279 err_printf(m, " PDP%d: 0x%016llx\n",
280 i, ring->vm_info.pdp[i]);
281 } else {
282 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
283 ring->vm_info.pp_dir_base);
284 }
285 }
362b8af7
BW		 286 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
287 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
288 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
289 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 290 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 291 hangcheck_action_to_str(ring->hangcheck_action),
292 ring->hangcheck_score);
84734a04
MK		 293}
294
295void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
296{
297 va_list args;
298
299 va_start(args, f);
300 i915_error_vprintf(e, f, args);
301 va_end(args);
302}
303
ab0e7ff9
CW		 304static void print_error_obj(struct drm_i915_error_state_buf *m,
305 struct drm_i915_error_object *obj)
306{
307 int page, offset, elt;
308
309 for (page = offset = 0; page < obj->page_count; page++) {
310 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
311 err_printf(m, "%08x : %08x\n", offset,
312 obj->pages[page][elt]);
313 offset += 4;
314 }
315 }
316}
317
84734a04
MK		 318int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
319 const struct i915_error_state_file_priv *error_priv)
320{
321 struct drm_device *dev = error_priv->dev;
322 drm_i915_private_t *dev_priv = dev->dev_private;
323 struct drm_i915_error_state *error = error_priv->error;
ab0e7ff9
CW		 324 int i, j, offset, elt;
325 int max_hangcheck_score;
84734a04
MK		 326
327 if (!error) {
328 err_printf(m, "no error state collected\n");
329 goto out;
330 }
331
cb383002 332 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 333 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
334 error->time.tv_usec);
335 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 336 max_hangcheck_score = 0;
337 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
338 if (error->ring[i].hangcheck_score > max_hangcheck_score)
339 max_hangcheck_score = error->ring[i].hangcheck_score;
340 }
341 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
342 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
343 error->ring[i].pid != -1) {
344 err_printf(m, "Active process (on ring %s): %s [%d]\n",
345 ring_str(i),
346 error->ring[i].comm,
347 error->ring[i].pid);
348 }
349 }
ffbab09b 350 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 351 err_printf(m, "EIR: 0x%08x\n", error->eir);
352 err_printf(m, "IER: 0x%08x\n", error->ier);
353 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
354 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
355 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
356 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 357 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 358
359 for (i = 0; i < dev_priv->num_fence_regs; i++)
360 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
361
362 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
363 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
364 error->extra_instdone[i]);
365
366 if (INTEL_INFO(dev)->gen >= 6) {
367 err_printf(m, "ERROR: 0x%08x\n", error->error);
368 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
369 }
370
371 if (INTEL_INFO(dev)->gen == 7)
372 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
373
362b8af7
BW		 374 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
375 err_printf(m, "%s command stream:\n", ring_str(i));
376 i915_ring_error_state(m, dev, &error->ring[i]);
377 }
84734a04
MK		 378
379 if (error->active_bo)
380 print_error_buffers(m, "Active",
95f5301d
BW		 381 error->active_bo[0],
382 error->active_bo_count[0]);
84734a04
MK		 383
384 if (error->pinned_bo)
385 print_error_buffers(m, "Pinned",
95f5301d
BW		 386 error->pinned_bo[0],
387 error->pinned_bo_count[0]);
84734a04
MK		 388
389 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
390 struct drm_i915_error_object *obj;
391
ab0e7ff9
CW		 392 obj = error->ring[i].batchbuffer;
393 if (obj) {
394 err_puts(m, dev_priv->ring[i].name);
395 if (error->ring[i].pid != -1)
396 err_printf(m, " (submitted by %s [%d])",
397 error->ring[i].comm,
398 error->ring[i].pid);
399 err_printf(m, " --- gtt_offset = 0x%08x\n",
84734a04 400 obj->gtt_offset);
ab0e7ff9
CW		 401 print_error_obj(m, obj);
402 }
403
404 obj = error->ring[i].wa_batchbuffer;
405 if (obj) {
406 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
407 dev_priv->ring[i].name, obj->gtt_offset);
408 print_error_obj(m, obj);
84734a04
MK		 409 }
410
411 if (error->ring[i].num_requests) {
412 err_printf(m, "%s --- %d requests\n",
413 dev_priv->ring[i].name,
414 error->ring[i].num_requests);
415 for (j = 0; j < error->ring[i].num_requests; j++) {
416 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
417 error->ring[i].requests[j].seqno,
418 error->ring[i].requests[j].jiffies,
419 error->ring[i].requests[j].tail);
420 }
421 }
422
423 if ((obj = error->ring[i].ringbuffer)) {
424 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
425 dev_priv->ring[i].name,
426 obj->gtt_offset);
ab0e7ff9 427 print_error_obj(m, obj);
84734a04
MK		 428 }
429
362b8af7 430 if ((obj = error->ring[i].hws_page)) {
f3ce3821
CW		 431 err_printf(m, "%s --- HW Status = 0x%08x\n",
432 dev_priv->ring[i].name,
433 obj->gtt_offset);
434 offset = 0;
435 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
436 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
437 offset,
438 obj->pages[0][elt],
439 obj->pages[0][elt+1],
440 obj->pages[0][elt+2],
441 obj->pages[0][elt+3]);
442 offset += 16;
443 }
444 }
445
372fbb8e 446 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 447 err_printf(m, "%s --- HW Context = 0x%08x\n",
448 dev_priv->ring[i].name,
449 obj->gtt_offset);
450 offset = 0;
451 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
452 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
453 offset,
454 obj->pages[0][elt],
455 obj->pages[0][elt+1],
456 obj->pages[0][elt+2],
457 obj->pages[0][elt+3]);
458 offset += 16;
459 }
460 }
461 }
462
463 if (error->overlay)
464 intel_overlay_print_error_state(m, error->overlay);
465
466 if (error->display)
467 intel_display_print_error_state(m, dev, error->display);
468
469out:
470 if (m->bytes == 0 && m->err)
471 return m->err;
472
473 return 0;
474}
475
476int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
477 size_t count, loff_t pos)
478{
479 memset(ebuf, 0, sizeof(*ebuf));
480
481 /* We need to have enough room to store any i915_error_state printf
482 * so that we can move it to start position.
483 */
484 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
485 ebuf->buf = kmalloc(ebuf->size,
486 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
487
488 if (ebuf->buf == NULL) {
489 ebuf->size = PAGE_SIZE;
490 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
491 }
492
493 if (ebuf->buf == NULL) {
494 ebuf->size = 128;
495 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
496 }
497
498 if (ebuf->buf == NULL)
499 return -ENOMEM;
500
501 ebuf->start = pos;
502
503 return 0;
504}
505
506static void i915_error_object_free(struct drm_i915_error_object *obj)
507{
508 int page;
509
510 if (obj == NULL)
511 return;
512
513 for (page = 0; page < obj->page_count; page++)
514 kfree(obj->pages[page]);
515
516 kfree(obj);
517}
518
519static void i915_error_state_free(struct kref *error_ref)
520{
521 struct drm_i915_error_state *error = container_of(error_ref,
522 typeof(*error), ref);
523 int i;
524
525 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
526 i915_error_object_free(error->ring[i].batchbuffer);
527 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 528 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 529 i915_error_object_free(error->ring[i].ctx);
530 kfree(error->ring[i].requests);
531 }
532
533 kfree(error->active_bo);
534 kfree(error->overlay);
535 kfree(error->display);
536 kfree(error);
537}
538
539static struct drm_i915_error_object *
540i915_error_object_create_sized(struct drm_i915_private *dev_priv,
541 struct drm_i915_gem_object *src,
a7b91078 542 struct i915_address_space *vm,
84734a04
MK		 543 const int num_pages)
544{
545 struct drm_i915_error_object *dst;
546 int i;
547 u32 reloc_offset;
548
549 if (src == NULL || src->pages == NULL)
550 return NULL;
551
552 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
553 if (dst == NULL)
554 return NULL;
555
a7b91078 556 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
84734a04
MK		 557 for (i = 0; i < num_pages; i++) {
558 unsigned long flags;
559 void *d;
560
561 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
562 if (d == NULL)
563 goto unwind;
564
565 local_irq_save(flags);
8b6124a6
CW		 566 if (src->cache_level == I915_CACHE_NONE &&
567 reloc_offset < dev_priv->gtt.mappable_end &&
496bfcb9
BW		 568 src->has_global_gtt_mapping &&
569 i915_is_ggtt(vm)) {
84734a04
MK		 570 void __iomem *s;
571
572 /* Simply ignore tiling or any overlapping fence.
573 * It's part of the error state, and this hopefully
574 * captures what the GPU read.
575 */
576
577 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
578 reloc_offset);
579 memcpy_fromio(d, s, PAGE_SIZE);
580 io_mapping_unmap_atomic(s);
581 } else if (src->stolen) {
582 unsigned long offset;
583
584 offset = dev_priv->mm.stolen_base;
585 offset += src->stolen->start;
586 offset += i << PAGE_SHIFT;
587
588 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
589 } else {
590 struct page *page;
591 void *s;
592
593 page = i915_gem_object_get_page(src, i);
594
595 drm_clflush_pages(&page, 1);
596
597 s = kmap_atomic(page);
598 memcpy(d, s, PAGE_SIZE);
599 kunmap_atomic(s);
600
601 drm_clflush_pages(&page, 1);
602 }
603 local_irq_restore(flags);
604
605 dst->pages[i] = d;
606
607 reloc_offset += PAGE_SIZE;
608 }
609 dst->page_count = num_pages;
610
611 return dst;
612
613unwind:
614 while (i--)
615 kfree(dst->pages[i]);
616 kfree(dst);
617 return NULL;
618}
a7b91078
BW		 619#define i915_error_object_create(dev_priv, src, vm) \
620 i915_error_object_create_sized((dev_priv), (src), (vm), \
621 (src)->base.size>>PAGE_SHIFT)
622
623#define i915_error_ggtt_object_create(dev_priv, src) \
624 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 625 (src)->base.size>>PAGE_SHIFT)
626
627static void capture_bo(struct drm_i915_error_buffer *err,
628 struct drm_i915_gem_object *obj)
629{
630 err->size = obj->base.size;
631 err->name = obj->base.name;
632 err->rseqno = obj->last_read_seqno;
633 err->wseqno = obj->last_write_seqno;
634 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
635 err->read_domains = obj->base.read_domains;
636 err->write_domain = obj->base.write_domain;
637 err->fence_reg = obj->fence_reg;
638 err->pinned = 0;
d7f46fc4 639 if (i915_gem_obj_is_pinned(obj))
84734a04
MK		 640 err->pinned = 1;
641 if (obj->user_pin_count > 0)
642 err->pinned = -1;
643 err->tiling = obj->tiling_mode;
644 err->dirty = obj->dirty;
645 err->purgeable = obj->madv != I915_MADV_WILLNEED;
646 err->ring = obj->ring ? obj->ring->id : -1;
647 err->cache_level = obj->cache_level;
648}
649
650static u32 capture_active_bo(struct drm_i915_error_buffer *err,
651 int count, struct list_head *head)
652{
ca191b13 653 struct i915_vma *vma;
84734a04
MK		 654 int i = 0;
655
ca191b13
BW		 656 list_for_each_entry(vma, head, mm_list) {
657 capture_bo(err++, vma->obj);
84734a04
MK		 658 if (++i == count)
659 break;
660 }
661
662 return i;
663}
664
665static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
666 int count, struct list_head *head)
667{
668 struct drm_i915_gem_object *obj;
669 int i = 0;
670
671 list_for_each_entry(obj, head, global_list) {
d7f46fc4 672 if (!i915_gem_obj_is_pinned(obj))
84734a04
MK		 673 continue;
674
675 capture_bo(err++, obj);
676 if (++i == count)
677 break;
678 }
679
680 return i;
681}
682
011cf577
BW		 683/* Generate a semi-unique error code. The code is not meant to have meaning, The
684 * code's only purpose is to try to prevent false duplicated bug reports by
685 * grossly estimating a GPU error state.
686 *
687 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
688 * the hang if we could strip the GTT offset information from it.
689 *
690 * It's only a small step better than a random number in its current form.
691 */
692static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 693 struct drm_i915_error_state *error,
694 int *ring_id)
011cf577
BW		 695{
696 uint32_t error_code = 0;
697 int i;
698
699 /* IPEHR would be an ideal way to detect errors, as it's the gross
700 * measure of "the command that hung." However, has some very common
701 * synchronization commands which almost always appear in the case
702 * strictly a client bug. Use instdone to differentiate those some.
703 */
cb383002
MK		 704 for (i = 0; i < I915_NUM_RINGS; i++) {
705 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
706 if (ring_id)
707 *ring_id = i;
708
011cf577 709 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 710 }
711 }
011cf577
BW		 712
713 return error_code;
714}
715
84734a04
MK		 716static void i915_gem_record_fences(struct drm_device *dev,
717 struct drm_i915_error_state *error)
718{
719 struct drm_i915_private *dev_priv = dev->dev_private;
720 int i;
721
722 /* Fences */
723 switch (INTEL_INFO(dev)->gen) {
5ab31333 724 case 8:
84734a04
MK		 725 case 7:
726 case 6:
727 for (i = 0; i < dev_priv->num_fence_regs; i++)
728 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
729 break;
730 case 5:
731 case 4:
732 for (i = 0; i < 16; i++)
733 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
734 break;
735 case 3:
736 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
737 for (i = 0; i < 8; i++)
738 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
739 case 2:
740 for (i = 0; i < 8; i++)
741 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
742 break;
743
744 default:
745 BUG();
746 }
747}
748
84734a04 749static void i915_record_ring_state(struct drm_device *dev,
362b8af7
BW		 750 struct intel_ring_buffer *ring,
751 struct drm_i915_error_ring *ering)
84734a04
MK		 752{
753 struct drm_i915_private *dev_priv = dev->dev_private;
754
755 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 756 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
757 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
758 ering->semaphore_mboxes[0]
84734a04 759 = I915_READ(RING_SYNC_0(ring->mmio_base));
362b8af7 760 ering->semaphore_mboxes[1]
84734a04 761 = I915_READ(RING_SYNC_1(ring->mmio_base));
362b8af7
BW		 762 ering->semaphore_seqno[0] = ring->sync_seqno[0];
763 ering->semaphore_seqno[1] = ring->sync_seqno[1];
84734a04
MK		 764 }
765
4e5aabfd 766 if (HAS_VEBOX(dev)) {
362b8af7 767 ering->semaphore_mboxes[2] =
4e5aabfd 768 I915_READ(RING_SYNC_2(ring->mmio_base));
362b8af7 769 ering->semaphore_seqno[2] = ring->sync_seqno[2];
4e5aabfd
BW		 770 }
771
84734a04 772 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 773 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
774 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
775 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
776 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
777 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
778 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
3dda20a9 779 if (INTEL_INFO(dev)->gen >= 8)
362b8af7
BW		 780 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
781 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 782 } else {
362b8af7
BW		 783 ering->faddr = I915_READ(DMA_FADD_I8XX);
784 ering->ipeir = I915_READ(IPEIR);
785 ering->ipehr = I915_READ(IPEHR);
786 ering->instdone = I915_READ(INSTDONE);
84734a04
MK		 787 }
788
362b8af7
BW		 789 ering->waiting = waitqueue_active(&ring->irq_queue);
790 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
791 ering->seqno = ring->get_seqno(ring, false);
792 ering->acthd = intel_ring_get_active_head(ring);
793 ering->head = I915_READ_HEAD(ring);
794 ering->tail = I915_READ_TAIL(ring);
795 ering->ctl = I915_READ_CTL(ring);
84734a04 796
f3ce3821
CW		 797 if (I915_NEED_GFX_HWS(dev)) {
798 int mmio;
799
800 if (IS_GEN7(dev)) {
801 switch (ring->id) {
802 default:
803 case RCS:
804 mmio = RENDER_HWS_PGA_GEN7;
805 break;
806 case BCS:
807 mmio = BLT_HWS_PGA_GEN7;
808 break;
809 case VCS:
810 mmio = BSD_HWS_PGA_GEN7;
811 break;
812 case VECS:
813 mmio = VEBOX_HWS_PGA_GEN7;
814 break;
815 }
816 } else if (IS_GEN6(ring->dev)) {
817 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
818 } else {
819 /* XXX: gen8 returns to sanity */
820 mmio = RING_HWS_PGA(ring->mmio_base);
821 }
822
362b8af7 823 ering->hws = I915_READ(mmio);
f3ce3821
CW		 824 }
825
362b8af7
BW		 826 ering->cpu_ring_head = ring->head;
827 ering->cpu_ring_tail = ring->tail;
da661464 828
362b8af7
BW		 829 ering->hangcheck_score = ring->hangcheck.score;
830 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 831
832 if (USES_PPGTT(dev)) {
833 int i;
834
835 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
836
837 switch (INTEL_INFO(dev)->gen) {
838 case 8:
839 for (i = 0; i < 4; i++) {
840 ering->vm_info.pdp[i] =
841 I915_READ(GEN8_RING_PDP_UDW(ring, i));
842 ering->vm_info.pdp[i] <<= 32;
843 ering->vm_info.pdp[i] |=
844 I915_READ(GEN8_RING_PDP_LDW(ring, i));
845 }
846 break;
847 case 7:
848 ering->vm_info.pp_dir_base = RING_PP_DIR_BASE(ring);
849 break;
850 case 6:
851 ering->vm_info.pp_dir_base = RING_PP_DIR_BASE_READ(ring);
852 break;
853 }
854 }
84734a04
MK		 855}
856
857
858static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
859 struct drm_i915_error_state *error,
860 struct drm_i915_error_ring *ering)
861{
862 struct drm_i915_private *dev_priv = ring->dev->dev_private;
863 struct drm_i915_gem_object *obj;
864
865 /* Currently render ring is the only HW context user */
866 if (ring->id != RCS || !error->ccid)
867 return;
868
869 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
870 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
871 ering->ctx = i915_error_object_create_sized(dev_priv,
a7b91078
BW		 872 obj,
873 &dev_priv->gtt.base,
874 1);
84734a04
MK		 875 break;
876 }
877 }
878}
879
880static void i915_gem_record_rings(struct drm_device *dev,
881 struct drm_i915_error_state *error)
882{
883 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 884 struct drm_i915_gem_request *request;
885 int i, count;
886
372fbb8e
CW		 887 for (i = 0; i < I915_NUM_RINGS; i++) {
888 struct intel_ring_buffer *ring = &dev_priv->ring[i];
889
890 if (ring->dev == NULL)
891 continue;
892
893 error->ring[i].valid = true;
894
362b8af7 895 i915_record_ring_state(dev, ring, &error->ring[i]);
84734a04 896
ab0e7ff9
CW		 897 error->ring[i].pid = -1;
898 request = i915_gem_find_active_request(ring);
899 if (request) {
900 /* We need to copy these to an anonymous buffer
901 * as the simplest method to avoid being overwritten
902 * by userspace.
903 */
904 error->ring[i].batchbuffer =
905 i915_error_object_create(dev_priv,
906 request->batch_obj,
907 request->ctx ?
908 request->ctx->vm :
909 &dev_priv->gtt.base);
910
911 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
912 ring->scratch.obj)
913 error->ring[i].wa_batchbuffer =
914 i915_error_ggtt_object_create(dev_priv,
915 ring->scratch.obj);
916
917 if (request->file_priv) {
918 struct task_struct *task;
919
920 rcu_read_lock();
921 task = pid_task(request->file_priv->file->pid,
922 PIDTYPE_PID);
923 if (task) {
924 strcpy(error->ring[i].comm, task->comm);
925 error->ring[i].pid = task->pid;
926 }
927 rcu_read_unlock();
928 }
929 }
84734a04
MK		 930
931 error->ring[i].ringbuffer =
a7b91078 932 i915_error_ggtt_object_create(dev_priv, ring->obj);
84734a04 933
f3ce3821 934 if (ring->status_page.obj)
362b8af7 935 error->ring[i].hws_page =
f3ce3821 936 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 937
938 i915_gem_record_active_context(ring, error, &error->ring[i]);
939
940 count = 0;
941 list_for_each_entry(request, &ring->request_list, list)
942 count++;
943
944 error->ring[i].num_requests = count;
945 error->ring[i].requests =
a1e22653 946 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 947 GFP_ATOMIC);
948 if (error->ring[i].requests == NULL) {
949 error->ring[i].num_requests = 0;
950 continue;
951 }
952
953 count = 0;
954 list_for_each_entry(request, &ring->request_list, list) {
955 struct drm_i915_error_request *erq;
956
957 erq = &error->ring[i].requests[count++];
958 erq->seqno = request->seqno;
959 erq->jiffies = request->emitted_jiffies;
960 erq->tail = request->tail;
961 }
962 }
963}
964
95f5301d
BW		 965/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
966 * VM.
967 */
968static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
969 struct drm_i915_error_state *error,
970 struct i915_address_space *vm,
971 const int ndx)
84734a04 972{
95f5301d 973 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 974 struct drm_i915_gem_object *obj;
95f5301d 975 struct i915_vma *vma;
84734a04
MK		 976 int i;
977
978 i = 0;
ca191b13 979 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 980 i++;
95f5301d 981 error->active_bo_count[ndx] = i;
84734a04 982 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
d7f46fc4 983 if (i915_gem_obj_is_pinned(obj))
84734a04 984 i++;
95f5301d 985 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 986
987 if (i) {
a1e22653 988 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 989 if (active_bo)
990 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 991 }
992
95f5301d
BW		 993 if (active_bo)
994 error->active_bo_count[ndx] =
995 capture_active_bo(active_bo,
996 error->active_bo_count[ndx],
5cef07e1 997 &vm->active_list);
84734a04 998
95f5301d
BW		 999 if (pinned_bo)
1000 error->pinned_bo_count[ndx] =
1001 capture_pinned_bo(pinned_bo,
1002 error->pinned_bo_count[ndx],
84734a04 1003 &dev_priv->mm.bound_list);
95f5301d
BW		 1004 error->active_bo[ndx] = active_bo;
1005 error->pinned_bo[ndx] = pinned_bo;
1006}
1007
1008static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1009 struct drm_i915_error_state *error)
1010{
1011 struct i915_address_space *vm;
1012 int cnt = 0, i = 0;
1013
1014 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1015 cnt++;
1016
95f5301d
BW		 1017 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1018 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1019 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1020 GFP_ATOMIC);
1021 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1022 GFP_ATOMIC);
1023
1024 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1025 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 1026}
1027
1d762aad
BW		 1028/* Capture all registers which don't fit into another category. */
1029static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1030 struct drm_i915_error_state *error)
84734a04 1031{
1d762aad 1032 struct drm_device *dev = dev_priv->dev;
84734a04
MK		 1033 int pipe;
1034
654c90c6
BW		 1035 /* General organization
1036 * 1. Registers specific to a single generation
1037 * 2. Registers which belong to multiple generations
1038 * 3. Feature specific registers.
1039 * 4. Everything else
1040 * Please try to follow the order.
1041 */
84734a04 1042
654c90c6
BW		 1043 /* 1: Registers specific to a single generation */
1044 if (IS_VALLEYVIEW(dev)) {
84734a04 1045 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
654c90c6
BW		 1046 error->forcewake = I915_READ(FORCEWAKE_VLV);
1047 }
84734a04 1048
654c90c6
BW		 1049 if (IS_GEN7(dev))
1050 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1051
91ec5d11 1052 if (IS_GEN6(dev)) {
84734a04 1053 error->forcewake = I915_READ(FORCEWAKE);
91ec5d11
BW		 1054 error->gab_ctl = I915_READ(GAB_CTL);
1055 error->gfx_mode = I915_READ(GFX_MODE);
1056 }
84734a04 1057
654c90c6
BW		 1058 if (IS_GEN2(dev))
1059 error->ier = I915_READ16(IER);
1060
1061 /* 2: Registers which belong to multiple generations */
1062 if (INTEL_INFO(dev)->gen >= 7)
1063 error->forcewake = I915_READ(FORCEWAKE_MT);
84734a04
MK		 1064
1065 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1066 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1067 error->error = I915_READ(ERROR_GEN6);
1068 error->done_reg = I915_READ(DONE_REG);
1069 }
1070
654c90c6 1071 /* 3: Feature specific registers */
91ec5d11
BW		 1072 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1073 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1074 error->gac_eco = I915_READ(GAC_ECO_BITS);
1075 }
1076
1077 /* 4: Everything else */
654c90c6
BW		 1078 if (HAS_HW_CONTEXTS(dev))
1079 error->ccid = I915_READ(CCID);
1080
1081 if (HAS_PCH_SPLIT(dev))
1082 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1083 else {
1084 error->ier = I915_READ(IER);
1085 for_each_pipe(pipe)
1086 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1087 }
1088
1089 /* 4: Everything else */
1090 error->eir = I915_READ(EIR);
1091 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1092
1093 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1094}
1095
cb383002 1096static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1097 struct drm_i915_error_state *error,
1098 bool wedged,
1099 const char *error_msg)
cb383002
MK		 1100{
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 u32 ecode;
58174462 1103 int ring_id = -1, len;
cb383002
MK		 1104
1105 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1106
58174462
MK		 1107 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1108 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1109
1110 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1111 len += scnprintf(error->error_msg + len,
1112 sizeof(error->error_msg) - len,
1113 ", in %s [%d]",
1114 error->ring[ring_id].comm,
1115 error->ring[ring_id].pid);
1116
1117 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1118 ", reason: %s, action: %s",
1119 error_msg,
1120 wedged ? "reset" : "continue");
cb383002
MK		 1121}
1122
1d762aad
BW		 1123/**
1124 * i915_capture_error_state - capture an error record for later analysis
1125 * @dev: drm device
1126 *
1127 * Should be called when an error is detected (either a hang or an error
1128 * interrupt) to capture error state from the time of the error. Fills
1129 * out a structure which becomes available in debugfs for user level tools
1130 * to pick up.
1131 */
58174462
MK		 1132void i915_capture_error_state(struct drm_device *dev, bool wedged,
1133 const char *error_msg)
1d762aad 1134{
53a4c6b2 1135 static bool warned;
1d762aad
BW		 1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 struct drm_i915_error_state *error;
1138 unsigned long flags;
1d762aad
BW		 1139
1140 /* Account for pipe specific data like PIPE*STAT */
1141 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1142 if (!error) {
1143 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1144 return;
1145 }
1146
011cf577
BW		 1147 kref_init(&error->ref);
1148
1149 i915_capture_reg_state(dev_priv, error);
1150 i915_gem_capture_buffers(dev_priv, error);
1151 i915_gem_record_fences(dev, error);
1152 i915_gem_record_rings(dev, error);
1d762aad 1153
84734a04
MK		 1154 do_gettimeofday(&error->time);
1155
1156 error->overlay = intel_overlay_capture_error_state(dev);
1157 error->display = intel_display_capture_error_state(dev);
1158
58174462 1159 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1160 DRM_INFO("%s\n", error->error_msg);
1161
84734a04
MK		 1162 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1163 if (dev_priv->gpu_error.first_error == NULL) {
1164 dev_priv->gpu_error.first_error = error;
1165 error = NULL;
1166 }
1167 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1168
cb383002 1169 if (error) {
84734a04 1170 i915_error_state_free(&error->ref);
cb383002
MK		 1171 return;
1172 }
1173
1174 if (!warned) {
1175 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1176 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1177 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1178 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1179 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1180 warned = true;
1181 }
84734a04
MK		 1182}
1183
1184void i915_error_state_get(struct drm_device *dev,
1185 struct i915_error_state_file_priv *error_priv)
1186{
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 unsigned long flags;
1189
1190 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1191 error_priv->error = dev_priv->gpu_error.first_error;
1192 if (error_priv->error)
1193 kref_get(&error_priv->error->ref);
1194 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1195
1196}
1197
1198void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1199{
1200 if (error_priv->error)
1201 kref_put(&error_priv->error->ref, i915_error_state_free);
1202}
1203
1204void i915_destroy_error_state(struct drm_device *dev)
1205{
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 struct drm_i915_error_state *error;
1208 unsigned long flags;
1209
1210 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1211 error = dev_priv->gpu_error.first_error;
1212 dev_priv->gpu_error.first_error = NULL;
1213 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1214
1215 if (error)
1216 kref_put(&error->ref, i915_error_state_free);
1217}
1218
1219const char *i915_cache_level_str(int type)
1220{
1221 switch (type) {
1222 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1223 case I915_CACHE_LLC: return " snooped or LLC";
1224 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1225 case I915_CACHE_WT: return " WT";
84734a04
MK		 1226 default: return "";
1227 }
1228}
1229
1230/* NB: please notice the memset */
1231void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1232{
1233 struct drm_i915_private *dev_priv = dev->dev_private;
1234 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1235
1236 switch (INTEL_INFO(dev)->gen) {
1237 case 2:
1238 case 3:
1239 instdone[0] = I915_READ(INSTDONE);
1240 break;
1241 case 4:
1242 case 5:
1243 case 6:
1244 instdone[0] = I915_READ(INSTDONE_I965);
1245 instdone[1] = I915_READ(INSTDONE1);
1246 break;
1247 default:
1248 WARN_ONCE(1, "Unsupported platform\n");
1249 case 7:
d0582ed2 1250 case 8:
84734a04
MK		 1251 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1252 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1253 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1254 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1255 break;
1256 }
1257}
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