]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/i915_gpu_error.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Identify active VM for batchbuffer capture
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47}
48
49static const char *pin_flag(int pinned)
50{
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57}
58
59static const char *tiling_flag(int tiling)
60{
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67}
68
69static const char *dirty_flag(int dirty)
70{
71 return dirty ? " dirty" : "";
72}
73
74static const char *purgeable_flag(int purgeable)
75{
76 return purgeable ? " purgeable" : "";
77}
78
79static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80{
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91}
92
93static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95{
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108}
109
110static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112{
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134}
135
136static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138{
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
e29bb4eb
CW		 146 va_list tmp;
147
148 va_copy(tmp, args);
149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
84734a04
MK		 150 return;
151 }
152
153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
154 if (len >= e->size - e->bytes)
155 len = e->size - e->bytes - 1;
156
157 __i915_error_advance(e, len);
158}
159
160static void i915_error_puts(struct drm_i915_error_state_buf *e,
161 const char *str)
162{
163 unsigned len;
164
165 if (!__i915_error_ok(e))
166 return;
167
168 len = strlen(str);
169
170 /* Seek the first printf which is hits start position */
171 if (e->pos < e->start) {
172 if (!__i915_error_seek(e, len))
173 return;
174 }
175
176 if (len >= e->size - e->bytes)
177 len = e->size - e->bytes - 1;
178 memcpy(e->buf + e->bytes, str, len);
179
180 __i915_error_advance(e, len);
181}
182
183#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
184#define err_puts(e, s) i915_error_puts(e, s)
185
186static void print_error_buffers(struct drm_i915_error_state_buf *m,
187 const char *name,
188 struct drm_i915_error_buffer *err,
189 int count)
190{
191 err_printf(m, "%s [%d]:\n", name, count);
192
193 while (count--) {
194 err_printf(m, " %08x %8u %02x %02x %x %x",
195 err->gtt_offset,
196 err->size,
197 err->read_domains,
198 err->write_domain,
199 err->rseqno, err->wseqno);
200 err_puts(m, pin_flag(err->pinned));
201 err_puts(m, tiling_flag(err->tiling));
202 err_puts(m, dirty_flag(err->dirty));
203 err_puts(m, purgeable_flag(err->purgeable));
204 err_puts(m, err->ring != -1 ? " " : "");
205 err_puts(m, ring_str(err->ring));
206 err_puts(m, i915_cache_level_str(err->cache_level));
207
208 if (err->name)
209 err_printf(m, " (name: %d)", err->name);
210 if (err->fence_reg != I915_FENCE_REG_NONE)
211 err_printf(m, " (fence: %d)", err->fence_reg);
212
213 err_puts(m, "\n");
214 err++;
215 }
216}
217
da661464
MK		 218static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
219{
220 switch (a) {
221 case HANGCHECK_IDLE:
222 return "idle";
223 case HANGCHECK_WAIT:
224 return "wait";
225 case HANGCHECK_ACTIVE:
226 return "active";
227 case HANGCHECK_KICK:
228 return "kick";
229 case HANGCHECK_HUNG:
230 return "hung";
231 }
232
233 return "unknown";
234}
235
84734a04
MK		 236static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
237 struct drm_device *dev,
238 struct drm_i915_error_state *error,
239 unsigned ring)
240{
241 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
242 err_printf(m, "%s command stream:\n", ring_str(ring));
243 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
244 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
245 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
246 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
247 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
248 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
250 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
94e39e28
CW		 252 if (INTEL_INFO(dev)->gen >= 4)
253 err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]);
84734a04
MK		 254 if (INTEL_INFO(dev)->gen >= 4)
255 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
256 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
257 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
258 if (INTEL_INFO(dev)->gen >= 6) {
259 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
260 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
261 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
262 error->semaphore_mboxes[ring][0],
263 error->semaphore_seqno[ring][0]);
264 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
265 error->semaphore_mboxes[ring][1],
266 error->semaphore_seqno[ring][1]);
4e5aabfd
BW		 267 if (HAS_VEBOX(dev)) {
268 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
269 error->semaphore_mboxes[ring][2],
270 error->semaphore_seqno[ring][2]);
271 }
84734a04
MK		 272 }
273 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
274 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
275 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
276 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
da661464
MK		 277 err_printf(m, " hangcheck: %s [%d]\n",
278 hangcheck_action_to_str(error->hangcheck_action[ring]),
279 error->hangcheck_score[ring]);
84734a04
MK		 280}
281
282void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
283{
284 va_list args;
285
286 va_start(args, f);
287 i915_error_vprintf(e, f, args);
288 va_end(args);
289}
290
291int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
292 const struct i915_error_state_file_priv *error_priv)
293{
294 struct drm_device *dev = error_priv->dev;
295 drm_i915_private_t *dev_priv = dev->dev_private;
296 struct drm_i915_error_state *error = error_priv->error;
297 struct intel_ring_buffer *ring;
298 int i, j, page, offset, elt;
299
300 if (!error) {
301 err_printf(m, "no error state collected\n");
302 goto out;
303 }
304
305 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
306 error->time.tv_usec);
307 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ffbab09b 308 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 309 err_printf(m, "EIR: 0x%08x\n", error->eir);
310 err_printf(m, "IER: 0x%08x\n", error->ier);
311 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
312 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
313 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
314 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 315 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 316
317 for (i = 0; i < dev_priv->num_fence_regs; i++)
318 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
319
320 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
321 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
322 error->extra_instdone[i]);
323
324 if (INTEL_INFO(dev)->gen >= 6) {
325 err_printf(m, "ERROR: 0x%08x\n", error->error);
326 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
327 }
328
329 if (INTEL_INFO(dev)->gen == 7)
330 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
331
332 for_each_ring(ring, dev_priv, i)
333 i915_ring_error_state(m, dev, error, i);
334
335 if (error->active_bo)
336 print_error_buffers(m, "Active",
95f5301d
BW		 337 error->active_bo[0],
338 error->active_bo_count[0]);
84734a04
MK		 339
340 if (error->pinned_bo)
341 print_error_buffers(m, "Pinned",
95f5301d
BW		 342 error->pinned_bo[0],
343 error->pinned_bo_count[0]);
84734a04
MK		 344
345 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
346 struct drm_i915_error_object *obj;
347
348 if ((obj = error->ring[i].batchbuffer)) {
349 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
350 dev_priv->ring[i].name,
351 obj->gtt_offset);
352 offset = 0;
353 for (page = 0; page < obj->page_count; page++) {
354 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
355 err_printf(m, "%08x : %08x\n", offset,
356 obj->pages[page][elt]);
357 offset += 4;
358 }
359 }
360 }
361
362 if (error->ring[i].num_requests) {
363 err_printf(m, "%s --- %d requests\n",
364 dev_priv->ring[i].name,
365 error->ring[i].num_requests);
366 for (j = 0; j < error->ring[i].num_requests; j++) {
367 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
368 error->ring[i].requests[j].seqno,
369 error->ring[i].requests[j].jiffies,
370 error->ring[i].requests[j].tail);
371 }
372 }
373
374 if ((obj = error->ring[i].ringbuffer)) {
375 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
376 dev_priv->ring[i].name,
377 obj->gtt_offset);
378 offset = 0;
379 for (page = 0; page < obj->page_count; page++) {
380 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
381 err_printf(m, "%08x : %08x\n",
382 offset,
383 obj->pages[page][elt]);
384 offset += 4;
385 }
386 }
387 }
388
389 obj = error->ring[i].ctx;
390 if (obj) {
391 err_printf(m, "%s --- HW Context = 0x%08x\n",
392 dev_priv->ring[i].name,
393 obj->gtt_offset);
394 offset = 0;
395 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
396 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
397 offset,
398 obj->pages[0][elt],
399 obj->pages[0][elt+1],
400 obj->pages[0][elt+2],
401 obj->pages[0][elt+3]);
402 offset += 16;
403 }
404 }
405 }
406
407 if (error->overlay)
408 intel_overlay_print_error_state(m, error->overlay);
409
410 if (error->display)
411 intel_display_print_error_state(m, dev, error->display);
412
413out:
414 if (m->bytes == 0 && m->err)
415 return m->err;
416
417 return 0;
418}
419
420int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
421 size_t count, loff_t pos)
422{
423 memset(ebuf, 0, sizeof(*ebuf));
424
425 /* We need to have enough room to store any i915_error_state printf
426 * so that we can move it to start position.
427 */
428 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
429 ebuf->buf = kmalloc(ebuf->size,
430 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
431
432 if (ebuf->buf == NULL) {
433 ebuf->size = PAGE_SIZE;
434 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
435 }
436
437 if (ebuf->buf == NULL) {
438 ebuf->size = 128;
439 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
440 }
441
442 if (ebuf->buf == NULL)
443 return -ENOMEM;
444
445 ebuf->start = pos;
446
447 return 0;
448}
449
450static void i915_error_object_free(struct drm_i915_error_object *obj)
451{
452 int page;
453
454 if (obj == NULL)
455 return;
456
457 for (page = 0; page < obj->page_count; page++)
458 kfree(obj->pages[page]);
459
460 kfree(obj);
461}
462
463static void i915_error_state_free(struct kref *error_ref)
464{
465 struct drm_i915_error_state *error = container_of(error_ref,
466 typeof(*error), ref);
467 int i;
468
469 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
470 i915_error_object_free(error->ring[i].batchbuffer);
471 i915_error_object_free(error->ring[i].ringbuffer);
472 i915_error_object_free(error->ring[i].ctx);
473 kfree(error->ring[i].requests);
474 }
475
476 kfree(error->active_bo);
477 kfree(error->overlay);
478 kfree(error->display);
479 kfree(error);
480}
481
482static struct drm_i915_error_object *
483i915_error_object_create_sized(struct drm_i915_private *dev_priv,
484 struct drm_i915_gem_object *src,
a7b91078 485 struct i915_address_space *vm,
84734a04
MK		 486 const int num_pages)
487{
488 struct drm_i915_error_object *dst;
489 int i;
490 u32 reloc_offset;
491
492 if (src == NULL || src->pages == NULL)
493 return NULL;
494
495 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
496 if (dst == NULL)
497 return NULL;
498
a7b91078 499 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
84734a04
MK		 500 for (i = 0; i < num_pages; i++) {
501 unsigned long flags;
502 void *d;
503
504 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
505 if (d == NULL)
506 goto unwind;
507
508 local_irq_save(flags);
509 if (reloc_offset < dev_priv->gtt.mappable_end &&
496bfcb9
BW		 510 src->has_global_gtt_mapping &&
511 i915_is_ggtt(vm)) {
84734a04
MK		 512 void __iomem *s;
513
514 /* Simply ignore tiling or any overlapping fence.
515 * It's part of the error state, and this hopefully
516 * captures what the GPU read.
517 */
518
519 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
520 reloc_offset);
521 memcpy_fromio(d, s, PAGE_SIZE);
522 io_mapping_unmap_atomic(s);
523 } else if (src->stolen) {
524 unsigned long offset;
525
526 offset = dev_priv->mm.stolen_base;
527 offset += src->stolen->start;
528 offset += i << PAGE_SHIFT;
529
530 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
531 } else {
532 struct page *page;
533 void *s;
534
535 page = i915_gem_object_get_page(src, i);
536
537 drm_clflush_pages(&page, 1);
538
539 s = kmap_atomic(page);
540 memcpy(d, s, PAGE_SIZE);
541 kunmap_atomic(s);
542
543 drm_clflush_pages(&page, 1);
544 }
545 local_irq_restore(flags);
546
547 dst->pages[i] = d;
548
549 reloc_offset += PAGE_SIZE;
550 }
551 dst->page_count = num_pages;
552
553 return dst;
554
555unwind:
556 while (i--)
557 kfree(dst->pages[i]);
558 kfree(dst);
559 return NULL;
560}
a7b91078
BW		 561#define i915_error_object_create(dev_priv, src, vm) \
562 i915_error_object_create_sized((dev_priv), (src), (vm), \
563 (src)->base.size>>PAGE_SHIFT)
564
565#define i915_error_ggtt_object_create(dev_priv, src) \
566 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 567 (src)->base.size>>PAGE_SHIFT)
568
569static void capture_bo(struct drm_i915_error_buffer *err,
570 struct drm_i915_gem_object *obj)
571{
572 err->size = obj->base.size;
573 err->name = obj->base.name;
574 err->rseqno = obj->last_read_seqno;
575 err->wseqno = obj->last_write_seqno;
576 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
577 err->read_domains = obj->base.read_domains;
578 err->write_domain = obj->base.write_domain;
579 err->fence_reg = obj->fence_reg;
580 err->pinned = 0;
581 if (obj->pin_count > 0)
582 err->pinned = 1;
583 if (obj->user_pin_count > 0)
584 err->pinned = -1;
585 err->tiling = obj->tiling_mode;
586 err->dirty = obj->dirty;
587 err->purgeable = obj->madv != I915_MADV_WILLNEED;
588 err->ring = obj->ring ? obj->ring->id : -1;
589 err->cache_level = obj->cache_level;
590}
591
592static u32 capture_active_bo(struct drm_i915_error_buffer *err,
593 int count, struct list_head *head)
594{
ca191b13 595 struct i915_vma *vma;
84734a04
MK		 596 int i = 0;
597
ca191b13
BW		 598 list_for_each_entry(vma, head, mm_list) {
599 capture_bo(err++, vma->obj);
84734a04
MK		 600 if (++i == count)
601 break;
602 }
603
604 return i;
605}
606
607static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
608 int count, struct list_head *head)
609{
610 struct drm_i915_gem_object *obj;
611 int i = 0;
612
613 list_for_each_entry(obj, head, global_list) {
614 if (obj->pin_count == 0)
615 continue;
616
617 capture_bo(err++, obj);
618 if (++i == count)
619 break;
620 }
621
622 return i;
623}
624
625static void i915_gem_record_fences(struct drm_device *dev,
626 struct drm_i915_error_state *error)
627{
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 int i;
630
631 /* Fences */
632 switch (INTEL_INFO(dev)->gen) {
5ab31333 633 case 8:
84734a04
MK		 634 case 7:
635 case 6:
636 for (i = 0; i < dev_priv->num_fence_regs; i++)
637 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
638 break;
639 case 5:
640 case 4:
641 for (i = 0; i < 16; i++)
642 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
643 break;
644 case 3:
645 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
646 for (i = 0; i < 8; i++)
647 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
648 case 2:
649 for (i = 0; i < 8; i++)
650 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
651 break;
652
653 default:
654 BUG();
655 }
656}
657
685987c6
BW		 658/* This assumes all batchbuffers are executed from the PPGTT. It might have to
659 * change in the future. */
660static bool is_active_vm(struct i915_address_space *vm,
661 struct intel_ring_buffer *ring)
662{
663 struct drm_device *dev = vm->dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
665 struct i915_hw_ppgtt *ppgtt;
666
667 if (INTEL_INFO(dev)->gen < 7)
668 return i915_is_ggtt(vm);
669
670 /* FIXME: This ignores that the global gtt vm is also on this list. */
671 ppgtt = container_of(vm, struct i915_hw_ppgtt, base);
672
673 if (INTEL_INFO(dev)->gen >= 8) {
674 u64 pdp0 = (u64)I915_READ(GEN8_RING_PDP_UDW(ring, 0)) << 32;
675 pdp0 |= I915_READ(GEN8_RING_PDP_LDW(ring, 0));
676 return pdp0 == ppgtt->pd_dma_addr[0];
677 } else {
678 u32 pp_db;
679 pp_db = I915_READ(RING_PP_DIR_BASE(ring));
680 return (pp_db >> 10) == ppgtt->pd_offset;
681 }
682}
683
84734a04
MK		 684static struct drm_i915_error_object *
685i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
686 struct intel_ring_buffer *ring)
687{
ca191b13
BW		 688 struct i915_address_space *vm;
689 struct i915_vma *vma;
84734a04 690 struct drm_i915_gem_object *obj;
685987c6 691 bool found_active = false;
84734a04
MK		 692 u32 seqno;
693
694 if (!ring->get_seqno)
695 return NULL;
696
697 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
698 u32 acthd = I915_READ(ACTHD);
699
700 if (WARN_ON(ring->id != RCS))
701 return NULL;
702
0d1aacac 703 obj = ring->scratch.obj;
84734a04
MK		 704 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
705 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
a7b91078 706 return i915_error_ggtt_object_create(dev_priv, obj);
84734a04
MK		 707 }
708
709 seqno = ring->get_seqno(ring, false);
ca191b13 710 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
685987c6
BW		 711 if (!is_active_vm(vm, ring))
712 continue;
713
714 found_active = true;
715
ca191b13
BW		 716 list_for_each_entry(vma, &vm->active_list, mm_list) {
717 obj = vma->obj;
718 if (obj->ring != ring)
719 continue;
84734a04 720
ca191b13
BW		 721 if (i915_seqno_passed(seqno, obj->last_read_seqno))
722 continue;
84734a04 723
ca191b13
BW		 724 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
725 continue;
84734a04 726
ca191b13
BW		 727 /* We need to copy these to an anonymous buffer as the simplest
728 * method to avoid being overwritten by userspace.
729 */
a7b91078 730 return i915_error_object_create(dev_priv, obj, vm);
ca191b13 731 }
84734a04
MK		 732 }
733
685987c6 734 WARN_ON(!found_active);
84734a04
MK		 735 return NULL;
736}
737
738static void i915_record_ring_state(struct drm_device *dev,
739 struct drm_i915_error_state *error,
740 struct intel_ring_buffer *ring)
741{
742 struct drm_i915_private *dev_priv = dev->dev_private;
743
744 if (INTEL_INFO(dev)->gen >= 6) {
745 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
746 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
747 error->semaphore_mboxes[ring->id][0]
748 = I915_READ(RING_SYNC_0(ring->mmio_base));
749 error->semaphore_mboxes[ring->id][1]
750 = I915_READ(RING_SYNC_1(ring->mmio_base));
751 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
752 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
753 }
754
4e5aabfd
BW		 755 if (HAS_VEBOX(dev)) {
756 error->semaphore_mboxes[ring->id][2] =
757 I915_READ(RING_SYNC_2(ring->mmio_base));
758 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
759 }
760
84734a04
MK		 761 if (INTEL_INFO(dev)->gen >= 4) {
762 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
763 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
764 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
765 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
766 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
767 if (ring->id == RCS)
768 error->bbaddr = I915_READ64(BB_ADDR);
94e39e28 769 error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04
MK		 770 } else {
771 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
772 error->ipeir[ring->id] = I915_READ(IPEIR);
773 error->ipehr[ring->id] = I915_READ(IPEHR);
774 error->instdone[ring->id] = I915_READ(INSTDONE);
775 }
776
777 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
778 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
779 error->seqno[ring->id] = ring->get_seqno(ring, false);
780 error->acthd[ring->id] = intel_ring_get_active_head(ring);
781 error->head[ring->id] = I915_READ_HEAD(ring);
782 error->tail[ring->id] = I915_READ_TAIL(ring);
783 error->ctl[ring->id] = I915_READ_CTL(ring);
784
785 error->cpu_ring_head[ring->id] = ring->head;
786 error->cpu_ring_tail[ring->id] = ring->tail;
da661464
MK		 787
788 error->hangcheck_score[ring->id] = ring->hangcheck.score;
789 error->hangcheck_action[ring->id] = ring->hangcheck.action;
84734a04
MK		 790}
791
792
793static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
794 struct drm_i915_error_state *error,
795 struct drm_i915_error_ring *ering)
796{
797 struct drm_i915_private *dev_priv = ring->dev->dev_private;
798 struct drm_i915_gem_object *obj;
799
800 /* Currently render ring is the only HW context user */
801 if (ring->id != RCS || !error->ccid)
802 return;
803
804 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
805 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
806 ering->ctx = i915_error_object_create_sized(dev_priv,
a7b91078
BW		 807 obj,
808 &dev_priv->gtt.base,
809 1);
84734a04
MK		 810 break;
811 }
812 }
813}
814
815static void i915_gem_record_rings(struct drm_device *dev,
816 struct drm_i915_error_state *error)
817{
818 struct drm_i915_private *dev_priv = dev->dev_private;
819 struct intel_ring_buffer *ring;
820 struct drm_i915_gem_request *request;
821 int i, count;
822
823 for_each_ring(ring, dev_priv, i) {
824 i915_record_ring_state(dev, error, ring);
825
826 error->ring[i].batchbuffer =
827 i915_error_first_batchbuffer(dev_priv, ring);
828
829 error->ring[i].ringbuffer =
a7b91078 830 i915_error_ggtt_object_create(dev_priv, ring->obj);
84734a04
MK		 831
832
833 i915_gem_record_active_context(ring, error, &error->ring[i]);
834
835 count = 0;
836 list_for_each_entry(request, &ring->request_list, list)
837 count++;
838
839 error->ring[i].num_requests = count;
840 error->ring[i].requests =
a1e22653 841 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 842 GFP_ATOMIC);
843 if (error->ring[i].requests == NULL) {
844 error->ring[i].num_requests = 0;
845 continue;
846 }
847
848 count = 0;
849 list_for_each_entry(request, &ring->request_list, list) {
850 struct drm_i915_error_request *erq;
851
852 erq = &error->ring[i].requests[count++];
853 erq->seqno = request->seqno;
854 erq->jiffies = request->emitted_jiffies;
855 erq->tail = request->tail;
856 }
857 }
858}
859
95f5301d
BW		 860/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
861 * VM.
862 */
863static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
864 struct drm_i915_error_state *error,
865 struct i915_address_space *vm,
866 const int ndx)
84734a04 867{
95f5301d 868 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 869 struct drm_i915_gem_object *obj;
95f5301d 870 struct i915_vma *vma;
84734a04
MK		 871 int i;
872
873 i = 0;
ca191b13 874 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 875 i++;
95f5301d 876 error->active_bo_count[ndx] = i;
84734a04
MK		 877 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
878 if (obj->pin_count)
879 i++;
95f5301d 880 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 881
882 if (i) {
a1e22653 883 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 884 if (active_bo)
885 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 886 }
887
95f5301d
BW		 888 if (active_bo)
889 error->active_bo_count[ndx] =
890 capture_active_bo(active_bo,
891 error->active_bo_count[ndx],
5cef07e1 892 &vm->active_list);
84734a04 893
95f5301d
BW		 894 if (pinned_bo)
895 error->pinned_bo_count[ndx] =
896 capture_pinned_bo(pinned_bo,
897 error->pinned_bo_count[ndx],
84734a04 898 &dev_priv->mm.bound_list);
95f5301d
BW		 899 error->active_bo[ndx] = active_bo;
900 error->pinned_bo[ndx] = pinned_bo;
901}
902
903static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
904 struct drm_i915_error_state *error)
905{
906 struct i915_address_space *vm;
907 int cnt = 0, i = 0;
908
909 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
910 cnt++;
911
912 if (WARN(cnt > 1, "Multiple VMs not yet supported\n"))
913 cnt = 1;
914
915 vm = &dev_priv->gtt.base;
916
917 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
918 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
919 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
920 GFP_ATOMIC);
921 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
922 GFP_ATOMIC);
923
924 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
925 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 926}
927
928/**
929 * i915_capture_error_state - capture an error record for later analysis
930 * @dev: drm device
931 *
932 * Should be called when an error is detected (either a hang or an error
933 * interrupt) to capture error state from the time of the error. Fills
934 * out a structure which becomes available in debugfs for user level tools
935 * to pick up.
936 */
937void i915_capture_error_state(struct drm_device *dev)
938{
939 struct drm_i915_private *dev_priv = dev->dev_private;
940 struct drm_i915_error_state *error;
941 unsigned long flags;
942 int pipe;
943
944 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
945 error = dev_priv->gpu_error.first_error;
946 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
947 if (error)
948 return;
949
950 /* Account for pipe specific data like PIPE*STAT */
951 error = kzalloc(sizeof(*error), GFP_ATOMIC);
952 if (!error) {
953 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
954 return;
955 }
956
f4689801
DV		 957 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
958 dev->primary->index);
959 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
960 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
961 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
962 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
84734a04
MK		 963
964 kref_init(&error->ref);
965 error->eir = I915_READ(EIR);
966 error->pgtbl_er = I915_READ(PGTBL_ER);
967 if (HAS_HW_CONTEXTS(dev))
968 error->ccid = I915_READ(CCID);
969
970 if (HAS_PCH_SPLIT(dev))
971 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
972 else if (IS_VALLEYVIEW(dev))
973 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
974 else if (IS_GEN2(dev))
975 error->ier = I915_READ16(IER);
976 else
977 error->ier = I915_READ(IER);
978
979 if (INTEL_INFO(dev)->gen >= 6)
980 error->derrmr = I915_READ(DERRMR);
981
982 if (IS_VALLEYVIEW(dev))
983 error->forcewake = I915_READ(FORCEWAKE_VLV);
984 else if (INTEL_INFO(dev)->gen >= 7)
985 error->forcewake = I915_READ(FORCEWAKE_MT);
986 else if (INTEL_INFO(dev)->gen == 6)
987 error->forcewake = I915_READ(FORCEWAKE);
988
989 if (!HAS_PCH_SPLIT(dev))
990 for_each_pipe(pipe)
991 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
992
993 if (INTEL_INFO(dev)->gen >= 6) {
994 error->error = I915_READ(ERROR_GEN6);
995 error->done_reg = I915_READ(DONE_REG);
996 }
997
998 if (INTEL_INFO(dev)->gen == 7)
999 error->err_int = I915_READ(GEN7_ERR_INT);
1000
1001 i915_get_extra_instdone(dev, error->extra_instdone);
1002
1003 i915_gem_capture_buffers(dev_priv, error);
1004 i915_gem_record_fences(dev, error);
1005 i915_gem_record_rings(dev, error);
1006
1007 do_gettimeofday(&error->time);
1008
1009 error->overlay = intel_overlay_capture_error_state(dev);
1010 error->display = intel_display_capture_error_state(dev);
1011
1012 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1013 if (dev_priv->gpu_error.first_error == NULL) {
1014 dev_priv->gpu_error.first_error = error;
1015 error = NULL;
1016 }
1017 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1018
1019 if (error)
1020 i915_error_state_free(&error->ref);
1021}
1022
1023void i915_error_state_get(struct drm_device *dev,
1024 struct i915_error_state_file_priv *error_priv)
1025{
1026 struct drm_i915_private *dev_priv = dev->dev_private;
1027 unsigned long flags;
1028
1029 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1030 error_priv->error = dev_priv->gpu_error.first_error;
1031 if (error_priv->error)
1032 kref_get(&error_priv->error->ref);
1033 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1034
1035}
1036
1037void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1038{
1039 if (error_priv->error)
1040 kref_put(&error_priv->error->ref, i915_error_state_free);
1041}
1042
1043void i915_destroy_error_state(struct drm_device *dev)
1044{
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046 struct drm_i915_error_state *error;
1047 unsigned long flags;
1048
1049 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1050 error = dev_priv->gpu_error.first_error;
1051 dev_priv->gpu_error.first_error = NULL;
1052 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1053
1054 if (error)
1055 kref_put(&error->ref, i915_error_state_free);
1056}
1057
1058const char *i915_cache_level_str(int type)
1059{
1060 switch (type) {
1061 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1062 case I915_CACHE_LLC: return " snooped or LLC";
1063 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1064 case I915_CACHE_WT: return " WT";
84734a04
MK		 1065 default: return "";
1066 }
1067}
1068
1069/* NB: please notice the memset */
1070void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1071{
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1074
1075 switch (INTEL_INFO(dev)->gen) {
1076 case 2:
1077 case 3:
1078 instdone[0] = I915_READ(INSTDONE);
1079 break;
1080 case 4:
1081 case 5:
1082 case 6:
1083 instdone[0] = I915_READ(INSTDONE_I965);
1084 instdone[1] = I915_READ(INSTDONE1);
1085 break;
1086 default:
1087 WARN_ONCE(1, "Unsupported platform\n");
1088 case 7:
d0582ed2 1089 case 8:
84734a04
MK		 1090 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1091 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1092 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1093 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1094 break;
1095 }
1096}
ubuntu-bionic-kernel mirror