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drm/i915: include hangcheck action and score in error_state
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47}
48
49static const char *pin_flag(int pinned)
50{
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57}
58
59static const char *tiling_flag(int tiling)
60{
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67}
68
69static const char *dirty_flag(int dirty)
70{
71 return dirty ? " dirty" : "";
72}
73
74static const char *purgeable_flag(int purgeable)
75{
76 return purgeable ? " purgeable" : "";
77}
78
79static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80{
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91}
92
93static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95{
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108}
109
110static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112{
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134}
135
136static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138{
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
146 len = vsnprintf(NULL, 0, f, args);
147 if (!__i915_error_seek(e, len))
148 return;
149 }
150
151 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
152 if (len >= e->size - e->bytes)
153 len = e->size - e->bytes - 1;
154
155 __i915_error_advance(e, len);
156}
157
158static void i915_error_puts(struct drm_i915_error_state_buf *e,
159 const char *str)
160{
161 unsigned len;
162
163 if (!__i915_error_ok(e))
164 return;
165
166 len = strlen(str);
167
168 /* Seek the first printf which is hits start position */
169 if (e->pos < e->start) {
170 if (!__i915_error_seek(e, len))
171 return;
172 }
173
174 if (len >= e->size - e->bytes)
175 len = e->size - e->bytes - 1;
176 memcpy(e->buf + e->bytes, str, len);
177
178 __i915_error_advance(e, len);
179}
180
181#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
182#define err_puts(e, s) i915_error_puts(e, s)
183
184static void print_error_buffers(struct drm_i915_error_state_buf *m,
185 const char *name,
186 struct drm_i915_error_buffer *err,
187 int count)
188{
189 err_printf(m, "%s [%d]:\n", name, count);
190
191 while (count--) {
192 err_printf(m, " %08x %8u %02x %02x %x %x",
193 err->gtt_offset,
194 err->size,
195 err->read_domains,
196 err->write_domain,
197 err->rseqno, err->wseqno);
198 err_puts(m, pin_flag(err->pinned));
199 err_puts(m, tiling_flag(err->tiling));
200 err_puts(m, dirty_flag(err->dirty));
201 err_puts(m, purgeable_flag(err->purgeable));
202 err_puts(m, err->ring != -1 ? " " : "");
203 err_puts(m, ring_str(err->ring));
204 err_puts(m, i915_cache_level_str(err->cache_level));
205
206 if (err->name)
207 err_printf(m, " (name: %d)", err->name);
208 if (err->fence_reg != I915_FENCE_REG_NONE)
209 err_printf(m, " (fence: %d)", err->fence_reg);
210
211 err_puts(m, "\n");
212 err++;
213 }
214}
215
da661464
MK		 216static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
217{
218 switch (a) {
219 case HANGCHECK_IDLE:
220 return "idle";
221 case HANGCHECK_WAIT:
222 return "wait";
223 case HANGCHECK_ACTIVE:
224 return "active";
225 case HANGCHECK_KICK:
226 return "kick";
227 case HANGCHECK_HUNG:
228 return "hung";
229 }
230
231 return "unknown";
232}
233
84734a04
MK		 234static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
235 struct drm_device *dev,
236 struct drm_i915_error_state *error,
237 unsigned ring)
238{
239 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
240 err_printf(m, "%s command stream:\n", ring_str(ring));
241 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
242 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
243 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
244 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
245 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
246 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
247 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
248 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
249 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
250
251 if (INTEL_INFO(dev)->gen >= 4)
252 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
253 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
254 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
255 if (INTEL_INFO(dev)->gen >= 6) {
256 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
257 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
258 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
259 error->semaphore_mboxes[ring][0],
260 error->semaphore_seqno[ring][0]);
261 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
262 error->semaphore_mboxes[ring][1],
263 error->semaphore_seqno[ring][1]);
4e5aabfd
BW		 264 if (HAS_VEBOX(dev)) {
265 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
266 error->semaphore_mboxes[ring][2],
267 error->semaphore_seqno[ring][2]);
268 }
84734a04
MK		 269 }
270 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
271 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
272 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
273 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
da661464
MK		 274 err_printf(m, " hangcheck: %s [%d]\n",
275 hangcheck_action_to_str(error->hangcheck_action[ring]),
276 error->hangcheck_score[ring]);
84734a04
MK		 277}
278
279void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
280{
281 va_list args;
282
283 va_start(args, f);
284 i915_error_vprintf(e, f, args);
285 va_end(args);
286}
287
288int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
289 const struct i915_error_state_file_priv *error_priv)
290{
291 struct drm_device *dev = error_priv->dev;
292 drm_i915_private_t *dev_priv = dev->dev_private;
293 struct drm_i915_error_state *error = error_priv->error;
294 struct intel_ring_buffer *ring;
295 int i, j, page, offset, elt;
296
297 if (!error) {
298 err_printf(m, "no error state collected\n");
299 goto out;
300 }
301
302 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
303 error->time.tv_usec);
304 err_printf(m, "Kernel: " UTS_RELEASE "\n");
305 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
306 err_printf(m, "EIR: 0x%08x\n", error->eir);
307 err_printf(m, "IER: 0x%08x\n", error->ier);
308 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
309 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
310 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
311 err_printf(m, "CCID: 0x%08x\n", error->ccid);
312
313 for (i = 0; i < dev_priv->num_fence_regs; i++)
314 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
315
316 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
317 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
318 error->extra_instdone[i]);
319
320 if (INTEL_INFO(dev)->gen >= 6) {
321 err_printf(m, "ERROR: 0x%08x\n", error->error);
322 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
323 }
324
325 if (INTEL_INFO(dev)->gen == 7)
326 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
327
328 for_each_ring(ring, dev_priv, i)
329 i915_ring_error_state(m, dev, error, i);
330
331 if (error->active_bo)
332 print_error_buffers(m, "Active",
95f5301d
BW		 333 error->active_bo[0],
334 error->active_bo_count[0]);
84734a04
MK		 335
336 if (error->pinned_bo)
337 print_error_buffers(m, "Pinned",
95f5301d
BW		 338 error->pinned_bo[0],
339 error->pinned_bo_count[0]);
84734a04
MK		 340
341 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
342 struct drm_i915_error_object *obj;
343
344 if ((obj = error->ring[i].batchbuffer)) {
345 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
346 dev_priv->ring[i].name,
347 obj->gtt_offset);
348 offset = 0;
349 for (page = 0; page < obj->page_count; page++) {
350 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
351 err_printf(m, "%08x : %08x\n", offset,
352 obj->pages[page][elt]);
353 offset += 4;
354 }
355 }
356 }
357
358 if (error->ring[i].num_requests) {
359 err_printf(m, "%s --- %d requests\n",
360 dev_priv->ring[i].name,
361 error->ring[i].num_requests);
362 for (j = 0; j < error->ring[i].num_requests; j++) {
363 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
364 error->ring[i].requests[j].seqno,
365 error->ring[i].requests[j].jiffies,
366 error->ring[i].requests[j].tail);
367 }
368 }
369
370 if ((obj = error->ring[i].ringbuffer)) {
371 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
372 dev_priv->ring[i].name,
373 obj->gtt_offset);
374 offset = 0;
375 for (page = 0; page < obj->page_count; page++) {
376 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
377 err_printf(m, "%08x : %08x\n",
378 offset,
379 obj->pages[page][elt]);
380 offset += 4;
381 }
382 }
383 }
384
385 obj = error->ring[i].ctx;
386 if (obj) {
387 err_printf(m, "%s --- HW Context = 0x%08x\n",
388 dev_priv->ring[i].name,
389 obj->gtt_offset);
390 offset = 0;
391 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
392 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
393 offset,
394 obj->pages[0][elt],
395 obj->pages[0][elt+1],
396 obj->pages[0][elt+2],
397 obj->pages[0][elt+3]);
398 offset += 16;
399 }
400 }
401 }
402
403 if (error->overlay)
404 intel_overlay_print_error_state(m, error->overlay);
405
406 if (error->display)
407 intel_display_print_error_state(m, dev, error->display);
408
409out:
410 if (m->bytes == 0 && m->err)
411 return m->err;
412
413 return 0;
414}
415
416int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
417 size_t count, loff_t pos)
418{
419 memset(ebuf, 0, sizeof(*ebuf));
420
421 /* We need to have enough room to store any i915_error_state printf
422 * so that we can move it to start position.
423 */
424 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
425 ebuf->buf = kmalloc(ebuf->size,
426 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
427
428 if (ebuf->buf == NULL) {
429 ebuf->size = PAGE_SIZE;
430 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
431 }
432
433 if (ebuf->buf == NULL) {
434 ebuf->size = 128;
435 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
436 }
437
438 if (ebuf->buf == NULL)
439 return -ENOMEM;
440
441 ebuf->start = pos;
442
443 return 0;
444}
445
446static void i915_error_object_free(struct drm_i915_error_object *obj)
447{
448 int page;
449
450 if (obj == NULL)
451 return;
452
453 for (page = 0; page < obj->page_count; page++)
454 kfree(obj->pages[page]);
455
456 kfree(obj);
457}
458
459static void i915_error_state_free(struct kref *error_ref)
460{
461 struct drm_i915_error_state *error = container_of(error_ref,
462 typeof(*error), ref);
463 int i;
464
465 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
466 i915_error_object_free(error->ring[i].batchbuffer);
467 i915_error_object_free(error->ring[i].ringbuffer);
468 i915_error_object_free(error->ring[i].ctx);
469 kfree(error->ring[i].requests);
470 }
471
472 kfree(error->active_bo);
473 kfree(error->overlay);
474 kfree(error->display);
475 kfree(error);
476}
477
478static struct drm_i915_error_object *
479i915_error_object_create_sized(struct drm_i915_private *dev_priv,
480 struct drm_i915_gem_object *src,
481 const int num_pages)
482{
483 struct drm_i915_error_object *dst;
484 int i;
485 u32 reloc_offset;
486
487 if (src == NULL || src->pages == NULL)
488 return NULL;
489
490 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
491 if (dst == NULL)
492 return NULL;
493
494 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
495 for (i = 0; i < num_pages; i++) {
496 unsigned long flags;
497 void *d;
498
499 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
500 if (d == NULL)
501 goto unwind;
502
503 local_irq_save(flags);
504 if (reloc_offset < dev_priv->gtt.mappable_end &&
505 src->has_global_gtt_mapping) {
506 void __iomem *s;
507
508 /* Simply ignore tiling or any overlapping fence.
509 * It's part of the error state, and this hopefully
510 * captures what the GPU read.
511 */
512
513 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
514 reloc_offset);
515 memcpy_fromio(d, s, PAGE_SIZE);
516 io_mapping_unmap_atomic(s);
517 } else if (src->stolen) {
518 unsigned long offset;
519
520 offset = dev_priv->mm.stolen_base;
521 offset += src->stolen->start;
522 offset += i << PAGE_SHIFT;
523
524 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
525 } else {
526 struct page *page;
527 void *s;
528
529 page = i915_gem_object_get_page(src, i);
530
531 drm_clflush_pages(&page, 1);
532
533 s = kmap_atomic(page);
534 memcpy(d, s, PAGE_SIZE);
535 kunmap_atomic(s);
536
537 drm_clflush_pages(&page, 1);
538 }
539 local_irq_restore(flags);
540
541 dst->pages[i] = d;
542
543 reloc_offset += PAGE_SIZE;
544 }
545 dst->page_count = num_pages;
546
547 return dst;
548
549unwind:
550 while (i--)
551 kfree(dst->pages[i]);
552 kfree(dst);
553 return NULL;
554}
555#define i915_error_object_create(dev_priv, src) \
556 i915_error_object_create_sized((dev_priv), (src), \
557 (src)->base.size>>PAGE_SHIFT)
558
559static void capture_bo(struct drm_i915_error_buffer *err,
560 struct drm_i915_gem_object *obj)
561{
562 err->size = obj->base.size;
563 err->name = obj->base.name;
564 err->rseqno = obj->last_read_seqno;
565 err->wseqno = obj->last_write_seqno;
566 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
567 err->read_domains = obj->base.read_domains;
568 err->write_domain = obj->base.write_domain;
569 err->fence_reg = obj->fence_reg;
570 err->pinned = 0;
571 if (obj->pin_count > 0)
572 err->pinned = 1;
573 if (obj->user_pin_count > 0)
574 err->pinned = -1;
575 err->tiling = obj->tiling_mode;
576 err->dirty = obj->dirty;
577 err->purgeable = obj->madv != I915_MADV_WILLNEED;
578 err->ring = obj->ring ? obj->ring->id : -1;
579 err->cache_level = obj->cache_level;
580}
581
582static u32 capture_active_bo(struct drm_i915_error_buffer *err,
583 int count, struct list_head *head)
584{
ca191b13 585 struct i915_vma *vma;
84734a04
MK		 586 int i = 0;
587
ca191b13
BW		 588 list_for_each_entry(vma, head, mm_list) {
589 capture_bo(err++, vma->obj);
84734a04
MK		 590 if (++i == count)
591 break;
592 }
593
594 return i;
595}
596
597static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
598 int count, struct list_head *head)
599{
600 struct drm_i915_gem_object *obj;
601 int i = 0;
602
603 list_for_each_entry(obj, head, global_list) {
604 if (obj->pin_count == 0)
605 continue;
606
607 capture_bo(err++, obj);
608 if (++i == count)
609 break;
610 }
611
612 return i;
613}
614
615static void i915_gem_record_fences(struct drm_device *dev,
616 struct drm_i915_error_state *error)
617{
618 struct drm_i915_private *dev_priv = dev->dev_private;
619 int i;
620
621 /* Fences */
622 switch (INTEL_INFO(dev)->gen) {
623 case 7:
624 case 6:
625 for (i = 0; i < dev_priv->num_fence_regs; i++)
626 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
627 break;
628 case 5:
629 case 4:
630 for (i = 0; i < 16; i++)
631 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
632 break;
633 case 3:
634 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
635 for (i = 0; i < 8; i++)
636 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
637 case 2:
638 for (i = 0; i < 8; i++)
639 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
640 break;
641
642 default:
643 BUG();
644 }
645}
646
647static struct drm_i915_error_object *
648i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
649 struct intel_ring_buffer *ring)
650{
ca191b13
BW		 651 struct i915_address_space *vm;
652 struct i915_vma *vma;
84734a04
MK		 653 struct drm_i915_gem_object *obj;
654 u32 seqno;
655
656 if (!ring->get_seqno)
657 return NULL;
658
659 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
660 u32 acthd = I915_READ(ACTHD);
661
662 if (WARN_ON(ring->id != RCS))
663 return NULL;
664
0d1aacac 665 obj = ring->scratch.obj;
84734a04
MK		 666 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
667 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
668 return i915_error_object_create(dev_priv, obj);
669 }
670
671 seqno = ring->get_seqno(ring, false);
ca191b13
BW		 672 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
673 list_for_each_entry(vma, &vm->active_list, mm_list) {
674 obj = vma->obj;
675 if (obj->ring != ring)
676 continue;
84734a04 677
ca191b13
BW		 678 if (i915_seqno_passed(seqno, obj->last_read_seqno))
679 continue;
84734a04 680
ca191b13
BW		 681 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
682 continue;
84734a04 683
ca191b13
BW		 684 /* We need to copy these to an anonymous buffer as the simplest
685 * method to avoid being overwritten by userspace.
686 */
687 return i915_error_object_create(dev_priv, obj);
688 }
84734a04
MK		 689 }
690
691 return NULL;
692}
693
694static void i915_record_ring_state(struct drm_device *dev,
695 struct drm_i915_error_state *error,
696 struct intel_ring_buffer *ring)
697{
698 struct drm_i915_private *dev_priv = dev->dev_private;
699
700 if (INTEL_INFO(dev)->gen >= 6) {
701 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
702 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
703 error->semaphore_mboxes[ring->id][0]
704 = I915_READ(RING_SYNC_0(ring->mmio_base));
705 error->semaphore_mboxes[ring->id][1]
706 = I915_READ(RING_SYNC_1(ring->mmio_base));
707 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
708 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
709 }
710
4e5aabfd
BW		 711 if (HAS_VEBOX(dev)) {
712 error->semaphore_mboxes[ring->id][2] =
713 I915_READ(RING_SYNC_2(ring->mmio_base));
714 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
715 }
716
84734a04
MK		 717 if (INTEL_INFO(dev)->gen >= 4) {
718 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
719 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
720 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
721 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
722 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
723 if (ring->id == RCS)
724 error->bbaddr = I915_READ64(BB_ADDR);
725 } else {
726 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
727 error->ipeir[ring->id] = I915_READ(IPEIR);
728 error->ipehr[ring->id] = I915_READ(IPEHR);
729 error->instdone[ring->id] = I915_READ(INSTDONE);
730 }
731
732 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
733 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
734 error->seqno[ring->id] = ring->get_seqno(ring, false);
735 error->acthd[ring->id] = intel_ring_get_active_head(ring);
736 error->head[ring->id] = I915_READ_HEAD(ring);
737 error->tail[ring->id] = I915_READ_TAIL(ring);
738 error->ctl[ring->id] = I915_READ_CTL(ring);
739
740 error->cpu_ring_head[ring->id] = ring->head;
741 error->cpu_ring_tail[ring->id] = ring->tail;
da661464
MK		 742
743 error->hangcheck_score[ring->id] = ring->hangcheck.score;
744 error->hangcheck_action[ring->id] = ring->hangcheck.action;
84734a04
MK		 745}
746
747
748static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
749 struct drm_i915_error_state *error,
750 struct drm_i915_error_ring *ering)
751{
752 struct drm_i915_private *dev_priv = ring->dev->dev_private;
753 struct drm_i915_gem_object *obj;
754
755 /* Currently render ring is the only HW context user */
756 if (ring->id != RCS || !error->ccid)
757 return;
758
759 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
760 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
761 ering->ctx = i915_error_object_create_sized(dev_priv,
762 obj, 1);
763 break;
764 }
765 }
766}
767
768static void i915_gem_record_rings(struct drm_device *dev,
769 struct drm_i915_error_state *error)
770{
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 struct intel_ring_buffer *ring;
773 struct drm_i915_gem_request *request;
774 int i, count;
775
776 for_each_ring(ring, dev_priv, i) {
777 i915_record_ring_state(dev, error, ring);
778
779 error->ring[i].batchbuffer =
780 i915_error_first_batchbuffer(dev_priv, ring);
781
782 error->ring[i].ringbuffer =
783 i915_error_object_create(dev_priv, ring->obj);
784
785
786 i915_gem_record_active_context(ring, error, &error->ring[i]);
787
788 count = 0;
789 list_for_each_entry(request, &ring->request_list, list)
790 count++;
791
792 error->ring[i].num_requests = count;
793 error->ring[i].requests =
794 kmalloc(count*sizeof(struct drm_i915_error_request),
795 GFP_ATOMIC);
796 if (error->ring[i].requests == NULL) {
797 error->ring[i].num_requests = 0;
798 continue;
799 }
800
801 count = 0;
802 list_for_each_entry(request, &ring->request_list, list) {
803 struct drm_i915_error_request *erq;
804
805 erq = &error->ring[i].requests[count++];
806 erq->seqno = request->seqno;
807 erq->jiffies = request->emitted_jiffies;
808 erq->tail = request->tail;
809 }
810 }
811}
812
95f5301d
BW		 813/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
814 * VM.
815 */
816static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
817 struct drm_i915_error_state *error,
818 struct i915_address_space *vm,
819 const int ndx)
84734a04 820{
95f5301d 821 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 822 struct drm_i915_gem_object *obj;
95f5301d 823 struct i915_vma *vma;
84734a04
MK		 824 int i;
825
826 i = 0;
ca191b13 827 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 828 i++;
95f5301d 829 error->active_bo_count[ndx] = i;
84734a04
MK		 830 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
831 if (obj->pin_count)
832 i++;
95f5301d 833 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 834
835 if (i) {
95f5301d
BW		 836 active_bo = kmalloc(sizeof(*active_bo)*i, GFP_ATOMIC);
837 if (active_bo)
838 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 839 }
840
95f5301d
BW		 841 if (active_bo)
842 error->active_bo_count[ndx] =
843 capture_active_bo(active_bo,
844 error->active_bo_count[ndx],
5cef07e1 845 &vm->active_list);
84734a04 846
95f5301d
BW		 847 if (pinned_bo)
848 error->pinned_bo_count[ndx] =
849 capture_pinned_bo(pinned_bo,
850 error->pinned_bo_count[ndx],
84734a04 851 &dev_priv->mm.bound_list);
95f5301d
BW		 852 error->active_bo[ndx] = active_bo;
853 error->pinned_bo[ndx] = pinned_bo;
854}
855
856static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
857 struct drm_i915_error_state *error)
858{
859 struct i915_address_space *vm;
860 int cnt = 0, i = 0;
861
862 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
863 cnt++;
864
865 if (WARN(cnt > 1, "Multiple VMs not yet supported\n"))
866 cnt = 1;
867
868 vm = &dev_priv->gtt.base;
869
870 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
871 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
872 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
873 GFP_ATOMIC);
874 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
875 GFP_ATOMIC);
876
877 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
878 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 879}
880
881/**
882 * i915_capture_error_state - capture an error record for later analysis
883 * @dev: drm device
884 *
885 * Should be called when an error is detected (either a hang or an error
886 * interrupt) to capture error state from the time of the error. Fills
887 * out a structure which becomes available in debugfs for user level tools
888 * to pick up.
889 */
890void i915_capture_error_state(struct drm_device *dev)
891{
892 struct drm_i915_private *dev_priv = dev->dev_private;
893 struct drm_i915_error_state *error;
894 unsigned long flags;
895 int pipe;
896
897 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
898 error = dev_priv->gpu_error.first_error;
899 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
900 if (error)
901 return;
902
903 /* Account for pipe specific data like PIPE*STAT */
904 error = kzalloc(sizeof(*error), GFP_ATOMIC);
905 if (!error) {
906 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
907 return;
908 }
909
910 DRM_INFO("capturing error event; look for more information in "
911 "/sys/class/drm/card%d/error\n", dev->primary->index);
912
913 kref_init(&error->ref);
914 error->eir = I915_READ(EIR);
915 error->pgtbl_er = I915_READ(PGTBL_ER);
916 if (HAS_HW_CONTEXTS(dev))
917 error->ccid = I915_READ(CCID);
918
919 if (HAS_PCH_SPLIT(dev))
920 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
921 else if (IS_VALLEYVIEW(dev))
922 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
923 else if (IS_GEN2(dev))
924 error->ier = I915_READ16(IER);
925 else
926 error->ier = I915_READ(IER);
927
928 if (INTEL_INFO(dev)->gen >= 6)
929 error->derrmr = I915_READ(DERRMR);
930
931 if (IS_VALLEYVIEW(dev))
932 error->forcewake = I915_READ(FORCEWAKE_VLV);
933 else if (INTEL_INFO(dev)->gen >= 7)
934 error->forcewake = I915_READ(FORCEWAKE_MT);
935 else if (INTEL_INFO(dev)->gen == 6)
936 error->forcewake = I915_READ(FORCEWAKE);
937
938 if (!HAS_PCH_SPLIT(dev))
939 for_each_pipe(pipe)
940 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
941
942 if (INTEL_INFO(dev)->gen >= 6) {
943 error->error = I915_READ(ERROR_GEN6);
944 error->done_reg = I915_READ(DONE_REG);
945 }
946
947 if (INTEL_INFO(dev)->gen == 7)
948 error->err_int = I915_READ(GEN7_ERR_INT);
949
950 i915_get_extra_instdone(dev, error->extra_instdone);
951
952 i915_gem_capture_buffers(dev_priv, error);
953 i915_gem_record_fences(dev, error);
954 i915_gem_record_rings(dev, error);
955
956 do_gettimeofday(&error->time);
957
958 error->overlay = intel_overlay_capture_error_state(dev);
959 error->display = intel_display_capture_error_state(dev);
960
961 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
962 if (dev_priv->gpu_error.first_error == NULL) {
963 dev_priv->gpu_error.first_error = error;
964 error = NULL;
965 }
966 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
967
968 if (error)
969 i915_error_state_free(&error->ref);
970}
971
972void i915_error_state_get(struct drm_device *dev,
973 struct i915_error_state_file_priv *error_priv)
974{
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 unsigned long flags;
977
978 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
979 error_priv->error = dev_priv->gpu_error.first_error;
980 if (error_priv->error)
981 kref_get(&error_priv->error->ref);
982 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
983
984}
985
986void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
987{
988 if (error_priv->error)
989 kref_put(&error_priv->error->ref, i915_error_state_free);
990}
991
992void i915_destroy_error_state(struct drm_device *dev)
993{
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 struct drm_i915_error_state *error;
996 unsigned long flags;
997
998 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
999 error = dev_priv->gpu_error.first_error;
1000 dev_priv->gpu_error.first_error = NULL;
1001 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1002
1003 if (error)
1004 kref_put(&error->ref, i915_error_state_free);
1005}
1006
1007const char *i915_cache_level_str(int type)
1008{
1009 switch (type) {
1010 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1011 case I915_CACHE_LLC: return " snooped or LLC";
1012 case I915_CACHE_L3_LLC: return " L3+LLC";
84734a04
MK		 1013 default: return "";
1014 }
1015}
1016
1017/* NB: please notice the memset */
1018void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1022
1023 switch (INTEL_INFO(dev)->gen) {
1024 case 2:
1025 case 3:
1026 instdone[0] = I915_READ(INSTDONE);
1027 break;
1028 case 4:
1029 case 5:
1030 case 6:
1031 instdone[0] = I915_READ(INSTDONE_I965);
1032 instdone[1] = I915_READ(INSTDONE1);
1033 break;
1034 default:
1035 WARN_ONCE(1, "Unsupported platform\n");
1036 case 7:
1037 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1038 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1039 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1040 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1041 break;
1042 }
1043}
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