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bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
bac427f8 | 24 | #include <linux/circ_buf.h> |
f8240835 AG |
25 | #include <linux/debugfs.h> |
26 | #include <linux/relay.h> | |
bac427f8 | 27 | #include "i915_drv.h" |
8c4f24f9 | 28 | #include "intel_uc.h" |
bac427f8 | 29 | |
44a28b1d | 30 | /** |
feda33ef | 31 | * DOC: GuC-based command submission |
44a28b1d DG |
32 | * |
33 | * i915_guc_client: | |
34 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
35 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
36 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
37 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
38 | * is mapped to client space. So the client can write Work Item then ring the | |
39 | * doorbell. | |
40 | * | |
41 | * To simplify the implementation, we allocate one gem object that contains all | |
42 | * pages for doorbell, process descriptor and workqueue. | |
43 | * | |
44 | * The Scratch registers: | |
45 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
46 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
47 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
48 | * Firmware writes a success/fail code back to the action register after | |
49 | * processes the request. The kernel driver polls waiting for this update and | |
50 | * then proceeds. | |
2d803c2d | 51 | * See intel_guc_send() |
44a28b1d DG |
52 | * |
53 | * Doorbells: | |
54 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
55 | * mapped into process space. | |
56 | * | |
57 | * Work Items: | |
58 | * There are several types of work items that the host may place into a | |
59 | * workqueue, each with its own requirements and limitations. Currently only | |
60 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
61 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
62 | * ELSP context descriptor dword into Work Item. | |
7a9347f9 | 63 | * See guc_wq_item_append() |
44a28b1d DG |
64 | * |
65 | */ | |
66 | ||
44a28b1d DG |
67 | /* |
68 | * Tell the GuC to allocate or deallocate a specific doorbell | |
69 | */ | |
70 | ||
a80bc45f AH |
71 | static int guc_allocate_doorbell(struct intel_guc *guc, |
72 | struct i915_guc_client *client) | |
44a28b1d | 73 | { |
2d803c2d AH |
74 | u32 action[] = { |
75 | INTEL_GUC_ACTION_ALLOCATE_DOORBELL, | |
76 | client->ctx_index | |
77 | }; | |
44a28b1d | 78 | |
2d803c2d | 79 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
44a28b1d DG |
80 | } |
81 | ||
a80bc45f AH |
82 | static int guc_release_doorbell(struct intel_guc *guc, |
83 | struct i915_guc_client *client) | |
44a28b1d | 84 | { |
2d803c2d AH |
85 | u32 action[] = { |
86 | INTEL_GUC_ACTION_DEALLOCATE_DOORBELL, | |
87 | client->ctx_index | |
88 | }; | |
685534ef | 89 | |
2d803c2d | 90 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
685534ef SAK |
91 | } |
92 | ||
44a28b1d DG |
93 | /* |
94 | * Initialise, update, or clear doorbell data shared with the GuC | |
95 | * | |
96 | * These functions modify shared data and so need access to the mapped | |
97 | * client object which contains the page being used for the doorbell | |
98 | */ | |
99 | ||
a667429b DG |
100 | static int guc_update_doorbell_id(struct intel_guc *guc, |
101 | struct i915_guc_client *client, | |
102 | u16 new_id) | |
44a28b1d | 103 | { |
8b797af1 | 104 | struct sg_table *sg = guc->ctx_pool_vma->pages; |
a667429b | 105 | void *doorbell_bitmap = guc->doorbell_bitmap; |
44a28b1d | 106 | struct guc_doorbell_info *doorbell; |
a667429b DG |
107 | struct guc_context_desc desc; |
108 | size_t len; | |
44a28b1d | 109 | |
72aa0d89 | 110 | doorbell = client->vaddr + client->doorbell_offset; |
44a28b1d | 111 | |
a667429b DG |
112 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID && |
113 | test_bit(client->doorbell_id, doorbell_bitmap)) { | |
114 | /* Deactivate the old doorbell */ | |
115 | doorbell->db_status = GUC_DOORBELL_DISABLED; | |
a80bc45f | 116 | (void)guc_release_doorbell(guc, client); |
a667429b DG |
117 | __clear_bit(client->doorbell_id, doorbell_bitmap); |
118 | } | |
119 | ||
120 | /* Update the GuC's idea of the doorbell ID */ | |
121 | len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
122 | sizeof(desc) * client->ctx_index); | |
123 | if (len != sizeof(desc)) | |
124 | return -EFAULT; | |
125 | desc.db_id = new_id; | |
126 | len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
127 | sizeof(desc) * client->ctx_index); | |
128 | if (len != sizeof(desc)) | |
129 | return -EFAULT; | |
130 | ||
131 | client->doorbell_id = new_id; | |
132 | if (new_id == GUC_INVALID_DOORBELL_ID) | |
133 | return 0; | |
134 | ||
135 | /* Activate the new doorbell */ | |
136 | __set_bit(new_id, doorbell_bitmap); | |
a667429b | 137 | doorbell->db_status = GUC_DOORBELL_ENABLED; |
597bdc8b | 138 | doorbell->cookie = client->doorbell_cookie; |
a80bc45f | 139 | return guc_allocate_doorbell(guc, client); |
a667429b DG |
140 | } |
141 | ||
44a28b1d DG |
142 | static void guc_disable_doorbell(struct intel_guc *guc, |
143 | struct i915_guc_client *client) | |
144 | { | |
a667429b | 145 | (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID); |
44a28b1d | 146 | |
44a28b1d DG |
147 | /* XXX: wait for any interrupts */ |
148 | /* XXX: wait for workqueue to drain */ | |
149 | } | |
150 | ||
f10d69a7 DG |
151 | static uint16_t |
152 | select_doorbell_register(struct intel_guc *guc, uint32_t priority) | |
153 | { | |
154 | /* | |
155 | * The bitmap tracks which doorbell registers are currently in use. | |
156 | * It is split into two halves; the first half is used for normal | |
157 | * priority contexts, the second half for high-priority ones. | |
158 | * Note that logically higher priorities are numerically less than | |
159 | * normal ones, so the test below means "is it high-priority?" | |
160 | */ | |
161 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
162 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
163 | const uint16_t start = hi_pri ? half : 0; | |
164 | const uint16_t end = start + half; | |
165 | uint16_t id; | |
166 | ||
167 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); | |
168 | if (id == end) | |
169 | id = GUC_INVALID_DOORBELL_ID; | |
170 | ||
171 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
172 | hi_pri ? "high" : "normal", id); | |
173 | ||
174 | return id; | |
175 | } | |
176 | ||
44a28b1d DG |
177 | /* |
178 | * Select, assign and relase doorbell cachelines | |
179 | * | |
180 | * These functions track which doorbell cachelines are in use. | |
2d803c2d | 181 | * The data they manipulate is protected by the intel_guc_send lock. |
44a28b1d DG |
182 | */ |
183 | ||
184 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
185 | { | |
186 | const uint32_t cacheline_size = cache_line_size(); | |
187 | uint32_t offset; | |
188 | ||
44a28b1d DG |
189 | /* Doorbell uses a single cache line within a page */ |
190 | offset = offset_in_page(guc->db_cacheline); | |
191 | ||
192 | /* Moving to next cache line to reduce contention */ | |
193 | guc->db_cacheline += cacheline_size; | |
194 | ||
44a28b1d DG |
195 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
196 | offset, guc->db_cacheline, cacheline_size); | |
197 | ||
198 | return offset; | |
199 | } | |
200 | ||
44a28b1d DG |
201 | /* |
202 | * Initialise the process descriptor shared with the GuC firmware. | |
203 | */ | |
7a9347f9 | 204 | static void guc_proc_desc_init(struct intel_guc *guc, |
44a28b1d DG |
205 | struct i915_guc_client *client) |
206 | { | |
207 | struct guc_process_desc *desc; | |
44a28b1d | 208 | |
72aa0d89 | 209 | desc = client->vaddr + client->proc_desc_offset; |
44a28b1d DG |
210 | |
211 | memset(desc, 0, sizeof(*desc)); | |
212 | ||
213 | /* | |
214 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
215 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
216 | * space for kernel clients (map on demand instead? May make debug | |
217 | * easier to have it mapped). | |
218 | */ | |
219 | desc->wq_base_addr = 0; | |
220 | desc->db_base_addr = 0; | |
221 | ||
222 | desc->context_id = client->ctx_index; | |
223 | desc->wq_size_bytes = client->wq_size; | |
224 | desc->wq_status = WQ_STATUS_ACTIVE; | |
225 | desc->priority = client->priority; | |
44a28b1d DG |
226 | } |
227 | ||
228 | /* | |
229 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
230 | * | |
231 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
232 | * data structures relating to this client (doorbell, process descriptor, | |
233 | * write queue, etc). | |
234 | */ | |
235 | ||
7a9347f9 | 236 | static void guc_ctx_desc_init(struct intel_guc *guc, |
44a28b1d DG |
237 | struct i915_guc_client *client) |
238 | { | |
397097b0 | 239 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
e2f80391 | 240 | struct intel_engine_cs *engine; |
e2efd130 | 241 | struct i915_gem_context *ctx = client->owner; |
44a28b1d DG |
242 | struct guc_context_desc desc; |
243 | struct sg_table *sg; | |
bafb0fce | 244 | unsigned int tmp; |
86e06cc0 | 245 | u32 gfx_addr; |
44a28b1d DG |
246 | |
247 | memset(&desc, 0, sizeof(desc)); | |
248 | ||
249 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
250 | desc.context_id = client->ctx_index; | |
251 | desc.priority = client->priority; | |
44a28b1d DG |
252 | desc.db_id = client->doorbell_id; |
253 | ||
bafb0fce | 254 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { |
9021ad03 | 255 | struct intel_context *ce = &ctx->engine[engine->id]; |
c18468c4 DG |
256 | uint32_t guc_engine_id = engine->guc_id; |
257 | struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id]; | |
d1675198 AD |
258 | |
259 | /* TODO: We have a design issue to be solved here. Only when we | |
260 | * receive the first batch, we know which engine is used by the | |
261 | * user. But here GuC expects the lrc and ring to be pinned. It | |
262 | * is not an issue for default context, which is the only one | |
263 | * for now who owns a GuC client. But for future owner of GuC | |
264 | * client, need to make sure lrc is pinned prior to enter here. | |
265 | */ | |
9021ad03 | 266 | if (!ce->state) |
d1675198 AD |
267 | break; /* XXX: continue? */ |
268 | ||
9021ad03 | 269 | lrc->context_desc = lower_32_bits(ce->lrc_desc); |
d1675198 AD |
270 | |
271 | /* The state page is after PPHWSP */ | |
57e88531 | 272 | lrc->ring_lcra = |
bde13ebd | 273 | i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; |
d1675198 | 274 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
c18468c4 | 275 | (guc_engine_id << GUC_ELC_ENGINE_OFFSET); |
d1675198 | 276 | |
bde13ebd | 277 | lrc->ring_begin = i915_ggtt_offset(ce->ring->vma); |
57e88531 CW |
278 | lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; |
279 | lrc->ring_next_free_location = lrc->ring_begin; | |
d1675198 AD |
280 | lrc->ring_current_tail_pointer_value = 0; |
281 | ||
c18468c4 | 282 | desc.engines_used |= (1 << guc_engine_id); |
d1675198 AD |
283 | } |
284 | ||
e02757d9 DG |
285 | DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", |
286 | client->engines, desc.engines_used); | |
d1675198 AD |
287 | WARN_ON(desc.engines_used == 0); |
288 | ||
44a28b1d | 289 | /* |
86e06cc0 DG |
290 | * The doorbell, process descriptor, and workqueue are all parts |
291 | * of the client object, which the GuC will reference via the GGTT | |
44a28b1d | 292 | */ |
bde13ebd | 293 | gfx_addr = i915_ggtt_offset(client->vma); |
8b797af1 | 294 | desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + |
86e06cc0 | 295 | client->doorbell_offset; |
72aa0d89 CW |
296 | desc.db_trigger_cpu = |
297 | (uintptr_t)client->vaddr + client->doorbell_offset; | |
86e06cc0 DG |
298 | desc.db_trigger_uk = gfx_addr + client->doorbell_offset; |
299 | desc.process_desc = gfx_addr + client->proc_desc_offset; | |
300 | desc.wq_addr = gfx_addr + client->wq_offset; | |
44a28b1d DG |
301 | desc.wq_size = client->wq_size; |
302 | ||
303 | /* | |
e2efd130 | 304 | * XXX: Take LRCs from an existing context if this is not an |
44a28b1d DG |
305 | * IsKMDCreatedContext client |
306 | */ | |
307 | desc.desc_private = (uintptr_t)client; | |
308 | ||
309 | /* Pool context is pinned already */ | |
8b797af1 | 310 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
311 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
312 | sizeof(desc) * client->ctx_index); | |
313 | } | |
314 | ||
7a9347f9 | 315 | static void guc_ctx_desc_fini(struct intel_guc *guc, |
44a28b1d DG |
316 | struct i915_guc_client *client) |
317 | { | |
318 | struct guc_context_desc desc; | |
319 | struct sg_table *sg; | |
320 | ||
321 | memset(&desc, 0, sizeof(desc)); | |
322 | ||
8b797af1 | 323 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
324 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
325 | sizeof(desc) * client->ctx_index); | |
326 | } | |
327 | ||
7c2c270d | 328 | /** |
7a9347f9 | 329 | * i915_guc_wq_reserve() - reserve space in the GuC's workqueue |
7c2c270d DG |
330 | * @request: request associated with the commands |
331 | * | |
332 | * Return: 0 if space is available | |
333 | * -EAGAIN if space is not currently available | |
334 | * | |
335 | * This function must be called (and must return 0) before a request | |
336 | * is submitted to the GuC via i915_guc_submit() below. Once a result | |
7a9347f9 DG |
337 | * of 0 has been returned, it must be balanced by a corresponding |
338 | * call to submit(). | |
7c2c270d | 339 | * |
7a9347f9 | 340 | * Reservation allows the caller to determine in advance that space |
7c2c270d DG |
341 | * will be available for the next submission before committing resources |
342 | * to it, and helps avoid late failures with complicated recovery paths. | |
343 | */ | |
7a9347f9 | 344 | int i915_guc_wq_reserve(struct drm_i915_gem_request *request) |
44a28b1d | 345 | { |
551aaecd | 346 | const size_t wqi_size = sizeof(struct guc_wq_item); |
7c2c270d | 347 | struct i915_guc_client *gc = request->i915->guc.execbuf_client; |
72aa0d89 | 348 | struct guc_process_desc *desc = gc->vaddr + gc->proc_desc_offset; |
551aaecd | 349 | u32 freespace; |
dadd481b | 350 | int ret; |
44a28b1d | 351 | |
dadd481b | 352 | spin_lock(&gc->wq_lock); |
551aaecd | 353 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); |
dadd481b CW |
354 | freespace -= gc->wq_rsvd; |
355 | if (likely(freespace >= wqi_size)) { | |
356 | gc->wq_rsvd += wqi_size; | |
357 | ret = 0; | |
358 | } else { | |
359 | gc->no_wq_space++; | |
360 | ret = -EAGAIN; | |
361 | } | |
362 | spin_unlock(&gc->wq_lock); | |
44a28b1d | 363 | |
dadd481b | 364 | return ret; |
44a28b1d DG |
365 | } |
366 | ||
5ba89908 CW |
367 | void i915_guc_wq_unreserve(struct drm_i915_gem_request *request) |
368 | { | |
369 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
370 | struct i915_guc_client *gc = request->i915->guc.execbuf_client; | |
371 | ||
372 | GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size); | |
373 | ||
374 | spin_lock(&gc->wq_lock); | |
375 | gc->wq_rsvd -= wqi_size; | |
376 | spin_unlock(&gc->wq_lock); | |
377 | } | |
378 | ||
7a9347f9 DG |
379 | /* Construct a Work Item and append it to the GuC's Work Queue */ |
380 | static void guc_wq_item_append(struct i915_guc_client *gc, | |
381 | struct drm_i915_gem_request *rq) | |
44a28b1d | 382 | { |
0a31afbc DG |
383 | /* wqi_len is in DWords, and does not include the one-word header */ |
384 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
385 | const u32 wqi_len = wqi_size/sizeof(u32) - 1; | |
c18468c4 | 386 | struct intel_engine_cs *engine = rq->engine; |
a5916e8f | 387 | struct guc_process_desc *desc; |
44a28b1d | 388 | struct guc_wq_item *wqi; |
72aa0d89 | 389 | u32 freespace, tail, wq_off; |
a7e02199 | 390 | |
72aa0d89 | 391 | desc = gc->vaddr + gc->proc_desc_offset; |
44a28b1d | 392 | |
7a9347f9 | 393 | /* Free space is guaranteed, see i915_guc_wq_reserve() above */ |
0a31afbc DG |
394 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); |
395 | GEM_BUG_ON(freespace < wqi_size); | |
396 | ||
397 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
398 | tail = rq->tail; | |
399 | GEM_BUG_ON(tail & 7); | |
400 | tail >>= 3; | |
401 | GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); | |
44a28b1d DG |
402 | |
403 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
404 | * should not have the case where structure wqi is across page, neither | |
405 | * wrapped to the beginning. This simplifies the implementation below. | |
406 | * | |
407 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
408 | * workqueue buffer dw by dw. | |
409 | */ | |
0a31afbc | 410 | BUILD_BUG_ON(wqi_size != 16); |
dadd481b | 411 | GEM_BUG_ON(gc->wq_rsvd < wqi_size); |
44a28b1d | 412 | |
0a31afbc DG |
413 | /* postincrement WQ tail for next time */ |
414 | wq_off = gc->wq_tail; | |
dadd481b | 415 | GEM_BUG_ON(wq_off & (wqi_size - 1)); |
0a31afbc DG |
416 | gc->wq_tail += wqi_size; |
417 | gc->wq_tail &= gc->wq_size - 1; | |
dadd481b | 418 | gc->wq_rsvd -= wqi_size; |
0a31afbc DG |
419 | |
420 | /* WQ starts from the page after doorbell / process_desc */ | |
72aa0d89 | 421 | wqi = gc->vaddr + wq_off + GUC_DB_SIZE; |
44a28b1d | 422 | |
0a31afbc | 423 | /* Now fill in the 4-word work queue item */ |
44a28b1d | 424 | wqi->header = WQ_TYPE_INORDER | |
0a31afbc | 425 | (wqi_len << WQ_LEN_SHIFT) | |
c18468c4 | 426 | (engine->guc_id << WQ_TARGET_SHIFT) | |
44a28b1d DG |
427 | WQ_NO_WCFLUSH_WAIT; |
428 | ||
429 | /* The GuC wants only the low-order word of the context descriptor */ | |
c18468c4 | 430 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine); |
44a28b1d | 431 | |
44a28b1d | 432 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
65e4760e | 433 | wqi->fence_id = rq->global_seqno; |
44a28b1d DG |
434 | } |
435 | ||
10d2c3e2 DG |
436 | static int guc_ring_doorbell(struct i915_guc_client *gc) |
437 | { | |
438 | struct guc_process_desc *desc; | |
439 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
440 | union guc_doorbell_qw *db; | |
441 | int attempt = 2, ret = -EAGAIN; | |
442 | ||
72aa0d89 | 443 | desc = gc->vaddr + gc->proc_desc_offset; |
10d2c3e2 DG |
444 | |
445 | /* Update the tail so it is visible to GuC */ | |
446 | desc->tail = gc->wq_tail; | |
447 | ||
448 | /* current cookie */ | |
449 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
357248bf | 450 | db_cmp.cookie = gc->doorbell_cookie; |
10d2c3e2 DG |
451 | |
452 | /* cookie to be updated */ | |
453 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
357248bf | 454 | db_exc.cookie = gc->doorbell_cookie + 1; |
10d2c3e2 DG |
455 | if (db_exc.cookie == 0) |
456 | db_exc.cookie = 1; | |
457 | ||
458 | /* pointer of current doorbell cacheline */ | |
72aa0d89 | 459 | db = gc->vaddr + gc->doorbell_offset; |
10d2c3e2 DG |
460 | |
461 | while (attempt--) { | |
462 | /* lets ring the doorbell */ | |
463 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
464 | db_cmp.value_qw, db_exc.value_qw); | |
465 | ||
466 | /* if the exchange was successfully executed */ | |
467 | if (db_ret.value_qw == db_cmp.value_qw) { | |
468 | /* db was successfully rung */ | |
357248bf | 469 | gc->doorbell_cookie = db_exc.cookie; |
10d2c3e2 DG |
470 | ret = 0; |
471 | break; | |
472 | } | |
473 | ||
474 | /* XXX: doorbell was lost and need to acquire it again */ | |
475 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
476 | break; | |
477 | ||
535b2f5e DG |
478 | DRM_WARN("Cookie mismatch. Expected %d, found %d\n", |
479 | db_cmp.cookie, db_ret.cookie); | |
10d2c3e2 DG |
480 | |
481 | /* update the cookie to newly read cookie from GuC */ | |
482 | db_cmp.cookie = db_ret.cookie; | |
483 | db_exc.cookie = db_ret.cookie + 1; | |
484 | if (db_exc.cookie == 0) | |
485 | db_exc.cookie = 1; | |
486 | } | |
487 | ||
488 | return ret; | |
489 | } | |
490 | ||
44a28b1d | 491 | /** |
34ba5a80 | 492 | * __i915_guc_submit() - Submit commands through GuC |
feda33ef | 493 | * @rq: request associated with the commands |
44a28b1d | 494 | * |
7a9347f9 DG |
495 | * The caller must have already called i915_guc_wq_reserve() above with |
496 | * a result of 0 (success), guaranteeing that there is space in the work | |
497 | * queue for the new request, so enqueuing the item cannot fail. | |
7c2c270d DG |
498 | * |
499 | * Bad Things Will Happen if the caller violates this protocol e.g. calls | |
7a9347f9 DG |
500 | * submit() when _reserve() says there's no space, or calls _submit() |
501 | * a different number of times from (successful) calls to _reserve(). | |
7c2c270d DG |
502 | * |
503 | * The only error here arises if the doorbell hardware isn't functioning | |
504 | * as expected, which really shouln't happen. | |
44a28b1d | 505 | */ |
34ba5a80 | 506 | static void __i915_guc_submit(struct drm_i915_gem_request *rq) |
44a28b1d | 507 | { |
ed4596ea | 508 | struct drm_i915_private *dev_priv = rq->i915; |
d55ac5bf CW |
509 | struct intel_engine_cs *engine = rq->engine; |
510 | unsigned int engine_id = engine->id; | |
7c2c270d DG |
511 | struct intel_guc *guc = &rq->i915->guc; |
512 | struct i915_guc_client *client = guc->execbuf_client; | |
0a31afbc | 513 | int b_ret; |
44a28b1d | 514 | |
dadd481b | 515 | spin_lock(&client->wq_lock); |
7a9347f9 | 516 | guc_wq_item_append(client, rq); |
ed4596ea AG |
517 | |
518 | /* WA to flush out the pending GMADR writes to ring buffer. */ | |
519 | if (i915_vma_is_map_and_fenceable(rq->ring->vma)) | |
520 | POSTING_READ_FW(GUC_STATUS); | |
521 | ||
0a31afbc | 522 | b_ret = guc_ring_doorbell(client); |
44a28b1d | 523 | |
397097b0 | 524 | client->submissions[engine_id] += 1; |
0a31afbc DG |
525 | client->retcode = b_ret; |
526 | if (b_ret) | |
44a28b1d | 527 | client->b_fail += 1; |
0a31afbc | 528 | |
397097b0 | 529 | guc->submissions[engine_id] += 1; |
65e4760e | 530 | guc->last_seqno[engine_id] = rq->global_seqno; |
dadd481b | 531 | spin_unlock(&client->wq_lock); |
44a28b1d DG |
532 | } |
533 | ||
34ba5a80 CW |
534 | static void i915_guc_submit(struct drm_i915_gem_request *rq) |
535 | { | |
536 | struct intel_engine_cs *engine = rq->engine; | |
537 | ||
538 | /* We keep the previous context alive until we retire the following | |
539 | * request. This ensures that any the context object is still pinned | |
540 | * for any residual writes the HW makes into it on the context switch | |
541 | * into the next object following the breadcrumb. Otherwise, we may | |
542 | * retire the context too early. | |
543 | */ | |
544 | rq->previous_context = engine->last_context; | |
545 | engine->last_context = rq->ctx; | |
546 | ||
547 | i915_gem_request_submit(rq); | |
548 | __i915_guc_submit(rq); | |
549 | } | |
550 | ||
44a28b1d DG |
551 | /* |
552 | * Everything below here is concerned with setup & teardown, and is | |
553 | * therefore not part of the somewhat time-critical batch-submission | |
554 | * path of i915_guc_submit() above. | |
555 | */ | |
556 | ||
bac427f8 | 557 | /** |
8b797af1 CW |
558 | * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage |
559 | * @guc: the guc | |
560 | * @size: size of area to allocate (both virtual space and memory) | |
bac427f8 | 561 | * |
8b797af1 CW |
562 | * This is a wrapper to create an object for use with the GuC. In order to |
563 | * use it inside the GuC, an object needs to be pinned lifetime, so we allocate | |
564 | * both some backing storage and a range inside the Global GTT. We must pin | |
565 | * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that | |
566 | * range is reserved inside GuC. | |
bac427f8 | 567 | * |
8b797af1 | 568 | * Return: A i915_vma if successful, otherwise an ERR_PTR. |
bac427f8 | 569 | */ |
8b797af1 | 570 | static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size) |
bac427f8 | 571 | { |
8b797af1 | 572 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
bac427f8 | 573 | struct drm_i915_gem_object *obj; |
8b797af1 CW |
574 | struct i915_vma *vma; |
575 | int ret; | |
bac427f8 | 576 | |
12d79d78 | 577 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b | 578 | if (IS_ERR(obj)) |
8b797af1 | 579 | return ERR_CAST(obj); |
bac427f8 | 580 | |
8b797af1 CW |
581 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); |
582 | if (IS_ERR(vma)) | |
583 | goto err; | |
bac427f8 | 584 | |
8b797af1 CW |
585 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, |
586 | PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
587 | if (ret) { | |
588 | vma = ERR_PTR(ret); | |
589 | goto err; | |
bac427f8 AD |
590 | } |
591 | ||
592 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
593 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
594 | ||
8b797af1 CW |
595 | return vma; |
596 | ||
597 | err: | |
598 | i915_gem_object_put(obj); | |
599 | return vma; | |
bac427f8 AD |
600 | } |
601 | ||
0daf556c DG |
602 | static void |
603 | guc_client_free(struct drm_i915_private *dev_priv, | |
604 | struct i915_guc_client *client) | |
44a28b1d | 605 | { |
44a28b1d DG |
606 | struct intel_guc *guc = &dev_priv->guc; |
607 | ||
608 | if (!client) | |
609 | return; | |
610 | ||
44a28b1d DG |
611 | /* |
612 | * XXX: wait for any outstanding submissions before freeing memory. | |
613 | * Be sure to drop any locks | |
614 | */ | |
615 | ||
72aa0d89 | 616 | if (client->vaddr) { |
0d92a6a4 | 617 | /* |
a667429b DG |
618 | * If we got as far as setting up a doorbell, make sure we |
619 | * shut it down before unmapping & deallocating the memory. | |
0d92a6a4 | 620 | */ |
a667429b | 621 | guc_disable_doorbell(guc, client); |
0d92a6a4 | 622 | |
72aa0d89 | 623 | i915_gem_object_unpin_map(client->vma->obj); |
0d92a6a4 DG |
624 | } |
625 | ||
19880c4a | 626 | i915_vma_unpin_and_release(&client->vma); |
44a28b1d DG |
627 | |
628 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
7a9347f9 | 629 | guc_ctx_desc_fini(guc, client); |
44a28b1d DG |
630 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); |
631 | } | |
632 | ||
633 | kfree(client); | |
634 | } | |
635 | ||
84b7f882 DG |
636 | /* Check that a doorbell register is in the expected state */ |
637 | static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id) | |
638 | { | |
639 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
640 | i915_reg_t drbreg = GEN8_DRBREGL(db_id); | |
641 | uint32_t value = I915_READ(drbreg); | |
642 | bool enabled = (value & GUC_DOORBELL_ENABLED) != 0; | |
643 | bool expected = test_bit(db_id, guc->doorbell_bitmap); | |
644 | ||
645 | if (enabled == expected) | |
646 | return true; | |
647 | ||
648 | DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n", | |
649 | db_id, drbreg.reg, value, | |
650 | expected ? "active" : "inactive"); | |
651 | ||
652 | return false; | |
653 | } | |
654 | ||
4d75787b | 655 | /* |
8888cd01 | 656 | * Borrow the first client to set up & tear down each unused doorbell |
4d75787b DG |
657 | * in turn, to ensure that all doorbell h/w is (re)initialised. |
658 | */ | |
659 | static void guc_init_doorbell_hw(struct intel_guc *guc) | |
660 | { | |
4d75787b | 661 | struct i915_guc_client *client = guc->execbuf_client; |
84b7f882 DG |
662 | uint16_t db_id; |
663 | int i, err; | |
4d75787b | 664 | |
4d357af4 | 665 | guc_disable_doorbell(guc, client); |
4d75787b DG |
666 | |
667 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) { | |
84b7f882 DG |
668 | /* Skip if doorbell is OK */ |
669 | if (guc_doorbell_check(guc, i)) | |
8888cd01 DG |
670 | continue; |
671 | ||
4d75787b | 672 | err = guc_update_doorbell_id(guc, client, i); |
84b7f882 DG |
673 | if (err) |
674 | DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n", | |
675 | i, err); | |
4d75787b DG |
676 | } |
677 | ||
4d357af4 CW |
678 | db_id = select_doorbell_register(guc, client->priority); |
679 | WARN_ON(db_id == GUC_INVALID_DOORBELL_ID); | |
680 | ||
4d75787b DG |
681 | err = guc_update_doorbell_id(guc, client, db_id); |
682 | if (err) | |
535b2f5e DG |
683 | DRM_WARN("Failed to restore doorbell to %d, err %d\n", |
684 | db_id, err); | |
4d75787b | 685 | |
84b7f882 DG |
686 | /* Read back & verify all doorbell registers */ |
687 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) | |
688 | (void)guc_doorbell_check(guc, i); | |
4d75787b DG |
689 | } |
690 | ||
44a28b1d DG |
691 | /** |
692 | * guc_client_alloc() - Allocate an i915_guc_client | |
0daf556c | 693 | * @dev_priv: driver private data structure |
ceae5317 | 694 | * @engines: The set of engines to enable for this client |
44a28b1d DG |
695 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
696 | * The kernel client to replace ExecList submission is created with | |
697 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
698 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
699 | * @ctx: the context that owns the client (we use the default render |
700 | * context) | |
44a28b1d | 701 | * |
0d92a6a4 | 702 | * Return: An i915_guc_client object if success, else NULL. |
44a28b1d | 703 | */ |
0daf556c DG |
704 | static struct i915_guc_client * |
705 | guc_client_alloc(struct drm_i915_private *dev_priv, | |
e02757d9 | 706 | uint32_t engines, |
0daf556c DG |
707 | uint32_t priority, |
708 | struct i915_gem_context *ctx) | |
44a28b1d DG |
709 | { |
710 | struct i915_guc_client *client; | |
44a28b1d | 711 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 | 712 | struct i915_vma *vma; |
72aa0d89 | 713 | void *vaddr; |
a667429b | 714 | uint16_t db_id; |
44a28b1d DG |
715 | |
716 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
717 | if (!client) | |
718 | return NULL; | |
719 | ||
d1675198 | 720 | client->owner = ctx; |
44a28b1d | 721 | client->guc = guc; |
e02757d9 DG |
722 | client->engines = engines; |
723 | client->priority = priority; | |
724 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
44a28b1d DG |
725 | |
726 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
727 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
728 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
729 | client->ctx_index = GUC_INVALID_CTX_ID; | |
730 | goto err; | |
731 | } | |
732 | ||
733 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
8b797af1 CW |
734 | vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE); |
735 | if (IS_ERR(vma)) | |
44a28b1d DG |
736 | goto err; |
737 | ||
0d92a6a4 | 738 | /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ |
8b797af1 | 739 | client->vma = vma; |
72aa0d89 CW |
740 | |
741 | vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); | |
742 | if (IS_ERR(vaddr)) | |
743 | goto err; | |
744 | ||
745 | client->vaddr = vaddr; | |
dadd481b CW |
746 | |
747 | spin_lock_init(&client->wq_lock); | |
44a28b1d DG |
748 | client->wq_offset = GUC_DB_SIZE; |
749 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d | 750 | |
f10d69a7 DG |
751 | db_id = select_doorbell_register(guc, client->priority); |
752 | if (db_id == GUC_INVALID_DOORBELL_ID) | |
753 | /* XXX: evict a doorbell instead? */ | |
754 | goto err; | |
755 | ||
44a28b1d DG |
756 | client->doorbell_offset = select_doorbell_cacheline(guc); |
757 | ||
758 | /* | |
759 | * Since the doorbell only requires a single cacheline, we can save | |
760 | * space by putting the application process descriptor in the same | |
761 | * page. Use the half of the page that doesn't include the doorbell. | |
762 | */ | |
763 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
764 | client->proc_desc_offset = 0; | |
765 | else | |
766 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
767 | ||
7a9347f9 DG |
768 | guc_proc_desc_init(guc, client); |
769 | guc_ctx_desc_init(guc, client); | |
4d357af4 CW |
770 | |
771 | /* For runtime client allocation we need to enable the doorbell. Not | |
772 | * required yet for the static execbuf_client as this special kernel | |
773 | * client is enabled from i915_guc_submission_enable(). | |
774 | * | |
775 | * guc_update_doorbell_id(guc, client, db_id); | |
776 | */ | |
44a28b1d | 777 | |
e02757d9 DG |
778 | DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n", |
779 | priority, client, client->engines, client->ctx_index); | |
a667429b DG |
780 | DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n", |
781 | client->doorbell_id, client->doorbell_offset); | |
44a28b1d DG |
782 | |
783 | return client; | |
784 | ||
785 | err: | |
0daf556c | 786 | guc_client_free(dev_priv, client); |
44a28b1d DG |
787 | return NULL; |
788 | } | |
789 | ||
f8240835 AG |
790 | /* |
791 | * Sub buffer switch callback. Called whenever relay has to switch to a new | |
792 | * sub buffer, relay stays on the same sub buffer if 0 is returned. | |
793 | */ | |
794 | static int subbuf_start_callback(struct rchan_buf *buf, | |
795 | void *subbuf, | |
796 | void *prev_subbuf, | |
797 | size_t prev_padding) | |
798 | { | |
799 | /* Use no-overwrite mode by default, where relay will stop accepting | |
800 | * new data if there are no empty sub buffers left. | |
801 | * There is no strict synchronization enforced by relay between Consumer | |
802 | * and Producer. In overwrite mode, there is a possibility of getting | |
803 | * inconsistent/garbled data, the producer could be writing on to the | |
804 | * same sub buffer from which Consumer is reading. This can't be avoided | |
805 | * unless Consumer is fast enough and can always run in tandem with | |
806 | * Producer. | |
807 | */ | |
808 | if (relay_buf_full(buf)) | |
809 | return 0; | |
810 | ||
811 | return 1; | |
812 | } | |
813 | ||
814 | /* | |
815 | * file_create() callback. Creates relay file in debugfs. | |
816 | */ | |
817 | static struct dentry *create_buf_file_callback(const char *filename, | |
818 | struct dentry *parent, | |
819 | umode_t mode, | |
820 | struct rchan_buf *buf, | |
821 | int *is_global) | |
822 | { | |
823 | struct dentry *buf_file; | |
824 | ||
f8240835 AG |
825 | /* This to enable the use of a single buffer for the relay channel and |
826 | * correspondingly have a single file exposed to User, through which | |
827 | * it can collect the logs in order without any post-processing. | |
1e6b8b0d | 828 | * Need to set 'is_global' even if parent is NULL for early logging. |
f8240835 AG |
829 | */ |
830 | *is_global = 1; | |
831 | ||
1e6b8b0d AG |
832 | if (!parent) |
833 | return NULL; | |
834 | ||
f8240835 AG |
835 | /* Not using the channel filename passed as an argument, since for each |
836 | * channel relay appends the corresponding CPU number to the filename | |
837 | * passed in relay_open(). This should be fine as relay just needs a | |
838 | * dentry of the file associated with the channel buffer and that file's | |
839 | * name need not be same as the filename passed as an argument. | |
840 | */ | |
841 | buf_file = debugfs_create_file("guc_log", mode, | |
842 | parent, buf, &relay_file_operations); | |
843 | return buf_file; | |
844 | } | |
845 | ||
846 | /* | |
847 | * file_remove() default callback. Removes relay file in debugfs. | |
848 | */ | |
849 | static int remove_buf_file_callback(struct dentry *dentry) | |
850 | { | |
851 | debugfs_remove(dentry); | |
852 | return 0; | |
853 | } | |
854 | ||
855 | /* relay channel callbacks */ | |
856 | static struct rchan_callbacks relay_callbacks = { | |
857 | .subbuf_start = subbuf_start_callback, | |
858 | .create_buf_file = create_buf_file_callback, | |
859 | .remove_buf_file = remove_buf_file_callback, | |
860 | }; | |
861 | ||
862 | static void guc_log_remove_relay_file(struct intel_guc *guc) | |
863 | { | |
864 | relay_close(guc->log.relay_chan); | |
865 | } | |
866 | ||
1e6b8b0d | 867 | static int guc_log_create_relay_channel(struct intel_guc *guc) |
f8240835 AG |
868 | { |
869 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
870 | struct rchan *guc_log_relay_chan; | |
f8240835 AG |
871 | size_t n_subbufs, subbuf_size; |
872 | ||
1e6b8b0d AG |
873 | /* Keep the size of sub buffers same as shared log buffer */ |
874 | subbuf_size = guc->log.vma->obj->base.size; | |
875 | ||
876 | /* Store up to 8 snapshots, which is large enough to buffer sufficient | |
877 | * boot time logs and provides enough leeway to User, in terms of | |
878 | * latency, for consuming the logs from relay. Also doesn't take | |
879 | * up too much memory. | |
880 | */ | |
881 | n_subbufs = 8; | |
882 | ||
883 | guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size, | |
884 | n_subbufs, &relay_callbacks, dev_priv); | |
885 | if (!guc_log_relay_chan) { | |
886 | DRM_ERROR("Couldn't create relay chan for GuC logging\n"); | |
887 | return -ENOMEM; | |
888 | } | |
889 | ||
890 | GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size); | |
891 | guc->log.relay_chan = guc_log_relay_chan; | |
892 | return 0; | |
893 | } | |
894 | ||
895 | static int guc_log_create_relay_file(struct intel_guc *guc) | |
896 | { | |
897 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
898 | struct dentry *log_dir; | |
899 | int ret; | |
900 | ||
f8240835 AG |
901 | /* For now create the log file in /sys/kernel/debug/dri/0 dir */ |
902 | log_dir = dev_priv->drm.primary->debugfs_root; | |
903 | ||
904 | /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is | |
905 | * not mounted and so can't create the relay file. | |
906 | * The relay API seems to fit well with debugfs only, for availing relay | |
907 | * there are 3 requirements which can be met for debugfs file only in a | |
908 | * straightforward/clean manner :- | |
909 | * i) Need the associated dentry pointer of the file, while opening the | |
910 | * relay channel. | |
911 | * ii) Should be able to use 'relay_file_operations' fops for the file. | |
912 | * iii) Set the 'i_private' field of file's inode to the pointer of | |
913 | * relay channel buffer. | |
914 | */ | |
915 | if (!log_dir) { | |
916 | DRM_ERROR("Debugfs dir not available yet for GuC log file\n"); | |
917 | return -ENODEV; | |
918 | } | |
919 | ||
1e6b8b0d AG |
920 | ret = relay_late_setup_files(guc->log.relay_chan, "guc_log", log_dir); |
921 | if (ret) { | |
922 | DRM_ERROR("Couldn't associate relay chan with file %d\n", ret); | |
923 | return ret; | |
f8240835 AG |
924 | } |
925 | ||
f8240835 AG |
926 | return 0; |
927 | } | |
928 | ||
4100b2ab SAK |
929 | static void guc_move_to_next_buf(struct intel_guc *guc) |
930 | { | |
f8240835 AG |
931 | /* Make sure the updates made in the sub buffer are visible when |
932 | * Consumer sees the following update to offset inside the sub buffer. | |
933 | */ | |
934 | smp_wmb(); | |
935 | ||
936 | /* All data has been written, so now move the offset of sub buffer. */ | |
937 | relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size); | |
938 | ||
939 | /* Switch to the next sub buffer */ | |
940 | relay_flush(guc->log.relay_chan); | |
4100b2ab SAK |
941 | } |
942 | ||
943 | static void *guc_get_write_buffer(struct intel_guc *guc) | |
944 | { | |
f8240835 AG |
945 | if (!guc->log.relay_chan) |
946 | return NULL; | |
947 | ||
948 | /* Just get the base address of a new sub buffer and copy data into it | |
949 | * ourselves. NULL will be returned in no-overwrite mode, if all sub | |
950 | * buffers are full. Could have used the relay_write() to indirectly | |
951 | * copy the data, but that would have been bit convoluted, as we need to | |
952 | * write to only certain locations inside a sub buffer which cannot be | |
953 | * done without using relay_reserve() along with relay_write(). So its | |
954 | * better to use relay_reserve() alone. | |
955 | */ | |
956 | return relay_reserve(guc->log.relay_chan, 0); | |
4100b2ab SAK |
957 | } |
958 | ||
5aa1ee4b AG |
959 | static bool |
960 | guc_check_log_buf_overflow(struct intel_guc *guc, | |
961 | enum guc_log_buffer_type type, unsigned int full_cnt) | |
962 | { | |
963 | unsigned int prev_full_cnt = guc->log.prev_overflow_count[type]; | |
964 | bool overflow = false; | |
965 | ||
966 | if (full_cnt != prev_full_cnt) { | |
967 | overflow = true; | |
968 | ||
969 | guc->log.prev_overflow_count[type] = full_cnt; | |
970 | guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt; | |
971 | ||
972 | if (full_cnt < prev_full_cnt) { | |
973 | /* buffer_full_cnt is a 4 bit counter */ | |
974 | guc->log.total_overflow_count[type] += 16; | |
975 | } | |
976 | DRM_ERROR_RATELIMITED("GuC log buffer overflow\n"); | |
977 | } | |
978 | ||
979 | return overflow; | |
980 | } | |
981 | ||
4100b2ab SAK |
982 | static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type) |
983 | { | |
984 | switch (type) { | |
985 | case GUC_ISR_LOG_BUFFER: | |
986 | return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE; | |
987 | case GUC_DPC_LOG_BUFFER: | |
988 | return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE; | |
989 | case GUC_CRASH_DUMP_LOG_BUFFER: | |
990 | return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE; | |
991 | default: | |
992 | MISSING_CASE(type); | |
993 | } | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static void guc_read_update_log_buffer(struct intel_guc *guc) | |
999 | { | |
6941f3c9 | 1000 | unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt; |
4100b2ab SAK |
1001 | struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state; |
1002 | struct guc_log_buffer_state log_buf_state_local; | |
4100b2ab SAK |
1003 | enum guc_log_buffer_type type; |
1004 | void *src_data, *dst_data; | |
6941f3c9 | 1005 | bool new_overflow; |
4100b2ab SAK |
1006 | |
1007 | if (WARN_ON(!guc->log.buf_addr)) | |
1008 | return; | |
1009 | ||
1010 | /* Get the pointer to shared GuC log buffer */ | |
1011 | log_buf_state = src_data = guc->log.buf_addr; | |
1012 | ||
1013 | /* Get the pointer to local buffer to store the logs */ | |
1014 | log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc); | |
1015 | ||
1016 | /* Actual logs are present from the 2nd page */ | |
1017 | src_data += PAGE_SIZE; | |
1018 | dst_data += PAGE_SIZE; | |
1019 | ||
1020 | for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) { | |
1021 | /* Make a copy of the state structure, inside GuC log buffer | |
1022 | * (which is uncached mapped), on the stack to avoid reading | |
1023 | * from it multiple times. | |
1024 | */ | |
1025 | memcpy(&log_buf_state_local, log_buf_state, | |
1026 | sizeof(struct guc_log_buffer_state)); | |
1027 | buffer_size = guc_get_log_buffer_size(type); | |
6941f3c9 | 1028 | read_offset = log_buf_state_local.read_ptr; |
4100b2ab | 1029 | write_offset = log_buf_state_local.sampled_write_ptr; |
5aa1ee4b AG |
1030 | full_cnt = log_buf_state_local.buffer_full_cnt; |
1031 | ||
1032 | /* Bookkeeping stuff */ | |
1033 | guc->log.flush_count[type] += log_buf_state_local.flush_to_file; | |
6941f3c9 | 1034 | new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt); |
4100b2ab SAK |
1035 | |
1036 | /* Update the state of shared log buffer */ | |
1037 | log_buf_state->read_ptr = write_offset; | |
1038 | log_buf_state->flush_to_file = 0; | |
1039 | log_buf_state++; | |
1040 | ||
1041 | if (unlikely(!log_buf_snapshot_state)) | |
1042 | continue; | |
1043 | ||
1044 | /* First copy the state structure in snapshot buffer */ | |
1045 | memcpy(log_buf_snapshot_state, &log_buf_state_local, | |
1046 | sizeof(struct guc_log_buffer_state)); | |
1047 | ||
1048 | /* The write pointer could have been updated by GuC firmware, | |
1049 | * after sending the flush interrupt to Host, for consistency | |
1050 | * set write pointer value to same value of sampled_write_ptr | |
1051 | * in the snapshot buffer. | |
1052 | */ | |
1053 | log_buf_snapshot_state->write_ptr = write_offset; | |
1054 | log_buf_snapshot_state++; | |
1055 | ||
1056 | /* Now copy the actual logs. */ | |
6941f3c9 AG |
1057 | if (unlikely(new_overflow)) { |
1058 | /* copy the whole buffer in case of overflow */ | |
1059 | read_offset = 0; | |
1060 | write_offset = buffer_size; | |
1061 | } else if (unlikely((read_offset > buffer_size) || | |
1062 | (write_offset > buffer_size))) { | |
1063 | DRM_ERROR("invalid log buffer state\n"); | |
1064 | /* copy whole buffer as offsets are unreliable */ | |
1065 | read_offset = 0; | |
1066 | write_offset = buffer_size; | |
1067 | } | |
1068 | ||
1069 | /* Just copy the newly written data */ | |
1070 | if (read_offset > write_offset) { | |
71706590 | 1071 | i915_memcpy_from_wc(dst_data, src_data, write_offset); |
6941f3c9 AG |
1072 | bytes_to_copy = buffer_size - read_offset; |
1073 | } else { | |
1074 | bytes_to_copy = write_offset - read_offset; | |
1075 | } | |
71706590 AG |
1076 | i915_memcpy_from_wc(dst_data + read_offset, |
1077 | src_data + read_offset, bytes_to_copy); | |
4100b2ab SAK |
1078 | |
1079 | src_data += buffer_size; | |
1080 | dst_data += buffer_size; | |
4100b2ab SAK |
1081 | } |
1082 | ||
1083 | if (log_buf_snapshot_state) | |
1084 | guc_move_to_next_buf(guc); | |
f8240835 AG |
1085 | else { |
1086 | /* Used rate limited to avoid deluge of messages, logs might be | |
1087 | * getting consumed by User at a slow rate. | |
1088 | */ | |
1089 | DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n"); | |
5aa1ee4b | 1090 | guc->log.capture_miss_count++; |
f8240835 | 1091 | } |
4100b2ab SAK |
1092 | } |
1093 | ||
1094 | static void guc_capture_logs_work(struct work_struct *work) | |
1095 | { | |
1096 | struct drm_i915_private *dev_priv = | |
1097 | container_of(work, struct drm_i915_private, guc.log.flush_work); | |
1098 | ||
1099 | i915_guc_capture_logs(dev_priv); | |
1100 | } | |
1101 | ||
1102 | static void guc_log_cleanup(struct intel_guc *guc) | |
1103 | { | |
1104 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
1105 | ||
1106 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1107 | ||
1108 | /* First disable the flush interrupt */ | |
1109 | gen9_disable_guc_interrupts(dev_priv); | |
1110 | ||
1111 | if (guc->log.flush_wq) | |
1112 | destroy_workqueue(guc->log.flush_wq); | |
1113 | ||
1114 | guc->log.flush_wq = NULL; | |
1115 | ||
f8240835 AG |
1116 | if (guc->log.relay_chan) |
1117 | guc_log_remove_relay_file(guc); | |
1118 | ||
1119 | guc->log.relay_chan = NULL; | |
1120 | ||
4100b2ab SAK |
1121 | if (guc->log.buf_addr) |
1122 | i915_gem_object_unpin_map(guc->log.vma->obj); | |
1123 | ||
1124 | guc->log.buf_addr = NULL; | |
1125 | } | |
1126 | ||
1127 | static int guc_log_create_extras(struct intel_guc *guc) | |
1128 | { | |
1129 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
1130 | void *vaddr; | |
1131 | int ret; | |
1132 | ||
1133 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1134 | ||
1135 | /* Nothing to do */ | |
1136 | if (i915.guc_log_level < 0) | |
1137 | return 0; | |
1138 | ||
1139 | if (!guc->log.buf_addr) { | |
71706590 AG |
1140 | /* Create a WC (Uncached for read) vmalloc mapping of log |
1141 | * buffer pages, so that we can directly get the data | |
1142 | * (up-to-date) from memory. | |
1143 | */ | |
1144 | vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC); | |
4100b2ab SAK |
1145 | if (IS_ERR(vaddr)) { |
1146 | ret = PTR_ERR(vaddr); | |
1147 | DRM_ERROR("Couldn't map log buffer pages %d\n", ret); | |
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | guc->log.buf_addr = vaddr; | |
1152 | } | |
1153 | ||
1e6b8b0d AG |
1154 | if (!guc->log.relay_chan) { |
1155 | /* Create a relay channel, so that we have buffers for storing | |
1156 | * the GuC firmware logs, the channel will be linked with a file | |
1157 | * later on when debugfs is registered. | |
1158 | */ | |
1159 | ret = guc_log_create_relay_channel(guc); | |
1160 | if (ret) | |
1161 | return ret; | |
1162 | } | |
1163 | ||
4100b2ab SAK |
1164 | if (!guc->log.flush_wq) { |
1165 | INIT_WORK(&guc->log.flush_work, guc_capture_logs_work); | |
1166 | ||
7ef54de7 AG |
1167 | /* |
1168 | * GuC log buffer flush work item has to do register access to | |
1169 | * send the ack to GuC and this work item, if not synced before | |
1170 | * suspend, can potentially get executed after the GFX device is | |
1171 | * suspended. | |
1172 | * By marking the WQ as freezable, we don't have to bother about | |
1173 | * flushing of this work item from the suspend hooks, the pending | |
1174 | * work item if any will be either executed before the suspend | |
1175 | * or scheduled later on resume. This way the handling of work | |
1176 | * item can be kept same between system suspend & rpm suspend. | |
4100b2ab | 1177 | */ |
7ef54de7 AG |
1178 | guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log", |
1179 | WQ_HIGHPRI | WQ_FREEZABLE); | |
4100b2ab SAK |
1180 | if (guc->log.flush_wq == NULL) { |
1181 | DRM_ERROR("Couldn't allocate the wq for GuC logging\n"); | |
1182 | return -ENOMEM; | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
7a9347f9 | 1189 | static void guc_log_create(struct intel_guc *guc) |
4c7e77fc | 1190 | { |
8b797af1 | 1191 | struct i915_vma *vma; |
4c7e77fc AD |
1192 | unsigned long offset; |
1193 | uint32_t size, flags; | |
1194 | ||
4c7e77fc AD |
1195 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) |
1196 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; | |
1197 | ||
1198 | /* The first page is to save log buffer state. Allocate one | |
1199 | * extra page for others in case for overlap */ | |
1200 | size = (1 + GUC_LOG_DPC_PAGES + 1 + | |
1201 | GUC_LOG_ISR_PAGES + 1 + | |
1202 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; | |
1203 | ||
d6b40b4b | 1204 | vma = guc->log.vma; |
8b797af1 | 1205 | if (!vma) { |
71706590 AG |
1206 | /* We require SSE 4.1 for fast reads from the GuC log buffer and |
1207 | * it should be present on the chipsets supporting GuC based | |
1208 | * submisssions. | |
1209 | */ | |
1210 | if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) { | |
1211 | /* logging will not be enabled */ | |
1212 | i915.guc_log_level = -1; | |
1213 | return; | |
1214 | } | |
1215 | ||
8b797af1 CW |
1216 | vma = guc_allocate_vma(guc, size); |
1217 | if (IS_ERR(vma)) { | |
4c7e77fc AD |
1218 | /* logging will be off */ |
1219 | i915.guc_log_level = -1; | |
1220 | return; | |
1221 | } | |
1222 | ||
d6b40b4b | 1223 | guc->log.vma = vma; |
4100b2ab SAK |
1224 | |
1225 | if (guc_log_create_extras(guc)) { | |
1226 | guc_log_cleanup(guc); | |
1227 | i915_vma_unpin_and_release(&guc->log.vma); | |
1228 | i915.guc_log_level = -1; | |
1229 | return; | |
1230 | } | |
4c7e77fc AD |
1231 | } |
1232 | ||
1233 | /* each allocated unit is a page */ | |
1234 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | | |
1235 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | | |
1236 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | | |
1237 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); | |
1238 | ||
bde13ebd | 1239 | offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */ |
d6b40b4b | 1240 | guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; |
4c7e77fc AD |
1241 | } |
1242 | ||
f8240835 AG |
1243 | static int guc_log_late_setup(struct intel_guc *guc) |
1244 | { | |
1245 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
1246 | int ret; | |
1247 | ||
1248 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1249 | ||
1250 | if (i915.guc_log_level < 0) | |
1251 | return -EINVAL; | |
1252 | ||
1253 | /* If log_level was set as -1 at boot time, then setup needed to | |
1254 | * handle log buffer flush interrupts would not have been done yet, | |
1255 | * so do that now. | |
1256 | */ | |
1257 | ret = guc_log_create_extras(guc); | |
1258 | if (ret) | |
1259 | goto err; | |
1260 | ||
1261 | ret = guc_log_create_relay_file(guc); | |
1262 | if (ret) | |
1263 | goto err; | |
1264 | ||
1265 | return 0; | |
1266 | err: | |
1267 | guc_log_cleanup(guc); | |
1268 | /* logging will remain off */ | |
1269 | i915.guc_log_level = -1; | |
1270 | return ret; | |
1271 | } | |
1272 | ||
7a9347f9 | 1273 | static void guc_policies_init(struct guc_policies *policies) |
463704d0 AD |
1274 | { |
1275 | struct guc_policy *policy; | |
1276 | u32 p, i; | |
1277 | ||
1278 | policies->dpc_promote_time = 500000; | |
1279 | policies->max_num_work_items = POLICY_MAX_NUM_WI; | |
1280 | ||
1281 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { | |
397097b0 | 1282 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
463704d0 AD |
1283 | policy = &policies->policy[p][i]; |
1284 | ||
1285 | policy->execution_quantum = 1000000; | |
1286 | policy->preemption_time = 500000; | |
1287 | policy->fault_time = 250000; | |
1288 | policy->policy_flags = 0; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | policies->is_valid = 1; | |
1293 | } | |
1294 | ||
7a9347f9 | 1295 | static void guc_addon_create(struct intel_guc *guc) |
68371a95 AD |
1296 | { |
1297 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
8b797af1 | 1298 | struct i915_vma *vma; |
68371a95 | 1299 | struct guc_ads *ads; |
463704d0 | 1300 | struct guc_policies *policies; |
5c148e04 | 1301 | struct guc_mmio_reg_state *reg_state; |
e2f80391 | 1302 | struct intel_engine_cs *engine; |
3b3f1650 | 1303 | enum intel_engine_id id; |
68371a95 | 1304 | struct page *page; |
b4ac5afc | 1305 | u32 size; |
68371a95 AD |
1306 | |
1307 | /* The ads obj includes the struct itself and buffers passed to GuC */ | |
5c148e04 AD |
1308 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
1309 | sizeof(struct guc_mmio_reg_state) + | |
1310 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; | |
68371a95 | 1311 | |
8b797af1 CW |
1312 | vma = guc->ads_vma; |
1313 | if (!vma) { | |
1314 | vma = guc_allocate_vma(guc, PAGE_ALIGN(size)); | |
1315 | if (IS_ERR(vma)) | |
68371a95 AD |
1316 | return; |
1317 | ||
8b797af1 | 1318 | guc->ads_vma = vma; |
68371a95 AD |
1319 | } |
1320 | ||
8b797af1 | 1321 | page = i915_vma_first_page(vma); |
68371a95 AD |
1322 | ads = kmap(page); |
1323 | ||
1324 | /* | |
1325 | * The GuC requires a "Golden Context" when it reinitialises | |
1326 | * engines after a reset. Here we use the Render ring default | |
1327 | * context, which must already exist and be pinned in the GGTT, | |
1328 | * so its address won't change after we've told the GuC where | |
1329 | * to find it. | |
1330 | */ | |
3b3f1650 | 1331 | engine = dev_priv->engine[RCS]; |
57e88531 | 1332 | ads->golden_context_lrca = engine->status_page.ggtt_offset; |
68371a95 | 1333 | |
3b3f1650 | 1334 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 1335 | ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); |
68371a95 | 1336 | |
463704d0 AD |
1337 | /* GuC scheduling policies */ |
1338 | policies = (void *)ads + sizeof(struct guc_ads); | |
7a9347f9 | 1339 | guc_policies_init(policies); |
463704d0 | 1340 | |
bde13ebd CW |
1341 | ads->scheduler_policies = |
1342 | i915_ggtt_offset(vma) + sizeof(struct guc_ads); | |
463704d0 | 1343 | |
5c148e04 AD |
1344 | /* MMIO reg state */ |
1345 | reg_state = (void *)policies + sizeof(struct guc_policies); | |
1346 | ||
3b3f1650 | 1347 | for_each_engine(engine, dev_priv, id) { |
e2f80391 TU |
1348 | reg_state->mmio_white_list[engine->guc_id].mmio_start = |
1349 | engine->mmio_base + GUC_MMIO_WHITE_LIST_START; | |
5c148e04 AD |
1350 | |
1351 | /* Nothing to be saved or restored for now. */ | |
e2f80391 | 1352 | reg_state->mmio_white_list[engine->guc_id].count = 0; |
5c148e04 AD |
1353 | } |
1354 | ||
1355 | ads->reg_state_addr = ads->scheduler_policies + | |
1356 | sizeof(struct guc_policies); | |
1357 | ||
1358 | ads->reg_state_buffer = ads->reg_state_addr + | |
1359 | sizeof(struct guc_mmio_reg_state); | |
1360 | ||
68371a95 AD |
1361 | kunmap(page); |
1362 | } | |
1363 | ||
bac427f8 AD |
1364 | /* |
1365 | * Set up the memory resources to be shared with the GuC. At this point, | |
1366 | * we require just one object that can be mapped through the GGTT. | |
1367 | */ | |
beffa517 | 1368 | int i915_guc_submission_init(struct drm_i915_private *dev_priv) |
bac427f8 | 1369 | { |
7a9347f9 DG |
1370 | const size_t ctxsize = sizeof(struct guc_context_desc); |
1371 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; | |
1372 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); | |
bac427f8 | 1373 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 | 1374 | struct i915_vma *vma; |
bac427f8 | 1375 | |
4d357af4 CW |
1376 | if (!HAS_GUC_SCHED(dev_priv)) |
1377 | return 0; | |
1378 | ||
29fb72c7 DG |
1379 | /* Wipe bitmap & delete client in case of reinitialisation */ |
1380 | bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS); | |
beffa517 | 1381 | i915_guc_submission_disable(dev_priv); |
29fb72c7 | 1382 | |
bac427f8 AD |
1383 | if (!i915.enable_guc_submission) |
1384 | return 0; /* not enabled */ | |
1385 | ||
8b797af1 | 1386 | if (guc->ctx_pool_vma) |
bac427f8 AD |
1387 | return 0; /* already allocated */ |
1388 | ||
7a9347f9 | 1389 | vma = guc_allocate_vma(guc, gemsize); |
8b797af1 CW |
1390 | if (IS_ERR(vma)) |
1391 | return PTR_ERR(vma); | |
bac427f8 | 1392 | |
8b797af1 | 1393 | guc->ctx_pool_vma = vma; |
bac427f8 | 1394 | ida_init(&guc->ctx_ids); |
7a9347f9 DG |
1395 | guc_log_create(guc); |
1396 | guc_addon_create(guc); | |
68371a95 | 1397 | |
4d357af4 CW |
1398 | guc->execbuf_client = guc_client_alloc(dev_priv, |
1399 | INTEL_INFO(dev_priv)->ring_mask, | |
1400 | GUC_CTX_PRIORITY_KMD_NORMAL, | |
1401 | dev_priv->kernel_context); | |
1402 | if (!guc->execbuf_client) { | |
1403 | DRM_ERROR("Failed to create GuC client for execbuf!\n"); | |
1404 | goto err; | |
1405 | } | |
1406 | ||
bac427f8 | 1407 | return 0; |
4d357af4 CW |
1408 | |
1409 | err: | |
1410 | i915_guc_submission_fini(dev_priv); | |
1411 | return -ENOMEM; | |
1412 | } | |
1413 | ||
1414 | static void guc_reset_wq(struct i915_guc_client *gc) | |
1415 | { | |
1416 | struct guc_process_desc *desc = gc->vaddr + gc->proc_desc_offset; | |
1417 | ||
1418 | desc->head = 0; | |
1419 | desc->tail = 0; | |
1420 | ||
1421 | gc->wq_tail = 0; | |
bac427f8 AD |
1422 | } |
1423 | ||
beffa517 | 1424 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv) |
44a28b1d | 1425 | { |
44a28b1d | 1426 | struct intel_guc *guc = &dev_priv->guc; |
4d357af4 | 1427 | struct i915_guc_client *client = guc->execbuf_client; |
ddd66c51 | 1428 | struct intel_engine_cs *engine; |
3b3f1650 | 1429 | enum intel_engine_id id; |
44a28b1d | 1430 | |
4d357af4 CW |
1431 | if (!client) |
1432 | return -ENODEV; | |
44a28b1d | 1433 | |
2d803c2d | 1434 | intel_guc_sample_forcewake(guc); |
4d357af4 CW |
1435 | |
1436 | guc_reset_wq(client); | |
4d75787b | 1437 | guc_init_doorbell_hw(guc); |
f5d3c3ea | 1438 | |
ddd66c51 | 1439 | /* Take over from manual control of ELSP (execlists) */ |
3b3f1650 | 1440 | for_each_engine(engine, dev_priv, id) { |
4d357af4 CW |
1441 | struct drm_i915_gem_request *rq; |
1442 | ||
ddd66c51 | 1443 | engine->submit_request = i915_guc_submit; |
20311bd3 | 1444 | engine->schedule = NULL; |
ddd66c51 | 1445 | |
821ed7df | 1446 | /* Replay the current set of previously submitted requests */ |
4d357af4 | 1447 | list_for_each_entry(rq, &engine->timeline->requests, link) { |
dadd481b | 1448 | client->wq_rsvd += sizeof(struct guc_wq_item); |
34ba5a80 | 1449 | __i915_guc_submit(rq); |
dadd481b | 1450 | } |
821ed7df CW |
1451 | } |
1452 | ||
44a28b1d DG |
1453 | return 0; |
1454 | } | |
1455 | ||
beffa517 | 1456 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv) |
44a28b1d | 1457 | { |
44a28b1d DG |
1458 | struct intel_guc *guc = &dev_priv->guc; |
1459 | ||
ddd66c51 CW |
1460 | if (!guc->execbuf_client) |
1461 | return; | |
1462 | ||
ddd66c51 CW |
1463 | /* Revert back to manual ELSP submission */ |
1464 | intel_execlists_enable_submission(dev_priv); | |
44a28b1d DG |
1465 | } |
1466 | ||
beffa517 | 1467 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv) |
bac427f8 | 1468 | { |
bac427f8 | 1469 | struct intel_guc *guc = &dev_priv->guc; |
4d357af4 CW |
1470 | struct i915_guc_client *client; |
1471 | ||
1472 | client = fetch_and_zero(&guc->execbuf_client); | |
1473 | if (!client) | |
1474 | return; | |
1475 | ||
1476 | guc_client_free(dev_priv, client); | |
bac427f8 | 1477 | |
19880c4a | 1478 | i915_vma_unpin_and_release(&guc->ads_vma); |
d6b40b4b | 1479 | i915_vma_unpin_and_release(&guc->log.vma); |
4c7e77fc | 1480 | |
8b797af1 | 1481 | if (guc->ctx_pool_vma) |
bac427f8 | 1482 | ida_destroy(&guc->ctx_ids); |
19880c4a | 1483 | i915_vma_unpin_and_release(&guc->ctx_pool_vma); |
bac427f8 | 1484 | } |
a1c41994 AD |
1485 | |
1486 | /** | |
1487 | * intel_guc_suspend() - notify GuC entering suspend state | |
1488 | * @dev: drm device | |
1489 | */ | |
1490 | int intel_guc_suspend(struct drm_device *dev) | |
1491 | { | |
fac5e23e | 1492 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1c41994 | 1493 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 1494 | struct i915_gem_context *ctx; |
a1c41994 AD |
1495 | u32 data[3]; |
1496 | ||
fce91f22 | 1497 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1498 | return 0; |
1499 | ||
26705e20 SAK |
1500 | gen9_disable_guc_interrupts(dev_priv); |
1501 | ||
ed54c1a1 | 1502 | ctx = dev_priv->kernel_context; |
a1c41994 | 1503 | |
a80bc45f | 1504 | data[0] = INTEL_GUC_ACTION_ENTER_S_STATE; |
a1c41994 AD |
1505 | /* any value greater than GUC_POWER_D0 */ |
1506 | data[1] = GUC_POWER_D1; | |
1507 | /* first page is shared data with GuC */ | |
bde13ebd | 1508 | data[2] = i915_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 | 1509 | |
2d803c2d | 1510 | return intel_guc_send(guc, data, ARRAY_SIZE(data)); |
a1c41994 AD |
1511 | } |
1512 | ||
1513 | ||
1514 | /** | |
1515 | * intel_guc_resume() - notify GuC resuming from suspend state | |
1516 | * @dev: drm device | |
1517 | */ | |
1518 | int intel_guc_resume(struct drm_device *dev) | |
1519 | { | |
fac5e23e | 1520 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1c41994 | 1521 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 1522 | struct i915_gem_context *ctx; |
a1c41994 AD |
1523 | u32 data[3]; |
1524 | ||
fce91f22 | 1525 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1526 | return 0; |
1527 | ||
26705e20 SAK |
1528 | if (i915.guc_log_level >= 0) |
1529 | gen9_enable_guc_interrupts(dev_priv); | |
1530 | ||
ed54c1a1 | 1531 | ctx = dev_priv->kernel_context; |
a1c41994 | 1532 | |
a80bc45f | 1533 | data[0] = INTEL_GUC_ACTION_EXIT_S_STATE; |
a1c41994 AD |
1534 | data[1] = GUC_POWER_D0; |
1535 | /* first page is shared data with GuC */ | |
bde13ebd | 1536 | data[2] = i915_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 | 1537 | |
2d803c2d | 1538 | return intel_guc_send(guc, data, ARRAY_SIZE(data)); |
a1c41994 | 1539 | } |
4100b2ab SAK |
1540 | |
1541 | void i915_guc_capture_logs(struct drm_i915_private *dev_priv) | |
1542 | { | |
1543 | guc_read_update_log_buffer(&dev_priv->guc); | |
1544 | ||
1545 | /* Generally device is expected to be active only at this | |
1546 | * time, so get/put should be really quick. | |
1547 | */ | |
1548 | intel_runtime_pm_get(dev_priv); | |
2d803c2d | 1549 | intel_guc_log_flush_complete(&dev_priv->guc); |
4100b2ab SAK |
1550 | intel_runtime_pm_put(dev_priv); |
1551 | } | |
f8240835 | 1552 | |
896a0cb0 SAK |
1553 | void i915_guc_flush_logs(struct drm_i915_private *dev_priv) |
1554 | { | |
1555 | if (!i915.enable_guc_submission || (i915.guc_log_level < 0)) | |
1556 | return; | |
1557 | ||
1558 | /* First disable the interrupts, will be renabled afterwards */ | |
1559 | gen9_disable_guc_interrupts(dev_priv); | |
1560 | ||
1561 | /* Before initiating the forceful flush, wait for any pending/ongoing | |
1562 | * flush to complete otherwise forceful flush may not actually happen. | |
1563 | */ | |
1564 | flush_work(&dev_priv->guc.log.flush_work); | |
1565 | ||
1566 | /* Ask GuC to update the log buffer state */ | |
2d803c2d | 1567 | intel_guc_log_flush(&dev_priv->guc); |
896a0cb0 SAK |
1568 | |
1569 | /* GuC would have updated log buffer by now, so capture it */ | |
1570 | i915_guc_capture_logs(dev_priv); | |
1571 | } | |
1572 | ||
f8240835 AG |
1573 | void i915_guc_unregister(struct drm_i915_private *dev_priv) |
1574 | { | |
1575 | if (!i915.enable_guc_submission) | |
1576 | return; | |
1577 | ||
1578 | mutex_lock(&dev_priv->drm.struct_mutex); | |
1579 | guc_log_cleanup(&dev_priv->guc); | |
1580 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1581 | } | |
1582 | ||
1583 | void i915_guc_register(struct drm_i915_private *dev_priv) | |
1584 | { | |
1585 | if (!i915.enable_guc_submission) | |
1586 | return; | |
1587 | ||
1588 | mutex_lock(&dev_priv->drm.struct_mutex); | |
1589 | guc_log_late_setup(&dev_priv->guc); | |
1590 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1591 | } | |
685534ef SAK |
1592 | |
1593 | int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) | |
1594 | { | |
1595 | union guc_log_control log_param; | |
1596 | int ret; | |
1597 | ||
1598 | log_param.value = control_val; | |
1599 | ||
1600 | if (log_param.verbosity < GUC_LOG_VERBOSITY_MIN || | |
1601 | log_param.verbosity > GUC_LOG_VERBOSITY_MAX) | |
1602 | return -EINVAL; | |
1603 | ||
1604 | /* This combination doesn't make sense & won't have any effect */ | |
1605 | if (!log_param.logging_enabled && (i915.guc_log_level < 0)) | |
1606 | return 0; | |
1607 | ||
2d803c2d | 1608 | ret = intel_guc_log_control(&dev_priv->guc, log_param.value); |
685534ef | 1609 | if (ret < 0) { |
a80bc45f | 1610 | DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret); |
685534ef SAK |
1611 | return ret; |
1612 | } | |
1613 | ||
1614 | i915.guc_log_level = log_param.verbosity; | |
1615 | ||
1616 | /* If log_level was set as -1 at boot time, then the relay channel file | |
1617 | * wouldn't have been created by now and interrupts also would not have | |
1618 | * been enabled. | |
1619 | */ | |
1620 | if (!dev_priv->guc.log.relay_chan) { | |
1621 | ret = guc_log_late_setup(&dev_priv->guc); | |
1622 | if (!ret) | |
1623 | gen9_enable_guc_interrupts(dev_priv); | |
1624 | } else if (!log_param.logging_enabled) { | |
1625 | /* Once logging is disabled, GuC won't generate logs & send an | |
1626 | * interrupt. But there could be some data in the log buffer | |
1627 | * which is yet to be captured. So request GuC to update the log | |
1628 | * buffer state and then collect the left over logs. | |
1629 | */ | |
1630 | i915_guc_flush_logs(dev_priv); | |
1631 | ||
1632 | /* As logging is disabled, update log level to reflect that */ | |
1633 | i915.guc_log_level = -1; | |
1634 | } else { | |
1635 | /* In case interrupts were disabled, enable them now */ | |
1636 | gen9_enable_guc_interrupts(dev_priv); | |
1637 | } | |
1638 | ||
1639 | return ret; | |
1640 | } |