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bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/circ_buf.h> | |
f8240835 AG |
26 | #include <linux/debugfs.h> |
27 | #include <linux/relay.h> | |
bac427f8 | 28 | #include "i915_drv.h" |
8c4f24f9 | 29 | #include "intel_uc.h" |
bac427f8 | 30 | |
44a28b1d | 31 | /** |
feda33ef | 32 | * DOC: GuC-based command submission |
44a28b1d DG |
33 | * |
34 | * i915_guc_client: | |
35 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
36 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
37 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
38 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
39 | * is mapped to client space. So the client can write Work Item then ring the | |
40 | * doorbell. | |
41 | * | |
42 | * To simplify the implementation, we allocate one gem object that contains all | |
43 | * pages for doorbell, process descriptor and workqueue. | |
44 | * | |
45 | * The Scratch registers: | |
46 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
47 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
48 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
49 | * Firmware writes a success/fail code back to the action register after | |
50 | * processes the request. The kernel driver polls waiting for this update and | |
51 | * then proceeds. | |
2d803c2d | 52 | * See intel_guc_send() |
44a28b1d DG |
53 | * |
54 | * Doorbells: | |
55 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
56 | * mapped into process space. | |
57 | * | |
58 | * Work Items: | |
59 | * There are several types of work items that the host may place into a | |
60 | * workqueue, each with its own requirements and limitations. Currently only | |
61 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
62 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
63 | * ELSP context descriptor dword into Work Item. | |
7a9347f9 | 64 | * See guc_wq_item_append() |
44a28b1d DG |
65 | * |
66 | */ | |
67 | ||
44a28b1d DG |
68 | /* |
69 | * Tell the GuC to allocate or deallocate a specific doorbell | |
70 | */ | |
71 | ||
a80bc45f AH |
72 | static int guc_allocate_doorbell(struct intel_guc *guc, |
73 | struct i915_guc_client *client) | |
44a28b1d | 74 | { |
2d803c2d AH |
75 | u32 action[] = { |
76 | INTEL_GUC_ACTION_ALLOCATE_DOORBELL, | |
77 | client->ctx_index | |
78 | }; | |
44a28b1d | 79 | |
2d803c2d | 80 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
44a28b1d DG |
81 | } |
82 | ||
a80bc45f AH |
83 | static int guc_release_doorbell(struct intel_guc *guc, |
84 | struct i915_guc_client *client) | |
44a28b1d | 85 | { |
2d803c2d AH |
86 | u32 action[] = { |
87 | INTEL_GUC_ACTION_DEALLOCATE_DOORBELL, | |
88 | client->ctx_index | |
89 | }; | |
685534ef | 90 | |
2d803c2d | 91 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
685534ef SAK |
92 | } |
93 | ||
44a28b1d DG |
94 | /* |
95 | * Initialise, update, or clear doorbell data shared with the GuC | |
96 | * | |
97 | * These functions modify shared data and so need access to the mapped | |
98 | * client object which contains the page being used for the doorbell | |
99 | */ | |
100 | ||
a667429b DG |
101 | static int guc_update_doorbell_id(struct intel_guc *guc, |
102 | struct i915_guc_client *client, | |
103 | u16 new_id) | |
44a28b1d | 104 | { |
8b797af1 | 105 | struct sg_table *sg = guc->ctx_pool_vma->pages; |
a667429b | 106 | void *doorbell_bitmap = guc->doorbell_bitmap; |
44a28b1d | 107 | struct guc_doorbell_info *doorbell; |
a667429b DG |
108 | struct guc_context_desc desc; |
109 | size_t len; | |
44a28b1d | 110 | |
72aa0d89 | 111 | doorbell = client->vaddr + client->doorbell_offset; |
44a28b1d | 112 | |
a667429b DG |
113 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID && |
114 | test_bit(client->doorbell_id, doorbell_bitmap)) { | |
115 | /* Deactivate the old doorbell */ | |
116 | doorbell->db_status = GUC_DOORBELL_DISABLED; | |
a80bc45f | 117 | (void)guc_release_doorbell(guc, client); |
a667429b DG |
118 | __clear_bit(client->doorbell_id, doorbell_bitmap); |
119 | } | |
120 | ||
121 | /* Update the GuC's idea of the doorbell ID */ | |
122 | len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
123 | sizeof(desc) * client->ctx_index); | |
124 | if (len != sizeof(desc)) | |
125 | return -EFAULT; | |
126 | desc.db_id = new_id; | |
127 | len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
128 | sizeof(desc) * client->ctx_index); | |
129 | if (len != sizeof(desc)) | |
130 | return -EFAULT; | |
131 | ||
132 | client->doorbell_id = new_id; | |
133 | if (new_id == GUC_INVALID_DOORBELL_ID) | |
134 | return 0; | |
135 | ||
136 | /* Activate the new doorbell */ | |
137 | __set_bit(new_id, doorbell_bitmap); | |
44a28b1d | 138 | doorbell->cookie = 0; |
a667429b | 139 | doorbell->db_status = GUC_DOORBELL_ENABLED; |
a80bc45f | 140 | return guc_allocate_doorbell(guc, client); |
a667429b DG |
141 | } |
142 | ||
143 | static int guc_init_doorbell(struct intel_guc *guc, | |
144 | struct i915_guc_client *client, | |
145 | uint16_t db_id) | |
146 | { | |
147 | return guc_update_doorbell_id(guc, client, db_id); | |
44a28b1d DG |
148 | } |
149 | ||
44a28b1d DG |
150 | static void guc_disable_doorbell(struct intel_guc *guc, |
151 | struct i915_guc_client *client) | |
152 | { | |
a667429b | 153 | (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID); |
44a28b1d | 154 | |
44a28b1d DG |
155 | /* XXX: wait for any interrupts */ |
156 | /* XXX: wait for workqueue to drain */ | |
157 | } | |
158 | ||
f10d69a7 DG |
159 | static uint16_t |
160 | select_doorbell_register(struct intel_guc *guc, uint32_t priority) | |
161 | { | |
162 | /* | |
163 | * The bitmap tracks which doorbell registers are currently in use. | |
164 | * It is split into two halves; the first half is used for normal | |
165 | * priority contexts, the second half for high-priority ones. | |
166 | * Note that logically higher priorities are numerically less than | |
167 | * normal ones, so the test below means "is it high-priority?" | |
168 | */ | |
169 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
170 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
171 | const uint16_t start = hi_pri ? half : 0; | |
172 | const uint16_t end = start + half; | |
173 | uint16_t id; | |
174 | ||
175 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); | |
176 | if (id == end) | |
177 | id = GUC_INVALID_DOORBELL_ID; | |
178 | ||
179 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
180 | hi_pri ? "high" : "normal", id); | |
181 | ||
182 | return id; | |
183 | } | |
184 | ||
44a28b1d DG |
185 | /* |
186 | * Select, assign and relase doorbell cachelines | |
187 | * | |
188 | * These functions track which doorbell cachelines are in use. | |
2d803c2d | 189 | * The data they manipulate is protected by the intel_guc_send lock. |
44a28b1d DG |
190 | */ |
191 | ||
192 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
193 | { | |
194 | const uint32_t cacheline_size = cache_line_size(); | |
195 | uint32_t offset; | |
196 | ||
44a28b1d DG |
197 | /* Doorbell uses a single cache line within a page */ |
198 | offset = offset_in_page(guc->db_cacheline); | |
199 | ||
200 | /* Moving to next cache line to reduce contention */ | |
201 | guc->db_cacheline += cacheline_size; | |
202 | ||
44a28b1d DG |
203 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
204 | offset, guc->db_cacheline, cacheline_size); | |
205 | ||
206 | return offset; | |
207 | } | |
208 | ||
44a28b1d DG |
209 | /* |
210 | * Initialise the process descriptor shared with the GuC firmware. | |
211 | */ | |
7a9347f9 | 212 | static void guc_proc_desc_init(struct intel_guc *guc, |
44a28b1d DG |
213 | struct i915_guc_client *client) |
214 | { | |
215 | struct guc_process_desc *desc; | |
44a28b1d | 216 | |
72aa0d89 | 217 | desc = client->vaddr + client->proc_desc_offset; |
44a28b1d DG |
218 | |
219 | memset(desc, 0, sizeof(*desc)); | |
220 | ||
221 | /* | |
222 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
223 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
224 | * space for kernel clients (map on demand instead? May make debug | |
225 | * easier to have it mapped). | |
226 | */ | |
227 | desc->wq_base_addr = 0; | |
228 | desc->db_base_addr = 0; | |
229 | ||
230 | desc->context_id = client->ctx_index; | |
231 | desc->wq_size_bytes = client->wq_size; | |
232 | desc->wq_status = WQ_STATUS_ACTIVE; | |
233 | desc->priority = client->priority; | |
44a28b1d DG |
234 | } |
235 | ||
236 | /* | |
237 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
238 | * | |
239 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
240 | * data structures relating to this client (doorbell, process descriptor, | |
241 | * write queue, etc). | |
242 | */ | |
243 | ||
7a9347f9 | 244 | static void guc_ctx_desc_init(struct intel_guc *guc, |
44a28b1d DG |
245 | struct i915_guc_client *client) |
246 | { | |
397097b0 | 247 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
e2f80391 | 248 | struct intel_engine_cs *engine; |
e2efd130 | 249 | struct i915_gem_context *ctx = client->owner; |
44a28b1d DG |
250 | struct guc_context_desc desc; |
251 | struct sg_table *sg; | |
bafb0fce | 252 | unsigned int tmp; |
86e06cc0 | 253 | u32 gfx_addr; |
44a28b1d DG |
254 | |
255 | memset(&desc, 0, sizeof(desc)); | |
256 | ||
257 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
258 | desc.context_id = client->ctx_index; | |
259 | desc.priority = client->priority; | |
44a28b1d DG |
260 | desc.db_id = client->doorbell_id; |
261 | ||
bafb0fce | 262 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { |
9021ad03 | 263 | struct intel_context *ce = &ctx->engine[engine->id]; |
c18468c4 DG |
264 | uint32_t guc_engine_id = engine->guc_id; |
265 | struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id]; | |
d1675198 AD |
266 | |
267 | /* TODO: We have a design issue to be solved here. Only when we | |
268 | * receive the first batch, we know which engine is used by the | |
269 | * user. But here GuC expects the lrc and ring to be pinned. It | |
270 | * is not an issue for default context, which is the only one | |
271 | * for now who owns a GuC client. But for future owner of GuC | |
272 | * client, need to make sure lrc is pinned prior to enter here. | |
273 | */ | |
9021ad03 | 274 | if (!ce->state) |
d1675198 AD |
275 | break; /* XXX: continue? */ |
276 | ||
9021ad03 | 277 | lrc->context_desc = lower_32_bits(ce->lrc_desc); |
d1675198 AD |
278 | |
279 | /* The state page is after PPHWSP */ | |
57e88531 | 280 | lrc->ring_lcra = |
bde13ebd | 281 | i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; |
d1675198 | 282 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
c18468c4 | 283 | (guc_engine_id << GUC_ELC_ENGINE_OFFSET); |
d1675198 | 284 | |
bde13ebd | 285 | lrc->ring_begin = i915_ggtt_offset(ce->ring->vma); |
57e88531 CW |
286 | lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; |
287 | lrc->ring_next_free_location = lrc->ring_begin; | |
d1675198 AD |
288 | lrc->ring_current_tail_pointer_value = 0; |
289 | ||
c18468c4 | 290 | desc.engines_used |= (1 << guc_engine_id); |
d1675198 AD |
291 | } |
292 | ||
e02757d9 DG |
293 | DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", |
294 | client->engines, desc.engines_used); | |
d1675198 AD |
295 | WARN_ON(desc.engines_used == 0); |
296 | ||
44a28b1d | 297 | /* |
86e06cc0 DG |
298 | * The doorbell, process descriptor, and workqueue are all parts |
299 | * of the client object, which the GuC will reference via the GGTT | |
44a28b1d | 300 | */ |
bde13ebd | 301 | gfx_addr = i915_ggtt_offset(client->vma); |
8b797af1 | 302 | desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + |
86e06cc0 | 303 | client->doorbell_offset; |
72aa0d89 CW |
304 | desc.db_trigger_cpu = |
305 | (uintptr_t)client->vaddr + client->doorbell_offset; | |
86e06cc0 DG |
306 | desc.db_trigger_uk = gfx_addr + client->doorbell_offset; |
307 | desc.process_desc = gfx_addr + client->proc_desc_offset; | |
308 | desc.wq_addr = gfx_addr + client->wq_offset; | |
44a28b1d DG |
309 | desc.wq_size = client->wq_size; |
310 | ||
311 | /* | |
e2efd130 | 312 | * XXX: Take LRCs from an existing context if this is not an |
44a28b1d DG |
313 | * IsKMDCreatedContext client |
314 | */ | |
315 | desc.desc_private = (uintptr_t)client; | |
316 | ||
317 | /* Pool context is pinned already */ | |
8b797af1 | 318 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
319 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
320 | sizeof(desc) * client->ctx_index); | |
321 | } | |
322 | ||
7a9347f9 | 323 | static void guc_ctx_desc_fini(struct intel_guc *guc, |
44a28b1d DG |
324 | struct i915_guc_client *client) |
325 | { | |
326 | struct guc_context_desc desc; | |
327 | struct sg_table *sg; | |
328 | ||
329 | memset(&desc, 0, sizeof(desc)); | |
330 | ||
8b797af1 | 331 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
332 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
333 | sizeof(desc) * client->ctx_index); | |
334 | } | |
335 | ||
7c2c270d | 336 | /** |
7a9347f9 | 337 | * i915_guc_wq_reserve() - reserve space in the GuC's workqueue |
7c2c270d DG |
338 | * @request: request associated with the commands |
339 | * | |
340 | * Return: 0 if space is available | |
341 | * -EAGAIN if space is not currently available | |
342 | * | |
343 | * This function must be called (and must return 0) before a request | |
344 | * is submitted to the GuC via i915_guc_submit() below. Once a result | |
7a9347f9 DG |
345 | * of 0 has been returned, it must be balanced by a corresponding |
346 | * call to submit(). | |
7c2c270d | 347 | * |
7a9347f9 | 348 | * Reservation allows the caller to determine in advance that space |
7c2c270d DG |
349 | * will be available for the next submission before committing resources |
350 | * to it, and helps avoid late failures with complicated recovery paths. | |
351 | */ | |
7a9347f9 | 352 | int i915_guc_wq_reserve(struct drm_i915_gem_request *request) |
44a28b1d | 353 | { |
551aaecd | 354 | const size_t wqi_size = sizeof(struct guc_wq_item); |
7c2c270d | 355 | struct i915_guc_client *gc = request->i915->guc.execbuf_client; |
72aa0d89 | 356 | struct guc_process_desc *desc = gc->vaddr + gc->proc_desc_offset; |
551aaecd | 357 | u32 freespace; |
dadd481b | 358 | int ret; |
44a28b1d | 359 | |
dadd481b | 360 | spin_lock(&gc->wq_lock); |
551aaecd | 361 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); |
dadd481b CW |
362 | freespace -= gc->wq_rsvd; |
363 | if (likely(freespace >= wqi_size)) { | |
364 | gc->wq_rsvd += wqi_size; | |
365 | ret = 0; | |
366 | } else { | |
367 | gc->no_wq_space++; | |
368 | ret = -EAGAIN; | |
369 | } | |
370 | spin_unlock(&gc->wq_lock); | |
44a28b1d | 371 | |
dadd481b | 372 | return ret; |
44a28b1d DG |
373 | } |
374 | ||
5ba89908 CW |
375 | void i915_guc_wq_unreserve(struct drm_i915_gem_request *request) |
376 | { | |
377 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
378 | struct i915_guc_client *gc = request->i915->guc.execbuf_client; | |
379 | ||
380 | GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size); | |
381 | ||
382 | spin_lock(&gc->wq_lock); | |
383 | gc->wq_rsvd -= wqi_size; | |
384 | spin_unlock(&gc->wq_lock); | |
385 | } | |
386 | ||
7a9347f9 DG |
387 | /* Construct a Work Item and append it to the GuC's Work Queue */ |
388 | static void guc_wq_item_append(struct i915_guc_client *gc, | |
389 | struct drm_i915_gem_request *rq) | |
44a28b1d | 390 | { |
0a31afbc DG |
391 | /* wqi_len is in DWords, and does not include the one-word header */ |
392 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
393 | const u32 wqi_len = wqi_size/sizeof(u32) - 1; | |
c18468c4 | 394 | struct intel_engine_cs *engine = rq->engine; |
a5916e8f | 395 | struct guc_process_desc *desc; |
44a28b1d | 396 | struct guc_wq_item *wqi; |
72aa0d89 | 397 | u32 freespace, tail, wq_off; |
a7e02199 | 398 | |
72aa0d89 | 399 | desc = gc->vaddr + gc->proc_desc_offset; |
44a28b1d | 400 | |
7a9347f9 | 401 | /* Free space is guaranteed, see i915_guc_wq_reserve() above */ |
0a31afbc DG |
402 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); |
403 | GEM_BUG_ON(freespace < wqi_size); | |
404 | ||
405 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
406 | tail = rq->tail; | |
407 | GEM_BUG_ON(tail & 7); | |
408 | tail >>= 3; | |
409 | GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); | |
44a28b1d DG |
410 | |
411 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
412 | * should not have the case where structure wqi is across page, neither | |
413 | * wrapped to the beginning. This simplifies the implementation below. | |
414 | * | |
415 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
416 | * workqueue buffer dw by dw. | |
417 | */ | |
0a31afbc | 418 | BUILD_BUG_ON(wqi_size != 16); |
dadd481b | 419 | GEM_BUG_ON(gc->wq_rsvd < wqi_size); |
44a28b1d | 420 | |
0a31afbc DG |
421 | /* postincrement WQ tail for next time */ |
422 | wq_off = gc->wq_tail; | |
dadd481b | 423 | GEM_BUG_ON(wq_off & (wqi_size - 1)); |
0a31afbc DG |
424 | gc->wq_tail += wqi_size; |
425 | gc->wq_tail &= gc->wq_size - 1; | |
dadd481b | 426 | gc->wq_rsvd -= wqi_size; |
0a31afbc DG |
427 | |
428 | /* WQ starts from the page after doorbell / process_desc */ | |
72aa0d89 | 429 | wqi = gc->vaddr + wq_off + GUC_DB_SIZE; |
44a28b1d | 430 | |
0a31afbc | 431 | /* Now fill in the 4-word work queue item */ |
44a28b1d | 432 | wqi->header = WQ_TYPE_INORDER | |
0a31afbc | 433 | (wqi_len << WQ_LEN_SHIFT) | |
c18468c4 | 434 | (engine->guc_id << WQ_TARGET_SHIFT) | |
44a28b1d DG |
435 | WQ_NO_WCFLUSH_WAIT; |
436 | ||
437 | /* The GuC wants only the low-order word of the context descriptor */ | |
c18468c4 | 438 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine); |
44a28b1d | 439 | |
44a28b1d | 440 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
65e4760e | 441 | wqi->fence_id = rq->global_seqno; |
44a28b1d DG |
442 | } |
443 | ||
10d2c3e2 DG |
444 | static int guc_ring_doorbell(struct i915_guc_client *gc) |
445 | { | |
446 | struct guc_process_desc *desc; | |
447 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
448 | union guc_doorbell_qw *db; | |
449 | int attempt = 2, ret = -EAGAIN; | |
450 | ||
72aa0d89 | 451 | desc = gc->vaddr + gc->proc_desc_offset; |
10d2c3e2 DG |
452 | |
453 | /* Update the tail so it is visible to GuC */ | |
454 | desc->tail = gc->wq_tail; | |
455 | ||
456 | /* current cookie */ | |
457 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
458 | db_cmp.cookie = gc->cookie; | |
459 | ||
460 | /* cookie to be updated */ | |
461 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
462 | db_exc.cookie = gc->cookie + 1; | |
463 | if (db_exc.cookie == 0) | |
464 | db_exc.cookie = 1; | |
465 | ||
466 | /* pointer of current doorbell cacheline */ | |
72aa0d89 | 467 | db = gc->vaddr + gc->doorbell_offset; |
10d2c3e2 DG |
468 | |
469 | while (attempt--) { | |
470 | /* lets ring the doorbell */ | |
471 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
472 | db_cmp.value_qw, db_exc.value_qw); | |
473 | ||
474 | /* if the exchange was successfully executed */ | |
475 | if (db_ret.value_qw == db_cmp.value_qw) { | |
476 | /* db was successfully rung */ | |
477 | gc->cookie = db_exc.cookie; | |
478 | ret = 0; | |
479 | break; | |
480 | } | |
481 | ||
482 | /* XXX: doorbell was lost and need to acquire it again */ | |
483 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
484 | break; | |
485 | ||
535b2f5e DG |
486 | DRM_WARN("Cookie mismatch. Expected %d, found %d\n", |
487 | db_cmp.cookie, db_ret.cookie); | |
10d2c3e2 DG |
488 | |
489 | /* update the cookie to newly read cookie from GuC */ | |
490 | db_cmp.cookie = db_ret.cookie; | |
491 | db_exc.cookie = db_ret.cookie + 1; | |
492 | if (db_exc.cookie == 0) | |
493 | db_exc.cookie = 1; | |
494 | } | |
495 | ||
496 | return ret; | |
497 | } | |
498 | ||
44a28b1d DG |
499 | /** |
500 | * i915_guc_submit() - Submit commands through GuC | |
feda33ef | 501 | * @rq: request associated with the commands |
44a28b1d | 502 | * |
7c2c270d DG |
503 | * Return: 0 on success, otherwise an errno. |
504 | * (Note: nonzero really shouldn't happen!) | |
505 | * | |
7a9347f9 DG |
506 | * The caller must have already called i915_guc_wq_reserve() above with |
507 | * a result of 0 (success), guaranteeing that there is space in the work | |
508 | * queue for the new request, so enqueuing the item cannot fail. | |
7c2c270d DG |
509 | * |
510 | * Bad Things Will Happen if the caller violates this protocol e.g. calls | |
7a9347f9 DG |
511 | * submit() when _reserve() says there's no space, or calls _submit() |
512 | * a different number of times from (successful) calls to _reserve(). | |
7c2c270d DG |
513 | * |
514 | * The only error here arises if the doorbell hardware isn't functioning | |
515 | * as expected, which really shouln't happen. | |
44a28b1d | 516 | */ |
ddd66c51 | 517 | static void i915_guc_submit(struct drm_i915_gem_request *rq) |
44a28b1d | 518 | { |
ed4596ea | 519 | struct drm_i915_private *dev_priv = rq->i915; |
d55ac5bf CW |
520 | struct intel_engine_cs *engine = rq->engine; |
521 | unsigned int engine_id = engine->id; | |
7c2c270d DG |
522 | struct intel_guc *guc = &rq->i915->guc; |
523 | struct i915_guc_client *client = guc->execbuf_client; | |
0a31afbc | 524 | int b_ret; |
44a28b1d | 525 | |
d55ac5bf CW |
526 | /* We keep the previous context alive until we retire the following |
527 | * request. This ensures that any the context object is still pinned | |
528 | * for any residual writes the HW makes into it on the context switch | |
529 | * into the next object following the breadcrumb. Otherwise, we may | |
530 | * retire the context too early. | |
531 | */ | |
532 | rq->previous_context = engine->last_context; | |
533 | engine->last_context = rq->ctx; | |
534 | ||
535 | i915_gem_request_submit(rq); | |
536 | ||
dadd481b | 537 | spin_lock(&client->wq_lock); |
7a9347f9 | 538 | guc_wq_item_append(client, rq); |
ed4596ea AG |
539 | |
540 | /* WA to flush out the pending GMADR writes to ring buffer. */ | |
541 | if (i915_vma_is_map_and_fenceable(rq->ring->vma)) | |
542 | POSTING_READ_FW(GUC_STATUS); | |
543 | ||
0a31afbc | 544 | b_ret = guc_ring_doorbell(client); |
44a28b1d | 545 | |
397097b0 | 546 | client->submissions[engine_id] += 1; |
0a31afbc DG |
547 | client->retcode = b_ret; |
548 | if (b_ret) | |
44a28b1d | 549 | client->b_fail += 1; |
0a31afbc | 550 | |
397097b0 | 551 | guc->submissions[engine_id] += 1; |
65e4760e | 552 | guc->last_seqno[engine_id] = rq->global_seqno; |
dadd481b | 553 | spin_unlock(&client->wq_lock); |
44a28b1d DG |
554 | } |
555 | ||
556 | /* | |
557 | * Everything below here is concerned with setup & teardown, and is | |
558 | * therefore not part of the somewhat time-critical batch-submission | |
559 | * path of i915_guc_submit() above. | |
560 | */ | |
561 | ||
bac427f8 | 562 | /** |
8b797af1 CW |
563 | * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage |
564 | * @guc: the guc | |
565 | * @size: size of area to allocate (both virtual space and memory) | |
bac427f8 | 566 | * |
8b797af1 CW |
567 | * This is a wrapper to create an object for use with the GuC. In order to |
568 | * use it inside the GuC, an object needs to be pinned lifetime, so we allocate | |
569 | * both some backing storage and a range inside the Global GTT. We must pin | |
570 | * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that | |
571 | * range is reserved inside GuC. | |
bac427f8 | 572 | * |
8b797af1 | 573 | * Return: A i915_vma if successful, otherwise an ERR_PTR. |
bac427f8 | 574 | */ |
8b797af1 | 575 | static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size) |
bac427f8 | 576 | { |
8b797af1 | 577 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
bac427f8 | 578 | struct drm_i915_gem_object *obj; |
8b797af1 CW |
579 | struct i915_vma *vma; |
580 | int ret; | |
bac427f8 | 581 | |
91c8a326 | 582 | obj = i915_gem_object_create(&dev_priv->drm, size); |
fe3db79b | 583 | if (IS_ERR(obj)) |
8b797af1 | 584 | return ERR_CAST(obj); |
bac427f8 | 585 | |
8b797af1 CW |
586 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); |
587 | if (IS_ERR(vma)) | |
588 | goto err; | |
bac427f8 | 589 | |
8b797af1 CW |
590 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, |
591 | PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
592 | if (ret) { | |
593 | vma = ERR_PTR(ret); | |
594 | goto err; | |
bac427f8 AD |
595 | } |
596 | ||
597 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
598 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
599 | ||
8b797af1 CW |
600 | return vma; |
601 | ||
602 | err: | |
603 | i915_gem_object_put(obj); | |
604 | return vma; | |
bac427f8 AD |
605 | } |
606 | ||
0daf556c DG |
607 | static void |
608 | guc_client_free(struct drm_i915_private *dev_priv, | |
609 | struct i915_guc_client *client) | |
44a28b1d | 610 | { |
44a28b1d DG |
611 | struct intel_guc *guc = &dev_priv->guc; |
612 | ||
613 | if (!client) | |
614 | return; | |
615 | ||
44a28b1d DG |
616 | /* |
617 | * XXX: wait for any outstanding submissions before freeing memory. | |
618 | * Be sure to drop any locks | |
619 | */ | |
620 | ||
72aa0d89 | 621 | if (client->vaddr) { |
0d92a6a4 | 622 | /* |
a667429b DG |
623 | * If we got as far as setting up a doorbell, make sure we |
624 | * shut it down before unmapping & deallocating the memory. | |
0d92a6a4 | 625 | */ |
a667429b | 626 | guc_disable_doorbell(guc, client); |
0d92a6a4 | 627 | |
72aa0d89 | 628 | i915_gem_object_unpin_map(client->vma->obj); |
0d92a6a4 DG |
629 | } |
630 | ||
19880c4a | 631 | i915_vma_unpin_and_release(&client->vma); |
44a28b1d DG |
632 | |
633 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
7a9347f9 | 634 | guc_ctx_desc_fini(guc, client); |
44a28b1d DG |
635 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); |
636 | } | |
637 | ||
638 | kfree(client); | |
639 | } | |
640 | ||
84b7f882 DG |
641 | /* Check that a doorbell register is in the expected state */ |
642 | static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id) | |
643 | { | |
644 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
645 | i915_reg_t drbreg = GEN8_DRBREGL(db_id); | |
646 | uint32_t value = I915_READ(drbreg); | |
647 | bool enabled = (value & GUC_DOORBELL_ENABLED) != 0; | |
648 | bool expected = test_bit(db_id, guc->doorbell_bitmap); | |
649 | ||
650 | if (enabled == expected) | |
651 | return true; | |
652 | ||
653 | DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n", | |
654 | db_id, drbreg.reg, value, | |
655 | expected ? "active" : "inactive"); | |
656 | ||
657 | return false; | |
658 | } | |
659 | ||
4d75787b | 660 | /* |
8888cd01 | 661 | * Borrow the first client to set up & tear down each unused doorbell |
4d75787b DG |
662 | * in turn, to ensure that all doorbell h/w is (re)initialised. |
663 | */ | |
664 | static void guc_init_doorbell_hw(struct intel_guc *guc) | |
665 | { | |
4d75787b | 666 | struct i915_guc_client *client = guc->execbuf_client; |
84b7f882 DG |
667 | uint16_t db_id; |
668 | int i, err; | |
4d75787b | 669 | |
84b7f882 | 670 | /* Save client's original doorbell selection */ |
4d75787b DG |
671 | db_id = client->doorbell_id; |
672 | ||
673 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) { | |
84b7f882 DG |
674 | /* Skip if doorbell is OK */ |
675 | if (guc_doorbell_check(guc, i)) | |
8888cd01 DG |
676 | continue; |
677 | ||
4d75787b | 678 | err = guc_update_doorbell_id(guc, client, i); |
84b7f882 DG |
679 | if (err) |
680 | DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n", | |
681 | i, err); | |
4d75787b DG |
682 | } |
683 | ||
684 | /* Restore to original value */ | |
685 | err = guc_update_doorbell_id(guc, client, db_id); | |
686 | if (err) | |
535b2f5e DG |
687 | DRM_WARN("Failed to restore doorbell to %d, err %d\n", |
688 | db_id, err); | |
4d75787b | 689 | |
84b7f882 DG |
690 | /* Read back & verify all doorbell registers */ |
691 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) | |
692 | (void)guc_doorbell_check(guc, i); | |
4d75787b DG |
693 | } |
694 | ||
44a28b1d DG |
695 | /** |
696 | * guc_client_alloc() - Allocate an i915_guc_client | |
0daf556c | 697 | * @dev_priv: driver private data structure |
ceae5317 | 698 | * @engines: The set of engines to enable for this client |
44a28b1d DG |
699 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
700 | * The kernel client to replace ExecList submission is created with | |
701 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
702 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
703 | * @ctx: the context that owns the client (we use the default render |
704 | * context) | |
44a28b1d | 705 | * |
0d92a6a4 | 706 | * Return: An i915_guc_client object if success, else NULL. |
44a28b1d | 707 | */ |
0daf556c DG |
708 | static struct i915_guc_client * |
709 | guc_client_alloc(struct drm_i915_private *dev_priv, | |
e02757d9 | 710 | uint32_t engines, |
0daf556c DG |
711 | uint32_t priority, |
712 | struct i915_gem_context *ctx) | |
44a28b1d DG |
713 | { |
714 | struct i915_guc_client *client; | |
44a28b1d | 715 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 | 716 | struct i915_vma *vma; |
72aa0d89 | 717 | void *vaddr; |
a667429b | 718 | uint16_t db_id; |
44a28b1d DG |
719 | |
720 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
721 | if (!client) | |
722 | return NULL; | |
723 | ||
d1675198 | 724 | client->owner = ctx; |
44a28b1d | 725 | client->guc = guc; |
e02757d9 DG |
726 | client->engines = engines; |
727 | client->priority = priority; | |
728 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
44a28b1d DG |
729 | |
730 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
731 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
732 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
733 | client->ctx_index = GUC_INVALID_CTX_ID; | |
734 | goto err; | |
735 | } | |
736 | ||
737 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
8b797af1 CW |
738 | vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE); |
739 | if (IS_ERR(vma)) | |
44a28b1d DG |
740 | goto err; |
741 | ||
0d92a6a4 | 742 | /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ |
8b797af1 | 743 | client->vma = vma; |
72aa0d89 CW |
744 | |
745 | vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); | |
746 | if (IS_ERR(vaddr)) | |
747 | goto err; | |
748 | ||
749 | client->vaddr = vaddr; | |
dadd481b CW |
750 | |
751 | spin_lock_init(&client->wq_lock); | |
44a28b1d DG |
752 | client->wq_offset = GUC_DB_SIZE; |
753 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d | 754 | |
f10d69a7 DG |
755 | db_id = select_doorbell_register(guc, client->priority); |
756 | if (db_id == GUC_INVALID_DOORBELL_ID) | |
757 | /* XXX: evict a doorbell instead? */ | |
758 | goto err; | |
759 | ||
44a28b1d DG |
760 | client->doorbell_offset = select_doorbell_cacheline(guc); |
761 | ||
762 | /* | |
763 | * Since the doorbell only requires a single cacheline, we can save | |
764 | * space by putting the application process descriptor in the same | |
765 | * page. Use the half of the page that doesn't include the doorbell. | |
766 | */ | |
767 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
768 | client->proc_desc_offset = 0; | |
769 | else | |
770 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
771 | ||
7a9347f9 DG |
772 | guc_proc_desc_init(guc, client); |
773 | guc_ctx_desc_init(guc, client); | |
a667429b | 774 | if (guc_init_doorbell(guc, client, db_id)) |
44a28b1d DG |
775 | goto err; |
776 | ||
e02757d9 DG |
777 | DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n", |
778 | priority, client, client->engines, client->ctx_index); | |
a667429b DG |
779 | DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n", |
780 | client->doorbell_id, client->doorbell_offset); | |
44a28b1d DG |
781 | |
782 | return client; | |
783 | ||
784 | err: | |
0daf556c | 785 | guc_client_free(dev_priv, client); |
44a28b1d DG |
786 | return NULL; |
787 | } | |
788 | ||
f8240835 AG |
789 | /* |
790 | * Sub buffer switch callback. Called whenever relay has to switch to a new | |
791 | * sub buffer, relay stays on the same sub buffer if 0 is returned. | |
792 | */ | |
793 | static int subbuf_start_callback(struct rchan_buf *buf, | |
794 | void *subbuf, | |
795 | void *prev_subbuf, | |
796 | size_t prev_padding) | |
797 | { | |
798 | /* Use no-overwrite mode by default, where relay will stop accepting | |
799 | * new data if there are no empty sub buffers left. | |
800 | * There is no strict synchronization enforced by relay between Consumer | |
801 | * and Producer. In overwrite mode, there is a possibility of getting | |
802 | * inconsistent/garbled data, the producer could be writing on to the | |
803 | * same sub buffer from which Consumer is reading. This can't be avoided | |
804 | * unless Consumer is fast enough and can always run in tandem with | |
805 | * Producer. | |
806 | */ | |
807 | if (relay_buf_full(buf)) | |
808 | return 0; | |
809 | ||
810 | return 1; | |
811 | } | |
812 | ||
813 | /* | |
814 | * file_create() callback. Creates relay file in debugfs. | |
815 | */ | |
816 | static struct dentry *create_buf_file_callback(const char *filename, | |
817 | struct dentry *parent, | |
818 | umode_t mode, | |
819 | struct rchan_buf *buf, | |
820 | int *is_global) | |
821 | { | |
822 | struct dentry *buf_file; | |
823 | ||
f8240835 AG |
824 | /* This to enable the use of a single buffer for the relay channel and |
825 | * correspondingly have a single file exposed to User, through which | |
826 | * it can collect the logs in order without any post-processing. | |
1e6b8b0d | 827 | * Need to set 'is_global' even if parent is NULL for early logging. |
f8240835 AG |
828 | */ |
829 | *is_global = 1; | |
830 | ||
1e6b8b0d AG |
831 | if (!parent) |
832 | return NULL; | |
833 | ||
f8240835 AG |
834 | /* Not using the channel filename passed as an argument, since for each |
835 | * channel relay appends the corresponding CPU number to the filename | |
836 | * passed in relay_open(). This should be fine as relay just needs a | |
837 | * dentry of the file associated with the channel buffer and that file's | |
838 | * name need not be same as the filename passed as an argument. | |
839 | */ | |
840 | buf_file = debugfs_create_file("guc_log", mode, | |
841 | parent, buf, &relay_file_operations); | |
842 | return buf_file; | |
843 | } | |
844 | ||
845 | /* | |
846 | * file_remove() default callback. Removes relay file in debugfs. | |
847 | */ | |
848 | static int remove_buf_file_callback(struct dentry *dentry) | |
849 | { | |
850 | debugfs_remove(dentry); | |
851 | return 0; | |
852 | } | |
853 | ||
854 | /* relay channel callbacks */ | |
855 | static struct rchan_callbacks relay_callbacks = { | |
856 | .subbuf_start = subbuf_start_callback, | |
857 | .create_buf_file = create_buf_file_callback, | |
858 | .remove_buf_file = remove_buf_file_callback, | |
859 | }; | |
860 | ||
861 | static void guc_log_remove_relay_file(struct intel_guc *guc) | |
862 | { | |
863 | relay_close(guc->log.relay_chan); | |
864 | } | |
865 | ||
1e6b8b0d | 866 | static int guc_log_create_relay_channel(struct intel_guc *guc) |
f8240835 AG |
867 | { |
868 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
869 | struct rchan *guc_log_relay_chan; | |
f8240835 AG |
870 | size_t n_subbufs, subbuf_size; |
871 | ||
1e6b8b0d AG |
872 | /* Keep the size of sub buffers same as shared log buffer */ |
873 | subbuf_size = guc->log.vma->obj->base.size; | |
874 | ||
875 | /* Store up to 8 snapshots, which is large enough to buffer sufficient | |
876 | * boot time logs and provides enough leeway to User, in terms of | |
877 | * latency, for consuming the logs from relay. Also doesn't take | |
878 | * up too much memory. | |
879 | */ | |
880 | n_subbufs = 8; | |
881 | ||
882 | guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size, | |
883 | n_subbufs, &relay_callbacks, dev_priv); | |
884 | if (!guc_log_relay_chan) { | |
885 | DRM_ERROR("Couldn't create relay chan for GuC logging\n"); | |
886 | return -ENOMEM; | |
887 | } | |
888 | ||
889 | GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size); | |
890 | guc->log.relay_chan = guc_log_relay_chan; | |
891 | return 0; | |
892 | } | |
893 | ||
894 | static int guc_log_create_relay_file(struct intel_guc *guc) | |
895 | { | |
896 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
897 | struct dentry *log_dir; | |
898 | int ret; | |
899 | ||
f8240835 AG |
900 | /* For now create the log file in /sys/kernel/debug/dri/0 dir */ |
901 | log_dir = dev_priv->drm.primary->debugfs_root; | |
902 | ||
903 | /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is | |
904 | * not mounted and so can't create the relay file. | |
905 | * The relay API seems to fit well with debugfs only, for availing relay | |
906 | * there are 3 requirements which can be met for debugfs file only in a | |
907 | * straightforward/clean manner :- | |
908 | * i) Need the associated dentry pointer of the file, while opening the | |
909 | * relay channel. | |
910 | * ii) Should be able to use 'relay_file_operations' fops for the file. | |
911 | * iii) Set the 'i_private' field of file's inode to the pointer of | |
912 | * relay channel buffer. | |
913 | */ | |
914 | if (!log_dir) { | |
915 | DRM_ERROR("Debugfs dir not available yet for GuC log file\n"); | |
916 | return -ENODEV; | |
917 | } | |
918 | ||
1e6b8b0d AG |
919 | ret = relay_late_setup_files(guc->log.relay_chan, "guc_log", log_dir); |
920 | if (ret) { | |
921 | DRM_ERROR("Couldn't associate relay chan with file %d\n", ret); | |
922 | return ret; | |
f8240835 AG |
923 | } |
924 | ||
f8240835 AG |
925 | return 0; |
926 | } | |
927 | ||
4100b2ab SAK |
928 | static void guc_move_to_next_buf(struct intel_guc *guc) |
929 | { | |
f8240835 AG |
930 | /* Make sure the updates made in the sub buffer are visible when |
931 | * Consumer sees the following update to offset inside the sub buffer. | |
932 | */ | |
933 | smp_wmb(); | |
934 | ||
935 | /* All data has been written, so now move the offset of sub buffer. */ | |
936 | relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size); | |
937 | ||
938 | /* Switch to the next sub buffer */ | |
939 | relay_flush(guc->log.relay_chan); | |
4100b2ab SAK |
940 | } |
941 | ||
942 | static void *guc_get_write_buffer(struct intel_guc *guc) | |
943 | { | |
f8240835 AG |
944 | if (!guc->log.relay_chan) |
945 | return NULL; | |
946 | ||
947 | /* Just get the base address of a new sub buffer and copy data into it | |
948 | * ourselves. NULL will be returned in no-overwrite mode, if all sub | |
949 | * buffers are full. Could have used the relay_write() to indirectly | |
950 | * copy the data, but that would have been bit convoluted, as we need to | |
951 | * write to only certain locations inside a sub buffer which cannot be | |
952 | * done without using relay_reserve() along with relay_write(). So its | |
953 | * better to use relay_reserve() alone. | |
954 | */ | |
955 | return relay_reserve(guc->log.relay_chan, 0); | |
4100b2ab SAK |
956 | } |
957 | ||
5aa1ee4b AG |
958 | static bool |
959 | guc_check_log_buf_overflow(struct intel_guc *guc, | |
960 | enum guc_log_buffer_type type, unsigned int full_cnt) | |
961 | { | |
962 | unsigned int prev_full_cnt = guc->log.prev_overflow_count[type]; | |
963 | bool overflow = false; | |
964 | ||
965 | if (full_cnt != prev_full_cnt) { | |
966 | overflow = true; | |
967 | ||
968 | guc->log.prev_overflow_count[type] = full_cnt; | |
969 | guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt; | |
970 | ||
971 | if (full_cnt < prev_full_cnt) { | |
972 | /* buffer_full_cnt is a 4 bit counter */ | |
973 | guc->log.total_overflow_count[type] += 16; | |
974 | } | |
975 | DRM_ERROR_RATELIMITED("GuC log buffer overflow\n"); | |
976 | } | |
977 | ||
978 | return overflow; | |
979 | } | |
980 | ||
4100b2ab SAK |
981 | static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type) |
982 | { | |
983 | switch (type) { | |
984 | case GUC_ISR_LOG_BUFFER: | |
985 | return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE; | |
986 | case GUC_DPC_LOG_BUFFER: | |
987 | return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE; | |
988 | case GUC_CRASH_DUMP_LOG_BUFFER: | |
989 | return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE; | |
990 | default: | |
991 | MISSING_CASE(type); | |
992 | } | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
997 | static void guc_read_update_log_buffer(struct intel_guc *guc) | |
998 | { | |
6941f3c9 | 999 | unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt; |
4100b2ab SAK |
1000 | struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state; |
1001 | struct guc_log_buffer_state log_buf_state_local; | |
4100b2ab SAK |
1002 | enum guc_log_buffer_type type; |
1003 | void *src_data, *dst_data; | |
6941f3c9 | 1004 | bool new_overflow; |
4100b2ab SAK |
1005 | |
1006 | if (WARN_ON(!guc->log.buf_addr)) | |
1007 | return; | |
1008 | ||
1009 | /* Get the pointer to shared GuC log buffer */ | |
1010 | log_buf_state = src_data = guc->log.buf_addr; | |
1011 | ||
1012 | /* Get the pointer to local buffer to store the logs */ | |
1013 | log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc); | |
1014 | ||
1015 | /* Actual logs are present from the 2nd page */ | |
1016 | src_data += PAGE_SIZE; | |
1017 | dst_data += PAGE_SIZE; | |
1018 | ||
1019 | for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) { | |
1020 | /* Make a copy of the state structure, inside GuC log buffer | |
1021 | * (which is uncached mapped), on the stack to avoid reading | |
1022 | * from it multiple times. | |
1023 | */ | |
1024 | memcpy(&log_buf_state_local, log_buf_state, | |
1025 | sizeof(struct guc_log_buffer_state)); | |
1026 | buffer_size = guc_get_log_buffer_size(type); | |
6941f3c9 | 1027 | read_offset = log_buf_state_local.read_ptr; |
4100b2ab | 1028 | write_offset = log_buf_state_local.sampled_write_ptr; |
5aa1ee4b AG |
1029 | full_cnt = log_buf_state_local.buffer_full_cnt; |
1030 | ||
1031 | /* Bookkeeping stuff */ | |
1032 | guc->log.flush_count[type] += log_buf_state_local.flush_to_file; | |
6941f3c9 | 1033 | new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt); |
4100b2ab SAK |
1034 | |
1035 | /* Update the state of shared log buffer */ | |
1036 | log_buf_state->read_ptr = write_offset; | |
1037 | log_buf_state->flush_to_file = 0; | |
1038 | log_buf_state++; | |
1039 | ||
1040 | if (unlikely(!log_buf_snapshot_state)) | |
1041 | continue; | |
1042 | ||
1043 | /* First copy the state structure in snapshot buffer */ | |
1044 | memcpy(log_buf_snapshot_state, &log_buf_state_local, | |
1045 | sizeof(struct guc_log_buffer_state)); | |
1046 | ||
1047 | /* The write pointer could have been updated by GuC firmware, | |
1048 | * after sending the flush interrupt to Host, for consistency | |
1049 | * set write pointer value to same value of sampled_write_ptr | |
1050 | * in the snapshot buffer. | |
1051 | */ | |
1052 | log_buf_snapshot_state->write_ptr = write_offset; | |
1053 | log_buf_snapshot_state++; | |
1054 | ||
1055 | /* Now copy the actual logs. */ | |
6941f3c9 AG |
1056 | if (unlikely(new_overflow)) { |
1057 | /* copy the whole buffer in case of overflow */ | |
1058 | read_offset = 0; | |
1059 | write_offset = buffer_size; | |
1060 | } else if (unlikely((read_offset > buffer_size) || | |
1061 | (write_offset > buffer_size))) { | |
1062 | DRM_ERROR("invalid log buffer state\n"); | |
1063 | /* copy whole buffer as offsets are unreliable */ | |
1064 | read_offset = 0; | |
1065 | write_offset = buffer_size; | |
1066 | } | |
1067 | ||
1068 | /* Just copy the newly written data */ | |
1069 | if (read_offset > write_offset) { | |
71706590 | 1070 | i915_memcpy_from_wc(dst_data, src_data, write_offset); |
6941f3c9 AG |
1071 | bytes_to_copy = buffer_size - read_offset; |
1072 | } else { | |
1073 | bytes_to_copy = write_offset - read_offset; | |
1074 | } | |
71706590 AG |
1075 | i915_memcpy_from_wc(dst_data + read_offset, |
1076 | src_data + read_offset, bytes_to_copy); | |
4100b2ab SAK |
1077 | |
1078 | src_data += buffer_size; | |
1079 | dst_data += buffer_size; | |
4100b2ab SAK |
1080 | } |
1081 | ||
1082 | if (log_buf_snapshot_state) | |
1083 | guc_move_to_next_buf(guc); | |
f8240835 AG |
1084 | else { |
1085 | /* Used rate limited to avoid deluge of messages, logs might be | |
1086 | * getting consumed by User at a slow rate. | |
1087 | */ | |
1088 | DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n"); | |
5aa1ee4b | 1089 | guc->log.capture_miss_count++; |
f8240835 | 1090 | } |
4100b2ab SAK |
1091 | } |
1092 | ||
1093 | static void guc_capture_logs_work(struct work_struct *work) | |
1094 | { | |
1095 | struct drm_i915_private *dev_priv = | |
1096 | container_of(work, struct drm_i915_private, guc.log.flush_work); | |
1097 | ||
1098 | i915_guc_capture_logs(dev_priv); | |
1099 | } | |
1100 | ||
1101 | static void guc_log_cleanup(struct intel_guc *guc) | |
1102 | { | |
1103 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
1104 | ||
1105 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1106 | ||
1107 | /* First disable the flush interrupt */ | |
1108 | gen9_disable_guc_interrupts(dev_priv); | |
1109 | ||
1110 | if (guc->log.flush_wq) | |
1111 | destroy_workqueue(guc->log.flush_wq); | |
1112 | ||
1113 | guc->log.flush_wq = NULL; | |
1114 | ||
f8240835 AG |
1115 | if (guc->log.relay_chan) |
1116 | guc_log_remove_relay_file(guc); | |
1117 | ||
1118 | guc->log.relay_chan = NULL; | |
1119 | ||
4100b2ab SAK |
1120 | if (guc->log.buf_addr) |
1121 | i915_gem_object_unpin_map(guc->log.vma->obj); | |
1122 | ||
1123 | guc->log.buf_addr = NULL; | |
1124 | } | |
1125 | ||
1126 | static int guc_log_create_extras(struct intel_guc *guc) | |
1127 | { | |
1128 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
1129 | void *vaddr; | |
1130 | int ret; | |
1131 | ||
1132 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1133 | ||
1134 | /* Nothing to do */ | |
1135 | if (i915.guc_log_level < 0) | |
1136 | return 0; | |
1137 | ||
1138 | if (!guc->log.buf_addr) { | |
71706590 AG |
1139 | /* Create a WC (Uncached for read) vmalloc mapping of log |
1140 | * buffer pages, so that we can directly get the data | |
1141 | * (up-to-date) from memory. | |
1142 | */ | |
1143 | vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC); | |
4100b2ab SAK |
1144 | if (IS_ERR(vaddr)) { |
1145 | ret = PTR_ERR(vaddr); | |
1146 | DRM_ERROR("Couldn't map log buffer pages %d\n", ret); | |
1147 | return ret; | |
1148 | } | |
1149 | ||
1150 | guc->log.buf_addr = vaddr; | |
1151 | } | |
1152 | ||
1e6b8b0d AG |
1153 | if (!guc->log.relay_chan) { |
1154 | /* Create a relay channel, so that we have buffers for storing | |
1155 | * the GuC firmware logs, the channel will be linked with a file | |
1156 | * later on when debugfs is registered. | |
1157 | */ | |
1158 | ret = guc_log_create_relay_channel(guc); | |
1159 | if (ret) | |
1160 | return ret; | |
1161 | } | |
1162 | ||
4100b2ab SAK |
1163 | if (!guc->log.flush_wq) { |
1164 | INIT_WORK(&guc->log.flush_work, guc_capture_logs_work); | |
1165 | ||
7ef54de7 AG |
1166 | /* |
1167 | * GuC log buffer flush work item has to do register access to | |
1168 | * send the ack to GuC and this work item, if not synced before | |
1169 | * suspend, can potentially get executed after the GFX device is | |
1170 | * suspended. | |
1171 | * By marking the WQ as freezable, we don't have to bother about | |
1172 | * flushing of this work item from the suspend hooks, the pending | |
1173 | * work item if any will be either executed before the suspend | |
1174 | * or scheduled later on resume. This way the handling of work | |
1175 | * item can be kept same between system suspend & rpm suspend. | |
4100b2ab | 1176 | */ |
7ef54de7 AG |
1177 | guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log", |
1178 | WQ_HIGHPRI | WQ_FREEZABLE); | |
4100b2ab SAK |
1179 | if (guc->log.flush_wq == NULL) { |
1180 | DRM_ERROR("Couldn't allocate the wq for GuC logging\n"); | |
1181 | return -ENOMEM; | |
1182 | } | |
1183 | } | |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
7a9347f9 | 1188 | static void guc_log_create(struct intel_guc *guc) |
4c7e77fc | 1189 | { |
8b797af1 | 1190 | struct i915_vma *vma; |
4c7e77fc AD |
1191 | unsigned long offset; |
1192 | uint32_t size, flags; | |
1193 | ||
4c7e77fc AD |
1194 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) |
1195 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; | |
1196 | ||
1197 | /* The first page is to save log buffer state. Allocate one | |
1198 | * extra page for others in case for overlap */ | |
1199 | size = (1 + GUC_LOG_DPC_PAGES + 1 + | |
1200 | GUC_LOG_ISR_PAGES + 1 + | |
1201 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; | |
1202 | ||
d6b40b4b | 1203 | vma = guc->log.vma; |
8b797af1 | 1204 | if (!vma) { |
71706590 AG |
1205 | /* We require SSE 4.1 for fast reads from the GuC log buffer and |
1206 | * it should be present on the chipsets supporting GuC based | |
1207 | * submisssions. | |
1208 | */ | |
1209 | if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) { | |
1210 | /* logging will not be enabled */ | |
1211 | i915.guc_log_level = -1; | |
1212 | return; | |
1213 | } | |
1214 | ||
8b797af1 CW |
1215 | vma = guc_allocate_vma(guc, size); |
1216 | if (IS_ERR(vma)) { | |
4c7e77fc AD |
1217 | /* logging will be off */ |
1218 | i915.guc_log_level = -1; | |
1219 | return; | |
1220 | } | |
1221 | ||
d6b40b4b | 1222 | guc->log.vma = vma; |
4100b2ab SAK |
1223 | |
1224 | if (guc_log_create_extras(guc)) { | |
1225 | guc_log_cleanup(guc); | |
1226 | i915_vma_unpin_and_release(&guc->log.vma); | |
1227 | i915.guc_log_level = -1; | |
1228 | return; | |
1229 | } | |
4c7e77fc AD |
1230 | } |
1231 | ||
1232 | /* each allocated unit is a page */ | |
1233 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | | |
1234 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | | |
1235 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | | |
1236 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); | |
1237 | ||
bde13ebd | 1238 | offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */ |
d6b40b4b | 1239 | guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; |
4c7e77fc AD |
1240 | } |
1241 | ||
f8240835 AG |
1242 | static int guc_log_late_setup(struct intel_guc *guc) |
1243 | { | |
1244 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
1245 | int ret; | |
1246 | ||
1247 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
1248 | ||
1249 | if (i915.guc_log_level < 0) | |
1250 | return -EINVAL; | |
1251 | ||
1252 | /* If log_level was set as -1 at boot time, then setup needed to | |
1253 | * handle log buffer flush interrupts would not have been done yet, | |
1254 | * so do that now. | |
1255 | */ | |
1256 | ret = guc_log_create_extras(guc); | |
1257 | if (ret) | |
1258 | goto err; | |
1259 | ||
1260 | ret = guc_log_create_relay_file(guc); | |
1261 | if (ret) | |
1262 | goto err; | |
1263 | ||
1264 | return 0; | |
1265 | err: | |
1266 | guc_log_cleanup(guc); | |
1267 | /* logging will remain off */ | |
1268 | i915.guc_log_level = -1; | |
1269 | return ret; | |
1270 | } | |
1271 | ||
7a9347f9 | 1272 | static void guc_policies_init(struct guc_policies *policies) |
463704d0 AD |
1273 | { |
1274 | struct guc_policy *policy; | |
1275 | u32 p, i; | |
1276 | ||
1277 | policies->dpc_promote_time = 500000; | |
1278 | policies->max_num_work_items = POLICY_MAX_NUM_WI; | |
1279 | ||
1280 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { | |
397097b0 | 1281 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
463704d0 AD |
1282 | policy = &policies->policy[p][i]; |
1283 | ||
1284 | policy->execution_quantum = 1000000; | |
1285 | policy->preemption_time = 500000; | |
1286 | policy->fault_time = 250000; | |
1287 | policy->policy_flags = 0; | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | policies->is_valid = 1; | |
1292 | } | |
1293 | ||
7a9347f9 | 1294 | static void guc_addon_create(struct intel_guc *guc) |
68371a95 AD |
1295 | { |
1296 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
8b797af1 | 1297 | struct i915_vma *vma; |
68371a95 | 1298 | struct guc_ads *ads; |
463704d0 | 1299 | struct guc_policies *policies; |
5c148e04 | 1300 | struct guc_mmio_reg_state *reg_state; |
e2f80391 | 1301 | struct intel_engine_cs *engine; |
3b3f1650 | 1302 | enum intel_engine_id id; |
68371a95 | 1303 | struct page *page; |
b4ac5afc | 1304 | u32 size; |
68371a95 AD |
1305 | |
1306 | /* The ads obj includes the struct itself and buffers passed to GuC */ | |
5c148e04 AD |
1307 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
1308 | sizeof(struct guc_mmio_reg_state) + | |
1309 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; | |
68371a95 | 1310 | |
8b797af1 CW |
1311 | vma = guc->ads_vma; |
1312 | if (!vma) { | |
1313 | vma = guc_allocate_vma(guc, PAGE_ALIGN(size)); | |
1314 | if (IS_ERR(vma)) | |
68371a95 AD |
1315 | return; |
1316 | ||
8b797af1 | 1317 | guc->ads_vma = vma; |
68371a95 AD |
1318 | } |
1319 | ||
8b797af1 | 1320 | page = i915_vma_first_page(vma); |
68371a95 AD |
1321 | ads = kmap(page); |
1322 | ||
1323 | /* | |
1324 | * The GuC requires a "Golden Context" when it reinitialises | |
1325 | * engines after a reset. Here we use the Render ring default | |
1326 | * context, which must already exist and be pinned in the GGTT, | |
1327 | * so its address won't change after we've told the GuC where | |
1328 | * to find it. | |
1329 | */ | |
3b3f1650 | 1330 | engine = dev_priv->engine[RCS]; |
57e88531 | 1331 | ads->golden_context_lrca = engine->status_page.ggtt_offset; |
68371a95 | 1332 | |
3b3f1650 | 1333 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 1334 | ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); |
68371a95 | 1335 | |
463704d0 AD |
1336 | /* GuC scheduling policies */ |
1337 | policies = (void *)ads + sizeof(struct guc_ads); | |
7a9347f9 | 1338 | guc_policies_init(policies); |
463704d0 | 1339 | |
bde13ebd CW |
1340 | ads->scheduler_policies = |
1341 | i915_ggtt_offset(vma) + sizeof(struct guc_ads); | |
463704d0 | 1342 | |
5c148e04 AD |
1343 | /* MMIO reg state */ |
1344 | reg_state = (void *)policies + sizeof(struct guc_policies); | |
1345 | ||
3b3f1650 | 1346 | for_each_engine(engine, dev_priv, id) { |
e2f80391 TU |
1347 | reg_state->mmio_white_list[engine->guc_id].mmio_start = |
1348 | engine->mmio_base + GUC_MMIO_WHITE_LIST_START; | |
5c148e04 AD |
1349 | |
1350 | /* Nothing to be saved or restored for now. */ | |
e2f80391 | 1351 | reg_state->mmio_white_list[engine->guc_id].count = 0; |
5c148e04 AD |
1352 | } |
1353 | ||
1354 | ads->reg_state_addr = ads->scheduler_policies + | |
1355 | sizeof(struct guc_policies); | |
1356 | ||
1357 | ads->reg_state_buffer = ads->reg_state_addr + | |
1358 | sizeof(struct guc_mmio_reg_state); | |
1359 | ||
68371a95 AD |
1360 | kunmap(page); |
1361 | } | |
1362 | ||
bac427f8 AD |
1363 | /* |
1364 | * Set up the memory resources to be shared with the GuC. At this point, | |
1365 | * we require just one object that can be mapped through the GGTT. | |
1366 | */ | |
beffa517 | 1367 | int i915_guc_submission_init(struct drm_i915_private *dev_priv) |
bac427f8 | 1368 | { |
7a9347f9 DG |
1369 | const size_t ctxsize = sizeof(struct guc_context_desc); |
1370 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; | |
1371 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); | |
bac427f8 | 1372 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 | 1373 | struct i915_vma *vma; |
bac427f8 | 1374 | |
29fb72c7 DG |
1375 | /* Wipe bitmap & delete client in case of reinitialisation */ |
1376 | bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS); | |
beffa517 | 1377 | i915_guc_submission_disable(dev_priv); |
29fb72c7 | 1378 | |
bac427f8 AD |
1379 | if (!i915.enable_guc_submission) |
1380 | return 0; /* not enabled */ | |
1381 | ||
8b797af1 | 1382 | if (guc->ctx_pool_vma) |
bac427f8 AD |
1383 | return 0; /* already allocated */ |
1384 | ||
7a9347f9 | 1385 | vma = guc_allocate_vma(guc, gemsize); |
8b797af1 CW |
1386 | if (IS_ERR(vma)) |
1387 | return PTR_ERR(vma); | |
bac427f8 | 1388 | |
8b797af1 | 1389 | guc->ctx_pool_vma = vma; |
bac427f8 | 1390 | ida_init(&guc->ctx_ids); |
7a9347f9 DG |
1391 | guc_log_create(guc); |
1392 | guc_addon_create(guc); | |
68371a95 | 1393 | |
bac427f8 AD |
1394 | return 0; |
1395 | } | |
1396 | ||
beffa517 | 1397 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv) |
44a28b1d | 1398 | { |
44a28b1d | 1399 | struct intel_guc *guc = &dev_priv->guc; |
3b3f1650 | 1400 | struct drm_i915_gem_request *request; |
44a28b1d | 1401 | struct i915_guc_client *client; |
ddd66c51 | 1402 | struct intel_engine_cs *engine; |
3b3f1650 | 1403 | enum intel_engine_id id; |
44a28b1d DG |
1404 | |
1405 | /* client for execbuf submission */ | |
0daf556c | 1406 | client = guc_client_alloc(dev_priv, |
e02757d9 | 1407 | INTEL_INFO(dev_priv)->ring_mask, |
0ca5fa3a CW |
1408 | GUC_CTX_PRIORITY_KMD_NORMAL, |
1409 | dev_priv->kernel_context); | |
44a28b1d | 1410 | if (!client) { |
535b2f5e | 1411 | DRM_ERROR("Failed to create normal GuC client!\n"); |
44a28b1d DG |
1412 | return -ENOMEM; |
1413 | } | |
1414 | ||
1415 | guc->execbuf_client = client; | |
2d803c2d | 1416 | intel_guc_sample_forcewake(guc); |
4d75787b | 1417 | guc_init_doorbell_hw(guc); |
f5d3c3ea | 1418 | |
ddd66c51 | 1419 | /* Take over from manual control of ELSP (execlists) */ |
3b3f1650 | 1420 | for_each_engine(engine, dev_priv, id) { |
ddd66c51 | 1421 | engine->submit_request = i915_guc_submit; |
20311bd3 | 1422 | engine->schedule = NULL; |
ddd66c51 | 1423 | |
821ed7df | 1424 | /* Replay the current set of previously submitted requests */ |
73cb9701 CW |
1425 | list_for_each_entry(request, |
1426 | &engine->timeline->requests, link) { | |
dadd481b | 1427 | client->wq_rsvd += sizeof(struct guc_wq_item); |
5590af3e CW |
1428 | if (i915_sw_fence_done(&request->submit)) |
1429 | i915_guc_submit(request); | |
dadd481b | 1430 | } |
821ed7df CW |
1431 | } |
1432 | ||
44a28b1d DG |
1433 | return 0; |
1434 | } | |
1435 | ||
beffa517 | 1436 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv) |
44a28b1d | 1437 | { |
44a28b1d DG |
1438 | struct intel_guc *guc = &dev_priv->guc; |
1439 | ||
ddd66c51 CW |
1440 | if (!guc->execbuf_client) |
1441 | return; | |
1442 | ||
ddd66c51 CW |
1443 | /* Revert back to manual ELSP submission */ |
1444 | intel_execlists_enable_submission(dev_priv); | |
f4ea6bdd CW |
1445 | |
1446 | guc_client_free(dev_priv, guc->execbuf_client); | |
1447 | guc->execbuf_client = NULL; | |
44a28b1d DG |
1448 | } |
1449 | ||
beffa517 | 1450 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv) |
bac427f8 | 1451 | { |
bac427f8 AD |
1452 | struct intel_guc *guc = &dev_priv->guc; |
1453 | ||
19880c4a | 1454 | i915_vma_unpin_and_release(&guc->ads_vma); |
d6b40b4b | 1455 | i915_vma_unpin_and_release(&guc->log.vma); |
4c7e77fc | 1456 | |
8b797af1 | 1457 | if (guc->ctx_pool_vma) |
bac427f8 | 1458 | ida_destroy(&guc->ctx_ids); |
19880c4a | 1459 | i915_vma_unpin_and_release(&guc->ctx_pool_vma); |
bac427f8 | 1460 | } |
a1c41994 AD |
1461 | |
1462 | /** | |
1463 | * intel_guc_suspend() - notify GuC entering suspend state | |
1464 | * @dev: drm device | |
1465 | */ | |
1466 | int intel_guc_suspend(struct drm_device *dev) | |
1467 | { | |
fac5e23e | 1468 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1c41994 | 1469 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 1470 | struct i915_gem_context *ctx; |
a1c41994 AD |
1471 | u32 data[3]; |
1472 | ||
fce91f22 | 1473 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1474 | return 0; |
1475 | ||
26705e20 SAK |
1476 | gen9_disable_guc_interrupts(dev_priv); |
1477 | ||
ed54c1a1 | 1478 | ctx = dev_priv->kernel_context; |
a1c41994 | 1479 | |
a80bc45f | 1480 | data[0] = INTEL_GUC_ACTION_ENTER_S_STATE; |
a1c41994 AD |
1481 | /* any value greater than GUC_POWER_D0 */ |
1482 | data[1] = GUC_POWER_D1; | |
1483 | /* first page is shared data with GuC */ | |
bde13ebd | 1484 | data[2] = i915_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 | 1485 | |
2d803c2d | 1486 | return intel_guc_send(guc, data, ARRAY_SIZE(data)); |
a1c41994 AD |
1487 | } |
1488 | ||
1489 | ||
1490 | /** | |
1491 | * intel_guc_resume() - notify GuC resuming from suspend state | |
1492 | * @dev: drm device | |
1493 | */ | |
1494 | int intel_guc_resume(struct drm_device *dev) | |
1495 | { | |
fac5e23e | 1496 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1c41994 | 1497 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 1498 | struct i915_gem_context *ctx; |
a1c41994 AD |
1499 | u32 data[3]; |
1500 | ||
fce91f22 | 1501 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1502 | return 0; |
1503 | ||
26705e20 SAK |
1504 | if (i915.guc_log_level >= 0) |
1505 | gen9_enable_guc_interrupts(dev_priv); | |
1506 | ||
ed54c1a1 | 1507 | ctx = dev_priv->kernel_context; |
a1c41994 | 1508 | |
a80bc45f | 1509 | data[0] = INTEL_GUC_ACTION_EXIT_S_STATE; |
a1c41994 AD |
1510 | data[1] = GUC_POWER_D0; |
1511 | /* first page is shared data with GuC */ | |
bde13ebd | 1512 | data[2] = i915_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 | 1513 | |
2d803c2d | 1514 | return intel_guc_send(guc, data, ARRAY_SIZE(data)); |
a1c41994 | 1515 | } |
4100b2ab SAK |
1516 | |
1517 | void i915_guc_capture_logs(struct drm_i915_private *dev_priv) | |
1518 | { | |
1519 | guc_read_update_log_buffer(&dev_priv->guc); | |
1520 | ||
1521 | /* Generally device is expected to be active only at this | |
1522 | * time, so get/put should be really quick. | |
1523 | */ | |
1524 | intel_runtime_pm_get(dev_priv); | |
2d803c2d | 1525 | intel_guc_log_flush_complete(&dev_priv->guc); |
4100b2ab SAK |
1526 | intel_runtime_pm_put(dev_priv); |
1527 | } | |
f8240835 | 1528 | |
896a0cb0 SAK |
1529 | void i915_guc_flush_logs(struct drm_i915_private *dev_priv) |
1530 | { | |
1531 | if (!i915.enable_guc_submission || (i915.guc_log_level < 0)) | |
1532 | return; | |
1533 | ||
1534 | /* First disable the interrupts, will be renabled afterwards */ | |
1535 | gen9_disable_guc_interrupts(dev_priv); | |
1536 | ||
1537 | /* Before initiating the forceful flush, wait for any pending/ongoing | |
1538 | * flush to complete otherwise forceful flush may not actually happen. | |
1539 | */ | |
1540 | flush_work(&dev_priv->guc.log.flush_work); | |
1541 | ||
1542 | /* Ask GuC to update the log buffer state */ | |
2d803c2d | 1543 | intel_guc_log_flush(&dev_priv->guc); |
896a0cb0 SAK |
1544 | |
1545 | /* GuC would have updated log buffer by now, so capture it */ | |
1546 | i915_guc_capture_logs(dev_priv); | |
1547 | } | |
1548 | ||
f8240835 AG |
1549 | void i915_guc_unregister(struct drm_i915_private *dev_priv) |
1550 | { | |
1551 | if (!i915.enable_guc_submission) | |
1552 | return; | |
1553 | ||
1554 | mutex_lock(&dev_priv->drm.struct_mutex); | |
1555 | guc_log_cleanup(&dev_priv->guc); | |
1556 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1557 | } | |
1558 | ||
1559 | void i915_guc_register(struct drm_i915_private *dev_priv) | |
1560 | { | |
1561 | if (!i915.enable_guc_submission) | |
1562 | return; | |
1563 | ||
1564 | mutex_lock(&dev_priv->drm.struct_mutex); | |
1565 | guc_log_late_setup(&dev_priv->guc); | |
1566 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1567 | } | |
685534ef SAK |
1568 | |
1569 | int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) | |
1570 | { | |
1571 | union guc_log_control log_param; | |
1572 | int ret; | |
1573 | ||
1574 | log_param.value = control_val; | |
1575 | ||
1576 | if (log_param.verbosity < GUC_LOG_VERBOSITY_MIN || | |
1577 | log_param.verbosity > GUC_LOG_VERBOSITY_MAX) | |
1578 | return -EINVAL; | |
1579 | ||
1580 | /* This combination doesn't make sense & won't have any effect */ | |
1581 | if (!log_param.logging_enabled && (i915.guc_log_level < 0)) | |
1582 | return 0; | |
1583 | ||
2d803c2d | 1584 | ret = intel_guc_log_control(&dev_priv->guc, log_param.value); |
685534ef | 1585 | if (ret < 0) { |
a80bc45f | 1586 | DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret); |
685534ef SAK |
1587 | return ret; |
1588 | } | |
1589 | ||
1590 | i915.guc_log_level = log_param.verbosity; | |
1591 | ||
1592 | /* If log_level was set as -1 at boot time, then the relay channel file | |
1593 | * wouldn't have been created by now and interrupts also would not have | |
1594 | * been enabled. | |
1595 | */ | |
1596 | if (!dev_priv->guc.log.relay_chan) { | |
1597 | ret = guc_log_late_setup(&dev_priv->guc); | |
1598 | if (!ret) | |
1599 | gen9_enable_guc_interrupts(dev_priv); | |
1600 | } else if (!log_param.logging_enabled) { | |
1601 | /* Once logging is disabled, GuC won't generate logs & send an | |
1602 | * interrupt. But there could be some data in the log buffer | |
1603 | * which is yet to be captured. So request GuC to update the log | |
1604 | * buffer state and then collect the left over logs. | |
1605 | */ | |
1606 | i915_guc_flush_logs(dev_priv); | |
1607 | ||
1608 | /* As logging is disabled, update log level to reflect that */ | |
1609 | i915.guc_log_level = -1; | |
1610 | } else { | |
1611 | /* In case interrupts were disabled, enable them now */ | |
1612 | gen9_enable_guc_interrupts(dev_priv); | |
1613 | } | |
1614 | ||
1615 | return ret; | |
1616 | } |