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bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/circ_buf.h> | |
26 | #include "i915_drv.h" | |
27 | #include "intel_guc.h" | |
28 | ||
44a28b1d | 29 | /** |
feda33ef | 30 | * DOC: GuC-based command submission |
44a28b1d DG |
31 | * |
32 | * i915_guc_client: | |
33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
34 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
37 | * is mapped to client space. So the client can write Work Item then ring the | |
38 | * doorbell. | |
39 | * | |
40 | * To simplify the implementation, we allocate one gem object that contains all | |
41 | * pages for doorbell, process descriptor and workqueue. | |
42 | * | |
43 | * The Scratch registers: | |
44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
46 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
47 | * Firmware writes a success/fail code back to the action register after | |
48 | * processes the request. The kernel driver polls waiting for this update and | |
49 | * then proceeds. | |
50 | * See host2guc_action() | |
51 | * | |
52 | * Doorbells: | |
53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
54 | * mapped into process space. | |
55 | * | |
56 | * Work Items: | |
57 | * There are several types of work items that the host may place into a | |
58 | * workqueue, each with its own requirements and limitations. Currently only | |
59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
60 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
61 | * ELSP context descriptor dword into Work Item. | |
62 | * See guc_add_workqueue_item() | |
63 | * | |
64 | */ | |
65 | ||
66 | /* | |
67 | * Read GuC command/status register (SOFT_SCRATCH_0) | |
68 | * Return true if it contains a response rather than a command | |
69 | */ | |
70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, | |
71 | u32 *status) | |
72 | { | |
73 | u32 val = I915_READ(SOFT_SCRATCH(0)); | |
74 | *status = val; | |
75 | return GUC2HOST_IS_RESPONSE(val); | |
76 | } | |
77 | ||
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) | |
79 | { | |
80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
81 | u32 status; | |
82 | int i; | |
83 | int ret; | |
84 | ||
85 | if (WARN_ON(len < 1 || len > 15)) | |
86 | return -EINVAL; | |
87 | ||
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
44a28b1d DG |
89 | |
90 | dev_priv->guc.action_count += 1; | |
91 | dev_priv->guc.action_cmd = data[0]; | |
92 | ||
93 | for (i = 0; i < len; i++) | |
94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); | |
95 | ||
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); | |
97 | ||
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); | |
99 | ||
ab0e455b DG |
100 | /* |
101 | * Fast commands should complete in less than 10us, so sample quickly | |
102 | * up to that length of time, then switch to a slower sleep-wait loop. | |
103 | * No HOST2GUC command should ever take longer than 10ms. | |
104 | */ | |
105 | ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10); | |
106 | if (ret) | |
107 | ret = wait_for(host2guc_action_response(dev_priv, &status), 10); | |
44a28b1d DG |
108 | if (status != GUC2HOST_STATUS_SUCCESS) { |
109 | /* | |
110 | * Either the GuC explicitly returned an error (which | |
111 | * we convert to -EIO here) or no response at all was | |
112 | * received within the timeout limit (-ETIMEDOUT) | |
113 | */ | |
114 | if (ret != -ETIMEDOUT) | |
115 | ret = -EIO; | |
116 | ||
535b2f5e DG |
117 | DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n", |
118 | data[0], ret, status, I915_READ(SOFT_SCRATCH(15))); | |
44a28b1d DG |
119 | |
120 | dev_priv->guc.action_fail += 1; | |
121 | dev_priv->guc.action_err = ret; | |
122 | } | |
123 | dev_priv->guc.action_status = status; | |
124 | ||
44a28b1d DG |
125 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
130 | /* | |
131 | * Tell the GuC to allocate or deallocate a specific doorbell | |
132 | */ | |
133 | ||
134 | static int host2guc_allocate_doorbell(struct intel_guc *guc, | |
135 | struct i915_guc_client *client) | |
136 | { | |
137 | u32 data[2]; | |
138 | ||
139 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; | |
140 | data[1] = client->ctx_index; | |
141 | ||
142 | return host2guc_action(guc, data, 2); | |
143 | } | |
144 | ||
145 | static int host2guc_release_doorbell(struct intel_guc *guc, | |
146 | struct i915_guc_client *client) | |
147 | { | |
148 | u32 data[2]; | |
149 | ||
150 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; | |
151 | data[1] = client->ctx_index; | |
152 | ||
153 | return host2guc_action(guc, data, 2); | |
154 | } | |
155 | ||
f5d3c3ea AD |
156 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
157 | struct i915_guc_client *client) | |
158 | { | |
159 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
160 | u32 data[2]; | |
161 | ||
162 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; | |
93f25318 | 163 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
61251512 | 164 | if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) |
93f25318 AD |
165 | data[1] = 0; |
166 | else | |
167 | /* bit 0 and 1 are for Render and Media domain separately */ | |
168 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; | |
169 | ||
170 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
f5d3c3ea AD |
171 | } |
172 | ||
44a28b1d DG |
173 | /* |
174 | * Initialise, update, or clear doorbell data shared with the GuC | |
175 | * | |
176 | * These functions modify shared data and so need access to the mapped | |
177 | * client object which contains the page being used for the doorbell | |
178 | */ | |
179 | ||
a667429b DG |
180 | static int guc_update_doorbell_id(struct intel_guc *guc, |
181 | struct i915_guc_client *client, | |
182 | u16 new_id) | |
44a28b1d | 183 | { |
8b797af1 | 184 | struct sg_table *sg = guc->ctx_pool_vma->pages; |
a667429b | 185 | void *doorbell_bitmap = guc->doorbell_bitmap; |
44a28b1d | 186 | struct guc_doorbell_info *doorbell; |
a667429b DG |
187 | struct guc_context_desc desc; |
188 | size_t len; | |
44a28b1d | 189 | |
0d92a6a4 | 190 | doorbell = client->client_base + client->doorbell_offset; |
44a28b1d | 191 | |
a667429b DG |
192 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID && |
193 | test_bit(client->doorbell_id, doorbell_bitmap)) { | |
194 | /* Deactivate the old doorbell */ | |
195 | doorbell->db_status = GUC_DOORBELL_DISABLED; | |
196 | (void)host2guc_release_doorbell(guc, client); | |
197 | __clear_bit(client->doorbell_id, doorbell_bitmap); | |
198 | } | |
199 | ||
200 | /* Update the GuC's idea of the doorbell ID */ | |
201 | len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
202 | sizeof(desc) * client->ctx_index); | |
203 | if (len != sizeof(desc)) | |
204 | return -EFAULT; | |
205 | desc.db_id = new_id; | |
206 | len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
207 | sizeof(desc) * client->ctx_index); | |
208 | if (len != sizeof(desc)) | |
209 | return -EFAULT; | |
210 | ||
211 | client->doorbell_id = new_id; | |
212 | if (new_id == GUC_INVALID_DOORBELL_ID) | |
213 | return 0; | |
214 | ||
215 | /* Activate the new doorbell */ | |
216 | __set_bit(new_id, doorbell_bitmap); | |
44a28b1d | 217 | doorbell->cookie = 0; |
a667429b DG |
218 | doorbell->db_status = GUC_DOORBELL_ENABLED; |
219 | return host2guc_allocate_doorbell(guc, client); | |
220 | } | |
221 | ||
222 | static int guc_init_doorbell(struct intel_guc *guc, | |
223 | struct i915_guc_client *client, | |
224 | uint16_t db_id) | |
225 | { | |
226 | return guc_update_doorbell_id(guc, client, db_id); | |
44a28b1d DG |
227 | } |
228 | ||
44a28b1d DG |
229 | static void guc_disable_doorbell(struct intel_guc *guc, |
230 | struct i915_guc_client *client) | |
231 | { | |
a667429b | 232 | (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID); |
44a28b1d | 233 | |
44a28b1d DG |
234 | /* XXX: wait for any interrupts */ |
235 | /* XXX: wait for workqueue to drain */ | |
236 | } | |
237 | ||
f10d69a7 DG |
238 | static uint16_t |
239 | select_doorbell_register(struct intel_guc *guc, uint32_t priority) | |
240 | { | |
241 | /* | |
242 | * The bitmap tracks which doorbell registers are currently in use. | |
243 | * It is split into two halves; the first half is used for normal | |
244 | * priority contexts, the second half for high-priority ones. | |
245 | * Note that logically higher priorities are numerically less than | |
246 | * normal ones, so the test below means "is it high-priority?" | |
247 | */ | |
248 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
249 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
250 | const uint16_t start = hi_pri ? half : 0; | |
251 | const uint16_t end = start + half; | |
252 | uint16_t id; | |
253 | ||
254 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); | |
255 | if (id == end) | |
256 | id = GUC_INVALID_DOORBELL_ID; | |
257 | ||
258 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
259 | hi_pri ? "high" : "normal", id); | |
260 | ||
261 | return id; | |
262 | } | |
263 | ||
44a28b1d DG |
264 | /* |
265 | * Select, assign and relase doorbell cachelines | |
266 | * | |
267 | * These functions track which doorbell cachelines are in use. | |
268 | * The data they manipulate is protected by the host2guc lock. | |
269 | */ | |
270 | ||
271 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
272 | { | |
273 | const uint32_t cacheline_size = cache_line_size(); | |
274 | uint32_t offset; | |
275 | ||
44a28b1d DG |
276 | /* Doorbell uses a single cache line within a page */ |
277 | offset = offset_in_page(guc->db_cacheline); | |
278 | ||
279 | /* Moving to next cache line to reduce contention */ | |
280 | guc->db_cacheline += cacheline_size; | |
281 | ||
44a28b1d DG |
282 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
283 | offset, guc->db_cacheline, cacheline_size); | |
284 | ||
285 | return offset; | |
286 | } | |
287 | ||
44a28b1d DG |
288 | /* |
289 | * Initialise the process descriptor shared with the GuC firmware. | |
290 | */ | |
291 | static void guc_init_proc_desc(struct intel_guc *guc, | |
292 | struct i915_guc_client *client) | |
293 | { | |
294 | struct guc_process_desc *desc; | |
44a28b1d | 295 | |
0d92a6a4 | 296 | desc = client->client_base + client->proc_desc_offset; |
44a28b1d DG |
297 | |
298 | memset(desc, 0, sizeof(*desc)); | |
299 | ||
300 | /* | |
301 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
302 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
303 | * space for kernel clients (map on demand instead? May make debug | |
304 | * easier to have it mapped). | |
305 | */ | |
306 | desc->wq_base_addr = 0; | |
307 | desc->db_base_addr = 0; | |
308 | ||
309 | desc->context_id = client->ctx_index; | |
310 | desc->wq_size_bytes = client->wq_size; | |
311 | desc->wq_status = WQ_STATUS_ACTIVE; | |
312 | desc->priority = client->priority; | |
44a28b1d DG |
313 | } |
314 | ||
315 | /* | |
316 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
317 | * | |
318 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
319 | * data structures relating to this client (doorbell, process descriptor, | |
320 | * write queue, etc). | |
321 | */ | |
322 | ||
323 | static void guc_init_ctx_desc(struct intel_guc *guc, | |
324 | struct i915_guc_client *client) | |
325 | { | |
397097b0 | 326 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
e2f80391 | 327 | struct intel_engine_cs *engine; |
e2efd130 | 328 | struct i915_gem_context *ctx = client->owner; |
44a28b1d DG |
329 | struct guc_context_desc desc; |
330 | struct sg_table *sg; | |
bafb0fce | 331 | unsigned int tmp; |
86e06cc0 | 332 | u32 gfx_addr; |
44a28b1d DG |
333 | |
334 | memset(&desc, 0, sizeof(desc)); | |
335 | ||
336 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
337 | desc.context_id = client->ctx_index; | |
338 | desc.priority = client->priority; | |
44a28b1d DG |
339 | desc.db_id = client->doorbell_id; |
340 | ||
bafb0fce | 341 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { |
9021ad03 | 342 | struct intel_context *ce = &ctx->engine[engine->id]; |
c18468c4 DG |
343 | uint32_t guc_engine_id = engine->guc_id; |
344 | struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id]; | |
d1675198 AD |
345 | |
346 | /* TODO: We have a design issue to be solved here. Only when we | |
347 | * receive the first batch, we know which engine is used by the | |
348 | * user. But here GuC expects the lrc and ring to be pinned. It | |
349 | * is not an issue for default context, which is the only one | |
350 | * for now who owns a GuC client. But for future owner of GuC | |
351 | * client, need to make sure lrc is pinned prior to enter here. | |
352 | */ | |
9021ad03 | 353 | if (!ce->state) |
d1675198 AD |
354 | break; /* XXX: continue? */ |
355 | ||
9021ad03 | 356 | lrc->context_desc = lower_32_bits(ce->lrc_desc); |
d1675198 AD |
357 | |
358 | /* The state page is after PPHWSP */ | |
57e88531 | 359 | lrc->ring_lcra = |
bde13ebd | 360 | i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; |
d1675198 | 361 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
c18468c4 | 362 | (guc_engine_id << GUC_ELC_ENGINE_OFFSET); |
d1675198 | 363 | |
bde13ebd | 364 | lrc->ring_begin = i915_ggtt_offset(ce->ring->vma); |
57e88531 CW |
365 | lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; |
366 | lrc->ring_next_free_location = lrc->ring_begin; | |
d1675198 AD |
367 | lrc->ring_current_tail_pointer_value = 0; |
368 | ||
c18468c4 | 369 | desc.engines_used |= (1 << guc_engine_id); |
d1675198 AD |
370 | } |
371 | ||
e02757d9 DG |
372 | DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", |
373 | client->engines, desc.engines_used); | |
d1675198 AD |
374 | WARN_ON(desc.engines_used == 0); |
375 | ||
44a28b1d | 376 | /* |
86e06cc0 DG |
377 | * The doorbell, process descriptor, and workqueue are all parts |
378 | * of the client object, which the GuC will reference via the GGTT | |
44a28b1d | 379 | */ |
bde13ebd | 380 | gfx_addr = i915_ggtt_offset(client->vma); |
8b797af1 | 381 | desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + |
86e06cc0 DG |
382 | client->doorbell_offset; |
383 | desc.db_trigger_cpu = (uintptr_t)client->client_base + | |
384 | client->doorbell_offset; | |
385 | desc.db_trigger_uk = gfx_addr + client->doorbell_offset; | |
386 | desc.process_desc = gfx_addr + client->proc_desc_offset; | |
387 | desc.wq_addr = gfx_addr + client->wq_offset; | |
44a28b1d DG |
388 | desc.wq_size = client->wq_size; |
389 | ||
390 | /* | |
e2efd130 | 391 | * XXX: Take LRCs from an existing context if this is not an |
44a28b1d DG |
392 | * IsKMDCreatedContext client |
393 | */ | |
394 | desc.desc_private = (uintptr_t)client; | |
395 | ||
396 | /* Pool context is pinned already */ | |
8b797af1 | 397 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
398 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
399 | sizeof(desc) * client->ctx_index); | |
400 | } | |
401 | ||
402 | static void guc_fini_ctx_desc(struct intel_guc *guc, | |
403 | struct i915_guc_client *client) | |
404 | { | |
405 | struct guc_context_desc desc; | |
406 | struct sg_table *sg; | |
407 | ||
408 | memset(&desc, 0, sizeof(desc)); | |
409 | ||
8b797af1 | 410 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
411 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
412 | sizeof(desc) * client->ctx_index); | |
413 | } | |
414 | ||
7c2c270d DG |
415 | /** |
416 | * i915_guc_wq_check_space() - check that the GuC can accept a request | |
417 | * @request: request associated with the commands | |
418 | * | |
419 | * Return: 0 if space is available | |
420 | * -EAGAIN if space is not currently available | |
421 | * | |
422 | * This function must be called (and must return 0) before a request | |
423 | * is submitted to the GuC via i915_guc_submit() below. Once a result | |
424 | * of 0 has been returned, it remains valid until (but only until) | |
425 | * the next call to submit(). | |
426 | * | |
427 | * This precheck allows the caller to determine in advance that space | |
428 | * will be available for the next submission before committing resources | |
429 | * to it, and helps avoid late failures with complicated recovery paths. | |
430 | */ | |
431 | int i915_guc_wq_check_space(struct drm_i915_gem_request *request) | |
44a28b1d | 432 | { |
551aaecd | 433 | const size_t wqi_size = sizeof(struct guc_wq_item); |
7c2c270d | 434 | struct i915_guc_client *gc = request->i915->guc.execbuf_client; |
44a28b1d | 435 | struct guc_process_desc *desc; |
551aaecd | 436 | u32 freespace; |
44a28b1d | 437 | |
7c2c270d | 438 | GEM_BUG_ON(gc == NULL); |
a7e02199 | 439 | |
0d92a6a4 | 440 | desc = gc->client_base + gc->proc_desc_offset; |
44a28b1d | 441 | |
551aaecd DG |
442 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); |
443 | if (likely(freespace >= wqi_size)) | |
444 | return 0; | |
5a843307 | 445 | |
551aaecd | 446 | gc->no_wq_space += 1; |
44a28b1d | 447 | |
551aaecd | 448 | return -EAGAIN; |
44a28b1d DG |
449 | } |
450 | ||
0a31afbc DG |
451 | static void guc_add_workqueue_item(struct i915_guc_client *gc, |
452 | struct drm_i915_gem_request *rq) | |
44a28b1d | 453 | { |
0a31afbc DG |
454 | /* wqi_len is in DWords, and does not include the one-word header */ |
455 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
456 | const u32 wqi_len = wqi_size/sizeof(u32) - 1; | |
c18468c4 | 457 | struct intel_engine_cs *engine = rq->engine; |
a5916e8f | 458 | struct guc_process_desc *desc; |
44a28b1d DG |
459 | struct guc_wq_item *wqi; |
460 | void *base; | |
0a31afbc | 461 | u32 freespace, tail, wq_off, wq_page; |
a7e02199 | 462 | |
a5916e8f | 463 | desc = gc->client_base + gc->proc_desc_offset; |
44a28b1d | 464 | |
0a31afbc DG |
465 | /* Free space is guaranteed, see i915_guc_wq_check_space() above */ |
466 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); | |
467 | GEM_BUG_ON(freespace < wqi_size); | |
468 | ||
469 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
470 | tail = rq->tail; | |
471 | GEM_BUG_ON(tail & 7); | |
472 | tail >>= 3; | |
473 | GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); | |
44a28b1d DG |
474 | |
475 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
476 | * should not have the case where structure wqi is across page, neither | |
477 | * wrapped to the beginning. This simplifies the implementation below. | |
478 | * | |
479 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
480 | * workqueue buffer dw by dw. | |
481 | */ | |
0a31afbc | 482 | BUILD_BUG_ON(wqi_size != 16); |
44a28b1d | 483 | |
0a31afbc DG |
484 | /* postincrement WQ tail for next time */ |
485 | wq_off = gc->wq_tail; | |
486 | gc->wq_tail += wqi_size; | |
487 | gc->wq_tail &= gc->wq_size - 1; | |
488 | GEM_BUG_ON(wq_off & (wqi_size - 1)); | |
489 | ||
490 | /* WQ starts from the page after doorbell / process_desc */ | |
491 | wq_page = (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT; | |
44a28b1d | 492 | wq_off &= PAGE_SIZE - 1; |
8b797af1 | 493 | base = kmap_atomic(i915_gem_object_get_page(gc->vma->obj, wq_page)); |
44a28b1d DG |
494 | wqi = (struct guc_wq_item *)((char *)base + wq_off); |
495 | ||
0a31afbc | 496 | /* Now fill in the 4-word work queue item */ |
44a28b1d | 497 | wqi->header = WQ_TYPE_INORDER | |
0a31afbc | 498 | (wqi_len << WQ_LEN_SHIFT) | |
c18468c4 | 499 | (engine->guc_id << WQ_TARGET_SHIFT) | |
44a28b1d DG |
500 | WQ_NO_WCFLUSH_WAIT; |
501 | ||
502 | /* The GuC wants only the low-order word of the context descriptor */ | |
c18468c4 | 503 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine); |
44a28b1d | 504 | |
44a28b1d | 505 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
04769652 | 506 | wqi->fence_id = rq->fence.seqno; |
44a28b1d DG |
507 | |
508 | kunmap_atomic(base); | |
44a28b1d DG |
509 | } |
510 | ||
10d2c3e2 DG |
511 | static int guc_ring_doorbell(struct i915_guc_client *gc) |
512 | { | |
513 | struct guc_process_desc *desc; | |
514 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
515 | union guc_doorbell_qw *db; | |
516 | int attempt = 2, ret = -EAGAIN; | |
517 | ||
518 | desc = gc->client_base + gc->proc_desc_offset; | |
519 | ||
520 | /* Update the tail so it is visible to GuC */ | |
521 | desc->tail = gc->wq_tail; | |
522 | ||
523 | /* current cookie */ | |
524 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
525 | db_cmp.cookie = gc->cookie; | |
526 | ||
527 | /* cookie to be updated */ | |
528 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
529 | db_exc.cookie = gc->cookie + 1; | |
530 | if (db_exc.cookie == 0) | |
531 | db_exc.cookie = 1; | |
532 | ||
533 | /* pointer of current doorbell cacheline */ | |
534 | db = gc->client_base + gc->doorbell_offset; | |
535 | ||
536 | while (attempt--) { | |
537 | /* lets ring the doorbell */ | |
538 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
539 | db_cmp.value_qw, db_exc.value_qw); | |
540 | ||
541 | /* if the exchange was successfully executed */ | |
542 | if (db_ret.value_qw == db_cmp.value_qw) { | |
543 | /* db was successfully rung */ | |
544 | gc->cookie = db_exc.cookie; | |
545 | ret = 0; | |
546 | break; | |
547 | } | |
548 | ||
549 | /* XXX: doorbell was lost and need to acquire it again */ | |
550 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
551 | break; | |
552 | ||
535b2f5e DG |
553 | DRM_WARN("Cookie mismatch. Expected %d, found %d\n", |
554 | db_cmp.cookie, db_ret.cookie); | |
10d2c3e2 DG |
555 | |
556 | /* update the cookie to newly read cookie from GuC */ | |
557 | db_cmp.cookie = db_ret.cookie; | |
558 | db_exc.cookie = db_ret.cookie + 1; | |
559 | if (db_exc.cookie == 0) | |
560 | db_exc.cookie = 1; | |
561 | } | |
562 | ||
563 | return ret; | |
564 | } | |
565 | ||
44a28b1d DG |
566 | /** |
567 | * i915_guc_submit() - Submit commands through GuC | |
feda33ef | 568 | * @rq: request associated with the commands |
44a28b1d | 569 | * |
7c2c270d DG |
570 | * Return: 0 on success, otherwise an errno. |
571 | * (Note: nonzero really shouldn't happen!) | |
572 | * | |
573 | * The caller must have already called i915_guc_wq_check_space() above | |
574 | * with a result of 0 (success) since the last request submission. This | |
575 | * guarantees that there is space in the work queue for the new request, | |
576 | * so enqueuing the item cannot fail. | |
577 | * | |
578 | * Bad Things Will Happen if the caller violates this protocol e.g. calls | |
579 | * submit() when check() says there's no space, or calls submit() multiple | |
580 | * times with no intervening check(). | |
581 | * | |
582 | * The only error here arises if the doorbell hardware isn't functioning | |
583 | * as expected, which really shouln't happen. | |
44a28b1d | 584 | */ |
ddd66c51 | 585 | static void i915_guc_submit(struct drm_i915_gem_request *rq) |
44a28b1d | 586 | { |
0b63bb14 | 587 | unsigned int engine_id = rq->engine->id; |
7c2c270d DG |
588 | struct intel_guc *guc = &rq->i915->guc; |
589 | struct i915_guc_client *client = guc->execbuf_client; | |
0a31afbc | 590 | int b_ret; |
44a28b1d | 591 | |
0a31afbc DG |
592 | guc_add_workqueue_item(client, rq); |
593 | b_ret = guc_ring_doorbell(client); | |
44a28b1d | 594 | |
397097b0 | 595 | client->submissions[engine_id] += 1; |
0a31afbc DG |
596 | client->retcode = b_ret; |
597 | if (b_ret) | |
44a28b1d | 598 | client->b_fail += 1; |
0a31afbc | 599 | |
397097b0 | 600 | guc->submissions[engine_id] += 1; |
04769652 | 601 | guc->last_seqno[engine_id] = rq->fence.seqno; |
44a28b1d DG |
602 | } |
603 | ||
604 | /* | |
605 | * Everything below here is concerned with setup & teardown, and is | |
606 | * therefore not part of the somewhat time-critical batch-submission | |
607 | * path of i915_guc_submit() above. | |
608 | */ | |
609 | ||
bac427f8 | 610 | /** |
8b797af1 CW |
611 | * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage |
612 | * @guc: the guc | |
613 | * @size: size of area to allocate (both virtual space and memory) | |
bac427f8 | 614 | * |
8b797af1 CW |
615 | * This is a wrapper to create an object for use with the GuC. In order to |
616 | * use it inside the GuC, an object needs to be pinned lifetime, so we allocate | |
617 | * both some backing storage and a range inside the Global GTT. We must pin | |
618 | * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that | |
619 | * range is reserved inside GuC. | |
bac427f8 | 620 | * |
8b797af1 | 621 | * Return: A i915_vma if successful, otherwise an ERR_PTR. |
bac427f8 | 622 | */ |
8b797af1 | 623 | static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size) |
bac427f8 | 624 | { |
8b797af1 | 625 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
bac427f8 | 626 | struct drm_i915_gem_object *obj; |
8b797af1 CW |
627 | struct i915_vma *vma; |
628 | int ret; | |
bac427f8 | 629 | |
91c8a326 | 630 | obj = i915_gem_object_create(&dev_priv->drm, size); |
fe3db79b | 631 | if (IS_ERR(obj)) |
8b797af1 | 632 | return ERR_CAST(obj); |
bac427f8 | 633 | |
8b797af1 CW |
634 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); |
635 | if (IS_ERR(vma)) | |
636 | goto err; | |
bac427f8 | 637 | |
8b797af1 CW |
638 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, |
639 | PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
640 | if (ret) { | |
641 | vma = ERR_PTR(ret); | |
642 | goto err; | |
bac427f8 AD |
643 | } |
644 | ||
645 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
646 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
647 | ||
8b797af1 CW |
648 | return vma; |
649 | ||
650 | err: | |
651 | i915_gem_object_put(obj); | |
652 | return vma; | |
bac427f8 AD |
653 | } |
654 | ||
0daf556c DG |
655 | static void |
656 | guc_client_free(struct drm_i915_private *dev_priv, | |
657 | struct i915_guc_client *client) | |
44a28b1d | 658 | { |
44a28b1d DG |
659 | struct intel_guc *guc = &dev_priv->guc; |
660 | ||
661 | if (!client) | |
662 | return; | |
663 | ||
44a28b1d DG |
664 | /* |
665 | * XXX: wait for any outstanding submissions before freeing memory. | |
666 | * Be sure to drop any locks | |
667 | */ | |
668 | ||
0d92a6a4 DG |
669 | if (client->client_base) { |
670 | /* | |
a667429b DG |
671 | * If we got as far as setting up a doorbell, make sure we |
672 | * shut it down before unmapping & deallocating the memory. | |
0d92a6a4 | 673 | */ |
a667429b | 674 | guc_disable_doorbell(guc, client); |
0d92a6a4 DG |
675 | |
676 | kunmap(kmap_to_page(client->client_base)); | |
677 | } | |
678 | ||
19880c4a | 679 | i915_vma_unpin_and_release(&client->vma); |
44a28b1d DG |
680 | |
681 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
682 | guc_fini_ctx_desc(guc, client); | |
683 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); | |
684 | } | |
685 | ||
686 | kfree(client); | |
687 | } | |
688 | ||
84b7f882 DG |
689 | /* Check that a doorbell register is in the expected state */ |
690 | static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id) | |
691 | { | |
692 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
693 | i915_reg_t drbreg = GEN8_DRBREGL(db_id); | |
694 | uint32_t value = I915_READ(drbreg); | |
695 | bool enabled = (value & GUC_DOORBELL_ENABLED) != 0; | |
696 | bool expected = test_bit(db_id, guc->doorbell_bitmap); | |
697 | ||
698 | if (enabled == expected) | |
699 | return true; | |
700 | ||
701 | DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n", | |
702 | db_id, drbreg.reg, value, | |
703 | expected ? "active" : "inactive"); | |
704 | ||
705 | return false; | |
706 | } | |
707 | ||
4d75787b | 708 | /* |
8888cd01 | 709 | * Borrow the first client to set up & tear down each unused doorbell |
4d75787b DG |
710 | * in turn, to ensure that all doorbell h/w is (re)initialised. |
711 | */ | |
712 | static void guc_init_doorbell_hw(struct intel_guc *guc) | |
713 | { | |
4d75787b | 714 | struct i915_guc_client *client = guc->execbuf_client; |
84b7f882 DG |
715 | uint16_t db_id; |
716 | int i, err; | |
4d75787b | 717 | |
84b7f882 | 718 | /* Save client's original doorbell selection */ |
4d75787b DG |
719 | db_id = client->doorbell_id; |
720 | ||
721 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) { | |
84b7f882 DG |
722 | /* Skip if doorbell is OK */ |
723 | if (guc_doorbell_check(guc, i)) | |
8888cd01 DG |
724 | continue; |
725 | ||
4d75787b | 726 | err = guc_update_doorbell_id(guc, client, i); |
84b7f882 DG |
727 | if (err) |
728 | DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n", | |
729 | i, err); | |
4d75787b DG |
730 | } |
731 | ||
732 | /* Restore to original value */ | |
733 | err = guc_update_doorbell_id(guc, client, db_id); | |
734 | if (err) | |
535b2f5e DG |
735 | DRM_WARN("Failed to restore doorbell to %d, err %d\n", |
736 | db_id, err); | |
4d75787b | 737 | |
84b7f882 DG |
738 | /* Read back & verify all doorbell registers */ |
739 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) | |
740 | (void)guc_doorbell_check(guc, i); | |
4d75787b DG |
741 | } |
742 | ||
44a28b1d DG |
743 | /** |
744 | * guc_client_alloc() - Allocate an i915_guc_client | |
0daf556c | 745 | * @dev_priv: driver private data structure |
ceae5317 | 746 | * @engines: The set of engines to enable for this client |
44a28b1d DG |
747 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
748 | * The kernel client to replace ExecList submission is created with | |
749 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
750 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
751 | * @ctx: the context that owns the client (we use the default render |
752 | * context) | |
44a28b1d | 753 | * |
0d92a6a4 | 754 | * Return: An i915_guc_client object if success, else NULL. |
44a28b1d | 755 | */ |
0daf556c DG |
756 | static struct i915_guc_client * |
757 | guc_client_alloc(struct drm_i915_private *dev_priv, | |
e02757d9 | 758 | uint32_t engines, |
0daf556c DG |
759 | uint32_t priority, |
760 | struct i915_gem_context *ctx) | |
44a28b1d DG |
761 | { |
762 | struct i915_guc_client *client; | |
44a28b1d | 763 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 | 764 | struct i915_vma *vma; |
a667429b | 765 | uint16_t db_id; |
44a28b1d DG |
766 | |
767 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
768 | if (!client) | |
769 | return NULL; | |
770 | ||
d1675198 | 771 | client->owner = ctx; |
44a28b1d | 772 | client->guc = guc; |
e02757d9 DG |
773 | client->engines = engines; |
774 | client->priority = priority; | |
775 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
44a28b1d DG |
776 | |
777 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
778 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
779 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
780 | client->ctx_index = GUC_INVALID_CTX_ID; | |
781 | goto err; | |
782 | } | |
783 | ||
784 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
8b797af1 CW |
785 | vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE); |
786 | if (IS_ERR(vma)) | |
44a28b1d DG |
787 | goto err; |
788 | ||
0d92a6a4 | 789 | /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ |
8b797af1 CW |
790 | client->vma = vma; |
791 | client->client_base = kmap(i915_vma_first_page(vma)); | |
44a28b1d DG |
792 | client->wq_offset = GUC_DB_SIZE; |
793 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d | 794 | |
f10d69a7 DG |
795 | db_id = select_doorbell_register(guc, client->priority); |
796 | if (db_id == GUC_INVALID_DOORBELL_ID) | |
797 | /* XXX: evict a doorbell instead? */ | |
798 | goto err; | |
799 | ||
44a28b1d DG |
800 | client->doorbell_offset = select_doorbell_cacheline(guc); |
801 | ||
802 | /* | |
803 | * Since the doorbell only requires a single cacheline, we can save | |
804 | * space by putting the application process descriptor in the same | |
805 | * page. Use the half of the page that doesn't include the doorbell. | |
806 | */ | |
807 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
808 | client->proc_desc_offset = 0; | |
809 | else | |
810 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
811 | ||
44a28b1d DG |
812 | guc_init_proc_desc(guc, client); |
813 | guc_init_ctx_desc(guc, client); | |
a667429b | 814 | if (guc_init_doorbell(guc, client, db_id)) |
44a28b1d DG |
815 | goto err; |
816 | ||
e02757d9 DG |
817 | DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n", |
818 | priority, client, client->engines, client->ctx_index); | |
a667429b DG |
819 | DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n", |
820 | client->doorbell_id, client->doorbell_offset); | |
44a28b1d DG |
821 | |
822 | return client; | |
823 | ||
824 | err: | |
0daf556c | 825 | guc_client_free(dev_priv, client); |
44a28b1d DG |
826 | return NULL; |
827 | } | |
828 | ||
4c7e77fc AD |
829 | static void guc_create_log(struct intel_guc *guc) |
830 | { | |
8b797af1 | 831 | struct i915_vma *vma; |
4c7e77fc AD |
832 | unsigned long offset; |
833 | uint32_t size, flags; | |
834 | ||
835 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) | |
836 | return; | |
837 | ||
838 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) | |
839 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; | |
840 | ||
841 | /* The first page is to save log buffer state. Allocate one | |
842 | * extra page for others in case for overlap */ | |
843 | size = (1 + GUC_LOG_DPC_PAGES + 1 + | |
844 | GUC_LOG_ISR_PAGES + 1 + | |
845 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; | |
846 | ||
8b797af1 CW |
847 | vma = guc->log_vma; |
848 | if (!vma) { | |
849 | vma = guc_allocate_vma(guc, size); | |
850 | if (IS_ERR(vma)) { | |
4c7e77fc AD |
851 | /* logging will be off */ |
852 | i915.guc_log_level = -1; | |
853 | return; | |
854 | } | |
855 | ||
8b797af1 | 856 | guc->log_vma = vma; |
4c7e77fc AD |
857 | } |
858 | ||
859 | /* each allocated unit is a page */ | |
860 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | | |
861 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | | |
862 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | | |
863 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); | |
864 | ||
bde13ebd | 865 | offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */ |
4c7e77fc AD |
866 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; |
867 | } | |
868 | ||
463704d0 AD |
869 | static void init_guc_policies(struct guc_policies *policies) |
870 | { | |
871 | struct guc_policy *policy; | |
872 | u32 p, i; | |
873 | ||
874 | policies->dpc_promote_time = 500000; | |
875 | policies->max_num_work_items = POLICY_MAX_NUM_WI; | |
876 | ||
877 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { | |
397097b0 | 878 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
463704d0 AD |
879 | policy = &policies->policy[p][i]; |
880 | ||
881 | policy->execution_quantum = 1000000; | |
882 | policy->preemption_time = 500000; | |
883 | policy->fault_time = 250000; | |
884 | policy->policy_flags = 0; | |
885 | } | |
886 | } | |
887 | ||
888 | policies->is_valid = 1; | |
889 | } | |
890 | ||
68371a95 AD |
891 | static void guc_create_ads(struct intel_guc *guc) |
892 | { | |
893 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
8b797af1 | 894 | struct i915_vma *vma; |
68371a95 | 895 | struct guc_ads *ads; |
463704d0 | 896 | struct guc_policies *policies; |
5c148e04 | 897 | struct guc_mmio_reg_state *reg_state; |
e2f80391 | 898 | struct intel_engine_cs *engine; |
68371a95 | 899 | struct page *page; |
b4ac5afc | 900 | u32 size; |
68371a95 AD |
901 | |
902 | /* The ads obj includes the struct itself and buffers passed to GuC */ | |
5c148e04 AD |
903 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
904 | sizeof(struct guc_mmio_reg_state) + | |
905 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; | |
68371a95 | 906 | |
8b797af1 CW |
907 | vma = guc->ads_vma; |
908 | if (!vma) { | |
909 | vma = guc_allocate_vma(guc, PAGE_ALIGN(size)); | |
910 | if (IS_ERR(vma)) | |
68371a95 AD |
911 | return; |
912 | ||
8b797af1 | 913 | guc->ads_vma = vma; |
68371a95 AD |
914 | } |
915 | ||
8b797af1 | 916 | page = i915_vma_first_page(vma); |
68371a95 AD |
917 | ads = kmap(page); |
918 | ||
919 | /* | |
920 | * The GuC requires a "Golden Context" when it reinitialises | |
921 | * engines after a reset. Here we use the Render ring default | |
922 | * context, which must already exist and be pinned in the GGTT, | |
923 | * so its address won't change after we've told the GuC where | |
924 | * to find it. | |
925 | */ | |
4a570db5 | 926 | engine = &dev_priv->engine[RCS]; |
57e88531 | 927 | ads->golden_context_lrca = engine->status_page.ggtt_offset; |
68371a95 | 928 | |
b4ac5afc | 929 | for_each_engine(engine, dev_priv) |
e2f80391 | 930 | ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); |
68371a95 | 931 | |
463704d0 AD |
932 | /* GuC scheduling policies */ |
933 | policies = (void *)ads + sizeof(struct guc_ads); | |
934 | init_guc_policies(policies); | |
935 | ||
bde13ebd CW |
936 | ads->scheduler_policies = |
937 | i915_ggtt_offset(vma) + sizeof(struct guc_ads); | |
463704d0 | 938 | |
5c148e04 AD |
939 | /* MMIO reg state */ |
940 | reg_state = (void *)policies + sizeof(struct guc_policies); | |
941 | ||
b4ac5afc | 942 | for_each_engine(engine, dev_priv) { |
e2f80391 TU |
943 | reg_state->mmio_white_list[engine->guc_id].mmio_start = |
944 | engine->mmio_base + GUC_MMIO_WHITE_LIST_START; | |
5c148e04 AD |
945 | |
946 | /* Nothing to be saved or restored for now. */ | |
e2f80391 | 947 | reg_state->mmio_white_list[engine->guc_id].count = 0; |
5c148e04 AD |
948 | } |
949 | ||
950 | ads->reg_state_addr = ads->scheduler_policies + | |
951 | sizeof(struct guc_policies); | |
952 | ||
953 | ads->reg_state_buffer = ads->reg_state_addr + | |
954 | sizeof(struct guc_mmio_reg_state); | |
955 | ||
68371a95 AD |
956 | kunmap(page); |
957 | } | |
958 | ||
bac427f8 AD |
959 | /* |
960 | * Set up the memory resources to be shared with the GuC. At this point, | |
961 | * we require just one object that can be mapped through the GGTT. | |
962 | */ | |
beffa517 | 963 | int i915_guc_submission_init(struct drm_i915_private *dev_priv) |
bac427f8 | 964 | { |
bac427f8 | 965 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 CW |
966 | struct i915_vma *vma; |
967 | u32 size; | |
bac427f8 | 968 | |
29fb72c7 DG |
969 | /* Wipe bitmap & delete client in case of reinitialisation */ |
970 | bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS); | |
beffa517 | 971 | i915_guc_submission_disable(dev_priv); |
29fb72c7 | 972 | |
bac427f8 AD |
973 | if (!i915.enable_guc_submission) |
974 | return 0; /* not enabled */ | |
975 | ||
8b797af1 | 976 | if (guc->ctx_pool_vma) |
bac427f8 AD |
977 | return 0; /* already allocated */ |
978 | ||
8b797af1 CW |
979 | size = PAGE_ALIGN(GUC_MAX_GPU_CONTEXTS*sizeof(struct guc_context_desc)); |
980 | vma = guc_allocate_vma(guc, size); | |
981 | if (IS_ERR(vma)) | |
982 | return PTR_ERR(vma); | |
bac427f8 | 983 | |
8b797af1 | 984 | guc->ctx_pool_vma = vma; |
bac427f8 | 985 | ida_init(&guc->ctx_ids); |
4c7e77fc | 986 | guc_create_log(guc); |
68371a95 AD |
987 | guc_create_ads(guc); |
988 | ||
bac427f8 AD |
989 | return 0; |
990 | } | |
991 | ||
beffa517 | 992 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv) |
44a28b1d | 993 | { |
44a28b1d DG |
994 | struct intel_guc *guc = &dev_priv->guc; |
995 | struct i915_guc_client *client; | |
ddd66c51 | 996 | struct intel_engine_cs *engine; |
821ed7df | 997 | struct drm_i915_gem_request *request; |
44a28b1d DG |
998 | |
999 | /* client for execbuf submission */ | |
0daf556c | 1000 | client = guc_client_alloc(dev_priv, |
e02757d9 | 1001 | INTEL_INFO(dev_priv)->ring_mask, |
0ca5fa3a CW |
1002 | GUC_CTX_PRIORITY_KMD_NORMAL, |
1003 | dev_priv->kernel_context); | |
44a28b1d | 1004 | if (!client) { |
535b2f5e | 1005 | DRM_ERROR("Failed to create normal GuC client!\n"); |
44a28b1d DG |
1006 | return -ENOMEM; |
1007 | } | |
1008 | ||
1009 | guc->execbuf_client = client; | |
f5d3c3ea | 1010 | host2guc_sample_forcewake(guc, client); |
4d75787b | 1011 | guc_init_doorbell_hw(guc); |
f5d3c3ea | 1012 | |
ddd66c51 | 1013 | /* Take over from manual control of ELSP (execlists) */ |
821ed7df | 1014 | for_each_engine(engine, dev_priv) { |
ddd66c51 CW |
1015 | engine->submit_request = i915_guc_submit; |
1016 | ||
821ed7df CW |
1017 | /* Replay the current set of previously submitted requests */ |
1018 | list_for_each_entry(request, &engine->request_list, link) | |
1019 | i915_guc_submit(request); | |
1020 | } | |
1021 | ||
44a28b1d DG |
1022 | return 0; |
1023 | } | |
1024 | ||
beffa517 | 1025 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv) |
44a28b1d | 1026 | { |
44a28b1d DG |
1027 | struct intel_guc *guc = &dev_priv->guc; |
1028 | ||
ddd66c51 CW |
1029 | if (!guc->execbuf_client) |
1030 | return; | |
1031 | ||
ddd66c51 CW |
1032 | /* Revert back to manual ELSP submission */ |
1033 | intel_execlists_enable_submission(dev_priv); | |
f4ea6bdd CW |
1034 | |
1035 | guc_client_free(dev_priv, guc->execbuf_client); | |
1036 | guc->execbuf_client = NULL; | |
44a28b1d DG |
1037 | } |
1038 | ||
beffa517 | 1039 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv) |
bac427f8 | 1040 | { |
bac427f8 AD |
1041 | struct intel_guc *guc = &dev_priv->guc; |
1042 | ||
19880c4a CW |
1043 | i915_vma_unpin_and_release(&guc->ads_vma); |
1044 | i915_vma_unpin_and_release(&guc->log_vma); | |
4c7e77fc | 1045 | |
8b797af1 | 1046 | if (guc->ctx_pool_vma) |
bac427f8 | 1047 | ida_destroy(&guc->ctx_ids); |
19880c4a | 1048 | i915_vma_unpin_and_release(&guc->ctx_pool_vma); |
bac427f8 | 1049 | } |
a1c41994 AD |
1050 | |
1051 | /** | |
1052 | * intel_guc_suspend() - notify GuC entering suspend state | |
1053 | * @dev: drm device | |
1054 | */ | |
1055 | int intel_guc_suspend(struct drm_device *dev) | |
1056 | { | |
fac5e23e | 1057 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1c41994 | 1058 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 1059 | struct i915_gem_context *ctx; |
a1c41994 AD |
1060 | u32 data[3]; |
1061 | ||
fce91f22 | 1062 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1063 | return 0; |
1064 | ||
ed54c1a1 | 1065 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
1066 | |
1067 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; | |
1068 | /* any value greater than GUC_POWER_D0 */ | |
1069 | data[1] = GUC_POWER_D1; | |
1070 | /* first page is shared data with GuC */ | |
bde13ebd | 1071 | data[2] = i915_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 AD |
1072 | |
1073 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
1074 | } | |
1075 | ||
1076 | ||
1077 | /** | |
1078 | * intel_guc_resume() - notify GuC resuming from suspend state | |
1079 | * @dev: drm device | |
1080 | */ | |
1081 | int intel_guc_resume(struct drm_device *dev) | |
1082 | { | |
fac5e23e | 1083 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1c41994 | 1084 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 1085 | struct i915_gem_context *ctx; |
a1c41994 AD |
1086 | u32 data[3]; |
1087 | ||
fce91f22 | 1088 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1089 | return 0; |
1090 | ||
ed54c1a1 | 1091 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
1092 | |
1093 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; | |
1094 | data[1] = GUC_POWER_D0; | |
1095 | /* first page is shared data with GuC */ | |
bde13ebd | 1096 | data[2] = i915_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 AD |
1097 | |
1098 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
1099 | } |